cs89x0.c revision 1.43
1 /* $NetBSD: cs89x0.c,v 1.43 2019/04/25 10:08:45 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher Gilbert 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright 1997 31 * Digital Equipment Corporation. All rights reserved. 32 * 33 * This software is furnished under license and may be used and 34 * copied only in accordance with the following terms and conditions. 35 * Subject to these conditions, you may download, copy, install, 36 * use, modify and distribute this software in source and/or binary 37 * form. No title or ownership is transferred hereby. 38 * 39 * 1) Any source code used, modified or distributed must reproduce 40 * and retain this copyright notice and list of conditions as 41 * they appear in the source file. 42 * 43 * 2) No right is granted to use any trade name, trademark, or logo of 44 * Digital Equipment Corporation. Neither the "Digital Equipment 45 * Corporation" name nor any trademark or logo of Digital Equipment 46 * Corporation may be used to endorse or promote products derived 47 * from this software without the prior written permission of 48 * Digital Equipment Corporation. 49 * 50 * 3) This software is provided "AS-IS" and any express or implied 51 * warranties, including but not limited to, any implied warranties 52 * of merchantability, fitness for a particular purpose, or 53 * non-infringement are disclaimed. In no event shall DIGITAL be 54 * liable for any damages whatsoever, and in particular, DIGITAL 55 * shall not be liable for special, indirect, consequential, or 56 * incidental damages or damages for lost profits, loss of 57 * revenue or loss of use, whether such damages arise in contract, 58 * negligence, tort, under statute, in equity, at law or otherwise, 59 * even if advised of the possibility of such damage. 60 */ 61 62 /* 63 **++ 64 ** FACILITY 65 ** 66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 67 ** 68 ** ABSTRACT 69 ** 70 ** This module provides standard ethernet access for INET protocols 71 ** only. 72 ** 73 ** AUTHORS 74 ** 75 ** Peter Dettori SEA - Software Engineering. 76 ** 77 ** CREATION DATE: 78 ** 79 ** 13-Feb-1997. 80 ** 81 ** MODIFICATION HISTORY (Digital): 82 ** 83 ** Revision 1.27 1998/01/20 17:59:40 cgd 84 ** update for moved headers 85 ** 86 ** Revision 1.26 1998/01/12 19:29:36 cgd 87 ** use arm32/isa versions of isadma code. 88 ** 89 ** Revision 1.25 1997/12/12 01:35:27 cgd 90 ** convert to use new arp code (from Brini) 91 ** 92 ** Revision 1.24 1997/12/10 22:31:56 cgd 93 ** trim some fat (get rid of ability to explicitly supply enet addr, since 94 ** it was never used and added a bunch of code which really doesn't belong in 95 ** an enet driver), and clean up slightly. 96 ** 97 ** Revision 1.23 1997/10/06 16:42:12 cgd 98 ** copyright notices 99 ** 100 ** Revision 1.22 1997/06/20 19:38:01 chaiken 101 ** fixes some smartcard problems 102 ** 103 ** Revision 1.21 1997/06/10 02:56:20 grohn 104 ** Added call to ledNetActive 105 ** 106 ** Revision 1.20 1997/06/05 00:47:06 dettori 107 ** Changed cs_process_rx_dma to reset and re-initialise the 108 ** ethernet chip when DMA gets out of sync, or mbufs 109 ** can't be allocated. 110 ** 111 ** Revision 1.19 1997/06/03 03:09:58 dettori 112 ** Turn off sc_txbusy flag when a transmit underrun 113 ** occurs. 114 ** 115 ** Revision 1.18 1997/06/02 00:04:35 dettori 116 ** redefined the transmit table to get around the nfs_timer bug while we are 117 ** looking into it further. 118 ** 119 ** Also changed interrupts from EDGE to LEVEL. 120 ** 121 ** Revision 1.17 1997/05/27 23:31:01 dettori 122 ** Pulled out changes to DMAMODE defines. 123 ** 124 ** Revision 1.16 1997/05/23 04:25:16 cgd 125 ** reformat log so it fits in 80cols 126 ** 127 ** Revision 1.15 1997/05/23 04:22:18 cgd 128 ** remove the existing copyright notice (which Peter Dettori indicated 129 ** was incorrect, copied from an existing NetBSD file only so that the 130 ** file would have a copyright notice on it, and which he'd intended to 131 ** replace). Replace it with a Digital copyright notice, cloned from 132 ** ess.c. It's not really correct either (it indicates that the source 133 ** is Digital confidential!), but is better than nothing and more 134 ** correct than what was there before. 135 ** 136 ** Revision 1.14 1997/05/23 04:12:50 cgd 137 ** use an adaptive transmit start algorithm: start by telling the chip 138 ** to start transmitting after 381 bytes have been fed to it. if that 139 ** gets transmit underruns, ramp down to 1021 bytes then "whole 140 ** packet." If successful at a given level for a while, try the next 141 ** more agressive level. This code doesn't ever try to start 142 ** transmitting after 5 bytes have been sent to the NIC, because 143 ** that underruns rather regularly. The back-off and ramp-up mechanism 144 ** could probably be tuned a little bit, but this works well enough to 145 ** support > 1MB/s transmit rates on a clear ethernet (which is about 146 ** 20-25% better than the driver had previously been getting). 147 ** 148 ** Revision 1.13 1997/05/22 21:06:54 cgd 149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 150 ** casting from uint8_t * to uint16_t * without worrying about alignment 151 ** issues. This would cause bogus data to be spit out for mbufs with 152 ** misaligned data. For instance, it caused the following bits to appear 153 ** on the wire: 154 ** ... etBND 1S2C .SHA(K) R ... 155 ** 11112222333344445555 156 ** which should have appeared as: 157 ** ... NetBSD 1.2C (SHARK) ... 158 ** 11112222333344445555 159 ** Note the apparent 'rotate' of the bytes in the word, which was due to 160 ** incorrect unaligned accesses. This data corruption was the cause of 161 ** incoming telnet/rlogin hangs. 162 ** 163 ** Revision 1.12 1997/05/22 01:55:32 cgd 164 ** reformat log so it fits in 80cols 165 ** 166 ** Revision 1.11 1997/05/22 01:50:27 cgd 167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 168 ** so packets aimed at other hosts don't get sent to ether_input(). 169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 170 ** you can easily tell (`strings`) what version of the driver is in your 171 ** kernel binary. 172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 173 ** safe, and not really a performance win anyway. (It was only used when 174 ** setting up the multicast logical address filter, which is an 175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 176 ** address check above, but the benefit of it vs. memcmp would be 177 ** inconsequential, there.) Use memcmp() instead. 178 ** * restructure csStartOuput to avoid the following bugs in the case where 179 ** txWait was being set: 180 ** * it would accidentally drop the outgoing packet if told to wait 181 ** but the outgoing packet queue was empty. 182 ** * it would bpf_mtap() the outgoing packet multiple times (once for 183 ** each time it was told to wait), and would also recalculate 184 ** the length of the outgoing packet each time it was told to 185 ** wait. 186 ** While there, rename txWait to txLoop, since with the new structure of 187 ** the code, the latter name makes more sense. 188 ** 189 ** Revision 1.10 1997/05/19 02:03:20 cgd 190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 194 ** as before. 195 ** 196 ** Revision 1.9 1997/05/19 01:45:37 cgd 197 ** create a new function, cs_ether_input(), which does received-packet 198 ** BPF and ether_input processing. This code used to be in three places, 199 ** and centralizing it will make adding IFF_PROMISC support much easier. 200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 201 ** do copies with bus_space_write_region_2(). It's more correct, and 202 ** potentially more efficient. That function needs to be gutted (to 203 ** deal properly with alignment issues, which it currently does wrong), 204 ** however, and the change doesn't gain much, so there's no point in 205 ** enabling it now. 206 ** 207 ** Revision 1.8 1997/05/19 01:17:10 cgd 208 ** fix a comment re: the setting of the TxConfig register. Clean up 209 ** interface counter maintenance (make it use standard idiom). 210 ** 211 **-- 212 */ 213 214 #include <sys/cdefs.h> 215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.43 2019/04/25 10:08:45 msaitoh Exp $"); 216 217 #include "opt_inet.h" 218 219 #include <sys/param.h> 220 #include <sys/systm.h> 221 #include <sys/mbuf.h> 222 #include <sys/syslog.h> 223 #include <sys/socket.h> 224 #include <sys/device.h> 225 #include <sys/malloc.h> 226 #include <sys/ioctl.h> 227 #include <sys/errno.h> 228 229 #include <sys/rndsource.h> 230 231 #include <net/if.h> 232 #include <net/if_ether.h> 233 #include <net/if_media.h> 234 #include <net/bpf.h> 235 236 #ifdef INET 237 #include <netinet/in.h> 238 #include <netinet/if_inarp.h> 239 #endif 240 241 #include <sys/bus.h> 242 #include <sys/intr.h> 243 244 #include <dev/ic/cs89x0reg.h> 245 #include <dev/ic/cs89x0var.h> 246 247 #ifdef SHARK 248 #include <shark/shark/sequoia.h> 249 #endif 250 251 /* 252 * MACRO DEFINITIONS 253 */ 254 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 255 256 /* 257 * FUNCTION PROTOTYPES 258 */ 259 static void cs_get_default_media(struct cs_softc *); 260 static int cs_get_params(struct cs_softc *); 261 static int cs_get_enaddr(struct cs_softc *); 262 static int cs_reset_chip(struct cs_softc *); 263 static void cs_reset(struct cs_softc *); 264 static int cs_ioctl(struct ifnet *, u_long, void *); 265 static void cs_initChip(struct cs_softc *); 266 static void cs_buffer_event(struct cs_softc *, uint16_t); 267 static void cs_transmit_event(struct cs_softc *, uint16_t); 268 static void cs_receive_event(struct cs_softc *, uint16_t); 269 static void cs_process_receive(struct cs_softc *); 270 static void cs_process_rx_early(struct cs_softc *); 271 static void cs_start_output(struct ifnet *); 272 static void cs_copy_tx_frame(struct cs_softc *, struct mbuf *); 273 static void cs_set_ladr_filt(struct cs_softc *, struct ethercom *); 274 static uint16_t cs_hash_index(char *); 275 static void cs_counter_event(struct cs_softc *, uint16_t); 276 277 static int cs_mediachange(struct ifnet *); 278 static void cs_mediastatus(struct ifnet *, struct ifmediareq *); 279 280 static bool cs_shutdown(device_t, int); 281 static int cs_enable(struct cs_softc *); 282 static void cs_disable(struct cs_softc *); 283 static void cs_stop(struct ifnet *, int); 284 static int cs_scan_eeprom(struct cs_softc *); 285 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, uint16_t *); 286 287 288 /* 289 * GLOBAL DECLARATIONS 290 */ 291 292 /* 293 * Xmit-early table. 294 * 295 * To get better performance, we tell the chip to start packet 296 * transmission before the whole packet is copied to the chip. 297 * However, this can fail under load. When it fails, we back off 298 * to a safer setting for a little while. 299 * 300 * txcmd is the value of txcmd used to indicate when to start transmission. 301 * better is the next 'better' state in the table. 302 * better_count is the number of output packets before transition to the 303 * better state. 304 * worse is the next 'worse' state in the table. 305 * 306 * Transition to the next worse state happens automatically when a 307 * transmittion underrun occurs. 308 */ 309 struct cs_xmit_early { 310 uint16_t txcmd; 311 int better; 312 int better_count; 313 int worse; 314 } cs_xmit_early_table[3] = { 315 { TX_CMD_START_381, 0, INT_MAX, 1, }, 316 { TX_CMD_START_1021, 0, 50000, 2, }, 317 { TX_CMD_START_ALL, 1, 5000, 2, }, 318 }; 319 320 int cs_default_media[] = { 321 IFM_ETHER | IFM_10_2, 322 IFM_ETHER | IFM_10_5, 323 IFM_ETHER | IFM_10_T, 324 IFM_ETHER | IFM_10_T | IFM_FDX, 325 }; 326 int cs_default_nmedia = __arraycount(cs_default_media); 327 328 int 329 cs_attach(struct cs_softc *sc, uint8_t *enaddr, int *media, 330 int nmedia, int defmedia) 331 { 332 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 333 const char *chipname, *medname; 334 uint16_t reg; 335 int i; 336 337 /* Start out in IO mode */ 338 sc->sc_memorymode = FALSE; 339 340 /* Make sure we're right */ 341 for (i = 0; i < 10000; i++) { 342 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 343 if (reg == EISA_NUM_CRYSTAL) 344 break; 345 } 346 if (i == 10000) { 347 aprint_error_dev(sc->sc_dev, "wrong id(0x%x)\n", reg); 348 return 1; /* XXX should panic? */ 349 } 350 351 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 352 sc->sc_prodid = reg & PROD_ID_MASK; 353 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 354 355 switch (sc->sc_prodid) { 356 case PROD_ID_CS8900: 357 chipname = "CS8900"; 358 break; 359 case PROD_ID_CS8920: 360 chipname = "CS8920"; 361 break; 362 case PROD_ID_CS8920M: 363 chipname = "CS8920M"; 364 break; 365 default: 366 panic("cs_attach: impossible"); 367 } 368 369 /* 370 * The first thing to do is check that the mbuf cluster size is 371 * greater than the MTU for an ethernet frame. The code depends on 372 * this and to port this to a OS where this was not the case would 373 * not be straightforward. 374 * 375 * We need 1 byte spare because our packet read loop can overrun. 376 * and we may need pad bytes to align ip header. 377 */ 378 if (MCLBYTES < ETHER_MAX_LEN + 1 + ALIGN(sizeof(struct ether_header)) 379 - sizeof(struct ether_header)) { 380 printf("%s: MCLBYTES too small for Ethernet frame\n", 381 device_xname(sc->sc_dev)); 382 return 1; 383 } 384 385 /* Start out not transmitting */ 386 sc->sc_txbusy = FALSE; 387 388 /* Set up early transmit threshhold */ 389 sc->sc_xe_ent = 0; 390 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 391 392 /* Initialize ifnet structure. */ 393 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 394 ifp->if_softc = sc; 395 ifp->if_start = cs_start_output; 396 ifp->if_init = cs_init; 397 ifp->if_ioctl = cs_ioctl; 398 ifp->if_stop = cs_stop; 399 ifp->if_watchdog = NULL; /* No watchdog at this stage */ 400 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 401 IFQ_SET_READY(&ifp->if_snd); 402 403 /* Initialize ifmedia structures. */ 404 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 405 406 if (media != NULL) { 407 for (i = 0; i < nmedia; i++) 408 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 409 ifmedia_set(&sc->sc_media, defmedia); 410 } else { 411 for (i = 0; i < cs_default_nmedia; i++) 412 ifmedia_add(&sc->sc_media, cs_default_media[i], 413 0, NULL); 414 cs_get_default_media(sc); 415 } 416 417 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 418 if (cs_scan_eeprom(sc) == CS_ERROR) { 419 /* 420 * Failed to scan the eeprom, pretend there isn't an 421 * eeprom 422 */ 423 aprint_error_dev(sc->sc_dev, 424 "unable to scan EEPROM\n"); 425 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM; 426 } 427 } 428 429 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 430 /* Get parameters from the EEPROM */ 431 if (cs_get_params(sc) == CS_ERROR) { 432 aprint_error_dev(sc->sc_dev, 433 "unable to get settings from EEPROM\n"); 434 return 1; 435 } 436 } 437 438 if (enaddr != NULL) 439 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 440 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 441 /* Get and store the Ethernet address */ 442 if (cs_get_enaddr(sc) == CS_ERROR) { 443 aprint_error_dev(sc->sc_dev, 444 "unable to read Ethernet address\n"); 445 return 1; 446 } 447 } else { 448 #if 1 449 int j; 450 uint v; 451 452 for (j = 0; j < 6; j += 2) { 453 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j); 454 sc->sc_enaddr[j + 0] = v; 455 sc->sc_enaddr[j + 1] = v >> 8; 456 } 457 #else 458 printf("%s: no Ethernet address!\n", device_xname(sc->sc_dev)); 459 return 1; 460 #endif 461 } 462 463 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 464 case IFM_10_2: 465 medname = "BNC"; 466 break; 467 case IFM_10_5: 468 medname = "AUI"; 469 break; 470 case IFM_10_T: 471 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 472 medname = "UTP <full-duplex>"; 473 else 474 medname = "UTP"; 475 break; 476 default: 477 panic("cs_attach: impossible"); 478 } 479 printf("%s: %s rev. %c, address %s, media %s\n", 480 device_xname(sc->sc_dev), 481 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 482 medname); 483 484 if (sc->sc_dma_attach) 485 (*sc->sc_dma_attach)(sc); 486 487 /* Attach the interface. */ 488 if_attach(ifp); 489 if_deferred_start_init(ifp, NULL); 490 ether_ifattach(ifp, sc->sc_enaddr); 491 492 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 493 RND_TYPE_NET, RND_FLAG_DEFAULT); 494 sc->sc_cfgflags |= CFGFLG_ATTACHED; 495 496 if (pmf_device_register1(sc->sc_dev, NULL, NULL, cs_shutdown)) 497 pmf_class_network_register(sc->sc_dev, ifp); 498 else 499 aprint_error_dev(sc->sc_dev, 500 "couldn't establish power handler\n"); 501 502 /* Reset the chip */ 503 if (cs_reset_chip(sc) == CS_ERROR) { 504 aprint_error_dev(sc->sc_dev, "reset failed\n"); 505 cs_detach(sc); 506 return 1; 507 } 508 509 return 0; 510 } 511 512 int 513 cs_detach(struct cs_softc *sc) 514 { 515 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 516 517 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 518 rnd_detach_source(&sc->rnd_source); 519 ether_ifdetach(ifp); 520 if_detach(ifp); 521 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 522 } 523 524 #if 0 525 /* XXX not necessary */ 526 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 527 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, 528 sc->sc_dmasize); 529 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, 530 sc->sc_dmasize); 531 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 532 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 533 } 534 #endif 535 536 pmf_device_deregister(sc->sc_dev); 537 538 return 0; 539 } 540 541 bool 542 cs_shutdown(device_t self, int howto) 543 { 544 struct cs_softc *sc; 545 546 sc = device_private(self); 547 cs_reset(sc); 548 549 return true; 550 } 551 552 void 553 cs_get_default_media(struct cs_softc *sc) 554 { 555 uint16_t adp_cfg, xmit_ctl; 556 557 if (cs_verify_eeprom(sc) == CS_ERROR) { 558 aprint_error_dev(sc->sc_dev, 559 "cs_get_default_media: EEPROM missing or bad\n"); 560 goto fakeit; 561 } 562 563 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) { 564 aprint_error_dev(sc->sc_dev, 565 "unable to read adapter config from EEPROM\n"); 566 goto fakeit; 567 } 568 569 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) { 570 aprint_error_dev(sc->sc_dev, 571 "unable to read transmit control from EEPROM\n"); 572 goto fakeit; 573 } 574 575 switch (adp_cfg & ADPTR_CFG_MEDIA) { 576 case ADPTR_CFG_AUI: 577 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 578 break; 579 case ADPTR_CFG_10BASE2: 580 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 581 break; 582 case ADPTR_CFG_10BASET: 583 default: 584 if (xmit_ctl & XMIT_CTL_FDX) 585 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 586 else 587 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 588 break; 589 } 590 return; 591 592 fakeit: 593 aprint_error_dev(sc->sc_dev, 594 "WARNING: default media setting may be inaccurate\n"); 595 /* XXX Arbitrary... */ 596 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 597 } 598 599 /* 600 * cs_scan_eeprom 601 * 602 * Attempt to take a complete copy of the eeprom into main memory. 603 * this will allow faster parsing of the eeprom data. 604 * 605 * Only tested against a 8920M's eeprom, but the data sheet for the 606 * 8920A indicates that is uses the same layout. 607 */ 608 int 609 cs_scan_eeprom(struct cs_softc *sc) 610 { 611 uint16_t result; 612 int i; 613 int eeprom_size; 614 uint8_t checksum = 0; 615 616 if (cs_verify_eeprom(sc) == CS_ERROR) { 617 aprint_error_dev(sc->sc_dev, 618 "cs_scan_params: EEPROM missing or bad\n"); 619 return CS_ERROR; 620 } 621 622 /* 623 * Read the 0th word from the eeprom, it will tell us the length 624 * and if the eeprom is valid 625 */ 626 cs_read_eeprom(sc, 0, &result); 627 628 /* Check the eeprom signature */ 629 if ((result & 0xE000) != 0xA000) { 630 /* Empty eeprom */ 631 return CS_ERROR; 632 } 633 634 /* 635 * Take the eeprom size (note the read value doesn't include the header 636 * word) 637 */ 638 eeprom_size = (result & 0xff) + 2; 639 640 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK); 641 if (sc->eeprom_data == NULL) { 642 /* No memory, treat this as if there's no eeprom */ 643 return CS_ERROR; 644 } 645 646 sc->eeprom_size = eeprom_size; 647 648 /* Read the eeprom into the buffer, also calculate the checksum */ 649 for (i = 0; i < (eeprom_size >> 1); i++) { 650 cs_read_eeprom(sc, i, &(sc->eeprom_data[i])); 651 checksum += (sc->eeprom_data[i] & 0xff00) >> 8; 652 checksum += (sc->eeprom_data[i] & 0x00ff); 653 } 654 655 /* 656 * Validate checksum calculation, the sum of all the bytes should be 0, 657 * as the high byte of the last word is the 2's complement of the 658 * sum to that point. 659 */ 660 if (checksum != 0) { 661 aprint_error_dev(sc->sc_dev, "eeprom checksum failure\n"); 662 return CS_ERROR; 663 } 664 665 return CS_OK; 666 } 667 668 static int 669 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, uint16_t *pValue) 670 { 671 int x, maxword; 672 673 /* Check that we have eeprom data */ 674 if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2)) 675 return CS_ERROR; 676 677 /* 678 * We only want to read the data words, the last word contains the 679 * checksum 680 */ 681 maxword = (sc->eeprom_size - 2) >> 1; 682 683 /* Start 1 word in, as the first word is the length and signature */ 684 x = 1; 685 686 while ( x < (maxword)) { 687 uint16_t header; 688 int group_size; 689 int offset; 690 int offset_max; 691 692 /* Read in the group header word */ 693 header = sc->eeprom_data[x]; 694 x++; /* Skip group header */ 695 696 /* 697 * Size of group in words is in the top 4 bits, note that it 698 * is one less than the number of words 699 */ 700 group_size = header & 0xF000; 701 702 /* 703 * CS8900 Data sheet says this should be 0x01ff, 704 * but my cs8920 eeprom has higher offsets, 705 * perhaps the 8920 allows higher offsets, otherwise 706 * it's writing to places that it shouldn't 707 */ 708 /* Work out the offsets this group covers */ 709 offset = header & 0x0FFF; 710 offset_max = offset + (group_size << 1); 711 712 /* Check if the pkgpg we're after is in this group */ 713 if ((offset <= pktpg) && (pktpg <= offset_max)) { 714 /* The pkgpg value we want is in here */ 715 int eeprom_location; 716 717 eeprom_location = ((pktpg - offset) >> 1) ; 718 719 *pValue = sc->eeprom_data[x + eeprom_location]; 720 return CS_OK; 721 } else { 722 /* Skip this group (+ 1 for first entry) */ 723 x += group_size + 1; 724 } 725 } 726 727 /* 728 * If we've fallen out here then we don't have a value in the EEPROM 729 * for this pktpg so return an error 730 */ 731 return CS_ERROR; 732 } 733 734 int 735 cs_get_params(struct cs_softc *sc) 736 { 737 uint16_t isaConfig; 738 uint16_t adapterConfig; 739 740 if (cs_verify_eeprom(sc) == CS_ERROR) { 741 aprint_error_dev(sc->sc_dev, 742 "cs_get_params: EEPROM missing or bad\n"); 743 return CS_ERROR; 744 } 745 746 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 747 /* Get ISA configuration from the EEPROM */ 748 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig) 749 == CS_ERROR) { 750 /* 751 * Eeprom doesn't have this value, use data sheet 752 * default 753 */ 754 isaConfig = 0x0017; 755 } 756 757 /* Get adapter configuration from the EEPROM */ 758 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL, 759 &adapterConfig) == CS_ERROR) { 760 /* 761 * Eeprom doesn't have this value, use data sheet 762 * default 763 */ 764 adapterConfig = 0x0015; 765 } 766 767 /* Copy the USE_SA flag */ 768 if (isaConfig & BUS_CTL_USE_SA) 769 sc->sc_cfgflags |= CFGFLG_USE_SA; 770 771 /* Copy the IO Channel Ready flag */ 772 if (isaConfig & BUS_CTL_IOCHRDY) 773 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 774 775 /* Copy the DC/DC Polarity flag */ 776 if (adapterConfig & SELF_CTL_HCB1) 777 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 778 } else { 779 /* Get ISA configuration from the EEPROM */ 780 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR) 781 goto eeprom_bad; 782 783 /* Get adapter configuration from the EEPROM */ 784 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) 785 == CS_ERROR) 786 goto eeprom_bad; 787 788 /* Copy the USE_SA flag */ 789 if (isaConfig & ISA_CFG_USE_SA) 790 sc->sc_cfgflags |= CFGFLG_USE_SA; 791 792 /* Copy the IO Channel Ready flag */ 793 if (isaConfig & ISA_CFG_IOCHRDY) 794 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 795 796 /* Copy the DC/DC Polarity flag */ 797 if (adapterConfig & ADPTR_CFG_DCDC_POL) 798 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 799 } 800 801 return CS_OK; 802 eeprom_bad: 803 aprint_error_dev(sc->sc_dev, 804 "cs_get_params: unable to read from EEPROM\n"); 805 return CS_ERROR; 806 } 807 808 int 809 cs_get_enaddr(struct cs_softc *sc) 810 { 811 uint16_t myea[ETHER_ADDR_LEN / sizeof(uint16_t)]; 812 int i; 813 814 if (cs_verify_eeprom(sc) == CS_ERROR) { 815 aprint_error_dev(sc->sc_dev, 816 "cs_get_enaddr: EEPROM missing or bad\n"); 817 return CS_ERROR; 818 } 819 820 /* Get Ethernet address from the EEPROM */ 821 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 822 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0]) 823 == CS_ERROR) 824 goto eeprom_bad; 825 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1]) 826 == CS_ERROR) 827 goto eeprom_bad; 828 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2]) 829 == CS_ERROR) 830 goto eeprom_bad; 831 } else { 832 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR) 833 goto eeprom_bad; 834 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR) 835 goto eeprom_bad; 836 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR) 837 goto eeprom_bad; 838 } 839 840 for (i = 0; i < __arraycount(myea); i++) { 841 sc->sc_enaddr[i * 2 + 0] = myea[i]; 842 sc->sc_enaddr[i * 2 + 1] = myea[i] >> 8; 843 } 844 845 return CS_OK; 846 847 eeprom_bad: 848 aprint_error_dev(sc->sc_dev, 849 "cs_get_enaddr: unable to read from EEPROM\n"); 850 return CS_ERROR; 851 } 852 853 int 854 cs_reset_chip(struct cs_softc *sc) 855 { 856 int intState; 857 int x; 858 859 /* Disable interrupts at the CPU so reset command is atomic */ 860 intState = splnet(); 861 862 /* 863 * We are now resetting the chip 864 * 865 * A spurious interrupt is generated by the chip when it is reset. This 866 * variable informs the interrupt handler to ignore this interrupt. 867 */ 868 sc->sc_resetting = TRUE; 869 870 /* Issue a reset command to the chip */ 871 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 872 873 /* Re-enable interrupts at the CPU */ 874 splx(intState); 875 876 /* The chip is always in IO mode after a reset */ 877 sc->sc_memorymode = FALSE; 878 879 /* If transmission was in progress, it is not now */ 880 sc->sc_txbusy = FALSE; 881 882 /* 883 * There was a delay(125); here, but it seems uneccesary 125 usec is 884 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 885 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 886 * should be sufficient. 887 */ 888 889 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 890 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 891 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 892 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 893 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 894 895 /* Wait until the EEPROM is not busy */ 896 for (x = 0; x < MAXLOOP; x++) { 897 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 898 break; 899 } 900 901 if (x == MAXLOOP) 902 return CS_ERROR; 903 904 /* Wait until initialization is done */ 905 for (x = 0; x < MAXLOOP; x++) { 906 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 907 break; 908 } 909 910 if (x == MAXLOOP) 911 return CS_ERROR; 912 913 /* Reset is no longer in progress */ 914 sc->sc_resetting = FALSE; 915 916 return CS_OK; 917 } 918 919 int 920 cs_verify_eeprom(struct cs_softc *sc) 921 { 922 uint16_t self_status; 923 924 /* Verify that the EEPROM is present and OK */ 925 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST); 926 if (((self_status & SELF_ST_EEP_PRES) && 927 (self_status & SELF_ST_EEP_OK)) == 0) 928 return CS_ERROR; 929 930 return CS_OK; 931 } 932 933 int 934 cs_read_eeprom(struct cs_softc *sc, int offset, uint16_t *pValue) 935 { 936 int x; 937 938 /* Ensure that the EEPROM is not busy */ 939 for (x = 0; x < MAXLOOP; x++) { 940 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 941 SELF_ST_SI_BUSY)) 942 break; 943 } 944 945 if (x == MAXLOOP) 946 return CS_ERROR; 947 948 /* Issue the command to read the offset within the EEPROM */ 949 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD, 950 offset | EEPROM_CMD_READ); 951 952 /* Wait until the command is completed */ 953 for (x = 0; x < MAXLOOP; x++) { 954 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 955 SELF_ST_SI_BUSY)) 956 break; 957 } 958 959 if (x == MAXLOOP) 960 return CS_ERROR; 961 962 /* Get the EEPROM data from the EEPROM Data register */ 963 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA); 964 965 return CS_OK; 966 } 967 968 void 969 cs_initChip(struct cs_softc *sc) 970 { 971 uint16_t busCtl; 972 uint16_t selfCtl; 973 uint16_t v; 974 uint16_t isaId; 975 int i; 976 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 977 978 /* Disable reception and transmission of frames */ 979 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 980 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 981 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 982 983 /* Disable interrupt at the chip */ 984 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 985 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 986 987 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 988 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 989 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 990 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 991 busCtl & ~BUS_CTL_IOCHRDY); 992 } else { 993 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 994 busCtl | BUS_CTL_IOCHRDY); 995 } 996 997 /* Set the Line Control register to match the media type */ 998 if (media == IFM_10_T) 999 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 1000 else 1001 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 1002 1003 /* 1004 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 1005 * enable the DC/DC converter 1006 */ 1007 selfCtl = SELF_CTL_HC1E; 1008 1009 /* If the media type is 10Base2 */ 1010 if (media == IFM_10_2) { 1011 /* Enable the DC/DC converter if it has a low enable. */ 1012 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 1013 /* 1014 * Set the HCB1 bit, which causes the HC1 pin to go 1015 * low. 1016 */ 1017 selfCtl |= SELF_CTL_HCB1; 1018 } else { /* Media type is 10BaseT or AUI */ 1019 /* Disable the DC/DC converter if it has a high enable. */ 1020 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 1021 /* 1022 * Set the HCB1 bit, which causes the HC1 pin to go 1023 * low. 1024 */ 1025 selfCtl |= SELF_CTL_HCB1; 1026 } 1027 } 1028 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 1029 1030 /* Enable normal link pulse */ 1031 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 1032 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 1033 1034 /* Enable full-duplex, if appropriate */ 1035 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 1036 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 1037 1038 /* RX_CTL set in cs_set_ladr_filt(), below */ 1039 1040 /* Enable all transmission interrupts */ 1041 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 1042 1043 /* Accept all receive interrupts */ 1044 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 1045 1046 /* 1047 * Configure Operational Modes 1048 * 1049 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this 1050 * is a better way to do it because the card has a counter which can be 1051 * read to update the RX_MISS counter. This saves many interrupts. 1052 * 1053 * I have turned on the tx and rx overflow interrupts to counter using 1054 * the receive miss interrupt. This is a better estimate of errors 1055 * and requires lower system overhead. 1056 */ 1057 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 1058 BUF_CFG_RX_DMA_IE); 1059 1060 if (sc->sc_dma_chipinit) 1061 (*sc->sc_dma_chipinit)(sc); 1062 1063 /* If memory mode is enabled */ 1064 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 1065 /* If external logic is present for address decoding */ 1066 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 1067 /* 1068 * Program the external logic to decode address bits 1069 * SA20-SA23 1070 */ 1071 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 1072 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 1073 EEPROM_CMD_ELSEL); 1074 } 1075 1076 /* 1077 * Write the packet page base physical address to the memory 1078 * base register. 1079 */ 1080 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 1081 sc->sc_pktpgaddr & 0xFFFF); 1082 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 1083 sc->sc_pktpgaddr >> 16); 1084 busCtl = BUS_CTL_MEM_MODE; 1085 1086 /* Tell the chip to read the addresses off the SA pins */ 1087 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 1088 busCtl |= BUS_CTL_USE_SA; 1089 } 1090 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1091 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 1092 1093 /* We are in memory mode now! */ 1094 sc->sc_memorymode = TRUE; 1095 1096 /* 1097 * Wait here (10ms) for the chip to swap over. this is the 1098 * maximum time that this could take. 1099 */ 1100 delay(10000); 1101 1102 /* Verify that we can read from the chip */ 1103 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 1104 1105 /* 1106 * As a last minute sanity check before actually using mapped 1107 * memory we verify that we can read the isa number from the 1108 * chip in memory mode. 1109 */ 1110 if (isaId != EISA_NUM_CRYSTAL) { 1111 aprint_error_dev(sc->sc_dev, 1112 "failed to enable memory mode\n"); 1113 sc->sc_memorymode = FALSE; 1114 } else { 1115 /* 1116 * We are in memory mode so if we aren't using DMA, 1117 * then program the chip to interrupt early. 1118 */ 1119 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 1120 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 1121 BUF_CFG_RX_DEST_IE | 1122 BUF_CFG_RX_MISS_OVER_IE | 1123 BUF_CFG_TX_COL_OVER_IE); 1124 } 1125 } 1126 1127 } 1128 1129 /* Put Ethernet address into the Individual Address register */ 1130 for (i = 0; i < 6; i += 2) { 1131 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8; 1132 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v); 1133 } 1134 1135 if (sc->sc_irq != -1) { 1136 /* Set the interrupt level in the chip */ 1137 if (sc->sc_prodid == PROD_ID_CS8900) { 1138 if (sc->sc_irq == 5) 1139 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 1140 else 1141 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 1142 (sc->sc_irq) - 10); 1143 } else { /* CS8920 */ 1144 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, 1145 sc->sc_irq); 1146 } 1147 } 1148 1149 /* Write the multicast mask to the address filter register */ 1150 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1151 1152 /* Enable reception and transmission of frames */ 1153 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 1154 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 1155 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 1156 1157 /* Enable interrupt at the chip */ 1158 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1159 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 1160 } 1161 1162 int 1163 cs_init(struct ifnet *ifp) 1164 { 1165 int intState; 1166 int error = CS_OK; 1167 struct cs_softc *sc = ifp->if_softc; 1168 1169 if (cs_enable(sc)) 1170 goto out; 1171 1172 cs_stop(ifp, 0); 1173 1174 intState = splnet(); 1175 1176 #if 0 1177 /* Mark the interface as down */ 1178 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 1179 #endif 1180 1181 #ifdef CS_DEBUG 1182 /* Enable debugging */ 1183 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 1184 #endif 1185 1186 /* Reset the chip */ 1187 if ((error = cs_reset_chip(sc)) == CS_OK) { 1188 /* Initialize the chip */ 1189 cs_initChip(sc); 1190 1191 /* Mark the interface as running */ 1192 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1193 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1194 sc->sc_ethercom.ec_if.if_timer = 0; 1195 1196 /* Assume we have carrier until we are told otherwise. */ 1197 sc->sc_carrier = 1; 1198 } else 1199 aprint_error_dev(sc->sc_dev, "unable to reset chip\n"); 1200 1201 splx(intState); 1202 out: 1203 if (error == CS_OK) 1204 return 0; 1205 return EIO; 1206 } 1207 1208 void 1209 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec) 1210 { 1211 struct ifnet *ifp = &ec->ec_if; 1212 struct ether_multi *enm; 1213 struct ether_multistep step; 1214 uint16_t af[4]; 1215 uint16_t port, mask, index; 1216 1217 /* 1218 * Set up multicast address filter by passing all multicast addresses 1219 * through a crc generator, and then using the high order 6 bits as an 1220 * index into the 64 bit logical address filter. The high order bit 1221 * selects the word, while the rest of the bits select the bit within 1222 * the word. 1223 */ 1224 if (ifp->if_flags & IFF_PROMISC) { 1225 /* Accept all valid frames. */ 1226 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1227 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1228 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1229 ifp->if_flags |= IFF_ALLMULTI; 1230 return; 1231 } 1232 1233 /* 1234 * Accept frames if a. crc valid, b. individual address match c. 1235 * broadcast address,and d. multicast addresses matched in the hash 1236 * filter 1237 */ 1238 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1239 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1240 1241 1242 /* 1243 * Start off with all multicast flag clear, set it if we need to 1244 * later, otherwise we will leave it. 1245 */ 1246 ifp->if_flags &= ~IFF_ALLMULTI; 1247 af[0] = af[1] = af[2] = af[3] = 0x0000; 1248 1249 /* 1250 * Loop through all the multicast addresses unless we get a range of 1251 * addresses, in which case we will just accept all packets. 1252 * Justification for this is given in the next comment. 1253 */ 1254 ETHER_FIRST_MULTI(step, ec, enm); 1255 while (enm != NULL) { 1256 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1257 sizeof enm->enm_addrlo)) { 1258 /* 1259 * We must listen to a range of multicast addresses. 1260 * For now, just accept all multicasts, rather than 1261 * trying to set only those filter bits needed to match 1262 * the range. (At this time, the only use of address 1263 * ranges is for IP multicast routing, for which the 1264 * range is big enough to require all bits set.) 1265 */ 1266 ifp->if_flags |= IFF_ALLMULTI; 1267 af[0] = af[1] = af[2] = af[3] = 0xffff; 1268 break; 1269 } else { 1270 /* 1271 * We have got an individual address so just set that 1272 * bit. 1273 */ 1274 index = cs_hash_index(enm->enm_addrlo); 1275 1276 /* Set the bit the Logical address filter. */ 1277 port = (uint16_t) (index >> 4); 1278 mask = (uint16_t) (1 << (index & 0xf)); 1279 af[port] |= mask; 1280 1281 ETHER_NEXT_MULTI(step, enm); 1282 } 1283 } 1284 1285 /* Now program the chip with the addresses */ 1286 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1287 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1288 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1289 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1290 return; 1291 } 1292 1293 uint16_t 1294 cs_hash_index(char *addr) 1295 { 1296 uint32_t crc; 1297 uint16_t hash_code; 1298 1299 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1300 1301 hash_code = crc >> 26; 1302 return hash_code; 1303 } 1304 1305 void 1306 cs_reset(struct cs_softc *sc) 1307 { 1308 1309 /* Mark the interface as down */ 1310 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1311 1312 /* Reset the chip */ 1313 cs_reset_chip(sc); 1314 } 1315 1316 int 1317 cs_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1318 { 1319 struct cs_softc *sc = ifp->if_softc; 1320 struct ifreq *ifr = data; 1321 int state; 1322 int result; 1323 1324 state = splnet(); 1325 1326 result = 0; /* Only set if something goes wrong */ 1327 1328 switch (cmd) { 1329 case SIOCGIFMEDIA: 1330 case SIOCSIFMEDIA: 1331 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1332 break; 1333 1334 default: 1335 result = ether_ioctl(ifp, cmd, data); 1336 if (result == ENETRESET) { 1337 if (ifp->if_flags & IFF_RUNNING) { 1338 /* 1339 * Multicast list has changed. Set the 1340 * hardware filter accordingly. 1341 */ 1342 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1343 } 1344 result = 0; 1345 } 1346 break; 1347 } 1348 1349 splx(state); 1350 1351 return result; 1352 } 1353 1354 int 1355 cs_mediachange(struct ifnet *ifp) 1356 { 1357 1358 /* 1359 * Current media is already set up. Just reset the interface 1360 * to let the new value take hold. 1361 */ 1362 cs_init(ifp); 1363 return 0; 1364 } 1365 1366 void 1367 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1368 { 1369 struct cs_softc *sc = ifp->if_softc; 1370 1371 /* The currently selected media is always the active media. */ 1372 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1373 1374 if (ifp->if_flags & IFF_UP) { 1375 /* Interface up, status is valid. */ 1376 ifmr->ifm_status = IFM_AVALID | 1377 (sc->sc_carrier ? IFM_ACTIVE : 0); 1378 } 1379 else ifmr->ifm_status = 0; 1380 } 1381 1382 int 1383 cs_intr(void *arg) 1384 { 1385 struct cs_softc *sc = arg; 1386 uint16_t Event; 1387 uint16_t rndEvent; 1388 1389 /*printf("cs_intr %p\n", sc);*/ 1390 /* Ignore any interrupts that happen while the chip is being reset */ 1391 if (sc->sc_resetting) { 1392 printf("%s: cs_intr: reset in progress\n", 1393 device_xname(sc->sc_dev)); 1394 return 1; 1395 } 1396 1397 /* Read an event from the Interrupt Status Queue */ 1398 if (sc->sc_memorymode) 1399 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1400 else 1401 Event = CS_READ_PORT(sc, PORT_ISQ); 1402 1403 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1404 return 0; /* Not ours */ 1405 1406 rndEvent = Event; 1407 1408 /* Process all the events in the Interrupt Status Queue */ 1409 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1410 /* Dispatch to an event handler based on the register number */ 1411 switch (Event & REG_NUM_MASK) { 1412 case REG_NUM_RX_EVENT: 1413 cs_receive_event(sc, Event); 1414 break; 1415 case REG_NUM_TX_EVENT: 1416 cs_transmit_event(sc, Event); 1417 break; 1418 case REG_NUM_BUF_EVENT: 1419 cs_buffer_event(sc, Event); 1420 break; 1421 case REG_NUM_TX_COL: 1422 case REG_NUM_RX_MISS: 1423 cs_counter_event(sc, Event); 1424 break; 1425 default: 1426 printf("%s: unknown interrupt event 0x%x\n", 1427 device_xname(sc->sc_dev), Event); 1428 break; 1429 } 1430 1431 /* Read another event from the Interrupt Status Queue */ 1432 if (sc->sc_memorymode) 1433 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1434 else 1435 Event = CS_READ_PORT(sc, PORT_ISQ); 1436 } 1437 1438 /* have handled the interrupt */ 1439 rnd_add_uint32(&sc->rnd_source, rndEvent); 1440 return 1; 1441 } 1442 1443 void 1444 cs_counter_event(struct cs_softc *sc, uint16_t cntEvent) 1445 { 1446 struct ifnet *ifp; 1447 uint16_t errorCount; 1448 1449 ifp = &sc->sc_ethercom.ec_if; 1450 1451 switch (cntEvent & REG_NUM_MASK) { 1452 case REG_NUM_TX_COL: 1453 /* The count should be read before an overflow occurs. */ 1454 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1455 /* 1456 * The tramsit event routine always checks the number of 1457 * collisions for any packet so we don't increment any 1458 * counters here, as they should already have been 1459 * considered. 1460 */ 1461 break; 1462 case REG_NUM_RX_MISS: 1463 /* 1464 * the count should be read before an overflow occurs. 1465 */ 1466 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1467 /* 1468 * Increment the input error count, the first 6bits are the 1469 * register id. 1470 */ 1471 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1472 break; 1473 default: 1474 /* do nothing */ 1475 break; 1476 } 1477 } 1478 1479 void 1480 cs_buffer_event(struct cs_softc *sc, uint16_t bufEvent) 1481 { 1482 1483 /* 1484 * Multiple events can be in the buffer event register at one time so 1485 * a standard switch statement will not suffice, here every event 1486 * must be checked. 1487 */ 1488 1489 /* 1490 * If 128 bits have been rxed by the time we get here, the dest event 1491 * will be cleared and 128 event will be set. 1492 */ 1493 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) 1494 cs_process_rx_early(sc); 1495 1496 if (bufEvent & BUF_EVENT_RX_DMA) { 1497 /* Process the receive data */ 1498 if (sc->sc_dma_process_rx) 1499 (*sc->sc_dma_process_rx)(sc); 1500 else 1501 /* Should panic? */ 1502 aprint_error_dev(sc->sc_dev, "unexpected DMA event\n"); 1503 } 1504 1505 if (bufEvent & BUF_EVENT_TX_UNDR) { 1506 #if 0 1507 /* 1508 * This can happen occasionally, and it's not worth worrying 1509 * about. 1510 */ 1511 printf("%s: transmit underrun (%d -> %d)\n", 1512 device_xname(sc->sc_dev), sc->sc_xe_ent, 1513 cs_xmit_early_table[sc->sc_xe_ent].worse); 1514 #endif 1515 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1516 sc->sc_xe_togo = 1517 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1518 1519 /* had an underrun, transmit is finished */ 1520 sc->sc_txbusy = FALSE; 1521 } 1522 1523 if (bufEvent & BUF_EVENT_SW_INT) 1524 printf("%s: software initiated interrupt\n", 1525 device_xname(sc->sc_dev)); 1526 } 1527 1528 void 1529 cs_transmit_event(struct cs_softc *sc, uint16_t txEvent) 1530 { 1531 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1532 1533 /* If there were any errors transmitting this frame */ 1534 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | 1535 TX_EVENT_OUT_WIN | TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1536 /* Increment the output error count */ 1537 ifp->if_oerrors++; 1538 1539 /* Note carrier loss. */ 1540 if (txEvent & TX_EVENT_LOSS_CRS) 1541 sc->sc_carrier = 0; 1542 1543 /* If debugging is enabled then log error messages */ 1544 if (ifp->if_flags & IFF_DEBUG) { 1545 if (txEvent & TX_EVENT_LOSS_CRS) 1546 aprint_error_dev(sc->sc_dev, "lost carrier\n"); 1547 1548 if (txEvent & TX_EVENT_SQE_ERR) 1549 aprint_error_dev(sc->sc_dev, "SQE error\n"); 1550 1551 if (txEvent & TX_EVENT_OUT_WIN) 1552 aprint_error_dev(sc->sc_dev, 1553 "out-of-window collision\n"); 1554 1555 if (txEvent & TX_EVENT_JABBER) 1556 aprint_error_dev(sc->sc_dev, "jabber\n"); 1557 1558 if (txEvent & TX_EVENT_16_COLL) 1559 aprint_error_dev(sc->sc_dev, 1560 "16 collisions\n"); 1561 } 1562 } else { 1563 /* Transmission successful, carrier is up. */ 1564 sc->sc_carrier = 1; 1565 #ifdef SHARK 1566 ledNetActive(); 1567 #endif 1568 } 1569 1570 /* Add the number of collisions for this frame */ 1571 if (txEvent & TX_EVENT_16_COLL) 1572 ifp->if_collisions += 16; 1573 else 1574 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1575 1576 ifp->if_opackets++; 1577 1578 /* Transmission is no longer in progress */ 1579 sc->sc_txbusy = FALSE; 1580 1581 /* If there is more to transmit, start the next transmission */ 1582 if_schedule_deferred_start(ifp); 1583 } 1584 1585 void 1586 cs_print_rx_errors(struct cs_softc *sc, uint16_t rxEvent) 1587 { 1588 1589 if (rxEvent & RX_EVENT_RUNT) 1590 aprint_error_dev(sc->sc_dev, "runt\n"); 1591 1592 if (rxEvent & RX_EVENT_X_DATA) 1593 aprint_error_dev(sc->sc_dev, "extra data\n"); 1594 1595 if (rxEvent & RX_EVENT_CRC_ERR) { 1596 if (rxEvent & RX_EVENT_DRIBBLE) 1597 aprint_error_dev(sc->sc_dev, "alignment error\n"); 1598 else 1599 aprint_error_dev(sc->sc_dev, "CRC error\n"); 1600 } else { 1601 if (rxEvent & RX_EVENT_DRIBBLE) 1602 aprint_error_dev(sc->sc_dev, "dribble bits\n"); 1603 } 1604 } 1605 1606 void 1607 cs_receive_event(struct cs_softc *sc, uint16_t rxEvent) 1608 { 1609 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1610 1611 /* If the frame was not received OK */ 1612 if (!(rxEvent & RX_EVENT_RX_OK)) { 1613 /* Increment the input error count */ 1614 ifp->if_ierrors++; 1615 1616 /* If debugging is enabled then log error messages. */ 1617 if (ifp->if_flags & IFF_DEBUG) { 1618 if (rxEvent != REG_NUM_RX_EVENT) { 1619 cs_print_rx_errors(sc, rxEvent); 1620 1621 /* 1622 * Must read the length of all received 1623 * frames 1624 */ 1625 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1626 1627 /* Skip the received frame */ 1628 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1629 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1630 RX_CFG_SKIP); 1631 } else 1632 aprint_error_dev(sc->sc_dev, "implied skip\n"); 1633 } 1634 } else { 1635 /* 1636 * process the received frame and pass it up to the upper 1637 * layers. 1638 */ 1639 cs_process_receive(sc); 1640 } 1641 } 1642 1643 void 1644 cs_ether_input(struct cs_softc *sc, struct mbuf *m) 1645 { 1646 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1647 1648 /* Pass the packet up. */ 1649 if_percpuq_enqueue(ifp->if_percpuq, m); 1650 } 1651 1652 void 1653 cs_process_receive(struct cs_softc *sc) 1654 { 1655 struct ifnet *ifp; 1656 struct mbuf *m; 1657 int totlen; 1658 uint16_t *pBuff, *pBuffLimit; 1659 int pad; 1660 unsigned int frameOffset = 0; /* XXX: gcc */ 1661 1662 #ifdef SHARK 1663 ledNetActive(); 1664 #endif 1665 1666 ifp = &sc->sc_ethercom.ec_if; 1667 1668 /* Received a packet; carrier is up. */ 1669 sc->sc_carrier = 1; 1670 1671 if (sc->sc_memorymode) { 1672 /* Initialize the frame offset */ 1673 frameOffset = PKTPG_RX_LENGTH; 1674 1675 /* Get the length of the received frame */ 1676 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1677 frameOffset += 2; 1678 } else { 1679 /* Drop status */ 1680 CS_READ_PORT(sc, PORT_RXTX_DATA); 1681 1682 /* Get the length of the received frame */ 1683 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1684 } 1685 1686 if (totlen > ETHER_MAX_LEN) { 1687 aprint_error_dev(sc->sc_dev, "invalid packet length %d\n", 1688 totlen); 1689 1690 /* Skip the received frame */ 1691 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1692 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1693 return; 1694 } 1695 1696 MGETHDR(m, M_DONTWAIT, MT_DATA); 1697 if (m == 0) { 1698 aprint_error_dev(sc->sc_dev, 1699 "cs_process_receive: unable to allocate mbuf\n"); 1700 ifp->if_ierrors++; 1701 /* 1702 * Couldn't allocate an mbuf so things are not good, may as 1703 * well drop the packet I think. 1704 * 1705 * have already read the length so we should be right to skip 1706 * the packet. 1707 */ 1708 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1709 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1710 return; 1711 } 1712 m_set_rcvif(m, ifp); 1713 m->m_pkthdr.len = totlen; 1714 1715 /* Number of bytes to align ip header on word boundary for ipintr */ 1716 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1717 1718 /* 1719 * Alloc mbuf cluster if we need. 1720 * We need 1 byte spare because following packet read loop can overrun. 1721 */ 1722 if (totlen + pad + 1 > MHLEN) { 1723 MCLGET(m, M_DONTWAIT); 1724 if ((m->m_flags & M_EXT) == 0) { 1725 /* Couldn't allocate an mbuf cluster */ 1726 aprint_error_dev(sc->sc_dev, 1727 "cs_process_receive: " 1728 "unable to allocate a cluster\n"); 1729 m_freem(m); 1730 1731 /* Skip the received frame */ 1732 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1733 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) 1734 | RX_CFG_SKIP); 1735 return; 1736 } 1737 } 1738 1739 /* Align ip header on word boundary for ipintr */ 1740 m->m_data += pad; 1741 1742 m->m_len = totlen; 1743 pBuff = mtod(m, uint16_t *); 1744 1745 /* Now read the data from the chip */ 1746 if (sc->sc_memorymode) { 1747 /* don't want to go over */ 1748 pBuffLimit = pBuff + (totlen + 1) / 2; 1749 1750 while (pBuff < pBuffLimit) { 1751 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1752 frameOffset += 2; 1753 } 1754 } else 1755 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1); 1756 1757 cs_ether_input(sc, m); 1758 } 1759 1760 void 1761 cs_process_rx_early(struct cs_softc *sc) 1762 { 1763 struct ifnet *ifp; 1764 struct mbuf *m; 1765 uint16_t frameCount, oldFrameCount; 1766 uint16_t rxEvent; 1767 uint16_t *pBuff; 1768 int pad; 1769 unsigned int frameOffset; 1770 1771 1772 ifp = &sc->sc_ethercom.ec_if; 1773 1774 /* Initialize the frame offset */ 1775 frameOffset = PKTPG_RX_FRAME; 1776 frameCount = 0; 1777 1778 MGETHDR(m, M_DONTWAIT, MT_DATA); 1779 if (m == 0) { 1780 aprint_error_dev(sc->sc_dev, 1781 "cs_process_rx_early: unable to allocate mbuf\n"); 1782 ifp->if_ierrors++; 1783 /* 1784 * Couldn't allocate an mbuf so things are not good, may as 1785 * well drop the packet I think. 1786 * 1787 * have already read the length so we should be right to skip 1788 * the packet. 1789 */ 1790 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1791 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1792 return; 1793 } 1794 m_set_rcvif(m, ifp); 1795 /* 1796 * Save processing by always using a mbuf cluster, guaranteed to fit 1797 * packet 1798 */ 1799 MCLGET(m, M_DONTWAIT); 1800 if ((m->m_flags & M_EXT) == 0) { 1801 /* Couldn't allocate an mbuf cluster */ 1802 aprint_error_dev(sc->sc_dev, 1803 "cs_process_rx_early: unable to allocate a cluster\n"); 1804 m_freem(m); 1805 /* Skip the frame */ 1806 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1807 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1808 return; 1809 } 1810 1811 /* Align ip header on word boundary for ipintr */ 1812 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1813 m->m_data += pad; 1814 1815 /* Set up the buffer pointer to point to the data area */ 1816 pBuff = mtod(m, uint16_t *); 1817 1818 /* 1819 * Now read the frame byte counter until we have finished reading the 1820 * frame 1821 */ 1822 oldFrameCount = 0; 1823 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1824 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1825 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1826 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1827 frameOffset += 2; 1828 } 1829 1830 /* Read the new count from the chip */ 1831 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1832 } 1833 1834 /* Update the mbuf counts */ 1835 m->m_len = oldFrameCount; 1836 m->m_pkthdr.len = oldFrameCount; 1837 1838 /* Now check the Rx Event register */ 1839 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1840 1841 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1842 /* 1843 * Do an implied skip, it seems to be more reliable than a 1844 * forced skip. 1845 */ 1846 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1847 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1848 1849 /* 1850 * Now read the RX_EVENT register to perform an implied skip. 1851 */ 1852 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1853 1854 cs_ether_input(sc, m); 1855 } else { 1856 m_freem(m); 1857 ifp->if_ierrors++; 1858 } 1859 } 1860 1861 void 1862 cs_start_output(struct ifnet *ifp) 1863 { 1864 struct cs_softc *sc; 1865 struct mbuf *pMbuf; 1866 struct mbuf *pMbufChain; 1867 uint16_t BusStatus; 1868 uint16_t Length; 1869 int txLoop = 0; 1870 int dropout = 0; 1871 1872 sc = ifp->if_softc; 1873 1874 /* Check that the interface is up and running */ 1875 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1876 return; 1877 1878 /* Don't interrupt a transmission in progress */ 1879 if (sc->sc_txbusy) 1880 return; 1881 1882 /* This loop will only run through once if transmission is successful */ 1883 /* 1884 * While there are packets to transmit and a transmit is not in 1885 * progress 1886 */ 1887 while (sc->sc_txbusy == 0 && dropout == 0) { 1888 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1889 if (pMbufChain == NULL) 1890 break; 1891 1892 /* 1893 * If BPF is listening on this interface, let it see the packet 1894 * before we commit it to the wire. 1895 */ 1896 bpf_mtap(ifp, pMbufChain, BPF_D_OUT); 1897 1898 /* Find the total length of the data to transmit */ 1899 Length = 0; 1900 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1901 Length += pMbuf->m_len; 1902 1903 do { 1904 /* 1905 * Request that the transmit be started after all 1906 * data has been copied 1907 * 1908 * In IO mode must write to the IO port not the packet 1909 * page address 1910 * 1911 * If this is changed to start transmission after a 1912 * small amount of data has been copied you tend to 1913 * get packet missed errors i think because the ISA 1914 * bus is too slow. Or possibly the copy routine is 1915 * not streamlined enough. 1916 */ 1917 if (sc->sc_memorymode) { 1918 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1919 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1920 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1921 } else { 1922 CS_WRITE_PORT(sc, PORT_TX_CMD, 1923 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1924 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1925 } 1926 1927 /* Adjust early-transmit machinery. */ 1928 if (--sc->sc_xe_togo == 0) { 1929 sc->sc_xe_ent = 1930 cs_xmit_early_table[sc->sc_xe_ent].better; 1931 sc->sc_xe_togo = 1932 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1933 } 1934 /* 1935 * Read the BusStatus register which indicates 1936 * success of the request 1937 */ 1938 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1939 1940 /* 1941 * If there was an error in the transmit bid free the 1942 * mbuf and go on. This is presuming that mbuf is 1943 * corrupt. 1944 */ 1945 if (BusStatus & BUS_ST_TX_BID_ERR) { 1946 aprint_error_dev(sc->sc_dev, 1947 "transmit bid error (too big)"); 1948 1949 /* Discard the bad mbuf chain */ 1950 m_freem(pMbufChain); 1951 sc->sc_ethercom.ec_if.if_oerrors++; 1952 1953 /* Loop up to transmit the next chain */ 1954 txLoop = 0; 1955 } else { 1956 if (BusStatus & BUS_ST_RDY4TXNOW) { 1957 /* 1958 * The chip is ready for transmission 1959 * now 1960 */ 1961 /* 1962 * Copy the frame to the chip to 1963 * start transmission 1964 */ 1965 cs_copy_tx_frame(sc, pMbufChain); 1966 1967 /* Free the mbuf chain */ 1968 m_freem(pMbufChain); 1969 1970 /* Transmission is now in progress */ 1971 sc->sc_txbusy = TRUE; 1972 txLoop = 0; 1973 } else { 1974 /* 1975 * If we get here we want to try 1976 * again with the same mbuf, until 1977 * the chip lets us transmit. 1978 */ 1979 txLoop++; 1980 if (txLoop > CS_OUTPUT_LOOP_MAX) { 1981 /* Free the mbuf chain */ 1982 m_freem(pMbufChain); 1983 /* 1984 * Transmission is not in 1985 * progress 1986 */ 1987 sc->sc_txbusy = FALSE; 1988 /* 1989 * Increment the output error 1990 * count 1991 */ 1992 ifp->if_oerrors++; 1993 /* 1994 * exit the routine and drop 1995 * the packet. 1996 */ 1997 txLoop = 0; 1998 dropout = 1; 1999 } 2000 } 2001 } 2002 } while (txLoop); 2003 } 2004 } 2005 2006 void 2007 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0) 2008 { 2009 struct mbuf *m; 2010 int len, leftover, frameoff; 2011 uint16_t dbuf; 2012 uint8_t *p; 2013 #ifdef DIAGNOSTIC 2014 uint8_t *lim; 2015 #endif 2016 2017 /* Initialize frame pointer and data port address */ 2018 frameoff = PKTPG_TX_FRAME; 2019 2020 /* Start out with no leftover data */ 2021 leftover = 0; 2022 dbuf = 0; 2023 2024 /* Process the chain of mbufs */ 2025 for (m = m0; m != NULL; m = m->m_next) { 2026 /* Process all of the data in a single mbuf. */ 2027 p = mtod(m, uint8_t *); 2028 len = m->m_len; 2029 #ifdef DIAGNOSTIC 2030 lim = p + len; 2031 #endif 2032 2033 while (len > 0) { 2034 if (leftover) { 2035 /* 2036 * Data left over (from mbuf or realignment). 2037 * Buffer the next byte, and write it and 2038 * the leftover data out. 2039 */ 2040 dbuf |= *p++ << 8; 2041 len--; 2042 if (sc->sc_memorymode) { 2043 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2044 frameoff += 2; 2045 } 2046 else { 2047 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2048 } 2049 leftover = 0; 2050 } else if ((long) p & 1) { 2051 /* Misaligned data. Buffer the next byte. */ 2052 dbuf = *p++; 2053 len--; 2054 leftover = 1; 2055 } else { 2056 /* 2057 * Aligned data. This is the case we like. 2058 * 2059 * Write-region out as much as we can, then 2060 * buffer the remaining byte (if any). 2061 */ 2062 leftover = len & 1; 2063 len &= ~1; 2064 if (sc->sc_memorymode) { 2065 MEM_WRITE_REGION_2(sc, frameoff, 2066 (uint16_t *) p, len >> 1); 2067 frameoff += len; 2068 } else 2069 IO_WRITE_MULTI_2(sc, PORT_RXTX_DATA, 2070 (uint16_t *)p, len >> 1); 2071 p += len; 2072 2073 if (leftover) 2074 dbuf = *p++; 2075 len = 0; 2076 } 2077 } 2078 if (len < 0) 2079 panic("cs_copy_tx_frame: negative len"); 2080 #ifdef DIAGNOSTIC 2081 if (p != lim) 2082 panic("cs_copy_tx_frame: p != lim"); 2083 #endif 2084 } 2085 if (leftover) { 2086 if (sc->sc_memorymode) 2087 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2088 else 2089 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2090 } 2091 } 2092 2093 static int 2094 cs_enable(struct cs_softc *sc) 2095 { 2096 2097 if (CS_IS_ENABLED(sc) == 0) { 2098 if (sc->sc_enable != NULL) { 2099 int error; 2100 2101 error = (*sc->sc_enable)(sc); 2102 if (error) 2103 return error; 2104 } 2105 sc->sc_cfgflags |= CFGFLG_ENABLED; 2106 } 2107 2108 return 0; 2109 } 2110 2111 static void 2112 cs_disable(struct cs_softc *sc) 2113 { 2114 2115 if (CS_IS_ENABLED(sc)) { 2116 if (sc->sc_disable != NULL) 2117 (*sc->sc_disable)(sc); 2118 2119 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2120 } 2121 } 2122 2123 static void 2124 cs_stop(struct ifnet *ifp, int disable) 2125 { 2126 struct cs_softc *sc = ifp->if_softc; 2127 2128 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2129 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2130 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2131 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2132 2133 if (disable) 2134 cs_disable(sc); 2135 2136 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2137 } 2138 2139 int 2140 cs_activate(device_t self, enum devact act) 2141 { 2142 struct cs_softc *sc = device_private(self); 2143 2144 switch (act) { 2145 case DVACT_DEACTIVATE: 2146 if_deactivate(&sc->sc_ethercom.ec_if); 2147 return 0; 2148 default: 2149 return EOPNOTSUPP; 2150 } 2151 } 2152
Indexes created Tue Sep 23 02:09:52 GMT 2025