cs89x0.c revision 1.5
1 /* $NetBSD: cs89x0.c,v 1.5 2002/05/14 19:23:45 augustss Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** FACILITY 39 ** 40 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 41 ** 42 ** ABSTRACT 43 ** 44 ** This module provides standard ethernet access for INET protocols 45 ** only. 46 ** 47 ** AUTHORS 48 ** 49 ** Peter Dettori SEA - Software Engineering. 50 ** 51 ** CREATION DATE: 52 ** 53 ** 13-Feb-1997. 54 ** 55 ** MODIFICATION HISTORY (Digital): 56 ** 57 ** Revision 1.27 1998/01/20 17:59:40 cgd 58 ** update for moved headers 59 ** 60 ** Revision 1.26 1998/01/12 19:29:36 cgd 61 ** use arm32/isa versions of isadma code. 62 ** 63 ** Revision 1.25 1997/12/12 01:35:27 cgd 64 ** convert to use new arp code (from Brini) 65 ** 66 ** Revision 1.24 1997/12/10 22:31:56 cgd 67 ** trim some fat (get rid of ability to explicitly supply enet addr, since 68 ** it was never used and added a bunch of code which really doesn't belong in 69 ** an enet driver), and clean up slightly. 70 ** 71 ** Revision 1.23 1997/10/06 16:42:12 cgd 72 ** copyright notices 73 ** 74 ** Revision 1.22 1997/06/20 19:38:01 chaiken 75 ** fixes some smartcard problems 76 ** 77 ** Revision 1.21 1997/06/10 02:56:20 grohn 78 ** Added call to ledNetActive 79 ** 80 ** Revision 1.20 1997/06/05 00:47:06 dettori 81 ** Changed cs_process_rx_dma to reset and re-initialise the 82 ** ethernet chip when DMA gets out of sync, or mbufs 83 ** can't be allocated. 84 ** 85 ** Revision 1.19 1997/06/03 03:09:58 dettori 86 ** Turn off sc_txbusy flag when a transmit underrun 87 ** occurs. 88 ** 89 ** Revision 1.18 1997/06/02 00:04:35 dettori 90 ** redefined the transmit table to get around the nfs_timer bug while we are 91 ** looking into it further. 92 ** 93 ** Also changed interrupts from EDGE to LEVEL. 94 ** 95 ** Revision 1.17 1997/05/27 23:31:01 dettori 96 ** Pulled out changes to DMAMODE defines. 97 ** 98 ** Revision 1.16 1997/05/23 04:25:16 cgd 99 ** reformat log so it fits in 80cols 100 ** 101 ** Revision 1.15 1997/05/23 04:22:18 cgd 102 ** remove the existing copyright notice (which Peter Dettori indicated 103 ** was incorrect, copied from an existing NetBSD file only so that the 104 ** file would have a copyright notice on it, and which he'd intended to 105 ** replace). Replace it with a Digital copyright notice, cloned from 106 ** ess.c. It's not really correct either (it indicates that the source 107 ** is Digital confidential!), but is better than nothing and more 108 ** correct than what was there before. 109 ** 110 ** Revision 1.14 1997/05/23 04:12:50 cgd 111 ** use an adaptive transmit start algorithm: start by telling the chip 112 ** to start transmitting after 381 bytes have been fed to it. if that 113 ** gets transmit underruns, ramp down to 1021 bytes then "whole 114 ** packet." If successful at a given level for a while, try the next 115 ** more agressive level. This code doesn't ever try to start 116 ** transmitting after 5 bytes have been sent to the NIC, because 117 ** that underruns rather regularly. The back-off and ramp-up mechanism 118 ** could probably be tuned a little bit, but this works well enough to 119 ** support > 1MB/s transmit rates on a clear ethernet (which is about 120 ** 20-25% better than the driver had previously been getting). 121 ** 122 ** Revision 1.13 1997/05/22 21:06:54 cgd 123 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 124 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 125 ** issues. This would cause bogus data to be spit out for mbufs with 126 ** misaligned data. For instance, it caused the following bits to appear 127 ** on the wire: 128 ** ... etBND 1S2C .SHA(K) R ... 129 ** 11112222333344445555 130 ** which should have appeared as: 131 ** ... NetBSD 1.2C (SHARK) ... 132 ** 11112222333344445555 133 ** Note the apparent 'rotate' of the bytes in the word, which was due to 134 ** incorrect unaligned accesses. This data corruption was the cause of 135 ** incoming telnet/rlogin hangs. 136 ** 137 ** Revision 1.12 1997/05/22 01:55:32 cgd 138 ** reformat log so it fits in 80cols 139 ** 140 ** Revision 1.11 1997/05/22 01:50:27 cgd 141 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 142 ** so packets aimed at other hosts don't get sent to ether_input(). 143 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 144 ** you can easily tell (`strings`) what version of the driver is in your 145 ** kernel binary. 146 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 147 ** safe, and not really a performance win anyway. (It was only used when 148 ** setting up the multicast logical address filter, which is an 149 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 150 ** address check above, but the benefit of it vs. memcmp would be 151 ** inconsequential, there.) Use memcmp() instead. 152 ** * restructure csStartOuput to avoid the following bugs in the case where 153 ** txWait was being set: 154 ** * it would accidentally drop the outgoing packet if told to wait 155 ** but the outgoing packet queue was empty. 156 ** * it would bpf_mtap() the outgoing packet multiple times (once for 157 ** each time it was told to wait), and would also recalculate 158 ** the length of the outgoing packet each time it was told to 159 ** wait. 160 ** While there, rename txWait to txLoop, since with the new structure of 161 ** the code, the latter name makes more sense. 162 ** 163 ** Revision 1.10 1997/05/19 02:03:20 cgd 164 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 165 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 166 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 167 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 168 ** as before. 169 ** 170 ** Revision 1.9 1997/05/19 01:45:37 cgd 171 ** create a new function, cs_ether_input(), which does received-packet 172 ** BPF and ether_input processing. This code used to be in three places, 173 ** and centralizing it will make adding IFF_PROMISC support much easier. 174 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 175 ** do copies with bus_space_write_region_2(). It's more correct, and 176 ** potentially more efficient. That function needs to be gutted (to 177 ** deal properly with alignment issues, which it currently does wrong), 178 ** however, and the change doesn't gain much, so there's no point in 179 ** enabling it now. 180 ** 181 ** Revision 1.8 1997/05/19 01:17:10 cgd 182 ** fix a comment re: the setting of the TxConfig register. Clean up 183 ** interface counter maintenance (make it use standard idiom). 184 ** 185 **-- 186 */ 187 188 #include <sys/cdefs.h> 189 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.5 2002/05/14 19:23:45 augustss Exp $"); 190 191 #include "opt_inet.h" 192 193 #include <sys/param.h> 194 #include <sys/systm.h> 195 #include <sys/mbuf.h> 196 #include <sys/syslog.h> 197 #include <sys/socket.h> 198 #include <sys/device.h> 199 #include <sys/malloc.h> 200 #include <sys/ioctl.h> 201 #include <sys/errno.h> 202 203 #include "rnd.h" 204 #if NRND > 0 205 #include <sys/rnd.h> 206 #endif 207 208 #include <net/if.h> 209 #include <net/if_ether.h> 210 #include <net/if_media.h> 211 #ifdef INET 212 #include <netinet/in.h> 213 #include <netinet/if_inarp.h> 214 #endif 215 216 #include "bpfilter.h" 217 #if NBPFILTER > 0 218 #include <net/bpf.h> 219 #include <net/bpfdesc.h> 220 #endif 221 222 #include <uvm/uvm_extern.h> 223 224 #include <machine/bus.h> 225 #include <machine/intr.h> 226 227 #include <dev/ic/cs89x0reg.h> 228 #include <dev/ic/cs89x0var.h> 229 230 #ifdef SHARK 231 #include <shark/shark/sequoia.h> 232 #endif 233 234 /* 235 * MACRO DEFINITIONS 236 */ 237 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 238 239 /* 240 * FUNCTION PROTOTYPES 241 */ 242 void cs_get_default_media(struct cs_softc *); 243 int cs_get_params(struct cs_softc *); 244 int cs_get_enaddr(struct cs_softc *); 245 int cs_reset_chip(struct cs_softc *); 246 void cs_reset(void *); 247 int cs_ioctl(struct ifnet *, u_long, caddr_t); 248 void cs_initChip(struct cs_softc *); 249 void cs_buffer_event(struct cs_softc *, u_int16_t); 250 void cs_transmit_event(struct cs_softc *, u_int16_t); 251 void cs_receive_event(struct cs_softc *, u_int16_t); 252 void cs_process_receive(struct cs_softc *); 253 void cs_process_rx_early(struct cs_softc *); 254 void cs_start_output(struct ifnet *); 255 void cs_copy_tx_frame(struct cs_softc *, struct mbuf *); 256 void cs_set_ladr_filt(struct cs_softc *, struct ethercom *); 257 u_int16_t cs_hash_index(char *); 258 void cs_counter_event(struct cs_softc *, u_int16_t); 259 260 int cs_mediachange(struct ifnet *); 261 void cs_mediastatus(struct ifnet *, struct ifmediareq *); 262 263 static int cs_enable(struct cs_softc *); 264 static void cs_disable(struct cs_softc *); 265 static void cs_stop(struct ifnet *, int); 266 static void cs_power(int, void *); 267 268 /* 269 * GLOBAL DECLARATIONS 270 */ 271 272 /* 273 * Xmit-early table. 274 * 275 * To get better performance, we tell the chip to start packet 276 * transmission before the whole packet is copied to the chip. 277 * However, this can fail under load. When it fails, we back off 278 * to a safer setting for a little while. 279 * 280 * txcmd is the value of txcmd used to indicate when to start transmission. 281 * better is the next 'better' state in the table. 282 * better_count is the number of output packets before transition to the 283 * better state. 284 * worse is the next 'worse' state in the table. 285 * 286 * Transition to the next worse state happens automatically when a 287 * transmittion underrun occurs. 288 */ 289 struct cs_xmit_early { 290 u_int16_t txcmd; 291 int better; 292 int better_count; 293 int worse; 294 } cs_xmit_early_table[3] = { 295 { TX_CMD_START_381, 0, INT_MAX, 1, }, 296 { TX_CMD_START_1021, 0, 50000, 2, }, 297 { TX_CMD_START_ALL, 1, 5000, 2, }, 298 }; 299 300 int cs_default_media[] = { 301 IFM_ETHER|IFM_10_2, 302 IFM_ETHER|IFM_10_5, 303 IFM_ETHER|IFM_10_T, 304 IFM_ETHER|IFM_10_T|IFM_FDX, 305 }; 306 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 307 308 int 309 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media, 310 int nmedia, int defmedia) 311 { 312 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 313 const char *chipname, *medname; 314 u_int16_t reg; 315 int i; 316 317 /* Start out in IO mode */ 318 sc->sc_memorymode = FALSE; 319 320 /* make sure we're right */ 321 for (i = 0; i < 10000; i++) { 322 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 323 if (reg == EISA_NUM_CRYSTAL) { 324 break; 325 } 326 } 327 if (i == 10000) { 328 printf("%s: wrong id(0x%x)\n", sc->sc_dev.dv_xname, reg); 329 return 1; /* XXX should panic? */ 330 } 331 332 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 333 sc->sc_prodid = reg & PROD_ID_MASK; 334 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 335 336 switch (sc->sc_prodid) { 337 case PROD_ID_CS8900: 338 chipname = "CS8900"; 339 break; 340 case PROD_ID_CS8920: 341 chipname = "CS8920"; 342 break; 343 case PROD_ID_CS8920M: 344 chipname = "CS8920M"; 345 break; 346 default: 347 panic("cs_attach: impossible"); 348 } 349 350 /* 351 * the first thing to do is check that the mbuf cluster size is 352 * greater than the MTU for an ethernet frame. The code depends on 353 * this and to port this to a OS where this was not the case would 354 * not be straightforward. 355 * 356 * we need 1 byte spare because our 357 * packet read loop can overrun. 358 * and we may need pad bytes to align ip header. 359 */ 360 if (MCLBYTES < ETHER_MAX_LEN + 1 + 361 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 362 printf("%s: MCLBYTES too small for Ethernet frame\n", 363 sc->sc_dev.dv_xname); 364 return 1; 365 } 366 367 /* Start out not transmitting */ 368 sc->sc_txbusy = FALSE; 369 370 /* Set up early transmit threshhold */ 371 sc->sc_xe_ent = 0; 372 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 373 374 /* Initialize ifnet structure. */ 375 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 376 ifp->if_softc = sc; 377 ifp->if_start = cs_start_output; 378 ifp->if_init = cs_init; 379 ifp->if_ioctl = cs_ioctl; 380 ifp->if_stop = cs_stop; 381 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 382 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 383 IFF_BROADCAST | IFF_MULTICAST; 384 IFQ_SET_READY(&ifp->if_snd); 385 386 /* Initialize ifmedia structures. */ 387 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 388 389 if (media != NULL) { 390 for (i = 0; i < nmedia; i++) 391 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 392 ifmedia_set(&sc->sc_media, defmedia); 393 } else { 394 for (i = 0; i < cs_default_nmedia; i++) 395 ifmedia_add(&sc->sc_media, cs_default_media[i], 396 0, NULL); 397 cs_get_default_media(sc); 398 } 399 400 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 401 /* Get parameters from the EEPROM */ 402 if (cs_get_params(sc) == CS_ERROR) { 403 printf("%s: unable to get settings from EEPROM\n", 404 sc->sc_dev.dv_xname); 405 return 1; 406 } 407 } 408 409 if (enaddr != NULL) 410 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 411 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 412 /* Get and store the Ethernet address */ 413 if (cs_get_enaddr(sc) == CS_ERROR) { 414 printf("%s: unable to read Ethernet address\n", 415 sc->sc_dev.dv_xname); 416 return 1; 417 } 418 } else { 419 printf("%s: no Ethernet address!\n", sc->sc_dev.dv_xname); 420 return 1; 421 } 422 423 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 424 case IFM_10_2: 425 medname = "BNC"; 426 break; 427 case IFM_10_5: 428 medname = "AUI"; 429 break; 430 case IFM_10_T: 431 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 432 medname = "UTP <full-duplex>"; 433 else 434 medname = "UTP"; 435 break; 436 default: 437 panic("cs_attach: impossible"); 438 } 439 printf("%s: %s rev. %c, address %s, media %s\n", sc->sc_dev.dv_xname, 440 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 441 medname); 442 443 if (sc->sc_dma_attach) 444 (*sc->sc_dma_attach)(sc); 445 446 sc->sc_sh = shutdownhook_establish(cs_reset, sc); 447 if (sc->sc_sh == NULL) { 448 printf("%s: unable to establish shutdownhook\n", 449 sc->sc_dev.dv_xname); 450 cs_detach(sc); 451 return 1; 452 } 453 454 /* Attach the interface. */ 455 if_attach(ifp); 456 ether_ifattach(ifp, sc->sc_enaddr); 457 458 #if NRND > 0 459 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 460 RND_TYPE_NET, 0); 461 #endif 462 sc->sc_cfgflags |= CFGFLG_ATTACHED; 463 464 /* Reset the chip */ 465 if (cs_reset_chip(sc) == CS_ERROR) { 466 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 467 cs_detach(sc); 468 return 1; 469 } 470 471 sc->sc_powerhook = powerhook_establish(cs_power, sc); 472 if (sc->sc_powerhook == 0) 473 printf("%s: warning: powerhook_establish failed\n", 474 sc->sc_dev.dv_xname); 475 476 return 0; 477 } 478 479 int 480 cs_detach(struct cs_softc *sc) 481 { 482 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 483 484 if (sc->sc_powerhook) { 485 powerhook_disestablish(sc->sc_powerhook); 486 sc->sc_powerhook = 0; 487 } 488 489 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 490 #if NRND > 0 491 rnd_detach_source(&sc->rnd_source); 492 #endif 493 ether_ifdetach(ifp); 494 if_detach(ifp); 495 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 496 } 497 498 if (sc->sc_sh != NULL) 499 shutdownhook_disestablish(sc->sc_sh); 500 501 #if 0 502 /* 503 * XXX not necessary 504 */ 505 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 506 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 507 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 508 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 509 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 510 } 511 #endif 512 513 return 0; 514 } 515 516 void 517 cs_get_default_media(struct cs_softc *sc) 518 { 519 u_int16_t adp_cfg, xmit_ctl; 520 521 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 522 printf("%s: cs_get_default_media: EEPROM missing or bad\n", 523 sc->sc_dev.dv_xname); 524 goto fakeit; 525 } 526 527 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 528 &adp_cfg) == CS_ERROR) { 529 printf("%s: unable to read adapter config from EEPROM\n", 530 sc->sc_dev.dv_xname); 531 goto fakeit; 532 } 533 534 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_XMIT_CTL, 535 &xmit_ctl) == CS_ERROR) { 536 printf("%s: unable to read transmit control from EEPROM\n", 537 sc->sc_dev.dv_xname); 538 goto fakeit; 539 } 540 541 switch (adp_cfg & ADPTR_CFG_MEDIA) { 542 case ADPTR_CFG_AUI: 543 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 544 break; 545 case ADPTR_CFG_10BASE2: 546 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 547 break; 548 case ADPTR_CFG_10BASET: 549 default: 550 if (xmit_ctl & XMIT_CTL_FDX) 551 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 552 else 553 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 554 break; 555 } 556 return; 557 558 fakeit: 559 printf("%s: WARNING: default media setting may be inaccurate\n", 560 sc->sc_dev.dv_xname); 561 /* XXX Arbitrary... */ 562 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 563 } 564 565 int 566 cs_get_params(struct cs_softc *sc) 567 { 568 u_int16_t isaConfig; 569 u_int16_t adapterConfig; 570 571 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 572 printf("%s: cs_get_params: EEPROM missing or bad\n", 573 sc->sc_dev.dv_xname); 574 return (CS_ERROR); 575 } 576 577 /* Get ISA configuration from the EEPROM */ 578 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ISA_CFG, 579 &isaConfig) == CS_ERROR) 580 goto eeprom_bad; 581 582 /* Get adapter configuration from the EEPROM */ 583 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 584 &adapterConfig) == CS_ERROR) 585 goto eeprom_bad; 586 587 /* Copy the USE_SA flag */ 588 if (isaConfig & ISA_CFG_USE_SA) 589 sc->sc_cfgflags |= CFGFLG_USE_SA; 590 591 /* Copy the IO Channel Ready flag */ 592 if (isaConfig & ISA_CFG_IOCHRDY) 593 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 594 595 /* Copy the DC/DC Polarity flag */ 596 if (adapterConfig & ADPTR_CFG_DCDC_POL) 597 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 598 599 return (CS_OK); 600 601 eeprom_bad: 602 printf("%s: cs_get_params: unable to read from EEPROM\n", 603 sc->sc_dev.dv_xname); 604 return (CS_ERROR); 605 } 606 607 int 608 cs_get_enaddr(struct cs_softc *sc) 609 { 610 u_int16_t *myea; 611 612 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 613 printf("%s: cs_get_enaddr: EEPROM missing or bad\n", 614 sc->sc_dev.dv_xname); 615 return (CS_ERROR); 616 } 617 618 myea = (u_int16_t *)sc->sc_enaddr; 619 620 /* Get Ethernet address from the EEPROM */ 621 /* XXX this will likely lose on a big-endian machine. -- cgd */ 622 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_H, 623 &myea[0]) == CS_ERROR) 624 goto eeprom_bad; 625 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_M, 626 &myea[1]) == CS_ERROR) 627 goto eeprom_bad; 628 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_L, 629 &myea[2]) == CS_ERROR) 630 goto eeprom_bad; 631 632 return (CS_OK); 633 634 eeprom_bad: 635 printf("%s: cs_get_enaddr: unable to read from EEPROM\n", 636 sc->sc_dev.dv_xname); 637 return (CS_ERROR); 638 } 639 640 int 641 cs_reset_chip(struct cs_softc *sc) 642 { 643 int intState; 644 int x; 645 646 /* Disable interrupts at the CPU so reset command is atomic */ 647 intState = splnet(); 648 649 /* 650 * We are now resetting the chip 651 * 652 * A spurious interrupt is generated by the chip when it is reset. This 653 * variable informs the interrupt handler to ignore this interrupt. 654 */ 655 sc->sc_resetting = TRUE; 656 657 /* Issue a reset command to the chip */ 658 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 659 660 /* Re-enable interrupts at the CPU */ 661 splx(intState); 662 663 /* The chip is always in IO mode after a reset */ 664 sc->sc_memorymode = FALSE; 665 666 /* If transmission was in progress, it is not now */ 667 sc->sc_txbusy = FALSE; 668 669 /* 670 * there was a delay(125); here, but it seems uneccesary 125 usec is 671 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 672 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 673 * should be sufficient. 674 */ 675 676 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 677 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 678 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 679 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 680 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 681 682 /* Wait until the EEPROM is not busy */ 683 for (x = 0; x < MAXLOOP; x++) { 684 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 685 break; 686 } 687 688 if (x == MAXLOOP) 689 return CS_ERROR; 690 691 /* Wait until initialization is done */ 692 for (x = 0; x < MAXLOOP; x++) { 693 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 694 break; 695 } 696 697 if (x == MAXLOOP) 698 return CS_ERROR; 699 700 /* Reset is no longer in progress */ 701 sc->sc_resetting = FALSE; 702 703 return CS_OK; 704 } 705 706 int 707 cs_verify_eeprom(bus_space_tag_t iot, bus_space_handle_t ioh) 708 { 709 u_int16_t self_status; 710 711 /* Verify that the EEPROM is present and OK */ 712 self_status = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST); 713 if (((self_status & SELF_ST_EEP_PRES) && 714 (self_status & SELF_ST_EEP_OK)) == 0) 715 return (CS_ERROR); 716 717 return (CS_OK); 718 } 719 720 int 721 cs_read_eeprom(bus_space_tag_t iot, bus_space_handle_t ioh, int offset, 722 u_int16_t *pValue) 723 { 724 int x; 725 726 /* Ensure that the EEPROM is not busy */ 727 for (x = 0; x < MAXLOOP; x++) { 728 if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 729 SELF_ST_SI_BUSY)) 730 break; 731 } 732 733 if (x == MAXLOOP) 734 return (CS_ERROR); 735 736 /* Issue the command to read the offset within the EEPROM */ 737 CS_WRITE_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_CMD, 738 offset | EEPROM_CMD_READ); 739 740 /* Wait until the command is completed */ 741 for (x = 0; x < MAXLOOP; x++) { 742 if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 743 SELF_ST_SI_BUSY)) 744 break; 745 } 746 747 if (x == MAXLOOP) 748 return (CS_ERROR); 749 750 /* Get the EEPROM data from the EEPROM Data register */ 751 *pValue = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_DATA); 752 753 return (CS_OK); 754 } 755 756 void 757 cs_initChip(struct cs_softc *sc) 758 { 759 u_int16_t busCtl; 760 u_int16_t selfCtl; 761 u_int16_t *myea; 762 u_int16_t isaId; 763 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 764 765 /* Disable reception and transmission of frames */ 766 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 767 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 768 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 769 770 /* Disable interrupt at the chip */ 771 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 772 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 773 774 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 775 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 776 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 777 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 778 busCtl & ~BUS_CTL_IOCHRDY); 779 } else { 780 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 781 busCtl | BUS_CTL_IOCHRDY); 782 } 783 784 /* Set the Line Control register to match the media type */ 785 if (media == IFM_10_T) 786 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 787 else 788 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 789 790 /* 791 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 792 * enable the DC/DC converter 793 */ 794 selfCtl = SELF_CTL_HC1E; 795 796 /* If the media type is 10Base2 */ 797 if (media == IFM_10_2) { 798 /* 799 * Enable the DC/DC converter if it has a low enable. 800 */ 801 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 802 /* 803 * Set the HCB1 bit, which causes the HC1 pin to go 804 * low. 805 */ 806 selfCtl |= SELF_CTL_HCB1; 807 } else { /* Media type is 10BaseT or AUI */ 808 /* 809 * Disable the DC/DC converter if it has a high enable. 810 */ 811 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 812 /* 813 * Set the HCB1 bit, which causes the HC1 pin to go 814 * low. 815 */ 816 selfCtl |= SELF_CTL_HCB1; 817 } 818 } 819 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 820 821 /* enable normal link pulse */ 822 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 823 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 824 825 /* Enable full-duplex, if appropriate */ 826 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 827 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 828 829 /* RX_CTL set in cs_set_ladr_filt(), below */ 830 831 /* enable all transmission interrupts */ 832 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 833 834 /* Accept all receive interrupts */ 835 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 836 837 /* 838 * Configure Operational Modes 839 * 840 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 841 * a better way to do it because the card has a counter which can be 842 * read to update the RX_MISS counter. This saves many interupts. 843 * 844 * I have turned on the tx and rx overflow interupts to counter using 845 * the receive miss interrupt. This is a better estimate of errors 846 * and requires lower system overhead. 847 */ 848 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 849 BUF_CFG_RX_DMA_IE); 850 851 if (sc->sc_dma_chipinit) 852 (*sc->sc_dma_chipinit)(sc); 853 854 /* If memory mode is enabled */ 855 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 856 /* If external logic is present for address decoding */ 857 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 858 /* 859 * Program the external logic to decode address bits 860 * SA20-SA23 861 */ 862 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 863 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 864 EEPROM_CMD_ELSEL); 865 } 866 867 /* 868 * Write the packet page base physical address to the memory 869 * base register. 870 */ 871 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 872 sc->sc_pktpgaddr & 0xFFFF); 873 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 874 sc->sc_pktpgaddr >> 16); 875 busCtl = BUS_CTL_MEM_MODE; 876 877 /* tell the chip to read the addresses off the SA pins */ 878 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 879 busCtl |= BUS_CTL_USE_SA; 880 } 881 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 882 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 883 884 /* We are in memory mode now! */ 885 sc->sc_memorymode = TRUE; 886 887 /* 888 * wait here (10ms) for the chip to swap over. this is the 889 * maximum time that this could take. 890 */ 891 delay(10000); 892 893 /* Verify that we can read from the chip */ 894 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 895 896 /* 897 * As a last minute sanity check before actually using mapped 898 * memory we verify that we can read the isa number from the 899 * chip in memory mode. 900 */ 901 if (isaId != EISA_NUM_CRYSTAL) { 902 printf("%s: failed to enable memory mode\n", 903 sc->sc_dev.dv_xname); 904 sc->sc_memorymode = FALSE; 905 } else { 906 /* 907 * we are in memory mode so if we aren't using DMA, 908 * then program the chip to interrupt early. 909 */ 910 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 911 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 912 BUF_CFG_RX_DEST_IE | 913 BUF_CFG_RX_MISS_OVER_IE | 914 BUF_CFG_TX_COL_OVER_IE); 915 } 916 } 917 918 } 919 920 /* Put Ethernet address into the Individual Address register */ 921 myea = (u_int16_t *)sc->sc_enaddr; 922 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 0, myea[0]); 923 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 2, myea[1]); 924 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 4, myea[2]); 925 926 if (sc->sc_irq != -1) { 927 /* Set the interrupt level in the chip */ 928 if (sc->sc_prodid == PROD_ID_CS8900) { 929 if (sc->sc_irq == 5) { 930 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 931 } else { 932 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 933 } 934 } 935 else { /* CS8920 */ 936 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 937 } 938 } 939 940 /* write the multicast mask to the address filter register */ 941 cs_set_ladr_filt(sc, &sc->sc_ethercom); 942 943 /* Enable reception and transmission of frames */ 944 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 945 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 946 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 947 948 /* Enable interrupt at the chip */ 949 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 950 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 951 } 952 953 int 954 cs_init(struct ifnet *ifp) 955 { 956 int intState; 957 int error = CS_OK; 958 struct cs_softc *sc = ifp->if_softc; 959 960 if (cs_enable(sc)) 961 goto out; 962 963 cs_stop(ifp, 0); 964 965 intState = splnet(); 966 967 #if 0 968 /* Mark the interface as down */ 969 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 970 #endif 971 972 #ifdef CS_DEBUG 973 /* Enable debugging */ 974 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 975 #endif 976 977 /* Reset the chip */ 978 if ((error = cs_reset_chip(sc)) == CS_OK) { 979 /* Initialize the chip */ 980 cs_initChip(sc); 981 982 /* Mark the interface as running */ 983 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 984 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 985 sc->sc_ethercom.ec_if.if_timer = 0; 986 987 /* Assume we have carrier until we are told otherwise. */ 988 sc->sc_carrier = 1; 989 } else { 990 printf("%s: unable to reset chip\n", sc->sc_dev.dv_xname); 991 } 992 993 splx(intState); 994 out: 995 if (error == CS_OK) 996 return 0; 997 return EIO; 998 } 999 1000 void 1001 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec) 1002 { 1003 struct ifnet *ifp = &ec->ec_if; 1004 struct ether_multi *enm; 1005 struct ether_multistep step; 1006 u_int16_t af[4]; 1007 u_int16_t port, mask, index; 1008 1009 /* 1010 * Set up multicast address filter by passing all multicast addresses 1011 * through a crc generator, and then using the high order 6 bits as an 1012 * index into the 64 bit logical address filter. The high order bit 1013 * selects the word, while the rest of the bits select the bit within 1014 * the word. 1015 */ 1016 if (ifp->if_flags & IFF_PROMISC) { 1017 /* accept all valid frames. */ 1018 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1019 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1020 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1021 ifp->if_flags |= IFF_ALLMULTI; 1022 return; 1023 } 1024 1025 /* 1026 * accept frames if a. crc valid, b. individual address match c. 1027 * broadcast address,and d. multicast addresses matched in the hash 1028 * filter 1029 */ 1030 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1031 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1032 1033 1034 /* 1035 * start off with all multicast flag clear, set it if we need to 1036 * later, otherwise we will leave it. 1037 */ 1038 ifp->if_flags &= ~IFF_ALLMULTI; 1039 af[0] = af[1] = af[2] = af[3] = 0x0000; 1040 1041 /* 1042 * Loop through all the multicast addresses unless we get a range of 1043 * addresses, in which case we will just accept all packets. 1044 * Justification for this is given in the next comment. 1045 */ 1046 ETHER_FIRST_MULTI(step, ec, enm); 1047 while (enm != NULL) { 1048 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1049 sizeof enm->enm_addrlo)) { 1050 /* 1051 * We must listen to a range of multicast addresses. 1052 * For now, just accept all multicasts, rather than 1053 * trying to set only those filter bits needed to match 1054 * the range. (At this time, the only use of address 1055 * ranges is for IP multicast routing, for which the 1056 * range is big enough to require all bits set.) 1057 */ 1058 ifp->if_flags |= IFF_ALLMULTI; 1059 af[0] = af[1] = af[2] = af[3] = 0xffff; 1060 break; 1061 } else { 1062 /* 1063 * we have got an individual address so just set that 1064 * bit. 1065 */ 1066 index = cs_hash_index(enm->enm_addrlo); 1067 1068 /* Set the bit the Logical address filter. */ 1069 port = (u_int16_t) (index >> 4); 1070 mask = (u_int16_t) (1 << (index & 0xf)); 1071 af[port] |= mask; 1072 1073 ETHER_NEXT_MULTI(step, enm); 1074 } 1075 } 1076 1077 /* now program the chip with the addresses */ 1078 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1079 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1080 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1081 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1082 return; 1083 } 1084 1085 u_int16_t 1086 cs_hash_index(char *addr) 1087 { 1088 uint32_t crc; 1089 uint16_t hash_code; 1090 1091 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1092 1093 hash_code = crc >> 26; 1094 return (hash_code); 1095 } 1096 1097 void 1098 cs_reset(void *arg) 1099 { 1100 struct cs_softc *sc = arg; 1101 1102 /* Mark the interface as down */ 1103 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1104 1105 /* Reset the chip */ 1106 cs_reset_chip(sc); 1107 } 1108 1109 int 1110 cs_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1111 { 1112 struct cs_softc *sc = ifp->if_softc; 1113 struct ifreq *ifr = (struct ifreq *) data; 1114 int state; 1115 int result; 1116 1117 state = splnet(); 1118 1119 result = 0; /* only set if something goes wrong */ 1120 1121 switch (cmd) { 1122 case SIOCGIFMEDIA: 1123 case SIOCSIFMEDIA: 1124 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1125 break; 1126 1127 default: 1128 result = ether_ioctl(ifp, cmd, data); 1129 if (result == ENETRESET) { 1130 if (CS_IS_ENABLED(sc)) { 1131 /* 1132 * Multicast list has changed. Set the 1133 * hardware filter accordingly. 1134 */ 1135 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1136 } 1137 result = 0; 1138 } 1139 break; 1140 } 1141 1142 splx(state); 1143 1144 return result; 1145 } 1146 1147 int 1148 cs_mediachange(struct ifnet *ifp) 1149 { 1150 1151 /* 1152 * Current media is already set up. Just reset the interface 1153 * to let the new value take hold. 1154 */ 1155 cs_init(ifp); 1156 return (0); 1157 } 1158 1159 void 1160 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1161 { 1162 struct cs_softc *sc = ifp->if_softc; 1163 1164 /* 1165 * The currently selected media is always the active media. 1166 */ 1167 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1168 1169 if (ifp->if_flags & IFF_UP) { 1170 /* Interface up, status is valid. */ 1171 ifmr->ifm_status = IFM_AVALID | 1172 (sc->sc_carrier ? IFM_ACTIVE : 0); 1173 } 1174 else ifmr->ifm_status = 0; 1175 } 1176 1177 int 1178 cs_intr(void *arg) 1179 { 1180 struct cs_softc *sc = arg; 1181 u_int16_t Event; 1182 #if NRND > 0 1183 u_int16_t rndEvent; 1184 #endif 1185 1186 /* Ignore any interrupts that happen while the chip is being reset */ 1187 if (sc->sc_resetting) { 1188 printf("%s: cs_intr: reset in progress\n", 1189 sc->sc_dev.dv_xname); 1190 return 1; 1191 } 1192 1193 /* Read an event from the Interrupt Status Queue */ 1194 if (sc->sc_memorymode) 1195 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1196 else 1197 Event = CS_READ_PORT(sc, PORT_ISQ); 1198 1199 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1200 return 0; /* not ours */ 1201 1202 #if NRND > 0 1203 rndEvent = Event; 1204 #endif 1205 1206 /* Process all the events in the Interrupt Status Queue */ 1207 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1208 /* Dispatch to an event handler based on the register number */ 1209 switch (Event & REG_NUM_MASK) { 1210 case REG_NUM_RX_EVENT: 1211 cs_receive_event(sc, Event); 1212 break; 1213 case REG_NUM_TX_EVENT: 1214 cs_transmit_event(sc, Event); 1215 break; 1216 case REG_NUM_BUF_EVENT: 1217 cs_buffer_event(sc, Event); 1218 break; 1219 case REG_NUM_TX_COL: 1220 case REG_NUM_RX_MISS: 1221 cs_counter_event(sc, Event); 1222 break; 1223 default: 1224 printf("%s: unknown interrupt event 0x%x\n", 1225 sc->sc_dev.dv_xname, Event); 1226 break; 1227 } 1228 1229 /* Read another event from the Interrupt Status Queue */ 1230 if (sc->sc_memorymode) 1231 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1232 else 1233 Event = CS_READ_PORT(sc, PORT_ISQ); 1234 } 1235 1236 /* have handled the interupt */ 1237 #if NRND > 0 1238 rnd_add_uint32(&sc->rnd_source, rndEvent); 1239 #endif 1240 return 1; 1241 } 1242 1243 void 1244 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent) 1245 { 1246 struct ifnet *ifp; 1247 u_int16_t errorCount; 1248 1249 ifp = &sc->sc_ethercom.ec_if; 1250 1251 switch (cntEvent & REG_NUM_MASK) { 1252 case REG_NUM_TX_COL: 1253 /* 1254 * the count should be read before an overflow occurs. 1255 */ 1256 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1257 /* 1258 * the tramsit event routine always checks the number of 1259 * collisions for any packet so we don't increment any 1260 * counters here, as they should already have been 1261 * considered. 1262 */ 1263 break; 1264 case REG_NUM_RX_MISS: 1265 /* 1266 * the count should be read before an overflow occurs. 1267 */ 1268 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1269 /* 1270 * Increment the input error count, the first 6bits are the 1271 * register id. 1272 */ 1273 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1274 break; 1275 default: 1276 /* do nothing */ 1277 break; 1278 } 1279 } 1280 1281 void 1282 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent) 1283 { 1284 struct ifnet *ifp; 1285 1286 ifp = &sc->sc_ethercom.ec_if; 1287 1288 /* 1289 * multiple events can be in the buffer event register at one time so 1290 * a standard switch statement will not suffice, here every event 1291 * must be checked. 1292 */ 1293 1294 /* 1295 * if 128 bits have been rxed by the time we get here, the dest event 1296 * will be cleared and 128 event will be set. 1297 */ 1298 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1299 cs_process_rx_early(sc); 1300 } 1301 1302 if (bufEvent & BUF_EVENT_RX_DMA) { 1303 /* process the receive data */ 1304 if (sc->sc_dma_process_rx) 1305 (*sc->sc_dma_process_rx)(sc); 1306 else 1307 /* should panic? */ 1308 printf("%s: unexpected dma event\n", sc->sc_dev.dv_xname); 1309 } 1310 1311 if (bufEvent & BUF_EVENT_TX_UNDR) { 1312 #if 0 1313 /* 1314 * This can happen occasionally, and it's not worth worrying 1315 * about. 1316 */ 1317 printf("%s: transmit underrun (%d -> %d)\n", 1318 sc->sc_dev.dv_xname, sc->sc_xe_ent, 1319 cs_xmit_early_table[sc->sc_xe_ent].worse); 1320 #endif 1321 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1322 sc->sc_xe_togo = 1323 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1324 1325 /* had an underrun, transmit is finished */ 1326 sc->sc_txbusy = FALSE; 1327 } 1328 1329 if (bufEvent & BUF_EVENT_SW_INT) { 1330 printf("%s: software initiated interrupt\n", 1331 sc->sc_dev.dv_xname); 1332 } 1333 } 1334 1335 void 1336 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent) 1337 { 1338 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1339 1340 /* If there were any errors transmitting this frame */ 1341 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1342 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1343 /* Increment the output error count */ 1344 ifp->if_oerrors++; 1345 1346 /* Note carrier loss. */ 1347 if (txEvent & TX_EVENT_LOSS_CRS) 1348 sc->sc_carrier = 0; 1349 1350 /* If debugging is enabled then log error messages */ 1351 if (ifp->if_flags & IFF_DEBUG) { 1352 if (txEvent & TX_EVENT_LOSS_CRS) { 1353 printf("%s: lost carrier\n", 1354 sc->sc_dev.dv_xname); 1355 } 1356 if (txEvent & TX_EVENT_SQE_ERR) { 1357 printf("%s: SQE error\n", 1358 sc->sc_dev.dv_xname); 1359 } 1360 if (txEvent & TX_EVENT_OUT_WIN) { 1361 printf("%s: out-of-window collision\n", 1362 sc->sc_dev.dv_xname); 1363 } 1364 if (txEvent & TX_EVENT_JABBER) { 1365 printf("%s: jabber\n", sc->sc_dev.dv_xname); 1366 } 1367 if (txEvent & TX_EVENT_16_COLL) { 1368 printf("%s: 16 collisions\n", 1369 sc->sc_dev.dv_xname); 1370 } 1371 } 1372 } 1373 else { 1374 /* Transmission successful, carrier is up. */ 1375 sc->sc_carrier = 1; 1376 #ifdef SHARK 1377 ledNetActive(); 1378 #endif 1379 } 1380 1381 /* Add the number of collisions for this frame */ 1382 if (txEvent & TX_EVENT_16_COLL) { 1383 ifp->if_collisions += 16; 1384 } else { 1385 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1386 } 1387 1388 ifp->if_opackets++; 1389 1390 /* Transmission is no longer in progress */ 1391 sc->sc_txbusy = FALSE; 1392 1393 /* If there is more to transmit */ 1394 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1395 /* Start the next transmission */ 1396 cs_start_output(ifp); 1397 } 1398 } 1399 1400 void 1401 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent) 1402 { 1403 1404 if (rxEvent & RX_EVENT_RUNT) 1405 printf("%s: runt\n", sc->sc_dev.dv_xname); 1406 1407 if (rxEvent & RX_EVENT_X_DATA) 1408 printf("%s: extra data\n", sc->sc_dev.dv_xname); 1409 1410 if (rxEvent & RX_EVENT_CRC_ERR) { 1411 if (rxEvent & RX_EVENT_DRIBBLE) 1412 printf("%s: alignment error\n", sc->sc_dev.dv_xname); 1413 else 1414 printf("%s: CRC error\n", sc->sc_dev.dv_xname); 1415 } else { 1416 if (rxEvent & RX_EVENT_DRIBBLE) 1417 printf("%s: dribble bits\n", sc->sc_dev.dv_xname); 1418 } 1419 } 1420 1421 void 1422 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent) 1423 { 1424 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1425 1426 /* If the frame was not received OK */ 1427 if (!(rxEvent & RX_EVENT_RX_OK)) { 1428 /* Increment the input error count */ 1429 ifp->if_ierrors++; 1430 1431 /* 1432 * If debugging is enabled then log error messages. 1433 */ 1434 if (ifp->if_flags & IFF_DEBUG) { 1435 if (rxEvent != REG_NUM_RX_EVENT) { 1436 cs_print_rx_errors(sc, rxEvent); 1437 1438 /* 1439 * Must read the length of all received 1440 * frames 1441 */ 1442 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1443 1444 /* Skip the received frame */ 1445 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1446 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1447 RX_CFG_SKIP); 1448 } else { 1449 printf("%s: implied skip\n", 1450 sc->sc_dev.dv_xname); 1451 } 1452 } 1453 } else { 1454 /* 1455 * process the received frame and pass it up to the upper 1456 * layers. 1457 */ 1458 cs_process_receive(sc); 1459 } 1460 } 1461 1462 void 1463 cs_ether_input(struct cs_softc *sc, struct mbuf *m) 1464 { 1465 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1466 1467 ifp->if_ipackets++; 1468 1469 #if NBPFILTER > 0 1470 /* 1471 * Check if there's a BPF listener on this interface. 1472 * If so, hand off the raw packet to BPF. 1473 */ 1474 if (ifp->if_bpf) 1475 bpf_mtap(ifp->if_bpf, m); 1476 #endif 1477 1478 /* Pass the packet up. */ 1479 (*ifp->if_input)(ifp, m); 1480 } 1481 1482 void 1483 cs_process_receive(struct cs_softc *sc) 1484 { 1485 struct ifnet *ifp; 1486 struct mbuf *m; 1487 int totlen; 1488 u_int16_t *pBuff, *pBuffLimit; 1489 int pad; 1490 unsigned int frameOffset; 1491 1492 #ifdef SHARK 1493 ledNetActive(); 1494 #endif 1495 1496 ifp = &sc->sc_ethercom.ec_if; 1497 1498 /* Received a packet; carrier is up. */ 1499 sc->sc_carrier = 1; 1500 1501 if (sc->sc_memorymode) { 1502 /* Initialize the frame offset */ 1503 frameOffset = PKTPG_RX_LENGTH; 1504 1505 /* Get the length of the received frame */ 1506 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1507 frameOffset += 2; 1508 } 1509 else { 1510 /* drop status */ 1511 CS_READ_PORT(sc, PORT_RXTX_DATA); 1512 1513 /* Get the length of the received frame */ 1514 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1515 } 1516 1517 if (totlen > ETHER_MAX_LEN) { 1518 printf("%s: invalid packet length\n", sc->sc_dev.dv_xname); 1519 1520 /* skip the received frame */ 1521 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1522 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1523 return; 1524 } 1525 1526 MGETHDR(m, M_DONTWAIT, MT_DATA); 1527 if (m == 0) { 1528 printf("%s: cs_process_receive: unable to allocate mbuf\n", 1529 sc->sc_dev.dv_xname); 1530 ifp->if_ierrors++; 1531 /* 1532 * couldn't allocate an mbuf so things are not good, may as 1533 * well drop the packet I think. 1534 * 1535 * have already read the length so we should be right to skip 1536 * the packet. 1537 */ 1538 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1539 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1540 return; 1541 } 1542 m->m_pkthdr.rcvif = ifp; 1543 m->m_pkthdr.len = totlen; 1544 1545 /* number of bytes to align ip header on word boundary for ipintr */ 1546 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1547 1548 /* 1549 * alloc mbuf cluster if we need. 1550 * we need 1 byte spare because following 1551 * packet read loop can overrun. 1552 */ 1553 if (totlen + pad + 1 > MHLEN) { 1554 MCLGET(m, M_DONTWAIT); 1555 if ((m->m_flags & M_EXT) == 0) { 1556 /* couldn't allocate an mbuf cluster */ 1557 printf("%s: cs_process_receive: unable to allocate a cluster\n", 1558 sc->sc_dev.dv_xname); 1559 m_freem(m); 1560 1561 /* skip the received frame */ 1562 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1563 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1564 return; 1565 } 1566 } 1567 1568 /* align ip header on word boundary for ipintr */ 1569 m->m_data += pad; 1570 1571 m->m_len = totlen; 1572 pBuff = mtod(m, u_int16_t *); 1573 1574 /* now read the data from the chip */ 1575 if (sc->sc_memorymode) { 1576 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1577 while (pBuff < pBuffLimit) { 1578 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1579 frameOffset += 2; 1580 } 1581 } 1582 else { 1583 bus_space_read_multi_2(sc->sc_iot, sc->sc_ioh, PORT_RXTX_DATA, 1584 pBuff, (totlen + 1)>>1); 1585 } 1586 1587 cs_ether_input(sc, m); 1588 } 1589 1590 void 1591 cs_process_rx_early(struct cs_softc *sc) 1592 { 1593 struct ifnet *ifp; 1594 struct mbuf *m; 1595 u_int16_t frameCount, oldFrameCount; 1596 u_int16_t rxEvent; 1597 u_int16_t *pBuff; 1598 int pad; 1599 unsigned int frameOffset; 1600 1601 1602 ifp = &sc->sc_ethercom.ec_if; 1603 1604 /* Initialize the frame offset */ 1605 frameOffset = PKTPG_RX_FRAME; 1606 frameCount = 0; 1607 1608 MGETHDR(m, M_DONTWAIT, MT_DATA); 1609 if (m == 0) { 1610 printf("%s: cs_process_rx_early: unable to allocate mbuf\n", 1611 sc->sc_dev.dv_xname); 1612 ifp->if_ierrors++; 1613 /* 1614 * couldn't allocate an mbuf so things are not good, may as 1615 * well drop the packet I think. 1616 * 1617 * have already read the length so we should be right to skip 1618 * the packet. 1619 */ 1620 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1621 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1622 return; 1623 } 1624 m->m_pkthdr.rcvif = ifp; 1625 /* 1626 * save processing by always using a mbuf cluster, guarenteed to fit 1627 * packet 1628 */ 1629 MCLGET(m, M_DONTWAIT); 1630 if ((m->m_flags & M_EXT) == 0) { 1631 /* couldn't allocate an mbuf cluster */ 1632 printf("%s: cs_process_rx_early: unable to allocate a cluster\n", 1633 sc->sc_dev.dv_xname); 1634 m_freem(m); 1635 /* skip the frame */ 1636 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1637 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1638 return; 1639 } 1640 1641 /* align ip header on word boundary for ipintr */ 1642 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1643 m->m_data += pad; 1644 1645 /* set up the buffer pointer to point to the data area */ 1646 pBuff = mtod(m, u_int16_t *); 1647 1648 /* 1649 * now read the frame byte counter until we have finished reading the 1650 * frame 1651 */ 1652 oldFrameCount = 0; 1653 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1654 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1655 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1656 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1657 frameOffset += 2; 1658 } 1659 1660 /* read the new count from the chip */ 1661 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1662 } 1663 1664 /* update the mbuf counts */ 1665 m->m_len = oldFrameCount; 1666 m->m_pkthdr.len = oldFrameCount; 1667 1668 /* now check the Rx Event register */ 1669 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1670 1671 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1672 /* 1673 * do an implied skip, it seems to be more reliable than a 1674 * forced skip. 1675 */ 1676 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1677 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1678 1679 /* 1680 * now read the RX_EVENT register to perform an implied skip. 1681 */ 1682 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1683 1684 cs_ether_input(sc, m); 1685 } else { 1686 m_freem(m); 1687 ifp->if_ierrors++; 1688 } 1689 } 1690 1691 void 1692 cs_start_output(struct ifnet *ifp) 1693 { 1694 struct cs_softc *sc; 1695 struct mbuf *pMbuf; 1696 struct mbuf *pMbufChain; 1697 u_int16_t BusStatus; 1698 u_int16_t Length; 1699 int txLoop = 0; 1700 int dropout = 0; 1701 1702 sc = ifp->if_softc; 1703 1704 /* check that the interface is up and running */ 1705 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1706 return; 1707 } 1708 1709 /* Don't interrupt a transmission in progress */ 1710 if (sc->sc_txbusy) { 1711 return; 1712 } 1713 1714 /* this loop will only run through once if transmission is successful */ 1715 /* 1716 * While there are packets to transmit and a transmit is not in 1717 * progress 1718 */ 1719 while (sc->sc_txbusy == 0 && dropout == 0) { 1720 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1721 if (pMbufChain == NULL) 1722 break; 1723 1724 #if NBPFILTER > 0 1725 /* 1726 * If BPF is listening on this interface, let it see the packet 1727 * before we commit it to the wire. 1728 */ 1729 if (ifp->if_bpf) 1730 bpf_mtap(ifp->if_bpf, pMbufChain); 1731 #endif 1732 1733 /* Find the total length of the data to transmit */ 1734 Length = 0; 1735 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1736 Length += pMbuf->m_len; 1737 1738 do { 1739 /* 1740 * Request that the transmit be started after all 1741 * data has been copied 1742 * 1743 * In IO mode must write to the IO port not the packet 1744 * page address 1745 * 1746 * If this is changed to start transmission after a 1747 * small amount of data has been copied you tend to 1748 * get packet missed errors i think because the ISA 1749 * bus is too slow. Or possibly the copy routine is 1750 * not streamlined enough. 1751 */ 1752 if (sc->sc_memorymode) { 1753 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1754 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1755 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1756 } 1757 else { 1758 CS_WRITE_PORT(sc, PORT_TX_CMD, 1759 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1760 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1761 } 1762 1763 /* 1764 * Adjust early-transmit machinery. 1765 */ 1766 if (--sc->sc_xe_togo == 0) { 1767 sc->sc_xe_ent = 1768 cs_xmit_early_table[sc->sc_xe_ent].better; 1769 sc->sc_xe_togo = 1770 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1771 } 1772 /* 1773 * Read the BusStatus register which indicates 1774 * success of the request 1775 */ 1776 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1777 1778 /* 1779 * If there was an error in the transmit bid free the 1780 * mbuf and go on. This is presuming that mbuf is 1781 * corrupt. 1782 */ 1783 if (BusStatus & BUS_ST_TX_BID_ERR) { 1784 printf("%s: transmit bid error (too big)", 1785 sc->sc_dev.dv_xname); 1786 1787 /* Discard the bad mbuf chain */ 1788 m_freem(pMbufChain); 1789 sc->sc_ethercom.ec_if.if_oerrors++; 1790 1791 /* Loop up to transmit the next chain */ 1792 txLoop = 0; 1793 } else { 1794 if (BusStatus & BUS_ST_RDY4TXNOW) { 1795 /* 1796 * The chip is ready for transmission 1797 * now 1798 */ 1799 /* 1800 * Copy the frame to the chip to 1801 * start transmission 1802 */ 1803 cs_copy_tx_frame(sc, pMbufChain); 1804 1805 /* Free the mbuf chain */ 1806 m_freem(pMbufChain); 1807 1808 /* Transmission is now in progress */ 1809 sc->sc_txbusy = TRUE; 1810 txLoop = 0; 1811 } else { 1812 /* 1813 * if we get here we want to try 1814 * again with the same mbuf, until 1815 * the chip lets us transmit. 1816 */ 1817 txLoop++; 1818 if (txLoop > CS_OUTPUT_LOOP_MAX) { 1819 /* Free the mbuf chain */ 1820 m_freem(pMbufChain); 1821 /* 1822 * Transmission is not in 1823 * progress 1824 */ 1825 sc->sc_txbusy = FALSE; 1826 /* 1827 * Increment the output error 1828 * count 1829 */ 1830 ifp->if_oerrors++; 1831 /* 1832 * exit the routine and drop 1833 * the packet. 1834 */ 1835 txLoop = 0; 1836 dropout = 1; 1837 } 1838 } 1839 } 1840 } while (txLoop); 1841 } 1842 } 1843 1844 void 1845 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0) 1846 { 1847 struct mbuf *m; 1848 int len, leftover, frameoff; 1849 u_int16_t dbuf; 1850 u_int8_t *p; 1851 #ifdef DIAGNOSTIC 1852 u_int8_t *lim; 1853 #endif 1854 1855 /* Initialize frame pointer and data port address */ 1856 frameoff = PKTPG_TX_FRAME; 1857 1858 /* start out with no leftover data */ 1859 leftover = 0; 1860 dbuf = 0; 1861 1862 /* Process the chain of mbufs */ 1863 for (m = m0; m != NULL; m = m->m_next) { 1864 /* 1865 * Process all of the data in a single mbuf. 1866 */ 1867 p = mtod(m, u_int8_t *); 1868 len = m->m_len; 1869 #ifdef DIAGNOSTIC 1870 lim = p + len; 1871 #endif 1872 1873 while (len > 0) { 1874 if (leftover) { 1875 /* 1876 * Data left over (from mbuf or realignment). 1877 * Buffer the next byte, and write it and 1878 * the leftover data out. 1879 */ 1880 dbuf |= *p++ << 8; 1881 len--; 1882 if (sc->sc_memorymode) { 1883 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 1884 frameoff += 2; 1885 } 1886 else { 1887 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 1888 } 1889 leftover = 0; 1890 } else if ((long) p & 1) { 1891 /* 1892 * Misaligned data. Buffer the next byte. 1893 */ 1894 dbuf = *p++; 1895 len--; 1896 leftover = 1; 1897 } else { 1898 /* 1899 * Aligned data. This is the case we like. 1900 * 1901 * Write-region out as much as we can, then 1902 * buffer the remaining byte (if any). 1903 */ 1904 leftover = len & 1; 1905 len &= ~1; 1906 if (sc->sc_memorymode) { 1907 bus_space_write_region_2(sc->sc_memt, sc->sc_memh, frameoff, 1908 (u_int16_t *) p, len >> 1); 1909 frameoff += len; 1910 } 1911 else { 1912 bus_space_write_multi_2(sc->sc_iot, sc->sc_ioh, 1913 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 1914 } 1915 p += len; 1916 1917 if (leftover) 1918 dbuf = *p++; 1919 len = 0; 1920 } 1921 } 1922 if (len < 0) 1923 panic("cs_copy_tx_frame: negative len"); 1924 #ifdef DIAGNOSTIC 1925 if (p != lim) 1926 panic("cs_copy_tx_frame: p != lim"); 1927 #endif 1928 } 1929 if (leftover) { 1930 if (sc->sc_memorymode) { 1931 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 1932 } 1933 else { 1934 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 1935 } 1936 } 1937 } 1938 1939 static int 1940 cs_enable(struct cs_softc *sc) 1941 { 1942 1943 if (CS_IS_ENABLED(sc) == 0) { 1944 if (sc->sc_enable != NULL) { 1945 int error; 1946 1947 error = (*sc->sc_enable)(sc); 1948 if (error) 1949 return (error); 1950 } 1951 sc->sc_cfgflags |= CFGFLG_ENABLED; 1952 } 1953 1954 return (0); 1955 } 1956 1957 static void 1958 cs_disable(struct cs_softc *sc) 1959 { 1960 1961 if (CS_IS_ENABLED(sc)) { 1962 if (sc->sc_disable != NULL) 1963 (*sc->sc_disable)(sc); 1964 1965 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 1966 } 1967 } 1968 1969 static void 1970 cs_stop(struct ifnet *ifp, int disable) 1971 { 1972 struct cs_softc *sc = ifp->if_softc; 1973 1974 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 1975 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 1976 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 1977 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 1978 1979 if (disable) { 1980 cs_disable(sc); 1981 } 1982 1983 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1984 } 1985 1986 int 1987 cs_activate(struct device *self, enum devact act) 1988 { 1989 struct cs_softc *sc = (void *)self; 1990 int s, error = 0; 1991 1992 s = splnet(); 1993 switch (act) { 1994 case DVACT_ACTIVATE: 1995 error = EOPNOTSUPP; 1996 break; 1997 1998 case DVACT_DEACTIVATE: 1999 if_deactivate(&sc->sc_ethercom.ec_if); 2000 break; 2001 } 2002 splx(s); 2003 2004 return error; 2005 } 2006 2007 static void 2008 cs_power(int why, void *arg) 2009 { 2010 struct cs_softc *sc = arg; 2011 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2012 int s; 2013 2014 s = splnet(); 2015 switch (why) { 2016 case PWR_STANDBY: 2017 case PWR_SUSPEND: 2018 cs_stop(ifp, 0); 2019 break; 2020 case PWR_RESUME: 2021 if (ifp->if_flags & IFF_UP) { 2022 cs_init(ifp); 2023 } 2024 break; 2025 case PWR_SOFTSUSPEND: 2026 case PWR_SOFTSTANDBY: 2027 case PWR_SOFTRESUME: 2028 break; 2029 } 2030 splx(s); 2031 } 2032
Indexes created Fri Oct 03 02:09:57 GMT 2025