dc21040reg.h revision 1.1
1 /*- 2 * Copyright (c) 1994, 1995 Matt Thomas (thomas (at) lkg.dec.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the author may not be used to endorse or promote products 11 * derived from this software withough specific prior written permission 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * $Id: dc21040reg.h,v 1.1 1995/06/05 00:38:18 cgd Exp $ 25 * 26 * $Log: dc21040reg.h,v $ 27 * Revision 1.1 1995/06/05 00:38:18 cgd 28 * Initial revision 29 * 30 * Revision 1.3 1995/05/05 19:44:34 thomas 31 * cogent em100 support 32 * 33 * Revision 1.1 1994/10/01 20:16:45 wollman 34 * Add Matt Thomas's DC21040 PCI Ethernet driver. (This is turning out 35 * to be quite a popular chip, so expect to see a number of products 36 * based on it.) 37 * 38 * Revision 1.2 1994/08/15 20:42:25 thomas 39 * misc additions 40 * 41 * Revision 1.1 1994/08/12 21:02:46 thomas 42 * Initial revision 43 * 44 * Revision 1.8 1994/08/05 20:20:54 thomas 45 * Enable change log 46 * 47 * Revision 1.7 1994/08/05 20:20:14 thomas 48 * *** empty log message *** 49 * 50 */ 51 52 #if !defined(_DC21040_H) 53 #define _DC21040_H 54 55 typedef signed int tulip_sint32_t; 56 typedef unsigned int tulip_uint32_t; 57 58 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 59 #define TULIP_BITFIELD2(a, b) b, a 60 #define TULIP_BITFIELD3(a, b, c) c, b, a 61 #define TULIP_BITFIELD4(a, b, c, d) d, c, b, a 62 #else 63 #define TULIP_BITFIELD2(a, b) a, b 64 #define TULIP_BITFIELD3(a, b, c) a, b, c 65 #define TULIP_BITFIELD4(a, b, c, d) a, b, c, d 66 #endif 67 68 typedef struct { 69 tulip_uint32_t d_status; 70 tulip_uint32_t TULIP_BITFIELD3(d_length1 : 11, 71 d_length2 : 11, 72 d_flag : 10); 73 tulip_uint32_t d_addr1; 74 tulip_uint32_t d_addr2; 75 } tulip_desc_t; 76 77 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = DC21040) */ 78 #define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */ 79 /* 80 * Transmit Status 81 */ 82 #define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */ 83 #define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */ 84 #define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */ 85 #define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */ 86 #define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */ 87 #define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */ 88 #define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */ 89 #define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */ 90 #define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */ 91 #define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */ 92 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */ 93 /* 94 * Receive Status 95 */ 96 #define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */ 97 #define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */ 98 #define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */ 99 #define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */ 100 #define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */ 101 #define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */ 102 #define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */ 103 #define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */ 104 #define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */ 105 #define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */ 106 #define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */ 107 #define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */ 108 #define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */ 109 110 111 #define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */ 112 #define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */ 113 114 #define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */ 115 #define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */ 116 #define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */ 117 #define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */ 118 #define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */ 119 #define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */ 120 #define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */ 121 #define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */ 122 123 /* 124 * The DC21040 Registers (IO Space Addresses) 125 */ 126 #define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */ 127 #define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */ 128 #define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */ 129 #define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */ 130 #define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */ 131 #define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */ 132 #define TULIP_REG_CMD 0x30 /* CSR6 -- Command */ 133 #define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */ 134 #define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */ 135 #define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */ 136 #define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */ 137 #define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */ 138 #define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */ 139 #define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */ 140 #define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */ 141 #define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */ 142 143 /* 144 * CSR5 -- Status Register 145 * CSR7 -- Interrupt Control 146 */ 147 #define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */ 148 #define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */ 149 #define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */ 150 #define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */ 151 #define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */ 152 #define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */ 153 #define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */ 154 #define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */ 155 #define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */ 156 #define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */ 157 #define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */ 158 #define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an 159 unavailable transmit descriptor */ 160 #define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */ 161 #define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/ 162 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */ 163 #define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */ 164 #define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive 165 packet before prefetch of next descriptor */ 166 #define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */ 167 #define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of 168 unavailable receive buffers */ 169 #define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */ 170 #define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame 171 from the receive FIFO as a result of 172 an unavailable receive buffer */ 173 #define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame 174 from the receive FIFO into the receive 175 buffer. */ 176 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */ 177 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */ 178 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */ 179 #define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (DC21040) */ 180 #define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (DC21040) */ 181 #define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (DC21140) */ 182 #define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (DC21040) */ 183 #define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchbog Timeout */ 184 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */ 185 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */ 186 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */ 187 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */ 188 #define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */ 189 #define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */ 190 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */ 191 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */ 192 193 /* 194 * CSR6 -- Command (Operation Mode) Register 195 */ 196 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (DC21140) */ 197 #define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (DC21140) */ 198 #define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (DC21140) */ 199 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (DC21140) */ 200 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Foward (DC21140) */ 201 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (DC21140) */ 202 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (DC21140) */ 203 #define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */ 204 #define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (DC21040) */ 205 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */ 206 #define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */ 207 #define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */ 208 #define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */ 209 #define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */ 210 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */ 211 #define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */ 212 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */ 213 #define TULIP_CMD_FULLDULPEX 0x00000200L /* (RW) Full Duplex Mode */ 214 #define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */ 215 #define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */ 216 #define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */ 217 #define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */ 218 #define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */ 219 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */ 220 #define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */ 221 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */ 222 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */ 223 224 225 #define TULIP_SIASTS_LINKFAIL 0x00000004L 226 #define TULIP_SIACONN_RESET 0x00000000L 227 228 #define TULIP_SIACONN_AUI 0x0000000DL 229 #define TULIP_SIACONN_10BASET 0x00000005L 230 231 #define TULIP_BUSMODE_SWRESET 0x00000001L 232 #define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL 233 #define TULIP_BUSMODE_BIGENDIAN 0x00000080L 234 #define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L 235 #define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L 236 #define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L 237 #define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L 238 #define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L 239 #define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L 240 #define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L 241 #define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L 242 #define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L 243 #define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L 244 #define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L 245 #define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L 246 #define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L 247 #define TULIP_BUSMODE_TXPOLL_200us 0x00020000L 248 #define TULIP_BUSMODE_TXPOLL_800us 0x00040000L 249 #define TULIP_BUSMODE_TXPOLL_1600us 0x00060000L 250 251 252 /* 253 * These are the defintitions used for the DEC DC21140 254 * evaluation board. 255 */ 256 #define TULIP_GP_EB_PINS 0x0000011F /* General Purpose Pin directions */ 257 #define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 258 #define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 259 #define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */ 260 261 /* 262 * There are the definitions used for the DEC DE500-XA 263 * 10/100 board 264 */ 265 #define TULIP_GP_DE500_PINS 0x0000010FL 266 #define TULIP_GP_DE500_NOTOK_10 0x00000080L 267 #define TULIP_GP_DE500_NOTOK_100 0x00000040L 268 #define TULIP_GP_DE500_HALFDUPLEX 0x00000008L 269 #define TULIP_GP_DE500_FORCE_100 0x00000001L 270 271 /* 272 * These are the defintitions used for the Cogent EM100 273 * DC21140 board. 274 */ 275 #define TULIP_GP_EM100_PINS 0x0000013F /* General Purpose Pin directions */ 276 #define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */ 277 #define TULIP_OUI_COGENT_0 0x00 278 #define TULIP_OUI_COGENT_1 0x00 279 #define TULIP_OUI_COGENT_2 0x94 280 #define TULIP_COGENT_EM100_ID 0x12 281 /* 282 * SROM definitions for the DC21140 and DC21041. 283 */ 284 #define SROMSEL 0x0800 285 #define SROMRD 0x4000 286 #define SROMWR 0x2000 287 #define SROMDIN 0x0008 288 #define SROMDOUT 0x0004 289 #define SROMDOUTON 0x0004 290 #define SROMDOUTOFF 0x0004 291 #define SROMCLKON 0x0002 292 #define SROMCLKOFF 0x0002 293 #define SROMCSON 0x0001 294 #define SROMCSOFF 0x0001 295 #define SROMCS 0x0001 296 297 #define SROMCMD_MODE 4 298 #define SROMCMD_WR 5 299 #define SROMCMD_RD 6 300 301 #define SROM_BITWIDTH 6 302 #endif /* !defined(_DC21040_H) */ 303
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