dc21040reg.h revision 1.1.1.4
1 /*- 2 * Copyright (c) 1994, 1995 Matt Thomas (thomas (at) lkg.dec.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the author may not be used to endorse or promote products 11 * derived from this software withough specific prior written permission 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * $Id: dc21040reg.h,v 1.1.1.4 1995/12/14 20:49:01 tls Exp $ 25 * 26 * $Log: dc21040reg.h,v $ 27 * Revision 1.1.1.4 1995/12/14 20:49:01 tls 28 * 95/12/12 snapshot of Matt Thomas's 'de' driver 29 * 30 * Revision 1.11 1995/10/05 00:15:08 thomas 31 * add dc21140 watchdog timer definitions 32 * 33 * Revision 1.10 1995/09/22 15:04:41 thomas 34 * Fix COGENT OUI 35 * 36 * Revision 1.9 1995/07/26 18:32:13 thomas 37 * Finish DE425 support for BSD/OS. 38 * Cleanup the PCI device ids 39 * misc other small changes 40 * 41 * Revision 1.8 1995/07/24 18:30:12 thomas 42 * More vestigal DE425 support. 43 * Workaround SMC failure to use correct SROM checksum 44 * Change probe slightly. 45 * 46 * Revision 1.7 1995/07/17 23:37:11 thomas 47 * disable auto-negotiation for now on DC21041 48 * 49 * Revision 1.6 1995/07/15 19:22:17 thomas 50 * dc21041 support 51 * 52 * Revision 1.5 1995/07/13 15:40:45 thomas 53 * Minor fixes & prelim support for ZNYX ZX342 54 * 55 * Revision 1.4 1995/07/05 22:40:21 thomas 56 * Add uint16_t 57 * 58 * Revision 1.3 1995/05/05 19:44:34 thomas 59 * cogent em100 support 60 * 61 * Revision 1.1 1994/10/01 20:16:45 wollman 62 * Add Matt Thomas's DC21040 PCI Ethernet driver. (This is turning out 63 * to be quite a popular chip, so expect to see a number of products 64 * based on it.) 65 * 66 * Revision 1.2 1994/08/15 20:42:25 thomas 67 * misc additions 68 * 69 * Revision 1.1 1994/08/12 21:02:46 thomas 70 * Initial revision 71 * 72 * Revision 1.8 1994/08/05 20:20:54 thomas 73 * Enable change log 74 * 75 * Revision 1.7 1994/08/05 20:20:14 thomas 76 * *** empty log message *** 77 * 78 */ 79 80 #if !defined(_DC21040_H) 81 #define _DC21040_H 82 83 typedef unsigned short tulip_uint16_t; 84 typedef unsigned int tulip_uint32_t; 85 86 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 87 #define TULIP_BITFIELD2(a, b) b, a 88 #define TULIP_BITFIELD3(a, b, c) c, b, a 89 #define TULIP_BITFIELD4(a, b, c, d) d, c, b, a 90 #else 91 #define TULIP_BITFIELD2(a, b) a, b 92 #define TULIP_BITFIELD3(a, b, c) a, b, c 93 #define TULIP_BITFIELD4(a, b, c, d) a, b, c, d 94 #endif 95 96 typedef struct { 97 tulip_uint32_t d_status; 98 tulip_uint32_t TULIP_BITFIELD3(d_length1 : 11, 99 d_length2 : 11, 100 d_flag : 10); 101 tulip_uint32_t d_addr1; 102 tulip_uint32_t d_addr2; 103 } tulip_desc_t; 104 105 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = DC21040) */ 106 #define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */ 107 /* 108 * Transmit Status 109 */ 110 #define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */ 111 #define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */ 112 #define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */ 113 #define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */ 114 #define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */ 115 #define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */ 116 #define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */ 117 #define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */ 118 #define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */ 119 #define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */ 120 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */ 121 /* 122 * Receive Status 123 */ 124 #define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */ 125 #define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */ 126 #define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */ 127 #define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */ 128 #define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */ 129 #define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */ 130 #define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */ 131 #define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */ 132 #define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */ 133 #define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */ 134 #define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */ 135 #define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */ 136 #define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */ 137 138 139 #define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */ 140 #define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */ 141 142 #define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */ 143 #define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */ 144 #define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */ 145 #define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */ 146 #define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */ 147 #define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */ 148 #define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */ 149 #define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */ 150 151 /* 152 * The DC21040 Registers (IO Space Addresses) 153 */ 154 #define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */ 155 #define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */ 156 #define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */ 157 #define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */ 158 #define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */ 159 #define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */ 160 #define TULIP_REG_CMD 0x30 /* CSR6 -- Command */ 161 #define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */ 162 #define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */ 163 #define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */ 164 #define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */ 165 #define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */ 166 #define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */ 167 #define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */ 168 #define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */ 169 #define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */ 170 171 /* 172 * CSR5 -- Status Register 173 * CSR7 -- Interrupt Control 174 */ 175 #define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */ 176 #define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */ 177 #define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */ 178 #define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */ 179 #define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */ 180 #define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */ 181 #define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */ 182 #define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */ 183 #define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */ 184 #define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */ 185 #define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */ 186 #define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an 187 unavailable transmit descriptor */ 188 #define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */ 189 #define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/ 190 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */ 191 #define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */ 192 #define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive 193 packet before prefetch of next descriptor */ 194 #define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */ 195 #define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of 196 unavailable receive buffers */ 197 #define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */ 198 #define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame 199 from the receive FIFO as a result of 200 an unavailable receive buffer */ 201 #define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame 202 from the receive FIFO into the receive 203 buffer. */ 204 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */ 205 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */ 206 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */ 207 #define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (DC21040) */ 208 #define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (DC21040) */ 209 #define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (DC21140) */ 210 #define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (DC21040) */ 211 #define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchbog Timeout */ 212 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */ 213 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */ 214 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */ 215 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */ 216 #define TULIP_STS_LINKPASS 0x00000010L /* (RW) LinkPass (DC21041) */ 217 #define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */ 218 #define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */ 219 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */ 220 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */ 221 222 /* 223 * CSR6 -- Command (Operation Mode) Register 224 */ 225 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (DC21140) */ 226 #define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (DC21140) */ 227 #define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (DC21140) */ 228 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (DC21140) */ 229 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Foward (DC21140) */ 230 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (DC21140) */ 231 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (DC21140) */ 232 #define TULIP_CMD_ENHCAPTEFFCT 0x00040000L /* (RW) Enhanced Capture Effecty (DC21041) */ 233 #define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */ 234 #define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (DC21040) */ 235 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */ 236 #define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */ 237 #define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */ 238 #define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */ 239 #define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */ 240 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */ 241 #define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */ 242 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */ 243 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */ 244 #define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */ 245 #define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */ 246 #define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */ 247 #define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */ 248 #define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */ 249 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */ 250 #define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */ 251 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */ 252 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */ 253 254 255 #define TULIP_SIASTS_OTHERRXACTIVITY 0x00000200L 256 #define TULIP_SIASTS_RXACTIVITY 0x00000100L 257 #define TULIP_SIASTS_LINKFAIL 0x00000004L 258 #define TULIP_SIACONN_RESET 0x00000000L 259 260 #define TULIP_SIACONN_AUI 0x0000000DL 261 #define TULIP_SIACONN_10BASET 0x00000005L 262 263 #define TULIP_DC21041_SIACONN_10BASET 0x0000EF01L 264 #define TULIP_DC21041_SIATXRX_10BASET 0x0000FF3FL 265 #define TULIP_DC21041_SIAGEN_10BASET 0x00000000L 266 267 #define TULIP_DC21041_SIACONN_AUI 0x0000EF09L 268 #define TULIP_DC21041_SIATXRX_AUI 0x0000F73DL 269 #define TULIP_DC21041_SIAGEN_AUI 0x0000000EL 270 271 #define TULIP_DC21041_SIACONN_BNC 0x0000EF09L 272 #define TULIP_DC21041_SIATXRX_BNC 0x0000F73DL 273 #define TULIP_DC21041_SIAGEN_BNC 0x00000006L 274 275 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L 276 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L 277 278 #define TULIP_BUSMODE_SWRESET 0x00000001L 279 #define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL 280 #define TULIP_BUSMODE_BIGENDIAN 0x00000080L 281 #define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L 282 #define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L 283 #define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L 284 #define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L 285 #define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L 286 #define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L 287 #define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L 288 #define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L 289 #define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L 290 #define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L 291 #define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L 292 #define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L 293 #define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L 294 #define TULIP_BUSMODE_TXPOLL_200000ns 0x00020000L 295 #define TULIP_BUSMODE_TXPOLL_800000ns 0x00040000L 296 #define TULIP_BUSMODE_TXPOLL_1600000ns 0x00060000L 297 #define TULIP_BUSMODE_TXPOLL_12800ns 0x00080000L /* DC21041 only */ 298 #define TULIP_BUSMODE_TXPOLL_25600ns 0x000A0000L /* DC21041 only */ 299 #define TULIP_BUSMODE_TXPOLL_51200ns 0x000C0000L /* DC21041 only */ 300 #define TULIP_BUSMODE_TXPOLL_102400ns 0x000E0000L /* DC21041 only */ 301 #define TULIP_BUSMODE_DESC_BIGENDIAN 0x00100000L /* DC21041 only */ 302 303 /* 304 * These are the defintitions used for the DEC DC21140 305 * evaluation board. 306 */ 307 #define TULIP_GP_EB_PINS 0x0000011F /* General Purpose Pin directions */ 308 #define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 309 #define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 310 #define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */ 311 312 /* 313 * There are the definitions used for the DEC DE500-XA 314 * 10/100 board 315 */ 316 #define TULIP_GP_DE500_PINS 0x0000010FL 317 #define TULIP_GP_DE500_NOTOK_10 0x00000080L 318 #define TULIP_GP_DE500_NOTOK_100 0x00000040L 319 #define TULIP_GP_DE500_HALFDUPLEX 0x00000008L 320 #define TULIP_GP_DE500_FORCE_100 0x00000001L 321 322 /* 323 * These are the defintitions used for the Cogent EM100 324 * DC21140 board. 325 */ 326 #define TULIP_GP_EM100_PINS 0x0000013F /* General Purpose Pin directions */ 327 #define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */ 328 #define TULIP_OUI_COGENT_0 0x00 329 #define TULIP_OUI_COGENT_1 0x00 330 #define TULIP_OUI_COGENT_2 0x92 331 #define TULIP_COGENT_EM100_ID 0x12 332 333 334 /* 335 * These are the defintitions used for the Znyx ZX342 336 * 10/100 board 337 */ 338 #define TULIP_GP_ZX34X_PINS 0x0000011F /* General Purpose Pin directions */ 339 #define TULIP_GP_ZX34X_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 340 #define TULIP_GP_ZX34X_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 341 #define TULIP_GP_ZX34X_INIT 0x00000009 342 #define TULIP_OUI_ZNYX_0 0x00 343 #define TULIP_OUI_ZNYX_1 0xC0 344 #define TULIP_OUI_ZNYX_2 0x95 345 346 347 /* 348 * SROM definitions for the DC21140 and DC21041. 349 */ 350 #define SROMSEL 0x0800 351 #define SROMRD 0x4000 352 #define SROMWR 0x2000 353 #define SROMDIN 0x0008 354 #define SROMDOUT 0x0004 355 #define SROMDOUTON 0x0004 356 #define SROMDOUTOFF 0x0004 357 #define SROMCLKON 0x0002 358 #define SROMCLKOFF 0x0002 359 #define SROMCSON 0x0001 360 #define SROMCSOFF 0x0001 361 #define SROMCS 0x0001 362 363 #define SROMCMD_MODE 4 364 #define SROMCMD_WR 5 365 #define SROMCMD_RD 6 366 367 #define SROM_BITWIDTH 6 368 369 /* 370 * Definitions for the DE425. 371 */ 372 #define DE425_CFID 0x08 /* Configuration Id */ 373 #define DE425_CFCS 0x0C /* Configuration Command-Status */ 374 #define DE425_CFRV 0x18 /* Configuration Revision */ 375 #define DE425_CFLT 0x1C /* Configuration Latency Timer */ 376 #define DE425_CBIO 0x28 /* Configuration Base IO Address */ 377 #define DE425_CFDA 0x2C /* Configuration Driver Area */ 378 #define DE425_ENETROM_OFFSET 0xC90 /* Offset in I/O space for ENETROM */ 379 #define DE425_CFG0 0xC88 /* IRQ register */ 380 381 #define DEC_VENDORID 0x1011 382 #define DC21040_CHIPID 0x0002 383 #define DC21140_CHIPID 0x0009 384 #define DC21041_CHIPID 0x0014 385 #define PCI_VENDORID(x) ((x) & 0xFFFF) 386 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF) 387 388 #endif /* !defined(_DC21040_H) */ 389
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