dc21040reg.h revision 1.5
1 /* $NetBSD: dc21040reg.h,v 1.5 1995/08/17 18:04:55 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1994, 1995 Matt Thomas (thomas (at) lkg.dec.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software withough specific prior written permission 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #if !defined(_DC21040_H) 28 #define _DC21040_H 29 30 typedef int32_t tulip_sint32_t; 31 typedef u_int32_t tulip_uint32_t; 32 33 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 34 #define TULIP_BITFIELD2(a, b) b, a 35 #define TULIP_BITFIELD3(a, b, c) c, b, a 36 #define TULIP_BITFIELD4(a, b, c, d) d, c, b, a 37 #else 38 #define TULIP_BITFIELD2(a, b) a, b 39 #define TULIP_BITFIELD3(a, b, c) a, b, c 40 #define TULIP_BITFIELD4(a, b, c, d) a, b, c, d 41 #endif 42 43 typedef struct { 44 tulip_uint32_t d_status; 45 tulip_uint32_t TULIP_BITFIELD3(d_length1 : 11, 46 d_length2 : 11, 47 d_flag : 10); 48 tulip_uint32_t d_addr1; 49 tulip_uint32_t d_addr2; 50 } tulip_desc_t; 51 52 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = DC21040) */ 53 #define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */ 54 /* 55 * Transmit Status 56 */ 57 #define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */ 58 #define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */ 59 #define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */ 60 #define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */ 61 #define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */ 62 #define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */ 63 #define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */ 64 #define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */ 65 #define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */ 66 #define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */ 67 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */ 68 /* 69 * Receive Status 70 */ 71 #define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */ 72 #define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */ 73 #define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */ 74 #define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */ 75 #define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */ 76 #define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */ 77 #define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */ 78 #define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */ 79 #define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */ 80 #define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */ 81 #define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */ 82 #define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */ 83 #define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */ 84 85 86 #define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */ 87 #define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */ 88 89 #define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */ 90 #define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */ 91 #define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */ 92 #define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */ 93 #define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */ 94 #define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */ 95 #define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */ 96 #define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */ 97 98 /* 99 * The DC21040 Registers (IO Space Addresses) 100 */ 101 #define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */ 102 #define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */ 103 #define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */ 104 #define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */ 105 #define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */ 106 #define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */ 107 #define TULIP_REG_CMD 0x30 /* CSR6 -- Command */ 108 #define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */ 109 #define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */ 110 #define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */ 111 #define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */ 112 #define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */ 113 #define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */ 114 #define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */ 115 #define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */ 116 #define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */ 117 118 /* 119 * CSR5 -- Status Register 120 * CSR7 -- Interrupt Control 121 */ 122 #define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */ 123 #define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */ 124 #define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */ 125 #define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */ 126 #define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */ 127 #define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */ 128 #define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */ 129 #define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */ 130 #define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */ 131 #define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */ 132 #define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */ 133 #define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an 134 unavailable transmit descriptor */ 135 #define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */ 136 #define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/ 137 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */ 138 #define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */ 139 #define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive 140 packet before prefetch of next descriptor */ 141 #define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */ 142 #define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of 143 unavailable receive buffers */ 144 #define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */ 145 #define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame 146 from the receive FIFO as a result of 147 an unavailable receive buffer */ 148 #define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame 149 from the receive FIFO into the receive 150 buffer. */ 151 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */ 152 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */ 153 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */ 154 #define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (DC21040) */ 155 #define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (DC21040) */ 156 #define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (DC21140) */ 157 #define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (DC21040) */ 158 #define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchbog Timeout */ 159 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */ 160 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */ 161 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */ 162 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */ 163 #define TULIP_STS_LINKPASS 0x00000010L /* (RW) LinkPass (DC21041) */ 164 #define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */ 165 #define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */ 166 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */ 167 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */ 168 169 /* 170 * CSR6 -- Command (Operation Mode) Register 171 */ 172 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (DC21140) */ 173 #define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (DC21140) */ 174 #define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (DC21140) */ 175 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (DC21140) */ 176 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Foward (DC21140) */ 177 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (DC21140) */ 178 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (DC21140) */ 179 #define TULIP_CMD_ENHCAPTEFFCT 0x00040000L /* (RW) Enhanced Capture Effecty (DC21041) */ 180 #define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */ 181 #define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (DC21040) */ 182 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */ 183 #define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */ 184 #define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */ 185 #define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */ 186 #define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */ 187 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */ 188 #define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */ 189 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */ 190 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */ 191 #define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */ 192 #define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */ 193 #define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */ 194 #define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */ 195 #define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */ 196 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */ 197 #define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */ 198 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */ 199 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */ 200 201 202 #define TULIP_SIASTS_OTHERRXACTIVITY 0x00000200L 203 #define TULIP_SIASTS_RXACTIVITY 0x00000100L 204 #define TULIP_SIASTS_LINKFAIL 0x00000004L 205 #define TULIP_SIACONN_RESET 0x00000000L 206 207 #define TULIP_SIACONN_AUI 0x0000000DL 208 #define TULIP_SIACONN_10BASET 0x00000005L 209 210 #define TULIP_DC21041_SIACONN_10BASET 0x0000EF01L 211 #define TULIP_DC21041_SIATXRX_10BASET 0x0000FF3FL 212 #define TULIP_DC21041_SIAGEN_10BASET 0x00000000L 213 214 #define TULIP_DC21041_SIACONN_AUI 0x0000EF09L 215 #define TULIP_DC21041_SIATXRX_AUI 0x0000F73DL 216 #define TULIP_DC21041_SIAGEN_AUI 0x0000000EL 217 218 #define TULIP_DC21041_SIACONN_BNC 0x0000EF09L 219 #define TULIP_DC21041_SIATXRX_BNC 0x0000F73DL 220 #define TULIP_DC21041_SIAGEN_BNC 0x00000006L 221 222 #define TULIP_BUSMODE_SWRESET 0x00000001L 223 #define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL 224 #define TULIP_BUSMODE_BIGENDIAN 0x00000080L 225 #define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L 226 #define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L 227 #define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L 228 #define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L 229 #define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L 230 #define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L 231 #define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L 232 #define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L 233 #define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L 234 #define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L 235 #define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L 236 #define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L 237 #define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L 238 #define TULIP_BUSMODE_TXPOLL_200000ns 0x00020000L 239 #define TULIP_BUSMODE_TXPOLL_800000ns 0x00040000L 240 #define TULIP_BUSMODE_TXPOLL_1600000ns 0x00060000L 241 #define TULIP_BUSMODE_TXPOLL_12800ns 0x00080000L /* DC21041 only */ 242 #define TULIP_BUSMODE_TXPOLL_25600ns 0x000A0000L /* DC21041 only */ 243 #define TULIP_BUSMODE_TXPOLL_51200ns 0x000C0000L /* DC21041 only */ 244 #define TULIP_BUSMODE_TXPOLL_102400ns 0x000E0000L /* DC21041 only */ 245 #define TULIP_BUSMODE_DESC_BIGENDIAN 0x00100000L /* DC21041 only */ 246 247 /* 248 * These are the defintitions used for the DEC DC21140 249 * evaluation board. 250 */ 251 #define TULIP_GP_EB_PINS 0x0000011F /* General Purpose Pin directions */ 252 #define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 253 #define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 254 #define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */ 255 256 /* 257 * There are the definitions used for the DEC DE500-XA 258 * 10/100 board 259 */ 260 #define TULIP_GP_DE500_PINS 0x0000010FL 261 #define TULIP_GP_DE500_NOTOK_10 0x00000080L 262 #define TULIP_GP_DE500_NOTOK_100 0x00000040L 263 #define TULIP_GP_DE500_HALFDUPLEX 0x00000008L 264 #define TULIP_GP_DE500_FORCE_100 0x00000001L 265 266 /* 267 * These are the defintitions used for the Cogent EM100 268 * DC21140 board. 269 */ 270 #define TULIP_GP_EM100_PINS 0x0000013F /* General Purpose Pin directions */ 271 #define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */ 272 #define TULIP_OUI_COGENT_0 0x00 273 #define TULIP_OUI_COGENT_1 0x00 274 #define TULIP_OUI_COGENT_2 0x94 275 #define TULIP_COGENT_EM100_ID 0x12 276 277 278 /* 279 * These are the defintitions used for the Znyx ZX342 280 * 10/100 board 281 */ 282 #define TULIP_GP_ZX34X_PINS 0x0000011F /* General Purpose Pin directions */ 283 #define TULIP_GP_ZX34X_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */ 284 #define TULIP_GP_ZX34X_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */ 285 #define TULIP_GP_ZX34X_INIT 0x00000009 286 #define TULIP_OUI_ZNYX_0 0x00 287 #define TULIP_OUI_ZNYX_1 0xC0 288 #define TULIP_OUI_ZNYX_2 0x95 289 290 291 /* 292 * SROM definitions for the DC21140 and DC21041. 293 */ 294 #define SROMSEL 0x0800 295 #define SROMRD 0x4000 296 #define SROMWR 0x2000 297 #define SROMDIN 0x0008 298 #define SROMDOUT 0x0004 299 #define SROMDOUTON 0x0004 300 #define SROMDOUTOFF 0x0004 301 #define SROMCLKON 0x0002 302 #define SROMCLKOFF 0x0002 303 #define SROMCSON 0x0001 304 #define SROMCSOFF 0x0001 305 #define SROMCS 0x0001 306 307 #define SROMCMD_MODE 4 308 #define SROMCMD_WR 5 309 #define SROMCMD_RD 6 310 311 #define SROM_BITWIDTH 6 312 313 /* 314 * Definitions for the DE425. 315 */ 316 #define DE425_CFID 0x08 /* Configuration Id */ 317 #define DE425_CFCS 0x0C /* Configuration Command-Status */ 318 #define DE425_CFRV 0x18 /* Configuration Revision */ 319 #define DE425_CFLT 0x1C /* Configuration Latency Timer */ 320 #define DE425_CBIO 0x28 /* Configuration Base IO Address */ 321 #define DE425_CFDA 0x2C /* Configuration Driver Area */ 322 #define DE425_ENETROM_OFFSET 0xC90 /* Offset in I/O space for ENETROM */ 323 #define DE425_CFG0 0xC88 /* IRQ register */ 324 325 #define DEC_VENDORID 0x1011 326 #define DC21040_CHIPID 0x0002 327 #define DC21140_CHIPID 0x0009 328 #define DC21041_CHIPID 0x0014 329 #define PCI_VENDORID(x) ((x) & 0xFFFF) 330 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF) 331 332 #endif /* !defined(_DC21040_H) */ 333
Indexes created Mon Sep 29 21:09:56 GMT 2025