dm9000.c revision 1.20
1 /* $NetBSD: dm9000.c,v 1.20 2019/05/28 07:41:48 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* based on sys/dev/ic/cs89x0.c */ 30 /* 31 * Copyright (c) 2004 Christopher Gilbert 32 * All rights reserved. 33 * 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The name of the company nor the name of the author may be used to 40 * endorse or promote products derived from this software without specific 41 * prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright 1997 58 * Digital Equipment Corporation. All rights reserved. 59 * 60 * This software is furnished under license and may be used and 61 * copied only in accordance with the following terms and conditions. 62 * Subject to these conditions, you may download, copy, install, 63 * use, modify and distribute this software in source and/or binary 64 * form. No title or ownership is transferred hereby. 65 * 66 * 1) Any source code used, modified or distributed must reproduce 67 * and retain this copyright notice and list of conditions as 68 * they appear in the source file. 69 * 70 * 2) No right is granted to use any trade name, trademark, or logo of 71 * Digital Equipment Corporation. Neither the "Digital Equipment 72 * Corporation" name nor any trademark or logo of Digital Equipment 73 * Corporation may be used to endorse or promote products derived 74 * from this software without the prior written permission of 75 * Digital Equipment Corporation. 76 * 77 * 3) This software is provided "AS-IS" and any express or implied 78 * warranties, including but not limited to, any implied warranties 79 * of merchantability, fitness for a particular purpose, or 80 * non-infringement are disclaimed. In no event shall DIGITAL be 81 * liable for any damages whatsoever, and in particular, DIGITAL 82 * shall not be liable for special, indirect, consequential, or 83 * incidental damages or damages for lost profits, loss of 84 * revenue or loss of use, whether such damages arise in contract, 85 * negligence, tort, under statute, in equity, at law or otherwise, 86 * even if advised of the possibility of such damage. 87 */ 88 89 #include <sys/cdefs.h> 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/mbuf.h> 95 #include <sys/syslog.h> 96 #include <sys/socket.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 #include <sys/ioctl.h> 100 #include <sys/errno.h> 101 102 #include <net/if.h> 103 #include <net/if_ether.h> 104 #include <net/if_media.h> 105 #include <net/bpf.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #include <sys/bus.h> 113 #include <sys/intr.h> 114 115 #include <dev/ic/dm9000var.h> 116 #include <dev/ic/dm9000reg.h> 117 118 #if 1 119 #undef DM9000_DEBUG 120 #undef DM9000_TX_DEBUG 121 #undef DM9000_TX_DATA_DEBUG 122 #undef DM9000_RX_DEBUG 123 #undef DM9000_RX_DATA_DEBUG 124 #else 125 #define DM9000_DEBUG 126 #define DM9000_TX_DEBUG 127 #define DM9000_TX_DATA_DEBUG 128 #define DM9000_RX_DEBUG 129 #define DM9000_RX_DATA_DEBUG 130 #endif 131 132 #ifdef DM9000_DEBUG 133 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 134 #else 135 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 136 #endif 137 138 #ifdef DM9000_TX_DEBUG 139 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 140 #else 141 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 142 #endif 143 144 #ifdef DM9000_RX_DEBUG 145 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 146 #else 147 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 148 #endif 149 150 #ifdef DM9000_RX_DATA_DEBUG 151 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 152 #else 153 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 154 #endif 155 156 #ifdef DM9000_TX_DATA_DEBUG 157 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 158 #else 159 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 160 #endif 161 162 /*** Internal PHY functions ***/ 163 uint16_t dme_phy_read(struct dme_softc *, int ); 164 void dme_phy_write(struct dme_softc *, int, uint16_t); 165 void dme_phy_init(struct dme_softc *); 166 void dme_phy_reset(struct dme_softc *); 167 void dme_phy_update_media(struct dme_softc *); 168 void dme_phy_check_link(void *); 169 170 /*** Methods registered in struct ifnet ***/ 171 void dme_start_output(struct ifnet *); 172 int dme_init(struct ifnet *); 173 int dme_ioctl(struct ifnet *, u_long, void *); 174 void dme_stop(struct ifnet *, int); 175 176 int dme_mediachange(struct ifnet *); 177 void dme_mediastatus(struct ifnet *, struct ifmediareq *); 178 179 /*** Internal methods ***/ 180 181 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */ 182 void dme_prepare(struct dme_softc *, struct ifnet *); 183 184 /* Transmit prepared data */ 185 void dme_transmit(struct dme_softc *); 186 187 /* Receive data */ 188 void dme_receive(struct dme_softc *, struct ifnet *); 189 190 /* Software Initialize/Reset of the DM9000 */ 191 void dme_reset(struct dme_softc *); 192 193 /* Configure multicast filter */ 194 void dme_set_addr_filter(struct dme_softc *); 195 196 /* Set media */ 197 int dme_set_media(struct dme_softc *, int ); 198 199 /* Read/write packet data from/to DM9000 IC in various transfer sizes */ 200 int dme_pkt_read_2(struct dme_softc *, struct ifnet *, struct mbuf **); 201 int dme_pkt_write_2(struct dme_softc *, struct mbuf *); 202 int dme_pkt_read_1(struct dme_softc *, struct ifnet *, struct mbuf **); 203 int dme_pkt_write_1(struct dme_softc *, struct mbuf *); 204 /* TODO: Implement 32 bit read/write functions */ 205 206 uint16_t 207 dme_phy_read(struct dme_softc *sc, int reg) 208 { 209 uint16_t val; 210 /* Select Register to read*/ 211 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 212 (reg & DM9000_EPAR_EROA_MASK)); 213 /* Select read operation (DM9000_EPCR_ERPRR) from the PHY */ 214 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY); 215 216 /* Wait until access to PHY has completed */ 217 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 218 ; 219 220 /* Reset ERPRR-bit */ 221 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 222 223 val = dme_read(sc, DM9000_EPDRL); 224 val += dme_read(sc, DM9000_EPDRH) << 8; 225 226 return val; 227 } 228 229 void 230 dme_phy_write(struct dme_softc *sc, int reg, uint16_t value) 231 { 232 /* Select Register to write*/ 233 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 234 (reg & DM9000_EPAR_EROA_MASK)); 235 236 /* Write data to the two data registers */ 237 dme_write(sc, DM9000_EPDRL, value & 0xFF); 238 dme_write(sc, DM9000_EPDRH, (value >> 8) & 0xFF); 239 240 /* Select write operation (DM9000_EPCR_ERPRW) from the PHY */ 241 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY); 242 243 /* Wait until access to PHY has completed */ 244 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 245 ; 246 247 /* Reset ERPRR-bit */ 248 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 249 } 250 251 void 252 dme_phy_init(struct dme_softc *sc) 253 { 254 u_int ifm_media = sc->sc_media.ifm_media; 255 uint32_t bmcr, anar; 256 257 bmcr = dme_phy_read(sc, DM9000_PHY_BMCR); 258 anar = dme_phy_read(sc, DM9000_PHY_ANAR); 259 260 anar = anar & ~DM9000_PHY_ANAR_10_HDX 261 & ~DM9000_PHY_ANAR_10_FDX 262 & ~DM9000_PHY_ANAR_TX_HDX 263 & ~DM9000_PHY_ANAR_TX_FDX; 264 265 switch (IFM_SUBTYPE(ifm_media)) { 266 case IFM_AUTO: 267 bmcr |= DM9000_PHY_BMCR_AUTO_NEG_EN; 268 anar |= DM9000_PHY_ANAR_10_HDX | 269 DM9000_PHY_ANAR_10_FDX | 270 DM9000_PHY_ANAR_TX_HDX | 271 DM9000_PHY_ANAR_TX_FDX; 272 break; 273 case IFM_10_T: 274 //bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 275 bmcr &= ~DM9000_PHY_BMCR_SPEED_SELECT; 276 if (ifm_media & IFM_FDX) 277 anar |= DM9000_PHY_ANAR_10_FDX; 278 else 279 anar |= DM9000_PHY_ANAR_10_HDX; 280 break; 281 case IFM_100_TX: 282 //bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 283 bmcr |= DM9000_PHY_BMCR_SPEED_SELECT; 284 if (ifm_media & IFM_FDX) 285 anar |= DM9000_PHY_ANAR_TX_FDX; 286 else 287 anar |= DM9000_PHY_ANAR_TX_HDX; 288 289 break; 290 } 291 292 if (ifm_media & IFM_FDX) 293 bmcr |= DM9000_PHY_BMCR_DUPLEX_MODE; 294 else 295 bmcr &= ~DM9000_PHY_BMCR_DUPLEX_MODE; 296 297 dme_phy_write(sc, DM9000_PHY_BMCR, bmcr); 298 dme_phy_write(sc, DM9000_PHY_ANAR, anar); 299 } 300 301 void 302 dme_phy_reset(struct dme_softc *sc) 303 { 304 uint32_t reg; 305 306 /* PHY Reset */ 307 dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET); 308 309 reg = dme_read(sc, DM9000_GPCR); 310 dme_write(sc, DM9000_GPCR, reg & ~DM9000_GPCR_GPIO0_OUT); 311 reg = dme_read(sc, DM9000_GPR); 312 dme_write(sc, DM9000_GPR, reg | DM9000_GPR_PHY_PWROFF); 313 314 dme_phy_init(sc); 315 316 reg = dme_read(sc, DM9000_GPR); 317 dme_write(sc, DM9000_GPR, reg & ~DM9000_GPR_PHY_PWROFF); 318 reg = dme_read(sc, DM9000_GPCR); 319 dme_write(sc, DM9000_GPCR, reg | DM9000_GPCR_GPIO0_OUT); 320 321 dme_phy_update_media(sc); 322 } 323 324 void 325 dme_phy_update_media(struct dme_softc *sc) 326 { 327 u_int ifm_media = sc->sc_media.ifm_media; 328 uint32_t reg; 329 330 if (IFM_SUBTYPE(ifm_media) == IFM_AUTO) { 331 /* If auto-negotiation is used, ensures that it is completed 332 before trying to extract any media information. */ 333 reg = dme_phy_read(sc, DM9000_PHY_BMSR); 334 if ((reg & DM9000_PHY_BMSR_AUTO_NEG_AB) == 0) { 335 /* Auto-negotation not possible, therefore there is no 336 reason to try obtain any media information. */ 337 return; 338 } 339 340 /* Then loop until the negotiation is completed. */ 341 while ((reg & DM9000_PHY_BMSR_AUTO_NEG_COM) == 0) { 342 /* TODO: Bail out after a finite number of attempts 343 in case something goes wrong. */ 344 preempt(); 345 reg = dme_phy_read(sc, DM9000_PHY_BMSR); 346 } 347 } 348 349 350 sc->sc_media_active = IFM_ETHER; 351 reg = dme_phy_read(sc, DM9000_PHY_BMCR); 352 353 if (reg & DM9000_PHY_BMCR_SPEED_SELECT) 354 sc->sc_media_active |= IFM_100_TX; 355 else 356 sc->sc_media_active |= IFM_10_T; 357 358 if (reg & DM9000_PHY_BMCR_DUPLEX_MODE) 359 sc->sc_media_active |= IFM_FDX; 360 } 361 362 void 363 dme_phy_check_link(void *arg) 364 { 365 struct dme_softc *sc = arg; 366 uint32_t reg; 367 int s; 368 369 s = splnet(); 370 371 reg = dme_read(sc, DM9000_NSR) & DM9000_NSR_LINKST; 372 373 if (reg) 374 reg = IFM_ETHER | IFM_AVALID | IFM_ACTIVE; 375 else { 376 reg = IFM_ETHER | IFM_AVALID; 377 sc->sc_media_active = IFM_NONE; 378 } 379 380 if ((sc->sc_media_status != reg) && (reg & IFM_ACTIVE)) 381 dme_phy_reset(sc); 382 383 sc->sc_media_status = reg; 384 385 callout_schedule(&sc->sc_link_callout, mstohz(2000)); 386 splx(s); 387 } 388 389 int 390 dme_set_media(struct dme_softc *sc, int media) 391 { 392 int s; 393 394 s = splnet(); 395 sc->sc_media.ifm_media = media; 396 dme_phy_reset(sc); 397 398 splx(s); 399 400 return 0; 401 } 402 403 int 404 dme_attach(struct dme_softc *sc, const uint8_t *enaddr) 405 { 406 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 407 uint8_t b[2]; 408 uint16_t io_mode; 409 410 dme_read_c(sc, DM9000_VID0, b, 2); 411 #if BYTE_ORDER == BIG_ENDIAN 412 sc->sc_vendor_id = (b[0] << 8) | b[1]; 413 #else 414 sc->sc_vendor_id = b[0] | (b[1] << 8); 415 #endif 416 dme_read_c(sc, DM9000_PID0, b, 2); 417 #if BYTE_ORDER == BIG_ENDIAN 418 sc->sc_product_id = (b[0] << 8) | b[1]; 419 #else 420 sc->sc_product_id = b[0] | (b[1] << 8); 421 #endif 422 /* TODO: Check the vendor ID as well */ 423 if (sc->sc_product_id != 0x9000) { 424 panic("dme_attach: product id mismatch (0x%hx != 0x9000)", 425 sc->sc_product_id); 426 } 427 428 /* Initialize ifnet structure. */ 429 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 430 ifp->if_softc = sc; 431 ifp->if_start = dme_start_output; 432 ifp->if_init = dme_init; 433 ifp->if_ioctl = dme_ioctl; 434 ifp->if_stop = dme_stop; 435 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 436 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 437 IFQ_SET_READY(&ifp->if_snd); 438 439 /* Initialize ifmedia structures. */ 440 ifmedia_init(&sc->sc_media, 0, dme_mediachange, dme_mediastatus); 441 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 442 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 443 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); 444 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 445 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); 446 447 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 448 449 if (enaddr != NULL) 450 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 451 /* TODO: Support an EEPROM attached to the DM9000 chip */ 452 453 callout_init(&sc->sc_link_callout, 0); 454 callout_setfunc(&sc->sc_link_callout, dme_phy_check_link, sc); 455 456 sc->sc_media_status = 0; 457 458 /* Configure DM9000 with the MAC address */ 459 dme_write_c(sc, DM9000_PAB0, sc->sc_enaddr, 6); 460 461 #ifdef DM9000_DEBUG 462 { 463 uint8_t macAddr[6]; 464 dme_read_c(sc, DM9000_PAB0, macAddr, 6); 465 printf("DM9000 configured with MAC address: "); 466 for (int i = 0; i < 6; i++) 467 printf("%02X:", macAddr[i]); 468 printf("\n"); 469 } 470 #endif 471 472 if_attach(ifp); 473 ether_ifattach(ifp, sc->sc_enaddr); 474 475 #ifdef DM9000_DEBUG 476 { 477 uint8_t network_state; 478 network_state = dme_read(sc, DM9000_NSR); 479 printf("DM9000 Link status: "); 480 if (network_state & DM9000_NSR_LINKST) { 481 if (network_state & DM9000_NSR_SPEED) 482 printf("10Mbps"); 483 else 484 printf("100Mbps"); 485 } else 486 printf("Down"); 487 printf("\n"); 488 } 489 #endif 490 491 io_mode = (dme_read(sc, DM9000_ISR) & 492 DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT; 493 494 DPRINTF(("DM9000 Operation Mode: ")); 495 switch (io_mode) { 496 case DM9000_MODE_16BIT: 497 DPRINTF(("16-bit mode")); 498 sc->sc_data_width = 2; 499 sc->sc_pkt_write = dme_pkt_write_2; 500 sc->sc_pkt_read = dme_pkt_read_2; 501 break; 502 case DM9000_MODE_32BIT: 503 DPRINTF(("32-bit mode")); 504 sc->sc_data_width = 4; 505 panic("32bit mode is unsupported\n"); 506 break; 507 case DM9000_MODE_8BIT: 508 DPRINTF(("8-bit mode")); 509 sc->sc_data_width = 1; 510 sc->sc_pkt_write = dme_pkt_write_1; 511 sc->sc_pkt_read = dme_pkt_read_1; 512 break; 513 default: 514 DPRINTF(("Invalid mode")); 515 break; 516 } 517 DPRINTF(("\n")); 518 519 callout_schedule(&sc->sc_link_callout, mstohz(2000)); 520 521 return 0; 522 } 523 524 int dme_intr(void *arg) 525 { 526 struct dme_softc *sc = arg; 527 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 528 uint8_t status; 529 530 531 DPRINTF(("dme_intr: Begin\n")); 532 533 /* Disable interrupts */ 534 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR ); 535 536 status = dme_read(sc, DM9000_ISR); 537 dme_write(sc, DM9000_ISR, status); 538 539 if (status & DM9000_ISR_PRS) { 540 if (ifp->if_flags & IFF_RUNNING ) 541 dme_receive(sc, ifp); 542 } 543 if (status & DM9000_ISR_PTS) { 544 uint8_t nsr; 545 uint8_t tx_status = 0x01; /* Initialize to an error value */ 546 547 /* A packet has been transmitted */ 548 sc->txbusy = 0; 549 550 nsr = dme_read(sc, DM9000_NSR); 551 552 if (nsr & DM9000_NSR_TX1END) { 553 tx_status = dme_read(sc, DM9000_TSR1); 554 TX_DPRINTF(("dme_intr: Sent using channel 0\n")); 555 } else if (nsr & DM9000_NSR_TX2END) { 556 tx_status = dme_read(sc, DM9000_TSR2); 557 TX_DPRINTF(("dme_intr: Sent using channel 1\n")); 558 } 559 560 if (tx_status == 0x0) { 561 /* Frame successfully sent */ 562 ifp->if_opackets++; 563 } else { 564 ifp->if_oerrors++; 565 } 566 567 /* If we have nothing ready to transmit, prepare something */ 568 if (!sc->txready) 569 dme_prepare(sc, ifp); 570 571 if (sc->txready) 572 dme_transmit(sc); 573 574 /* Prepare the next frame */ 575 dme_prepare(sc, ifp); 576 577 } 578 #ifdef notyet 579 if (status & DM9000_ISR_LNKCHNG) { 580 } 581 #endif 582 583 /* Enable interrupts again */ 584 dme_write(sc, DM9000_IMR, 585 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 586 587 DPRINTF(("dme_intr: End\n")); 588 589 return 1; 590 } 591 592 void 593 dme_start_output(struct ifnet *ifp) 594 { 595 struct dme_softc *sc; 596 597 sc = ifp->if_softc; 598 599 DPRINTF(("dme_start_output: Begin\n")); 600 601 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 602 printf("No output\n"); 603 return; 604 } 605 606 if (sc->txbusy && sc->txready) 607 panic("DM9000: Internal error, trying to send without" 608 " any empty queue\n"); 609 610 dme_prepare(sc, ifp); 611 612 if (sc->txbusy == 0) { 613 /* We are ready to transmit right away */ 614 dme_transmit(sc); 615 dme_prepare(sc, ifp); /* Prepare next one */ 616 } else { 617 /* We need to wait until the current packet has 618 * been transmitted. 619 */ 620 ifp->if_flags |= IFF_OACTIVE; 621 } 622 623 DPRINTF(("dme_start_output: End\n")); 624 } 625 626 void 627 dme_prepare(struct dme_softc *sc, struct ifnet *ifp) 628 { 629 struct mbuf *bufChain; 630 uint16_t length; 631 632 TX_DPRINTF(("dme_prepare: Entering\n")); 633 634 if (sc->txready) 635 panic("dme_prepare: Someone called us with txready set\n"); 636 637 IFQ_DEQUEUE(&ifp->if_snd, bufChain); 638 if (bufChain == NULL) { 639 TX_DPRINTF(("dme_prepare: Nothing to transmit\n")); 640 ifp->if_flags &= ~IFF_OACTIVE; /* Clear OACTIVE bit */ 641 return; /* Nothing to transmit */ 642 } 643 644 /* Element has now been removed from the queue, so we better send it */ 645 646 bpf_mtap(ifp, bufChain, BPF_D_OUT); 647 648 /* Setup the DM9000 to accept the writes, and then write each buf in 649 the chain. */ 650 651 TX_DATA_DPRINTF(("dme_prepare: Writing data: ")); 652 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD); 653 length = sc->sc_pkt_write(sc, bufChain); 654 TX_DATA_DPRINTF(("\n")); 655 656 if (length % sc->sc_data_width != 0) 657 panic("dme_prepare: length is not compatible with IO_MODE"); 658 659 sc->txready_length = length; 660 sc->txready = 1; 661 662 TX_DPRINTF(("dme_prepare: txbusy: %d\ndme_prepare: " 663 "txready: %d, txready_length: %d\n", 664 sc->txbusy, sc->txready, sc->txready_length)); 665 666 m_freem(bufChain); 667 668 TX_DPRINTF(("dme_prepare: Leaving\n")); 669 } 670 671 int 672 dme_init(struct ifnet *ifp) 673 { 674 int s; 675 struct dme_softc *sc = ifp->if_softc; 676 677 dme_stop(ifp, 0); 678 679 s = splnet(); 680 681 dme_reset(sc); 682 683 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 684 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 685 sc->sc_ethercom.ec_if.if_timer = 0; 686 687 splx(s); 688 689 return 0; 690 } 691 692 int 693 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data) 694 { 695 struct dme_softc *sc = ifp->if_softc; 696 struct ifreq *ifr = data; 697 int s, error = 0; 698 699 s = splnet(); 700 701 switch (cmd) { 702 case SIOCGIFMEDIA: 703 case SIOCSIFMEDIA: 704 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 705 break; 706 default: 707 error = ether_ioctl(ifp, cmd, data); 708 if (error == ENETRESET) { 709 if (ifp->if_flags && IFF_RUNNING) { 710 /* Address list has changed, reconfigure 711 filter */ 712 dme_set_addr_filter(sc); 713 } 714 error = 0; 715 } 716 break; 717 } 718 719 splx(s); 720 return error; 721 } 722 723 void 724 dme_stop(struct ifnet *ifp, int disable) 725 { 726 struct dme_softc *sc = ifp->if_softc; 727 728 /* Not quite sure what to do when called with disable == 0 */ 729 if (disable) { 730 /* Disable RX */ 731 dme_write(sc, DM9000_RCR, 0x0); 732 } 733 734 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 735 ifp->if_timer = 0; 736 } 737 738 int 739 dme_mediachange(struct ifnet *ifp) 740 { 741 struct dme_softc *sc = ifp->if_softc; 742 743 return dme_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 744 } 745 746 void 747 dme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 748 { 749 struct dme_softc *sc = ifp->if_softc; 750 751 ifmr->ifm_active = sc->sc_media_active; 752 ifmr->ifm_status = sc->sc_media_status; 753 } 754 755 void 756 dme_transmit(struct dme_softc *sc) 757 { 758 759 TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n", 760 sc->txready, sc->txbusy)); 761 762 dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff); 763 dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff ); 764 765 /* Request to send the packet */ 766 dme_read(sc, DM9000_ISR); 767 768 dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ); 769 770 sc->txready = 0; 771 sc->txbusy = 1; 772 sc->txready_length = 0; 773 } 774 775 void 776 dme_receive(struct dme_softc *sc, struct ifnet *ifp) 777 { 778 uint8_t ready = 0x01; 779 780 DPRINTF(("inside dme_receive\n")); 781 782 while (ready == 0x01) { 783 /* Packet received, retrieve it */ 784 785 /* Read without address increment to get the ready byte without 786 moving past it. */ 787 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 788 sc->dme_io, DM9000_MRCMDX); 789 /* Dummy ready */ 790 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 791 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 792 ready &= 0x03; /* we only want bits 1:0 */ 793 if (ready == 0x01) { 794 uint8_t rx_status; 795 struct mbuf *m; 796 797 /* Read with address increment. */ 798 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 799 sc->dme_io, DM9000_MRCMD); 800 801 rx_status = sc->sc_pkt_read(sc, ifp, &m); 802 if (m == NULL) { 803 /* failed to allocate a receive buffer */ 804 ifp->if_ierrors++; 805 RX_DPRINTF(("dme_receive: " 806 "Error allocating buffer\n")); 807 } else if (rx_status & (DM9000_RSR_CE | DM9000_RSR_PLE)) { 808 /* Error while receiving the packet, 809 * discard it and keep track of counters 810 */ 811 ifp->if_ierrors++; 812 RX_DPRINTF(("dme_receive: " 813 "Error reciving packet\n")); 814 } else if (rx_status & DM9000_RSR_LCS) { 815 ifp->if_collisions++; 816 } else { 817 if_percpuq_enqueue(ifp->if_percpuq, m); 818 } 819 820 } else if (ready != 0x00) { 821 /* Should this be logged somehow? */ 822 printf("%s: Resetting chip\n", 823 device_xname(sc->sc_dev)); 824 dme_reset(sc); 825 } 826 } 827 } 828 829 void 830 dme_reset(struct dme_softc *sc) 831 { 832 uint8_t var; 833 834 /* We only re-initialized the PHY in this function the first time it is 835 called. */ 836 if (!sc->sc_phy_initialized) { 837 /* PHY Reset */ 838 dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET); 839 840 /* PHY Power Down */ 841 var = dme_read(sc, DM9000_GPR); 842 dme_write(sc, DM9000_GPR, var | DM9000_GPR_PHY_PWROFF); 843 } 844 845 /* Reset the DM9000 twice, as described in section 2 of the Programming 846 Guide. 847 The PHY is initialized and enabled between those two resets. 848 */ 849 850 /* Software Reset*/ 851 dme_write(sc, DM9000_NCR, 852 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 853 delay(20); 854 dme_write(sc, DM9000_NCR, 0x0); 855 856 if (!sc->sc_phy_initialized) { 857 /* PHY Initialization */ 858 dme_phy_init(sc); 859 860 /* PHY Enable */ 861 var = dme_read(sc, DM9000_GPR); 862 dme_write(sc, DM9000_GPR, var & ~DM9000_GPR_PHY_PWROFF); 863 var = dme_read(sc, DM9000_GPCR); 864 dme_write(sc, DM9000_GPCR, var | DM9000_GPCR_GPIO0_OUT); 865 866 dme_write(sc, DM9000_NCR, 867 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 868 delay(20); 869 dme_write(sc, DM9000_NCR, 0x0); 870 } 871 872 /* Select internal PHY, no wakeup event, no collosion mode, 873 * normal loopback mode. 874 */ 875 dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL ); 876 877 /* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/ 878 dme_read(sc, DM9000_NSR); 879 880 /* Enable wraparound of read/write pointer, packet received latch, 881 * and packet transmitted latch. 882 */ 883 dme_write(sc, DM9000_IMR, 884 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 885 886 /* Setup multicast address filter, and enable RX. */ 887 dme_set_addr_filter(sc); 888 889 /* Obtain media information from PHY */ 890 dme_phy_update_media(sc); 891 892 sc->txbusy = 0; 893 sc->txready = 0; 894 sc->sc_phy_initialized = 1; 895 } 896 897 void 898 dme_set_addr_filter(struct dme_softc *sc) 899 { 900 struct ether_multi *enm; 901 struct ether_multistep step; 902 struct ethercom *ec; 903 struct ifnet *ifp; 904 uint16_t af[4]; 905 int i; 906 907 ec = &sc->sc_ethercom; 908 ifp = &ec->ec_if; 909 910 if (ifp->if_flags & IFF_PROMISC) { 911 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | 912 DM9000_RCR_WTDIS | 913 DM9000_RCR_PRMSC); 914 ifp->if_flags |= IFF_ALLMULTI; 915 return; 916 } 917 918 af[0] = af[1] = af[2] = af[3] = 0x0000; 919 ifp->if_flags &= ~IFF_ALLMULTI; 920 921 ETHER_LOCK(ec); 922 ETHER_FIRST_MULTI(step, ec, enm); 923 while (enm != NULL) { 924 uint16_t hash; 925 if (memcpy(enm->enm_addrlo, enm->enm_addrhi, 926 sizeof(enm->enm_addrlo))) { 927 /* 928 * We must listen to a range of multicast addresses. 929 * For now, just accept all multicasts, rather than 930 * trying to set only those filter bits needed to match 931 * the range. (At this time, the only use of address 932 * ranges is for IP multicast routing, for which the 933 * range is big enough to require all bits set.) 934 */ 935 ifp->if_flags |= IFF_ALLMULTI; 936 af[0] = af[1] = af[2] = af[3] = 0xffff; 937 break; 938 } else { 939 hash = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3F; 940 af[(uint16_t)(hash>>4)] |= (uint16_t)(1 << (hash % 16)); 941 ETHER_NEXT_MULTI(step, enm); 942 } 943 } 944 ETHER_UNLOCK(ec); 945 946 /* Write the multicast address filter */ 947 for (i = 0; i < 4; i++) { 948 dme_write(sc, DM9000_MAB0+i*2, af[i] & 0xFF); 949 dme_write(sc, DM9000_MAB0+i*2+1, (af[i] >> 8) & 0xFF); 950 } 951 952 /* Setup RX controls */ 953 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | DM9000_RCR_WTDIS); 954 } 955 956 int 957 dme_pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain) 958 { 959 int left_over_count = 0; /* Number of bytes from previous mbuf, which 960 need to be written with the next.*/ 961 uint16_t left_over_buf = 0; 962 int length = 0; 963 struct mbuf *buf; 964 uint8_t *write_ptr; 965 966 /* We expect that the DM9000 has been setup to accept writes before 967 this function is called. */ 968 969 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 970 int to_write = buf->m_len; 971 972 length += to_write; 973 974 write_ptr = buf->m_data; 975 while (to_write > 0 || 976 (buf->m_next == NULL && left_over_count > 0)) { 977 if (left_over_count > 0) { 978 uint8_t b = 0; 979 DPRINTF(("dme_pkt_write_16: " 980 "Writing left over byte\n")); 981 982 if (to_write > 0) { 983 b = *write_ptr; 984 to_write--; 985 write_ptr++; 986 987 DPRINTF(("Took single byte\n")); 988 } else { 989 DPRINTF(("Leftover in last run\n")); 990 length++; 991 } 992 993 /* Does shift direction depend on endianess? */ 994 left_over_buf = left_over_buf | (b << 8); 995 996 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 997 sc->dme_data, left_over_buf); 998 TX_DATA_DPRINTF(("%02X ", left_over_buf)); 999 left_over_count = 0; 1000 } else if ((long)write_ptr % 2 != 0) { 1001 /* Misaligned data */ 1002 DPRINTF(("dme_pkt_write_16: " 1003 "Detected misaligned data\n")); 1004 left_over_buf = *write_ptr; 1005 left_over_count = 1; 1006 write_ptr++; 1007 to_write--; 1008 } else { 1009 int i; 1010 uint16_t *dptr = (uint16_t *)write_ptr; 1011 1012 /* A block of aligned data. */ 1013 for (i = 0; i < to_write / 2; i++) { 1014 /* buf will be half-word aligned 1015 * all the time 1016 */ 1017 bus_space_write_2(sc->sc_iot, 1018 sc->sc_ioh, sc->dme_data, *dptr); 1019 TX_DATA_DPRINTF(("%02X %02X ", 1020 *dptr & 0xFF, (*dptr >> 8) & 0xFF)); 1021 dptr++; 1022 } 1023 1024 write_ptr += i * 2; 1025 if (to_write % 2 != 0) { 1026 DPRINTF(("dme_pkt_write_16: " 1027 "to_write %% 2: %d\n", 1028 to_write % 2)); 1029 left_over_count = 1; 1030 /* XXX: Does this depend on 1031 * the endianess? 1032 */ 1033 left_over_buf = *write_ptr; 1034 1035 write_ptr++; 1036 to_write--; 1037 DPRINTF(("dme_pkt_write_16: " 1038 "to_write (after): %d\n", 1039 to_write)); 1040 DPRINTF(("dme_pkt_write_16: i * 2: %d\n", 1041 i*2)); 1042 } 1043 to_write -= i * 2; 1044 } 1045 } /* while (...) */ 1046 } /* for (...) */ 1047 1048 return length; 1049 } 1050 1051 int 1052 dme_pkt_read_2(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf) 1053 { 1054 uint8_t rx_status; 1055 struct mbuf *m; 1056 uint16_t data; 1057 uint16_t frame_length; 1058 uint16_t i; 1059 uint16_t *buf; 1060 1061 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1062 1063 rx_status = data & 0xFF; 1064 frame_length = bus_space_read_2(sc->sc_iot, 1065 sc->sc_ioh, sc->dme_data); 1066 if (frame_length > ETHER_MAX_LEN) { 1067 printf("Got frame of length: %d\n", frame_length); 1068 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1069 panic("Something is rotten"); 1070 } 1071 RX_DPRINTF(("dme_receive: rx_statux: 0x%x, frame_length: %d\n", 1072 rx_status, frame_length)); 1073 1074 1075 m = dme_alloc_receive_buffer(ifp, frame_length); 1076 if (m == NULL) { 1077 /* 1078 * didn't get a receive buffer, so we read the rest of the 1079 * packet, throw it away and return an error 1080 */ 1081 for (i = 0; i < frame_length; i += 2 ) { 1082 data = bus_space_read_2(sc->sc_iot, 1083 sc->sc_ioh, sc->dme_data); 1084 } 1085 *outBuf = NULL; 1086 return 0; 1087 } 1088 1089 buf = mtod(m, uint16_t*); 1090 1091 RX_DPRINTF(("dme_receive: ")); 1092 1093 for (i = 0; i < frame_length; i += 2 ) { 1094 data = bus_space_read_2(sc->sc_iot, 1095 sc->sc_ioh, sc->dme_data); 1096 if ( (frame_length % 2 != 0) && 1097 (i == frame_length - 1) ) { 1098 data = data & 0xff; 1099 RX_DPRINTF((" L ")); 1100 } 1101 *buf = data; 1102 buf++; 1103 RX_DATA_DPRINTF(("%02X %02X ", data & 0xff, 1104 (data >> 8) & 0xff)); 1105 } 1106 1107 RX_DATA_DPRINTF(("\n")); 1108 RX_DPRINTF(("Read %d bytes\n", i)); 1109 1110 *outBuf = m; 1111 return rx_status; 1112 } 1113 1114 int 1115 dme_pkt_write_1(struct dme_softc *sc, struct mbuf *bufChain) 1116 { 1117 int length = 0, i; 1118 struct mbuf *buf; 1119 uint8_t *write_ptr; 1120 1121 /* 1122 * We expect that the DM9000 has been setup to accept writes before 1123 * this function is called. 1124 */ 1125 1126 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 1127 int to_write = buf->m_len; 1128 1129 length += to_write; 1130 1131 write_ptr = buf->m_data; 1132 for (i = 0; i < to_write; i++) { 1133 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1134 sc->dme_data, *write_ptr); 1135 write_ptr++; 1136 } 1137 } /* for (...) */ 1138 1139 return length; 1140 } 1141 1142 int 1143 dme_pkt_read_1(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf) 1144 { 1145 uint8_t rx_status; 1146 struct mbuf *m; 1147 uint8_t *buf; 1148 uint16_t frame_length; 1149 uint16_t i, reg; 1150 uint8_t data; 1151 1152 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1153 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1154 rx_status = reg & 0xFF; 1155 1156 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1157 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1158 frame_length = reg; 1159 1160 if (frame_length > ETHER_MAX_LEN) { 1161 printf("Got frame of length: %d\n", frame_length); 1162 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1163 panic("Something is rotten"); 1164 } 1165 RX_DPRINTF(("dme_receive: " 1166 "rx_statux: 0x%x, frame_length: %d\n", 1167 rx_status, frame_length)); 1168 1169 1170 m = dme_alloc_receive_buffer(ifp, frame_length); 1171 if (m == NULL) { 1172 /* 1173 * didn't get a receive buffer, so we read the rest of the 1174 * packet, throw it away and return an error 1175 */ 1176 for (i = 0; i < frame_length; i++ ) { 1177 data = bus_space_read_2(sc->sc_iot, 1178 sc->sc_ioh, sc->dme_data); 1179 } 1180 *outBuf = NULL; 1181 return 0; 1182 } 1183 1184 buf = mtod(m, uint8_t *); 1185 1186 RX_DPRINTF(("dme_receive: ")); 1187 1188 for (i = 0; i< frame_length; i += 1 ) { 1189 data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1190 *buf = data; 1191 buf++; 1192 RX_DATA_DPRINTF(("%02X ", data)); 1193 } 1194 1195 RX_DATA_DPRINTF(("\n")); 1196 RX_DPRINTF(("Read %d bytes\n", i)); 1197 1198 *outBuf = m; 1199 return rx_status; 1200 } 1201 1202 struct mbuf* 1203 dme_alloc_receive_buffer(struct ifnet *ifp, unsigned int frame_length) 1204 { 1205 struct dme_softc *sc = ifp->if_softc; 1206 struct mbuf *m; 1207 int pad; 1208 1209 MGETHDR(m, M_DONTWAIT, MT_DATA); 1210 if (m == NULL) return NULL; 1211 1212 m_set_rcvif(m, ifp); 1213 /* Ensure that we always allocate an even number of 1214 * bytes in order to avoid writing beyond the buffer 1215 */ 1216 m->m_pkthdr.len = frame_length + (frame_length % sc->sc_data_width); 1217 pad = ALIGN(sizeof(struct ether_header)) - 1218 sizeof(struct ether_header); 1219 /* All our frames have the CRC attached */ 1220 m->m_flags |= M_HASFCS; 1221 if (m->m_pkthdr.len + pad > MHLEN) { 1222 MCLGET(m, M_DONTWAIT); 1223 if ((m->m_flags & M_EXT) == 0) { 1224 m_freem(m); 1225 return NULL; 1226 } 1227 } 1228 1229 m->m_data += pad; 1230 m->m_len = frame_length + (frame_length % sc->sc_data_width); 1231 1232 return m; 1233 } 1234
Indexes created Fri Sep 26 20:09:58 GMT 2025