dm9000.c revision 1.21
1 /* $NetBSD: dm9000.c,v 1.21 2019/05/29 10:07:29 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* based on sys/dev/ic/cs89x0.c */ 30 /* 31 * Copyright (c) 2004 Christopher Gilbert 32 * All rights reserved. 33 * 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The name of the company nor the name of the author may be used to 40 * endorse or promote products derived from this software without specific 41 * prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright 1997 58 * Digital Equipment Corporation. All rights reserved. 59 * 60 * This software is furnished under license and may be used and 61 * copied only in accordance with the following terms and conditions. 62 * Subject to these conditions, you may download, copy, install, 63 * use, modify and distribute this software in source and/or binary 64 * form. No title or ownership is transferred hereby. 65 * 66 * 1) Any source code used, modified or distributed must reproduce 67 * and retain this copyright notice and list of conditions as 68 * they appear in the source file. 69 * 70 * 2) No right is granted to use any trade name, trademark, or logo of 71 * Digital Equipment Corporation. Neither the "Digital Equipment 72 * Corporation" name nor any trademark or logo of Digital Equipment 73 * Corporation may be used to endorse or promote products derived 74 * from this software without the prior written permission of 75 * Digital Equipment Corporation. 76 * 77 * 3) This software is provided "AS-IS" and any express or implied 78 * warranties, including but not limited to, any implied warranties 79 * of merchantability, fitness for a particular purpose, or 80 * non-infringement are disclaimed. In no event shall DIGITAL be 81 * liable for any damages whatsoever, and in particular, DIGITAL 82 * shall not be liable for special, indirect, consequential, or 83 * incidental damages or damages for lost profits, loss of 84 * revenue or loss of use, whether such damages arise in contract, 85 * negligence, tort, under statute, in equity, at law or otherwise, 86 * even if advised of the possibility of such damage. 87 */ 88 89 #include <sys/cdefs.h> 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/mbuf.h> 95 #include <sys/syslog.h> 96 #include <sys/socket.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 #include <sys/ioctl.h> 100 #include <sys/errno.h> 101 102 #include <net/if.h> 103 #include <net/if_ether.h> 104 #include <net/if_media.h> 105 #include <net/bpf.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #include <sys/bus.h> 113 #include <sys/intr.h> 114 115 #include <dev/ic/dm9000var.h> 116 #include <dev/ic/dm9000reg.h> 117 118 #if 1 119 #undef DM9000_DEBUG 120 #undef DM9000_TX_DEBUG 121 #undef DM9000_TX_DATA_DEBUG 122 #undef DM9000_RX_DEBUG 123 #undef DM9000_RX_DATA_DEBUG 124 #else 125 #define DM9000_DEBUG 126 #define DM9000_TX_DEBUG 127 #define DM9000_TX_DATA_DEBUG 128 #define DM9000_RX_DEBUG 129 #define DM9000_RX_DATA_DEBUG 130 #endif 131 132 #ifdef DM9000_DEBUG 133 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 134 #else 135 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 136 #endif 137 138 #ifdef DM9000_TX_DEBUG 139 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 140 #else 141 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 142 #endif 143 144 #ifdef DM9000_RX_DEBUG 145 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 146 #else 147 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 148 #endif 149 150 #ifdef DM9000_RX_DATA_DEBUG 151 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 152 #else 153 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 154 #endif 155 156 #ifdef DM9000_TX_DATA_DEBUG 157 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 158 #else 159 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 160 #endif 161 162 /*** Internal PHY functions ***/ 163 uint16_t dme_phy_read(struct dme_softc *, int ); 164 void dme_phy_write(struct dme_softc *, int, uint16_t); 165 void dme_phy_init(struct dme_softc *); 166 void dme_phy_reset(struct dme_softc *); 167 void dme_phy_update_media(struct dme_softc *); 168 void dme_phy_check_link(void *); 169 170 /*** Methods registered in struct ifnet ***/ 171 void dme_start_output(struct ifnet *); 172 int dme_init(struct ifnet *); 173 int dme_ioctl(struct ifnet *, u_long, void *); 174 void dme_stop(struct ifnet *, int); 175 176 int dme_mediachange(struct ifnet *); 177 void dme_mediastatus(struct ifnet *, struct ifmediareq *); 178 179 /*** Internal methods ***/ 180 181 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */ 182 void dme_prepare(struct dme_softc *, struct ifnet *); 183 184 /* Transmit prepared data */ 185 void dme_transmit(struct dme_softc *); 186 187 /* Receive data */ 188 void dme_receive(struct dme_softc *, struct ifnet *); 189 190 /* Software Initialize/Reset of the DM9000 */ 191 void dme_reset(struct dme_softc *); 192 193 /* Configure multicast filter */ 194 void dme_set_addr_filter(struct dme_softc *); 195 196 /* Set media */ 197 int dme_set_media(struct dme_softc *, int ); 198 199 /* Read/write packet data from/to DM9000 IC in various transfer sizes */ 200 int dme_pkt_read_2(struct dme_softc *, struct ifnet *, struct mbuf **); 201 int dme_pkt_write_2(struct dme_softc *, struct mbuf *); 202 int dme_pkt_read_1(struct dme_softc *, struct ifnet *, struct mbuf **); 203 int dme_pkt_write_1(struct dme_softc *, struct mbuf *); 204 /* TODO: Implement 32 bit read/write functions */ 205 206 uint16_t 207 dme_phy_read(struct dme_softc *sc, int reg) 208 { 209 uint16_t val; 210 /* Select Register to read*/ 211 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 212 (reg & DM9000_EPAR_EROA_MASK)); 213 /* Select read operation (DM9000_EPCR_ERPRR) from the PHY */ 214 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY); 215 216 /* Wait until access to PHY has completed */ 217 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 218 ; 219 220 /* Reset ERPRR-bit */ 221 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 222 223 val = dme_read(sc, DM9000_EPDRL); 224 val += dme_read(sc, DM9000_EPDRH) << 8; 225 226 return val; 227 } 228 229 void 230 dme_phy_write(struct dme_softc *sc, int reg, uint16_t value) 231 { 232 /* Select Register to write*/ 233 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 234 (reg & DM9000_EPAR_EROA_MASK)); 235 236 /* Write data to the two data registers */ 237 dme_write(sc, DM9000_EPDRL, value & 0xFF); 238 dme_write(sc, DM9000_EPDRH, (value >> 8) & 0xFF); 239 240 /* Select write operation (DM9000_EPCR_ERPRW) from the PHY */ 241 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY); 242 243 /* Wait until access to PHY has completed */ 244 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 245 ; 246 247 /* Reset ERPRR-bit */ 248 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 249 } 250 251 void 252 dme_phy_init(struct dme_softc *sc) 253 { 254 u_int ifm_media = sc->sc_media.ifm_media; 255 uint32_t bmcr, anar; 256 257 bmcr = dme_phy_read(sc, DM9000_PHY_BMCR); 258 anar = dme_phy_read(sc, DM9000_PHY_ANAR); 259 260 anar = anar & ~DM9000_PHY_ANAR_10_HDX 261 & ~DM9000_PHY_ANAR_10_FDX 262 & ~DM9000_PHY_ANAR_TX_HDX 263 & ~DM9000_PHY_ANAR_TX_FDX; 264 265 switch (IFM_SUBTYPE(ifm_media)) { 266 case IFM_AUTO: 267 bmcr |= DM9000_PHY_BMCR_AUTO_NEG_EN; 268 anar |= DM9000_PHY_ANAR_10_HDX | 269 DM9000_PHY_ANAR_10_FDX | 270 DM9000_PHY_ANAR_TX_HDX | 271 DM9000_PHY_ANAR_TX_FDX; 272 break; 273 case IFM_10_T: 274 //bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 275 bmcr &= ~DM9000_PHY_BMCR_SPEED_SELECT; 276 if (ifm_media & IFM_FDX) 277 anar |= DM9000_PHY_ANAR_10_FDX; 278 else 279 anar |= DM9000_PHY_ANAR_10_HDX; 280 break; 281 case IFM_100_TX: 282 //bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 283 bmcr |= DM9000_PHY_BMCR_SPEED_SELECT; 284 if (ifm_media & IFM_FDX) 285 anar |= DM9000_PHY_ANAR_TX_FDX; 286 else 287 anar |= DM9000_PHY_ANAR_TX_HDX; 288 289 break; 290 } 291 292 if (ifm_media & IFM_FDX) 293 bmcr |= DM9000_PHY_BMCR_DUPLEX_MODE; 294 else 295 bmcr &= ~DM9000_PHY_BMCR_DUPLEX_MODE; 296 297 dme_phy_write(sc, DM9000_PHY_BMCR, bmcr); 298 dme_phy_write(sc, DM9000_PHY_ANAR, anar); 299 } 300 301 void 302 dme_phy_reset(struct dme_softc *sc) 303 { 304 uint32_t reg; 305 306 /* PHY Reset */ 307 dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET); 308 309 reg = dme_read(sc, DM9000_GPCR); 310 dme_write(sc, DM9000_GPCR, reg & ~DM9000_GPCR_GPIO0_OUT); 311 reg = dme_read(sc, DM9000_GPR); 312 dme_write(sc, DM9000_GPR, reg | DM9000_GPR_PHY_PWROFF); 313 314 dme_phy_init(sc); 315 316 reg = dme_read(sc, DM9000_GPR); 317 dme_write(sc, DM9000_GPR, reg & ~DM9000_GPR_PHY_PWROFF); 318 reg = dme_read(sc, DM9000_GPCR); 319 dme_write(sc, DM9000_GPCR, reg | DM9000_GPCR_GPIO0_OUT); 320 321 dme_phy_update_media(sc); 322 } 323 324 void 325 dme_phy_update_media(struct dme_softc *sc) 326 { 327 u_int ifm_media = sc->sc_media.ifm_media; 328 uint32_t reg; 329 330 if (IFM_SUBTYPE(ifm_media) == IFM_AUTO) { 331 /* If auto-negotiation is used, ensures that it is completed 332 before trying to extract any media information. */ 333 reg = dme_phy_read(sc, DM9000_PHY_BMSR); 334 if ((reg & DM9000_PHY_BMSR_AUTO_NEG_AB) == 0) { 335 /* Auto-negotation not possible, therefore there is no 336 reason to try obtain any media information. */ 337 return; 338 } 339 340 /* Then loop until the negotiation is completed. */ 341 while ((reg & DM9000_PHY_BMSR_AUTO_NEG_COM) == 0) { 342 /* TODO: Bail out after a finite number of attempts 343 in case something goes wrong. */ 344 preempt(); 345 reg = dme_phy_read(sc, DM9000_PHY_BMSR); 346 } 347 } 348 349 350 sc->sc_media_active = IFM_ETHER; 351 reg = dme_phy_read(sc, DM9000_PHY_BMCR); 352 353 if (reg & DM9000_PHY_BMCR_SPEED_SELECT) 354 sc->sc_media_active |= IFM_100_TX; 355 else 356 sc->sc_media_active |= IFM_10_T; 357 358 if (reg & DM9000_PHY_BMCR_DUPLEX_MODE) 359 sc->sc_media_active |= IFM_FDX; 360 } 361 362 void 363 dme_phy_check_link(void *arg) 364 { 365 struct dme_softc *sc = arg; 366 uint32_t reg; 367 int s; 368 369 s = splnet(); 370 371 reg = dme_read(sc, DM9000_NSR) & DM9000_NSR_LINKST; 372 373 if (reg) 374 reg = IFM_ETHER | IFM_AVALID | IFM_ACTIVE; 375 else { 376 reg = IFM_ETHER | IFM_AVALID; 377 sc->sc_media_active = IFM_NONE; 378 } 379 380 if ((sc->sc_media_status != reg) && (reg & IFM_ACTIVE)) 381 dme_phy_reset(sc); 382 383 sc->sc_media_status = reg; 384 385 callout_schedule(&sc->sc_link_callout, mstohz(2000)); 386 splx(s); 387 } 388 389 int 390 dme_set_media(struct dme_softc *sc, int media) 391 { 392 int s; 393 394 s = splnet(); 395 sc->sc_media.ifm_media = media; 396 dme_phy_reset(sc); 397 398 splx(s); 399 400 return 0; 401 } 402 403 int 404 dme_attach(struct dme_softc *sc, const uint8_t *enaddr) 405 { 406 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 407 uint8_t b[2]; 408 uint16_t io_mode; 409 410 dme_read_c(sc, DM9000_VID0, b, 2); 411 #if BYTE_ORDER == BIG_ENDIAN 412 sc->sc_vendor_id = (b[0] << 8) | b[1]; 413 #else 414 sc->sc_vendor_id = b[0] | (b[1] << 8); 415 #endif 416 dme_read_c(sc, DM9000_PID0, b, 2); 417 #if BYTE_ORDER == BIG_ENDIAN 418 sc->sc_product_id = (b[0] << 8) | b[1]; 419 #else 420 sc->sc_product_id = b[0] | (b[1] << 8); 421 #endif 422 /* TODO: Check the vendor ID as well */ 423 if (sc->sc_product_id != 0x9000) { 424 panic("dme_attach: product id mismatch (0x%hx != 0x9000)", 425 sc->sc_product_id); 426 } 427 428 /* Initialize ifnet structure. */ 429 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 430 ifp->if_softc = sc; 431 ifp->if_start = dme_start_output; 432 ifp->if_init = dme_init; 433 ifp->if_ioctl = dme_ioctl; 434 ifp->if_stop = dme_stop; 435 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 436 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 437 IFQ_SET_READY(&ifp->if_snd); 438 439 /* Initialize ifmedia structures. */ 440 sc->sc_ethercom.ec_ifmedia = &sc->sc_media; 441 ifmedia_init(&sc->sc_media, 0, dme_mediachange, dme_mediastatus); 442 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 443 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 444 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); 445 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 446 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); 447 448 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 449 450 if (enaddr != NULL) 451 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 452 /* TODO: Support an EEPROM attached to the DM9000 chip */ 453 454 callout_init(&sc->sc_link_callout, 0); 455 callout_setfunc(&sc->sc_link_callout, dme_phy_check_link, sc); 456 457 sc->sc_media_status = 0; 458 459 /* Configure DM9000 with the MAC address */ 460 dme_write_c(sc, DM9000_PAB0, sc->sc_enaddr, 6); 461 462 #ifdef DM9000_DEBUG 463 { 464 uint8_t macAddr[6]; 465 dme_read_c(sc, DM9000_PAB0, macAddr, 6); 466 printf("DM9000 configured with MAC address: "); 467 for (int i = 0; i < 6; i++) 468 printf("%02X:", macAddr[i]); 469 printf("\n"); 470 } 471 #endif 472 473 if_attach(ifp); 474 ether_ifattach(ifp, sc->sc_enaddr); 475 476 #ifdef DM9000_DEBUG 477 { 478 uint8_t network_state; 479 network_state = dme_read(sc, DM9000_NSR); 480 printf("DM9000 Link status: "); 481 if (network_state & DM9000_NSR_LINKST) { 482 if (network_state & DM9000_NSR_SPEED) 483 printf("10Mbps"); 484 else 485 printf("100Mbps"); 486 } else 487 printf("Down"); 488 printf("\n"); 489 } 490 #endif 491 492 io_mode = (dme_read(sc, DM9000_ISR) & 493 DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT; 494 495 DPRINTF(("DM9000 Operation Mode: ")); 496 switch (io_mode) { 497 case DM9000_MODE_16BIT: 498 DPRINTF(("16-bit mode")); 499 sc->sc_data_width = 2; 500 sc->sc_pkt_write = dme_pkt_write_2; 501 sc->sc_pkt_read = dme_pkt_read_2; 502 break; 503 case DM9000_MODE_32BIT: 504 DPRINTF(("32-bit mode")); 505 sc->sc_data_width = 4; 506 panic("32bit mode is unsupported\n"); 507 break; 508 case DM9000_MODE_8BIT: 509 DPRINTF(("8-bit mode")); 510 sc->sc_data_width = 1; 511 sc->sc_pkt_write = dme_pkt_write_1; 512 sc->sc_pkt_read = dme_pkt_read_1; 513 break; 514 default: 515 DPRINTF(("Invalid mode")); 516 break; 517 } 518 DPRINTF(("\n")); 519 520 callout_schedule(&sc->sc_link_callout, mstohz(2000)); 521 522 return 0; 523 } 524 525 int dme_intr(void *arg) 526 { 527 struct dme_softc *sc = arg; 528 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 529 uint8_t status; 530 531 532 DPRINTF(("dme_intr: Begin\n")); 533 534 /* Disable interrupts */ 535 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR ); 536 537 status = dme_read(sc, DM9000_ISR); 538 dme_write(sc, DM9000_ISR, status); 539 540 if (status & DM9000_ISR_PRS) { 541 if (ifp->if_flags & IFF_RUNNING ) 542 dme_receive(sc, ifp); 543 } 544 if (status & DM9000_ISR_PTS) { 545 uint8_t nsr; 546 uint8_t tx_status = 0x01; /* Initialize to an error value */ 547 548 /* A packet has been transmitted */ 549 sc->txbusy = 0; 550 551 nsr = dme_read(sc, DM9000_NSR); 552 553 if (nsr & DM9000_NSR_TX1END) { 554 tx_status = dme_read(sc, DM9000_TSR1); 555 TX_DPRINTF(("dme_intr: Sent using channel 0\n")); 556 } else if (nsr & DM9000_NSR_TX2END) { 557 tx_status = dme_read(sc, DM9000_TSR2); 558 TX_DPRINTF(("dme_intr: Sent using channel 1\n")); 559 } 560 561 if (tx_status == 0x0) { 562 /* Frame successfully sent */ 563 ifp->if_opackets++; 564 } else { 565 ifp->if_oerrors++; 566 } 567 568 /* If we have nothing ready to transmit, prepare something */ 569 if (!sc->txready) 570 dme_prepare(sc, ifp); 571 572 if (sc->txready) 573 dme_transmit(sc); 574 575 /* Prepare the next frame */ 576 dme_prepare(sc, ifp); 577 578 } 579 #ifdef notyet 580 if (status & DM9000_ISR_LNKCHNG) { 581 } 582 #endif 583 584 /* Enable interrupts again */ 585 dme_write(sc, DM9000_IMR, 586 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 587 588 DPRINTF(("dme_intr: End\n")); 589 590 return 1; 591 } 592 593 void 594 dme_start_output(struct ifnet *ifp) 595 { 596 struct dme_softc *sc; 597 598 sc = ifp->if_softc; 599 600 DPRINTF(("dme_start_output: Begin\n")); 601 602 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 603 printf("No output\n"); 604 return; 605 } 606 607 if (sc->txbusy && sc->txready) 608 panic("DM9000: Internal error, trying to send without" 609 " any empty queue\n"); 610 611 dme_prepare(sc, ifp); 612 613 if (sc->txbusy == 0) { 614 /* We are ready to transmit right away */ 615 dme_transmit(sc); 616 dme_prepare(sc, ifp); /* Prepare next one */ 617 } else { 618 /* We need to wait until the current packet has 619 * been transmitted. 620 */ 621 ifp->if_flags |= IFF_OACTIVE; 622 } 623 624 DPRINTF(("dme_start_output: End\n")); 625 } 626 627 void 628 dme_prepare(struct dme_softc *sc, struct ifnet *ifp) 629 { 630 struct mbuf *bufChain; 631 uint16_t length; 632 633 TX_DPRINTF(("dme_prepare: Entering\n")); 634 635 if (sc->txready) 636 panic("dme_prepare: Someone called us with txready set\n"); 637 638 IFQ_DEQUEUE(&ifp->if_snd, bufChain); 639 if (bufChain == NULL) { 640 TX_DPRINTF(("dme_prepare: Nothing to transmit\n")); 641 ifp->if_flags &= ~IFF_OACTIVE; /* Clear OACTIVE bit */ 642 return; /* Nothing to transmit */ 643 } 644 645 /* Element has now been removed from the queue, so we better send it */ 646 647 bpf_mtap(ifp, bufChain, BPF_D_OUT); 648 649 /* Setup the DM9000 to accept the writes, and then write each buf in 650 the chain. */ 651 652 TX_DATA_DPRINTF(("dme_prepare: Writing data: ")); 653 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD); 654 length = sc->sc_pkt_write(sc, bufChain); 655 TX_DATA_DPRINTF(("\n")); 656 657 if (length % sc->sc_data_width != 0) 658 panic("dme_prepare: length is not compatible with IO_MODE"); 659 660 sc->txready_length = length; 661 sc->txready = 1; 662 663 TX_DPRINTF(("dme_prepare: txbusy: %d\ndme_prepare: " 664 "txready: %d, txready_length: %d\n", 665 sc->txbusy, sc->txready, sc->txready_length)); 666 667 m_freem(bufChain); 668 669 TX_DPRINTF(("dme_prepare: Leaving\n")); 670 } 671 672 int 673 dme_init(struct ifnet *ifp) 674 { 675 int s; 676 struct dme_softc *sc = ifp->if_softc; 677 678 dme_stop(ifp, 0); 679 680 s = splnet(); 681 682 dme_reset(sc); 683 684 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 685 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 686 sc->sc_ethercom.ec_if.if_timer = 0; 687 688 splx(s); 689 690 return 0; 691 } 692 693 int 694 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data) 695 { 696 struct dme_softc *sc = ifp->if_softc; 697 int s, error = 0; 698 699 s = splnet(); 700 701 switch (cmd) { 702 default: 703 error = ether_ioctl(ifp, cmd, data); 704 if (error == ENETRESET) { 705 if (ifp->if_flags && IFF_RUNNING) { 706 /* Address list has changed, reconfigure 707 filter */ 708 dme_set_addr_filter(sc); 709 } 710 error = 0; 711 } 712 break; 713 } 714 715 splx(s); 716 return error; 717 } 718 719 void 720 dme_stop(struct ifnet *ifp, int disable) 721 { 722 struct dme_softc *sc = ifp->if_softc; 723 724 /* Not quite sure what to do when called with disable == 0 */ 725 if (disable) { 726 /* Disable RX */ 727 dme_write(sc, DM9000_RCR, 0x0); 728 } 729 730 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 731 ifp->if_timer = 0; 732 } 733 734 int 735 dme_mediachange(struct ifnet *ifp) 736 { 737 struct dme_softc *sc = ifp->if_softc; 738 739 return dme_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 740 } 741 742 void 743 dme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 744 { 745 struct dme_softc *sc = ifp->if_softc; 746 747 ifmr->ifm_active = sc->sc_media_active; 748 ifmr->ifm_status = sc->sc_media_status; 749 } 750 751 void 752 dme_transmit(struct dme_softc *sc) 753 { 754 755 TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n", 756 sc->txready, sc->txbusy)); 757 758 dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff); 759 dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff ); 760 761 /* Request to send the packet */ 762 dme_read(sc, DM9000_ISR); 763 764 dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ); 765 766 sc->txready = 0; 767 sc->txbusy = 1; 768 sc->txready_length = 0; 769 } 770 771 void 772 dme_receive(struct dme_softc *sc, struct ifnet *ifp) 773 { 774 uint8_t ready = 0x01; 775 776 DPRINTF(("inside dme_receive\n")); 777 778 while (ready == 0x01) { 779 /* Packet received, retrieve it */ 780 781 /* Read without address increment to get the ready byte without 782 moving past it. */ 783 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 784 sc->dme_io, DM9000_MRCMDX); 785 /* Dummy ready */ 786 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 787 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 788 ready &= 0x03; /* we only want bits 1:0 */ 789 if (ready == 0x01) { 790 uint8_t rx_status; 791 struct mbuf *m; 792 793 /* Read with address increment. */ 794 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 795 sc->dme_io, DM9000_MRCMD); 796 797 rx_status = sc->sc_pkt_read(sc, ifp, &m); 798 if (m == NULL) { 799 /* failed to allocate a receive buffer */ 800 ifp->if_ierrors++; 801 RX_DPRINTF(("dme_receive: " 802 "Error allocating buffer\n")); 803 } else if (rx_status & (DM9000_RSR_CE | DM9000_RSR_PLE)) { 804 /* Error while receiving the packet, 805 * discard it and keep track of counters 806 */ 807 ifp->if_ierrors++; 808 RX_DPRINTF(("dme_receive: " 809 "Error reciving packet\n")); 810 } else if (rx_status & DM9000_RSR_LCS) { 811 ifp->if_collisions++; 812 } else { 813 if_percpuq_enqueue(ifp->if_percpuq, m); 814 } 815 816 } else if (ready != 0x00) { 817 /* Should this be logged somehow? */ 818 printf("%s: Resetting chip\n", 819 device_xname(sc->sc_dev)); 820 dme_reset(sc); 821 } 822 } 823 } 824 825 void 826 dme_reset(struct dme_softc *sc) 827 { 828 uint8_t var; 829 830 /* We only re-initialized the PHY in this function the first time it is 831 called. */ 832 if (!sc->sc_phy_initialized) { 833 /* PHY Reset */ 834 dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET); 835 836 /* PHY Power Down */ 837 var = dme_read(sc, DM9000_GPR); 838 dme_write(sc, DM9000_GPR, var | DM9000_GPR_PHY_PWROFF); 839 } 840 841 /* Reset the DM9000 twice, as described in section 2 of the Programming 842 Guide. 843 The PHY is initialized and enabled between those two resets. 844 */ 845 846 /* Software Reset*/ 847 dme_write(sc, DM9000_NCR, 848 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 849 delay(20); 850 dme_write(sc, DM9000_NCR, 0x0); 851 852 if (!sc->sc_phy_initialized) { 853 /* PHY Initialization */ 854 dme_phy_init(sc); 855 856 /* PHY Enable */ 857 var = dme_read(sc, DM9000_GPR); 858 dme_write(sc, DM9000_GPR, var & ~DM9000_GPR_PHY_PWROFF); 859 var = dme_read(sc, DM9000_GPCR); 860 dme_write(sc, DM9000_GPCR, var | DM9000_GPCR_GPIO0_OUT); 861 862 dme_write(sc, DM9000_NCR, 863 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 864 delay(20); 865 dme_write(sc, DM9000_NCR, 0x0); 866 } 867 868 /* Select internal PHY, no wakeup event, no collosion mode, 869 * normal loopback mode. 870 */ 871 dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL ); 872 873 /* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/ 874 dme_read(sc, DM9000_NSR); 875 876 /* Enable wraparound of read/write pointer, packet received latch, 877 * and packet transmitted latch. 878 */ 879 dme_write(sc, DM9000_IMR, 880 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 881 882 /* Setup multicast address filter, and enable RX. */ 883 dme_set_addr_filter(sc); 884 885 /* Obtain media information from PHY */ 886 dme_phy_update_media(sc); 887 888 sc->txbusy = 0; 889 sc->txready = 0; 890 sc->sc_phy_initialized = 1; 891 } 892 893 void 894 dme_set_addr_filter(struct dme_softc *sc) 895 { 896 struct ether_multi *enm; 897 struct ether_multistep step; 898 struct ethercom *ec; 899 struct ifnet *ifp; 900 uint16_t af[4]; 901 int i; 902 903 ec = &sc->sc_ethercom; 904 ifp = &ec->ec_if; 905 906 if (ifp->if_flags & IFF_PROMISC) { 907 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | 908 DM9000_RCR_WTDIS | 909 DM9000_RCR_PRMSC); 910 ifp->if_flags |= IFF_ALLMULTI; 911 return; 912 } 913 914 af[0] = af[1] = af[2] = af[3] = 0x0000; 915 ifp->if_flags &= ~IFF_ALLMULTI; 916 917 ETHER_LOCK(ec); 918 ETHER_FIRST_MULTI(step, ec, enm); 919 while (enm != NULL) { 920 uint16_t hash; 921 if (memcpy(enm->enm_addrlo, enm->enm_addrhi, 922 sizeof(enm->enm_addrlo))) { 923 /* 924 * We must listen to a range of multicast addresses. 925 * For now, just accept all multicasts, rather than 926 * trying to set only those filter bits needed to match 927 * the range. (At this time, the only use of address 928 * ranges is for IP multicast routing, for which the 929 * range is big enough to require all bits set.) 930 */ 931 ifp->if_flags |= IFF_ALLMULTI; 932 af[0] = af[1] = af[2] = af[3] = 0xffff; 933 break; 934 } else { 935 hash = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3F; 936 af[(uint16_t)(hash>>4)] |= (uint16_t)(1 << (hash % 16)); 937 ETHER_NEXT_MULTI(step, enm); 938 } 939 } 940 ETHER_UNLOCK(ec); 941 942 /* Write the multicast address filter */ 943 for (i = 0; i < 4; i++) { 944 dme_write(sc, DM9000_MAB0+i*2, af[i] & 0xFF); 945 dme_write(sc, DM9000_MAB0+i*2+1, (af[i] >> 8) & 0xFF); 946 } 947 948 /* Setup RX controls */ 949 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | DM9000_RCR_WTDIS); 950 } 951 952 int 953 dme_pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain) 954 { 955 int left_over_count = 0; /* Number of bytes from previous mbuf, which 956 need to be written with the next.*/ 957 uint16_t left_over_buf = 0; 958 int length = 0; 959 struct mbuf *buf; 960 uint8_t *write_ptr; 961 962 /* We expect that the DM9000 has been setup to accept writes before 963 this function is called. */ 964 965 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 966 int to_write = buf->m_len; 967 968 length += to_write; 969 970 write_ptr = buf->m_data; 971 while (to_write > 0 || 972 (buf->m_next == NULL && left_over_count > 0)) { 973 if (left_over_count > 0) { 974 uint8_t b = 0; 975 DPRINTF(("dme_pkt_write_16: " 976 "Writing left over byte\n")); 977 978 if (to_write > 0) { 979 b = *write_ptr; 980 to_write--; 981 write_ptr++; 982 983 DPRINTF(("Took single byte\n")); 984 } else { 985 DPRINTF(("Leftover in last run\n")); 986 length++; 987 } 988 989 /* Does shift direction depend on endianess? */ 990 left_over_buf = left_over_buf | (b << 8); 991 992 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 993 sc->dme_data, left_over_buf); 994 TX_DATA_DPRINTF(("%02X ", left_over_buf)); 995 left_over_count = 0; 996 } else if ((long)write_ptr % 2 != 0) { 997 /* Misaligned data */ 998 DPRINTF(("dme_pkt_write_16: " 999 "Detected misaligned data\n")); 1000 left_over_buf = *write_ptr; 1001 left_over_count = 1; 1002 write_ptr++; 1003 to_write--; 1004 } else { 1005 int i; 1006 uint16_t *dptr = (uint16_t *)write_ptr; 1007 1008 /* A block of aligned data. */ 1009 for (i = 0; i < to_write / 2; i++) { 1010 /* buf will be half-word aligned 1011 * all the time 1012 */ 1013 bus_space_write_2(sc->sc_iot, 1014 sc->sc_ioh, sc->dme_data, *dptr); 1015 TX_DATA_DPRINTF(("%02X %02X ", 1016 *dptr & 0xFF, (*dptr >> 8) & 0xFF)); 1017 dptr++; 1018 } 1019 1020 write_ptr += i * 2; 1021 if (to_write % 2 != 0) { 1022 DPRINTF(("dme_pkt_write_16: " 1023 "to_write %% 2: %d\n", 1024 to_write % 2)); 1025 left_over_count = 1; 1026 /* XXX: Does this depend on 1027 * the endianess? 1028 */ 1029 left_over_buf = *write_ptr; 1030 1031 write_ptr++; 1032 to_write--; 1033 DPRINTF(("dme_pkt_write_16: " 1034 "to_write (after): %d\n", 1035 to_write)); 1036 DPRINTF(("dme_pkt_write_16: i * 2: %d\n", 1037 i*2)); 1038 } 1039 to_write -= i * 2; 1040 } 1041 } /* while (...) */ 1042 } /* for (...) */ 1043 1044 return length; 1045 } 1046 1047 int 1048 dme_pkt_read_2(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf) 1049 { 1050 uint8_t rx_status; 1051 struct mbuf *m; 1052 uint16_t data; 1053 uint16_t frame_length; 1054 uint16_t i; 1055 uint16_t *buf; 1056 1057 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1058 1059 rx_status = data & 0xFF; 1060 frame_length = bus_space_read_2(sc->sc_iot, 1061 sc->sc_ioh, sc->dme_data); 1062 if (frame_length > ETHER_MAX_LEN) { 1063 printf("Got frame of length: %d\n", frame_length); 1064 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1065 panic("Something is rotten"); 1066 } 1067 RX_DPRINTF(("dme_receive: rx_statux: 0x%x, frame_length: %d\n", 1068 rx_status, frame_length)); 1069 1070 1071 m = dme_alloc_receive_buffer(ifp, frame_length); 1072 if (m == NULL) { 1073 /* 1074 * didn't get a receive buffer, so we read the rest of the 1075 * packet, throw it away and return an error 1076 */ 1077 for (i = 0; i < frame_length; i += 2 ) { 1078 data = bus_space_read_2(sc->sc_iot, 1079 sc->sc_ioh, sc->dme_data); 1080 } 1081 *outBuf = NULL; 1082 return 0; 1083 } 1084 1085 buf = mtod(m, uint16_t*); 1086 1087 RX_DPRINTF(("dme_receive: ")); 1088 1089 for (i = 0; i < frame_length; i += 2 ) { 1090 data = bus_space_read_2(sc->sc_iot, 1091 sc->sc_ioh, sc->dme_data); 1092 if ( (frame_length % 2 != 0) && 1093 (i == frame_length - 1) ) { 1094 data = data & 0xff; 1095 RX_DPRINTF((" L ")); 1096 } 1097 *buf = data; 1098 buf++; 1099 RX_DATA_DPRINTF(("%02X %02X ", data & 0xff, 1100 (data >> 8) & 0xff)); 1101 } 1102 1103 RX_DATA_DPRINTF(("\n")); 1104 RX_DPRINTF(("Read %d bytes\n", i)); 1105 1106 *outBuf = m; 1107 return rx_status; 1108 } 1109 1110 int 1111 dme_pkt_write_1(struct dme_softc *sc, struct mbuf *bufChain) 1112 { 1113 int length = 0, i; 1114 struct mbuf *buf; 1115 uint8_t *write_ptr; 1116 1117 /* 1118 * We expect that the DM9000 has been setup to accept writes before 1119 * this function is called. 1120 */ 1121 1122 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 1123 int to_write = buf->m_len; 1124 1125 length += to_write; 1126 1127 write_ptr = buf->m_data; 1128 for (i = 0; i < to_write; i++) { 1129 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1130 sc->dme_data, *write_ptr); 1131 write_ptr++; 1132 } 1133 } /* for (...) */ 1134 1135 return length; 1136 } 1137 1138 int 1139 dme_pkt_read_1(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf) 1140 { 1141 uint8_t rx_status; 1142 struct mbuf *m; 1143 uint8_t *buf; 1144 uint16_t frame_length; 1145 uint16_t i, reg; 1146 uint8_t data; 1147 1148 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1149 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1150 rx_status = reg & 0xFF; 1151 1152 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1153 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1154 frame_length = reg; 1155 1156 if (frame_length > ETHER_MAX_LEN) { 1157 printf("Got frame of length: %d\n", frame_length); 1158 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1159 panic("Something is rotten"); 1160 } 1161 RX_DPRINTF(("dme_receive: " 1162 "rx_statux: 0x%x, frame_length: %d\n", 1163 rx_status, frame_length)); 1164 1165 1166 m = dme_alloc_receive_buffer(ifp, frame_length); 1167 if (m == NULL) { 1168 /* 1169 * didn't get a receive buffer, so we read the rest of the 1170 * packet, throw it away and return an error 1171 */ 1172 for (i = 0; i < frame_length; i++ ) { 1173 data = bus_space_read_2(sc->sc_iot, 1174 sc->sc_ioh, sc->dme_data); 1175 } 1176 *outBuf = NULL; 1177 return 0; 1178 } 1179 1180 buf = mtod(m, uint8_t *); 1181 1182 RX_DPRINTF(("dme_receive: ")); 1183 1184 for (i = 0; i< frame_length; i += 1 ) { 1185 data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1186 *buf = data; 1187 buf++; 1188 RX_DATA_DPRINTF(("%02X ", data)); 1189 } 1190 1191 RX_DATA_DPRINTF(("\n")); 1192 RX_DPRINTF(("Read %d bytes\n", i)); 1193 1194 *outBuf = m; 1195 return rx_status; 1196 } 1197 1198 struct mbuf* 1199 dme_alloc_receive_buffer(struct ifnet *ifp, unsigned int frame_length) 1200 { 1201 struct dme_softc *sc = ifp->if_softc; 1202 struct mbuf *m; 1203 int pad; 1204 1205 MGETHDR(m, M_DONTWAIT, MT_DATA); 1206 if (m == NULL) return NULL; 1207 1208 m_set_rcvif(m, ifp); 1209 /* Ensure that we always allocate an even number of 1210 * bytes in order to avoid writing beyond the buffer 1211 */ 1212 m->m_pkthdr.len = frame_length + (frame_length % sc->sc_data_width); 1213 pad = ALIGN(sizeof(struct ether_header)) - 1214 sizeof(struct ether_header); 1215 /* All our frames have the CRC attached */ 1216 m->m_flags |= M_HASFCS; 1217 if (m->m_pkthdr.len + pad > MHLEN) { 1218 MCLGET(m, M_DONTWAIT); 1219 if ((m->m_flags & M_EXT) == 0) { 1220 m_freem(m); 1221 return NULL; 1222 } 1223 } 1224 1225 m->m_data += pad; 1226 m->m_len = frame_length + (frame_length % sc->sc_data_width); 1227 1228 return m; 1229 } 1230
Indexes created Fri Sep 26 20:09:58 GMT 2025