dm9000.c revision 1.27
1 /* $NetBSD: dm9000.c,v 1.27 2020/04/02 07:26:45 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* based on sys/dev/ic/cs89x0.c */ 30 /* 31 * Copyright (c) 2004 Christopher Gilbert 32 * All rights reserved. 33 * 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The name of the company nor the name of the author may be used to 40 * endorse or promote products derived from this software without specific 41 * prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright 1997 58 * Digital Equipment Corporation. All rights reserved. 59 * 60 * This software is furnished under license and may be used and 61 * copied only in accordance with the following terms and conditions. 62 * Subject to these conditions, you may download, copy, install, 63 * use, modify and distribute this software in source and/or binary 64 * form. No title or ownership is transferred hereby. 65 * 66 * 1) Any source code used, modified or distributed must reproduce 67 * and retain this copyright notice and list of conditions as 68 * they appear in the source file. 69 * 70 * 2) No right is granted to use any trade name, trademark, or logo of 71 * Digital Equipment Corporation. Neither the "Digital Equipment 72 * Corporation" name nor any trademark or logo of Digital Equipment 73 * Corporation may be used to endorse or promote products derived 74 * from this software without the prior written permission of 75 * Digital Equipment Corporation. 76 * 77 * 3) This software is provided "AS-IS" and any express or implied 78 * warranties, including but not limited to, any implied warranties 79 * of merchantability, fitness for a particular purpose, or 80 * non-infringement are disclaimed. In no event shall DIGITAL be 81 * liable for any damages whatsoever, and in particular, DIGITAL 82 * shall not be liable for special, indirect, consequential, or 83 * incidental damages or damages for lost profits, loss of 84 * revenue or loss of use, whether such damages arise in contract, 85 * negligence, tort, under statute, in equity, at law or otherwise, 86 * even if advised of the possibility of such damage. 87 */ 88 89 #include <sys/cdefs.h> 90 91 #include <sys/param.h> 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 #include <sys/device.h> 95 #include <sys/mbuf.h> 96 #include <sys/sockio.h> 97 #include <sys/malloc.h> 98 #include <sys/errno.h> 99 #include <sys/cprng.h> 100 #include <sys/rndsource.h> 101 #include <sys/kernel.h> 102 #include <sys/systm.h> 103 104 #include <net/if.h> 105 #include <net/if_dl.h> 106 #include <net/if_ether.h> 107 #include <net/if_media.h> 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 #include <net/bpf.h> 111 112 #include <dev/ic/dm9000var.h> 113 #include <dev/ic/dm9000reg.h> 114 115 #if 1 116 #undef DM9000_DEBUG 117 #undef DM9000_TX_DEBUG 118 #undef DM9000_TX_DATA_DEBUG 119 #undef DM9000_RX_DEBUG 120 #undef DM9000_RX_DATA_DEBUG 121 #else 122 #define DM9000_DEBUG 123 #define DM9000_TX_DEBUG 124 #define DM9000_TX_DATA_DEBUG 125 #define DM9000_RX_DEBUG 126 #define DM9000_RX_DATA_DEBUG 127 #endif 128 129 #ifdef DM9000_DEBUG 130 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 131 #else 132 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 133 #endif 134 135 #ifdef DM9000_TX_DEBUG 136 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 137 #else 138 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 139 #endif 140 141 #ifdef DM9000_RX_DEBUG 142 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 143 #else 144 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 145 #endif 146 147 #ifdef DM9000_RX_DATA_DEBUG 148 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 149 #else 150 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 151 #endif 152 153 #ifdef DM9000_TX_DATA_DEBUG 154 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 155 #else 156 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 157 #endif 158 159 static void dme_reset(struct dme_softc *); 160 static int dme_init(struct ifnet *); 161 static void dme_stop(struct ifnet *, int); 162 static void dme_start(struct ifnet *); 163 static int dme_ioctl(struct ifnet *, u_long, void *); 164 165 static void dme_set_rcvfilt(struct dme_softc *); 166 static void mii_statchg(struct ifnet *); 167 static void lnkchg(struct dme_softc *); 168 static void phy_tick(void *); 169 static int mii_readreg(device_t, int, int, uint16_t *); 170 static int mii_writereg(device_t, int, int, uint16_t); 171 172 static void dme_prepare(struct ifnet *); 173 static void dme_transmit(struct ifnet *); 174 static void dme_receive(struct ifnet *); 175 176 static int pkt_read_2(struct dme_softc *, struct mbuf **); 177 static int pkt_write_2(struct dme_softc *, struct mbuf *); 178 static int pkt_read_1(struct dme_softc *, struct mbuf **); 179 static int pkt_write_1(struct dme_softc *, struct mbuf *); 180 #define PKT_READ(ii,m) (*(ii)->sc_pkt_read)((ii),(m)) 181 #define PKT_WRITE(ii,m) (*(ii)->sc_pkt_write)((ii),(m)) 182 183 #define ETHER_IS_ONE(x) \ 184 (((x)[0] & (x)[1] & (x)[2] & (x)[3] & (x)[4] & (x)[5]) == 255) 185 #define ETHER_IS_ZERO(x) \ 186 (((x)[0] | (x)[1] | (x)[2] | (x)[3] | (x)[4] | (x)[5]) == 0) 187 188 int 189 dme_attach(struct dme_softc *sc, const uint8_t *notusedanymore) 190 { 191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 192 struct mii_data *mii = &sc->sc_mii; 193 struct ifmedia *ifm = &mii->mii_media; 194 uint8_t b[2]; 195 uint16_t io_mode; 196 uint8_t enaddr[ETHER_ADDR_LEN]; 197 prop_dictionary_t dict; 198 prop_data_t ea; 199 200 dme_read_c(sc, DM9000_VID0, b, 2); 201 sc->sc_vendor_id = le16toh((uint16_t)b[1] << 8 | b[0]); 202 dme_read_c(sc, DM9000_PID0, b, 2); 203 sc->sc_product_id = le16toh((uint16_t)b[1] << 8 | b[0]); 204 205 /* TODO: Check the vendor ID as well */ 206 if (sc->sc_product_id != 0x9000) { 207 panic("dme_attach: product id mismatch (0x%hx != 0x9000)", 208 sc->sc_product_id); 209 } 210 #if 1 || DM9000_DEBUG 211 { 212 dme_read_c(sc, DM9000_PAB0, enaddr, 6); 213 aprint_normal_dev(sc->sc_dev, 214 "DM9000 was configured with MAC address: %s\n", 215 ether_sprintf(enaddr)); 216 } 217 #endif 218 dict = device_properties(sc->sc_dev); 219 ea = (dict) ? prop_dictionary_get(dict, "mac-address") : NULL; 220 if (ea != NULL) { 221 /* 222 * If the MAC address is overriden by a device property, 223 * use that. 224 */ 225 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 226 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 227 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 228 } else { 229 /* 230 * If we did not get an externaly configure address, 231 * try to read one from the current setup, before 232 * resetting the chip. 233 */ 234 dme_read_c(sc, DM9000_PAB0, enaddr, 6); 235 if (ETHER_IS_ONE(enaddr) || ETHER_IS_ZERO(enaddr)) { 236 /* make a random MAC address */ 237 uint32_t maclo = 0x00f2 | (cprng_strong32() << 16); 238 uint32_t machi = cprng_strong32(); 239 enaddr[0] = maclo; 240 enaddr[1] = maclo >> 8; 241 enaddr[2] = maclo >> 16; 242 enaddr[3] = maclo >> 26; 243 enaddr[4] = machi; 244 enaddr[5] = machi >> 8; 245 } 246 } 247 /* TODO: perform explicit EEPROM read op if it's availble */ 248 249 dme_reset(sc); 250 251 mii->mii_ifp = ifp; 252 mii->mii_readreg = mii_readreg; 253 mii->mii_writereg = mii_writereg; 254 mii->mii_statchg = mii_statchg; 255 256 /* assume davicom PHY at 1. ext PHY could be hooked but only at 0-3 */ 257 sc->sc_ethercom.ec_mii = mii; 258 ifmedia_init(ifm, 0, ether_mediachange, ether_mediastatus); 259 mii_attach(sc->sc_dev, mii, 0xffffffff, 1 /* PHY 1 */, 260 MII_OFFSET_ANY, 0); 261 if (LIST_FIRST(&mii->mii_phys) == NULL) { 262 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 263 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 264 } else 265 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 266 ifm->ifm_media = ifm->ifm_cur->ifm_media; 267 268 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 269 ifp->if_softc = sc; 270 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 271 ifp->if_init = dme_init; 272 ifp->if_start = dme_start; 273 ifp->if_stop = dme_stop; 274 ifp->if_ioctl = dme_ioctl; 275 ifp->if_watchdog = NULL; /* no watchdog used */ 276 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 277 IFQ_SET_READY(&ifp->if_snd); 278 279 if_attach(ifp); 280 ether_ifattach(ifp, enaddr); 281 if_deferred_start_init(ifp, NULL); 282 283 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 284 RND_TYPE_NET, RND_FLAG_DEFAULT); 285 286 /* might be unnecessary as link change interrupt works well */ 287 callout_init(&sc->sc_link_callout, 0); 288 callout_setfunc(&sc->sc_link_callout, phy_tick, sc); 289 290 io_mode = (dme_read(sc, DM9000_ISR) & 291 DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT; 292 293 /* frame body read/write ops in 2 byte quantity or byte-wise. */ 294 DPRINTF(("DM9000 Operation Mode: ")); 295 switch (io_mode) { 296 case DM9000_MODE_8BIT: 297 DPRINTF(("8-bit mode")); 298 sc->sc_data_width = 1; 299 sc->sc_pkt_write = pkt_write_1; 300 sc->sc_pkt_read = pkt_read_1; 301 break; 302 case DM9000_MODE_16BIT: 303 DPRINTF(("16-bit mode")); 304 sc->sc_data_width = 2; 305 sc->sc_pkt_write = pkt_write_2; 306 sc->sc_pkt_read = pkt_read_2; 307 break; 308 case DM9000_MODE_32BIT: 309 DPRINTF(("32-bit mode")); 310 sc->sc_data_width = 4; 311 panic("32bit mode is unsupported\n"); 312 break; 313 default: 314 DPRINTF(("Invalid mode")); 315 break; 316 } 317 DPRINTF(("\n")); 318 319 return 0; 320 } 321 322 int 323 dme_detach(struct dme_softc *sc) 324 { 325 return 0; 326 } 327 328 /* Software Initialize/Reset of the DM9000 */ 329 static void 330 dme_reset(struct dme_softc *sc) 331 { 332 uint8_t misc; 333 334 /* We only re-initialized the PHY in this function the first time it is 335 * called. */ 336 if (!sc->sc_phy_initialized) { 337 /* PHY Reset */ 338 mii_writereg(sc->sc_dev, 1, MII_BMCR, BMCR_RESET); 339 340 /* PHY Power Down */ 341 misc = dme_read(sc, DM9000_GPR); 342 dme_write(sc, DM9000_GPR, misc | DM9000_GPR_PHY_PWROFF); 343 } 344 345 /* Reset the DM9000 twice, as described in section 2 of the Programming 346 * Guide. 347 * The PHY is initialized and enabled between those two resets. 348 */ 349 350 /* Software Reset */ 351 dme_write(sc, DM9000_NCR, 352 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 353 delay(20); 354 dme_write(sc, DM9000_NCR, 0x0); 355 356 if (!sc->sc_phy_initialized) { 357 /* PHY Enable */ 358 misc = dme_read(sc, DM9000_GPR); 359 dme_write(sc, DM9000_GPR, misc & ~DM9000_GPR_PHY_PWROFF); 360 misc = dme_read(sc, DM9000_GPCR); 361 dme_write(sc, DM9000_GPCR, misc | DM9000_GPCR_GPIO0_OUT); 362 363 dme_write(sc, DM9000_NCR, 364 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 365 delay(20); 366 dme_write(sc, DM9000_NCR, 0x0); 367 } 368 369 /* Select internal PHY, no wakeup event, no collosion mode, 370 * normal loopback mode. 371 */ 372 dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL); 373 374 /* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/ 375 dme_read(sc, DM9000_NSR); 376 377 /* Enable wraparound of read/write pointer, frame received latch, 378 * and frame transmitted latch. 379 */ 380 dme_write(sc, DM9000_IMR, 381 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 382 383 dme_write(sc, DM9000_RCR, 384 DM9000_RCR_DIS_CRC | DM9000_RCR_DIS_LONG | DM9000_RCR_WTDIS); 385 386 sc->sc_phy_initialized = 1; 387 } 388 389 static int 390 dme_init(struct ifnet *ifp) 391 { 392 struct dme_softc *sc = ifp->if_softc; 393 394 dme_stop(ifp, 0); 395 dme_reset(sc); 396 dme_write_c(sc, DM9000_PAB0, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 397 dme_set_rcvfilt(sc); 398 (void)ether_mediachange(ifp); 399 400 sc->txbusy = sc->txready = 0; 401 402 ifp->if_flags |= IFF_RUNNING; 403 ifp->if_flags &= ~IFF_OACTIVE; 404 callout_schedule(&sc->sc_link_callout, hz); 405 406 return 0; 407 } 408 409 /* Configure multicast filter */ 410 static void 411 dme_set_rcvfilt(struct dme_softc *sc) 412 { 413 struct ethercom *ec = &sc->sc_ethercom; 414 struct ifnet *ifp = &ec->ec_if; 415 struct ether_multi *enm; 416 struct ether_multistep step; 417 uint8_t mchash[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* 64bit mchash */ 418 uint32_t h = 0; 419 int rcr; 420 421 rcr = dme_read(sc, DM9000_RCR); 422 rcr &= ~(DM9000_RCR_PRMSC | DM9000_RCR_ALL); 423 dme_write(sc, DM9000_RCR, rcr &~ DM9000_RCR_RXEN); 424 425 ETHER_LOCK(ec); 426 if (ifp->if_flags & IFF_PROMISC) { 427 ec->ec_flags |= ETHER_F_ALLMULTI; 428 ETHER_UNLOCK(ec); 429 /* run promisc. mode */ 430 rcr |= DM9000_RCR_PRMSC; 431 goto update; 432 } 433 ec->ec_flags &= ~ETHER_F_ALLMULTI; 434 ETHER_FIRST_MULTI(step, ec, enm); 435 while (enm != NULL) { 436 if (memcpy(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 437 /* 438 * We must listen to a range of multicast addresses. 439 * For now, just accept all multicasts, rather than 440 * trying to set only those filter bits needed to match 441 * the range. (At this time, the only use of address 442 * ranges is for IP multicast routing, for which the 443 * range is big enough to require all bits set.) 444 */ 445 ec->ec_flags |= ETHER_F_ALLMULTI; 446 ETHER_UNLOCK(ec); 447 memset(mchash, 0xff, sizeof(mchash)); /* necessary? */ 448 /* accept all mulicast frame */ 449 rcr |= DM9000_RCR_ALL; 450 break; 451 } 452 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 453 /* 3(5:3) and 3(2:0) sampling to have uint8_t[8] */ 454 mchash[h / 8] |= 1 << (h % 8); 455 ETHER_NEXT_MULTI(step, enm); 456 } 457 ETHER_UNLOCK(ec); 458 /* DM9000 receive filter is always on */ 459 mchash[7] |= 0x80; /* to catch bcast frame */ 460 update: 461 dme_write_c(sc, DM9000_MAB0, mchash, sizeof(mchash)); 462 dme_write(sc, DM9000_RCR, rcr | DM9000_RCR_RXEN); 463 return; 464 } 465 466 void 467 lnkchg(struct dme_softc *sc) 468 { 469 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 470 struct ifmediareq ifmr; 471 472 ether_mediastatus(ifp, &ifmr); 473 } 474 475 static void 476 mii_statchg(struct ifnet *ifp) 477 { 478 struct dme_softc *sc = ifp->if_softc; 479 struct mii_data *mii = &sc->sc_mii; 480 uint8_t fcr, ncr; 481 482 #if 0 483 const uint8_t Mbps[2] = { 10, 100 }; 484 uint8_t nsr = dme_read(sc, DM9000_NSR); 485 int spd = Mbps[!!(nsr & DM9000_NSR_SPEED)]; 486 /* speed/duplexity available also in reg 0x11 of internal PHY */ 487 if (nsr & DM9000_NSR_LINKST) 488 printf("link up,spd%d", spd); 489 else 490 printf("link down"); 491 492 /* show resolved mii(4) parameters */ 493 printf("MII spd%d", 494 (int)(sc->sc_ethercom.ec_if.if_baudrate / IF_Mbps(1))); 495 if (mii->mii_media_active & IFM_FDX) 496 printf(",full-duplex"); 497 printf("\n"); 498 #endif 499 500 /* Adjust duplexity and PAUSE flow control. */ 501 fcr = dme_read(sc, DM9000_FCR) &~ DM9000_FCR_FLCE; 502 ncr = dme_read(sc, DM9000_NCR) &~ DM9000_NCR_FDX; 503 if ((mii->mii_media_active & IFM_FDX) 504 && (mii->mii_media_active & IFM_FLOW)) { 505 fcr |= DM9000_FCR_FLCE; 506 ncr |= DM9000_NCR_FDX; 507 } 508 dme_write(sc, DM9000_FCR, fcr); 509 dme_write(sc, DM9000_NCR, ncr); 510 } 511 512 static void 513 phy_tick(void *arg) 514 { 515 struct dme_softc *sc = arg; 516 struct mii_data *mii = &sc->sc_mii; 517 int s; 518 519 s = splnet(); 520 mii_tick(mii); 521 splx(s); 522 523 callout_schedule(&sc->sc_link_callout, hz); 524 } 525 526 static int 527 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 528 { 529 struct dme_softc *sc = device_private(self); 530 531 if (phy != 1) 532 return EINVAL; 533 534 /* Select Register to read*/ 535 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 536 (reg & DM9000_EPAR_EROA_MASK)); 537 /* Select read operation (DM9000_EPCR_ERPRR) from the PHY */ 538 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY); 539 540 /* Wait until access to PHY has completed */ 541 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 542 ; 543 544 /* Reset ERPRR-bit */ 545 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 546 547 *val = dme_read(sc, DM9000_EPDRL) | (dme_read(sc, DM9000_EPDRH) << 8); 548 return 0; 549 } 550 551 static int 552 mii_writereg(device_t self, int phy, int reg, uint16_t val) 553 { 554 struct dme_softc *sc = device_private(self); 555 556 if (phy != 1) 557 return EINVAL; 558 559 /* Select Register to write */ 560 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 561 (reg & DM9000_EPAR_EROA_MASK)); 562 563 /* Write data to the two data registers */ 564 dme_write(sc, DM9000_EPDRL, val & 0xFF); 565 dme_write(sc, DM9000_EPDRH, (val >> 8) & 0xFF); 566 567 /* Select write operation (DM9000_EPCR_ERPRW) from the PHY */ 568 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY); 569 570 /* Wait until access to PHY has completed */ 571 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 572 ; 573 574 /* Reset ERPRR-bit */ 575 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 576 577 return 0; 578 } 579 580 void 581 dme_stop(struct ifnet *ifp, int disable) 582 { 583 struct dme_softc *sc = ifp->if_softc; 584 585 /* Not quite sure what to do when called with disable == 0 */ 586 if (disable) { 587 /* Disable RX */ 588 dme_write(sc, DM9000_RCR, 0x0); 589 } 590 mii_down(&sc->sc_mii); 591 callout_stop(&sc->sc_link_callout); 592 593 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 594 ifp->if_timer = 0; 595 } 596 597 static void 598 dme_start(struct ifnet *ifp) 599 { 600 struct dme_softc *sc = ifp->if_softc; 601 602 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 603 printf("No output\n"); 604 return; 605 } 606 if (sc->txbusy && sc->txready) 607 panic("DM9000: Internal error, trying to send without" 608 " any empty queue\n"); 609 610 dme_prepare(ifp); 611 if (sc->txbusy) { 612 /* We need to wait until the current frame has 613 * been transmitted. 614 */ 615 ifp->if_flags |= IFF_OACTIVE; 616 return; 617 } 618 /* We are ready to transmit right away */ 619 dme_transmit(ifp); 620 dme_prepare(ifp); /* Prepare next one */ 621 } 622 623 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */ 624 static void 625 dme_prepare(struct ifnet *ifp) 626 { 627 struct dme_softc *sc = ifp->if_softc; 628 uint16_t length; 629 struct mbuf *m; 630 631 if (sc->txready) 632 panic("dme_prepare: Someone called us with txready set\n"); 633 634 IFQ_DEQUEUE(&ifp->if_snd, m); 635 if (m == NULL) { 636 TX_DPRINTF(("dme_prepare: Nothing to transmit\n")); 637 ifp->if_flags &= ~IFF_OACTIVE; /* Clear OACTIVE bit */ 638 return; /* Nothing to transmit */ 639 } 640 641 /* Element has now been removed from the queue, so we better send it */ 642 643 bpf_mtap(ifp, m, BPF_D_OUT); 644 645 /* Setup the DM9000 to accept the writes, and then write each buf in 646 the chain. */ 647 648 TX_DATA_DPRINTF(("dme_prepare: Writing data: ")); 649 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD); 650 length = PKT_WRITE(sc, m); 651 bpf_mtap(ifp, m, BPF_D_OUT); 652 TX_DATA_DPRINTF(("\n")); 653 654 if (length % sc->sc_data_width != 0) 655 panic("dme_prepare: length is not compatible with IO_MODE"); 656 657 sc->txready_length = length; 658 sc->txready = 1; 659 m_freem(m); 660 } 661 662 /* Transmit prepared data */ 663 static void 664 dme_transmit(struct ifnet *ifp) 665 { 666 struct dme_softc *sc = ifp->if_softc; 667 668 TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n", 669 sc->txready, sc->txbusy)); 670 671 /* prime frame length first */ 672 dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff); 673 dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff); 674 /* read isr next */ 675 dme_read(sc, DM9000_ISR); 676 /* finally issue a request to send */ 677 dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ); 678 sc->txready = 0; 679 sc->txbusy = 1; 680 sc->txready_length = 0; 681 } 682 683 /* Receive data */ 684 static void 685 dme_receive(struct ifnet *ifp) 686 { 687 struct dme_softc *sc = ifp->if_softc; 688 struct mbuf *m; 689 uint8_t avail, rsr; 690 691 DPRINTF(("inside dme_receive\n")); 692 693 /* frame has just arrived, retrieve it */ 694 /* called right after Rx frame available interrupt */ 695 do { 696 /* "no increment" read to get the avail byte without 697 moving past it. */ 698 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, 699 DM9000_MRCMDX); 700 /* Read twice */ 701 avail = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 702 avail = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 703 avail &= 03; /* 1:0 we only want these bits */ 704 if (avail == 01) { 705 /* Read with address increment. */ 706 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, 707 DM9000_MRCMD); 708 rsr = PKT_READ(sc, &m); 709 if (m == NULL) { 710 /* failed to allocate a receive buffer */ 711 RX_DPRINTF(("dme_receive: " 712 "Error allocating buffer\n")); 713 if_statinc(ifp, if_ierrors); 714 continue; 715 } 716 if (rsr & (DM9000_RSR_CE | DM9000_RSR_PLE)) { 717 /* Error while receiving the frame, 718 * discard it and keep track of counters 719 */ 720 RX_DPRINTF(("dme_receive: " 721 "Error reciving frame\n")); 722 if_statinc(ifp, if_ierrors); 723 continue; 724 } 725 if (rsr & DM9000_RSR_LCS) { 726 if_statinc(ifp, if_collisions); 727 continue; 728 } 729 /* pick and forward this frame to ifq */ 730 if_percpuq_enqueue(ifp->if_percpuq, m); 731 } else if (avail != 00) { 732 /* Should this be logged somehow? */ 733 printf("%s: Resetting chip\n", 734 device_xname(sc->sc_dev)); 735 dme_reset(sc); 736 break; 737 } 738 } while (avail == 01); 739 /* frame receieved successfully */ 740 } 741 742 int 743 dme_intr(void *arg) 744 { 745 struct dme_softc *sc = arg; 746 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 747 uint8_t isr, nsr, tsr; 748 749 DPRINTF(("dme_intr: Begin\n")); 750 751 /* Disable interrupts */ 752 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR); 753 754 isr = dme_read(sc, DM9000_ISR); 755 dme_write(sc, DM9000_ISR, isr); /* write to clear */ 756 757 if (isr & DM9000_ISR_PRS) { 758 KASSERT(ifp->if_flags & IFF_RUNNING); 759 dme_receive(ifp); 760 } 761 if (isr & DM9000_ISR_LNKCHNG) 762 lnkchg(sc); 763 if (isr & DM9000_ISR_PTS) { 764 tsr = 0x01; /* Initialize to an error value */ 765 766 /* A frame has been transmitted */ 767 sc->txbusy = 0; 768 769 nsr = dme_read(sc, DM9000_NSR); 770 if (nsr & DM9000_NSR_TX1END) { 771 tsr = dme_read(sc, DM9000_TSR1); 772 TX_DPRINTF(("dme_intr: Sent using channel 0\n")); 773 } else if (nsr & DM9000_NSR_TX2END) { 774 tsr = dme_read(sc, DM9000_TSR2); 775 TX_DPRINTF(("dme_intr: Sent using channel 1\n")); 776 } 777 778 if (tsr == 0x0) { 779 /* Frame successfully sent */ 780 if_statinc(ifp, if_opackets); 781 } else { 782 if_statinc(ifp, if_oerrors); 783 } 784 785 /* If we have nothing ready to transmit, prepare something */ 786 if (!sc->txready) 787 dme_prepare(ifp); 788 789 if (sc->txready) 790 dme_transmit(ifp); 791 792 /* Prepare the next frame */ 793 dme_prepare(ifp); 794 795 if_schedule_deferred_start(ifp); 796 } 797 798 /* Enable interrupts again */ 799 dme_write(sc, DM9000_IMR, 800 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 801 802 DPRINTF(("dme_intr: End\n")); 803 804 return (isr != 0); 805 } 806 807 static int 808 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data) 809 { 810 struct dme_softc *sc = ifp->if_softc; 811 struct ifreq *ifr = (struct ifreq *)data; 812 struct ifmedia *ifm = &sc->sc_mii.mii_media; 813 int s, error; 814 815 s = splnet(); 816 switch (cmd) { 817 case SIOCSIFMEDIA: 818 /* Flow control requires full-duplex mode. */ 819 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 820 (ifr->ifr_media & IFM_FDX) == 0) 821 ifr->ifr_media &= ~IFM_ETH_FMASK; 822 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 823 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 824 ifr->ifr_media |= 825 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 826 } 827 } 828 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 829 break; 830 default: 831 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 832 break; 833 error = 0; 834 if (cmd == SIOCSIFCAP) 835 error = (*ifp->if_init)(ifp); 836 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 837 ; 838 else if (ifp->if_flags && IFF_RUNNING) { 839 /* Address list has changed, reconfigure filter */ 840 dme_set_rcvfilt(sc); 841 } 842 break; 843 } 844 splx(s); 845 return error; 846 } 847 848 static struct mbuf * 849 dme_alloc_receive_buffer(struct ifnet *ifp, unsigned int frame_length) 850 { 851 struct dme_softc *sc = ifp->if_softc; 852 struct mbuf *m; 853 int pad, quantum; 854 855 quantum = sc->sc_data_width; 856 MGETHDR(m, M_DONTWAIT, MT_DATA); 857 if (m == NULL) 858 return NULL; 859 860 m_set_rcvif(m, ifp); 861 /* Ensure that we always allocate an even number of 862 * bytes in order to avoid writing beyond the buffer 863 */ 864 m->m_pkthdr.len = frame_length + (frame_length % quantum); 865 pad = ALIGN(sizeof(struct ether_header)) - 866 sizeof(struct ether_header); 867 /* All our frames have the CRC attached */ 868 m->m_flags |= M_HASFCS; 869 if (m->m_pkthdr.len + pad > MHLEN) { 870 MCLGET(m, M_DONTWAIT); 871 if ((m->m_flags & M_EXT) == 0) { 872 m_freem(m); 873 return NULL; 874 } 875 } 876 877 m->m_data += pad; 878 m->m_len = frame_length + (frame_length % quantum); 879 880 return m; 881 } 882 883 static int 884 pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain) 885 { 886 int left_over_count = 0; /* Number of bytes from previous mbuf, which 887 need to be written with the next.*/ 888 uint16_t left_over_buf = 0; 889 int length = 0; 890 struct mbuf *buf; 891 uint8_t *write_ptr; 892 893 /* We expect that the DM9000 has been setup to accept writes before 894 this function is called. */ 895 896 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 897 int to_write = buf->m_len; 898 899 length += to_write; 900 901 write_ptr = buf->m_data; 902 while (to_write > 0 || 903 (buf->m_next == NULL && left_over_count > 0)) { 904 if (left_over_count > 0) { 905 uint8_t b = 0; 906 DPRINTF(("pkt_write_16: " 907 "Writing left over byte\n")); 908 909 if (to_write > 0) { 910 b = *write_ptr; 911 to_write--; 912 write_ptr++; 913 914 DPRINTF(("Took single byte\n")); 915 } else { 916 DPRINTF(("Leftover in last run\n")); 917 length++; 918 } 919 920 /* Does shift direction depend on endianess? */ 921 left_over_buf = left_over_buf | (b << 8); 922 923 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 924 sc->dme_data, left_over_buf); 925 TX_DATA_DPRINTF(("%02X ", left_over_buf)); 926 left_over_count = 0; 927 } else if ((long)write_ptr % 2 != 0) { 928 /* Misaligned data */ 929 DPRINTF(("pkt_write_16: " 930 "Detected misaligned data\n")); 931 left_over_buf = *write_ptr; 932 left_over_count = 1; 933 write_ptr++; 934 to_write--; 935 } else { 936 int i; 937 uint16_t *dptr = (uint16_t *)write_ptr; 938 939 /* A block of aligned data. */ 940 for (i = 0; i < to_write / 2; i++) { 941 /* buf will be half-word aligned 942 * all the time 943 */ 944 bus_space_write_2(sc->sc_iot, 945 sc->sc_ioh, sc->dme_data, *dptr); 946 TX_DATA_DPRINTF(("%02X %02X ", 947 *dptr & 0xFF, (*dptr >> 8) & 0xFF)); 948 dptr++; 949 } 950 951 write_ptr += i * 2; 952 if (to_write % 2 != 0) { 953 DPRINTF(("pkt_write_16: " 954 "to_write %% 2: %d\n", 955 to_write % 2)); 956 left_over_count = 1; 957 /* XXX: Does this depend on 958 * the endianess? 959 */ 960 left_over_buf = *write_ptr; 961 962 write_ptr++; 963 to_write--; 964 DPRINTF(("pkt_write_16: " 965 "to_write (after): %d\n", 966 to_write)); 967 DPRINTF(("pkt_write_16: i * 2: %d\n", 968 i*2)); 969 } 970 to_write -= i * 2; 971 } 972 } /* while (...) */ 973 } /* for (...) */ 974 975 return length; 976 } 977 978 static int 979 pkt_read_2(struct dme_softc *sc, struct mbuf **outBuf) 980 { 981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 982 uint8_t rx_status; 983 struct mbuf *m; 984 uint16_t data; 985 uint16_t frame_length; 986 uint16_t i; 987 uint16_t *buf; 988 989 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->dme_data); 990 rx_status = data & 0xFF; 991 992 frame_length = bus_space_read_2(sc->sc_iot, 993 sc->sc_ioh, sc->dme_data); 994 if (frame_length > ETHER_MAX_LEN) { 995 printf("Got frame of length: %d\n", frame_length); 996 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 997 panic("Something is rotten"); 998 } 999 RX_DPRINTF(("dme_receive: rx_statux: 0x%x, frame_length: %d\n", 1000 rx_status, frame_length)); 1001 1002 m = dme_alloc_receive_buffer(ifp, frame_length); 1003 if (m == NULL) { 1004 /* 1005 * didn't get a receive buffer, so we read the rest of the 1006 * frame, throw it away and return an error 1007 */ 1008 for (i = 0; i < frame_length; i += 2) { 1009 data = bus_space_read_2(sc->sc_iot, 1010 sc->sc_ioh, sc->dme_data); 1011 } 1012 *outBuf = NULL; 1013 return 0; 1014 } 1015 1016 buf = mtod(m, uint16_t*); 1017 1018 RX_DPRINTF(("dme_receive: ")); 1019 1020 for (i = 0; i < frame_length; i += 2) { 1021 data = bus_space_read_2(sc->sc_iot, 1022 sc->sc_ioh, sc->dme_data); 1023 if ( (frame_length % 2 != 0) && 1024 (i == frame_length - 1) ) { 1025 data = data & 0xff; 1026 RX_DPRINTF((" L ")); 1027 } 1028 *buf = data; 1029 buf++; 1030 RX_DATA_DPRINTF(("%02X %02X ", data & 0xff, 1031 (data >> 8) & 0xff)); 1032 } 1033 1034 RX_DATA_DPRINTF(("\n")); 1035 RX_DPRINTF(("Read %d bytes\n", i)); 1036 1037 *outBuf = m; 1038 return rx_status; 1039 } 1040 1041 static int 1042 pkt_write_1(struct dme_softc *sc, struct mbuf *bufChain) 1043 { 1044 int length = 0, i; 1045 struct mbuf *buf; 1046 uint8_t *write_ptr; 1047 1048 /* 1049 * We expect that the DM9000 has been setup to accept writes before 1050 * this function is called. 1051 */ 1052 1053 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 1054 int to_write = buf->m_len; 1055 1056 length += to_write; 1057 1058 write_ptr = buf->m_data; 1059 for (i = 0; i < to_write; i++) { 1060 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1061 sc->dme_data, *write_ptr); 1062 write_ptr++; 1063 } 1064 } /* for (...) */ 1065 1066 return length; 1067 } 1068 1069 static int 1070 pkt_read_1(struct dme_softc *sc, struct mbuf **outBuf) 1071 { 1072 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1073 uint8_t rx_status; 1074 struct mbuf *m; 1075 uint8_t *buf; 1076 uint16_t frame_length; 1077 uint16_t i, reg; 1078 uint8_t data; 1079 1080 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1081 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1082 rx_status = reg & 0xFF; 1083 1084 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1085 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1086 frame_length = reg; 1087 1088 if (frame_length > ETHER_MAX_LEN) { 1089 printf("Got frame of length: %d\n", frame_length); 1090 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1091 panic("Something is rotten"); 1092 } 1093 RX_DPRINTF(("dme_receive: " 1094 "rx_statux: 0x%x, frame_length: %d\n", 1095 rx_status, frame_length)); 1096 1097 m = dme_alloc_receive_buffer(ifp, frame_length); 1098 if (m == NULL) { 1099 /* 1100 * didn't get a receive buffer, so we read the rest of the 1101 * frame, throw it away and return an error 1102 */ 1103 for (i = 0; i < frame_length; i++ ) { 1104 data = bus_space_read_2(sc->sc_iot, 1105 sc->sc_ioh, sc->dme_data); 1106 } 1107 *outBuf = NULL; 1108 return 0; 1109 } 1110 1111 buf = mtod(m, uint8_t *); 1112 1113 RX_DPRINTF(("dme_receive: ")); 1114 for (i = 0; i< frame_length; i += 1) { 1115 data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1116 *buf = data; 1117 buf++; 1118 RX_DATA_DPRINTF(("%02X ", data)); 1119 } 1120 1121 RX_DATA_DPRINTF(("\n")); 1122 RX_DPRINTF(("Read %d bytes\n", i)); 1123 1124 *outBuf = m; 1125 return rx_status; 1126 } 1127
Indexes created Fri Sep 26 20:09:58 GMT 2025