dm9000.c revision 1.29
1 /* $NetBSD: dm9000.c,v 1.29 2020/06/27 13:34:20 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* based on sys/dev/ic/cs89x0.c */ 30 /* 31 * Copyright (c) 2004 Christopher Gilbert 32 * All rights reserved. 33 * 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The name of the company nor the name of the author may be used to 40 * endorse or promote products derived from this software without specific 41 * prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright 1997 58 * Digital Equipment Corporation. All rights reserved. 59 * 60 * This software is furnished under license and may be used and 61 * copied only in accordance with the following terms and conditions. 62 * Subject to these conditions, you may download, copy, install, 63 * use, modify and distribute this software in source and/or binary 64 * form. No title or ownership is transferred hereby. 65 * 66 * 1) Any source code used, modified or distributed must reproduce 67 * and retain this copyright notice and list of conditions as 68 * they appear in the source file. 69 * 70 * 2) No right is granted to use any trade name, trademark, or logo of 71 * Digital Equipment Corporation. Neither the "Digital Equipment 72 * Corporation" name nor any trademark or logo of Digital Equipment 73 * Corporation may be used to endorse or promote products derived 74 * from this software without the prior written permission of 75 * Digital Equipment Corporation. 76 * 77 * 3) This software is provided "AS-IS" and any express or implied 78 * warranties, including but not limited to, any implied warranties 79 * of merchantability, fitness for a particular purpose, or 80 * non-infringement are disclaimed. In no event shall DIGITAL be 81 * liable for any damages whatsoever, and in particular, DIGITAL 82 * shall not be liable for special, indirect, consequential, or 83 * incidental damages or damages for lost profits, loss of 84 * revenue or loss of use, whether such damages arise in contract, 85 * negligence, tort, under statute, in equity, at law or otherwise, 86 * even if advised of the possibility of such damage. 87 */ 88 89 #include <sys/cdefs.h> 90 91 #include <sys/param.h> 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 #include <sys/device.h> 95 #include <sys/mbuf.h> 96 #include <sys/sockio.h> 97 #include <sys/malloc.h> 98 #include <sys/errno.h> 99 #include <sys/cprng.h> 100 #include <sys/rndsource.h> 101 #include <sys/kernel.h> 102 #include <sys/systm.h> 103 104 #include <net/if.h> 105 #include <net/if_dl.h> 106 #include <net/if_ether.h> 107 #include <net/if_media.h> 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 #include <net/bpf.h> 111 112 #include <dev/ic/dm9000var.h> 113 #include <dev/ic/dm9000reg.h> 114 115 #if 1 116 #undef DM9000_DEBUG 117 #undef DM9000_TX_DEBUG 118 #undef DM9000_TX_DATA_DEBUG 119 #undef DM9000_RX_DEBUG 120 #undef DM9000_RX_DATA_DEBUG 121 #else 122 #define DM9000_DEBUG 123 #define DM9000_TX_DEBUG 124 #define DM9000_TX_DATA_DEBUG 125 #define DM9000_RX_DEBUG 126 #define DM9000_RX_DATA_DEBUG 127 #endif 128 129 #ifdef DM9000_DEBUG 130 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 131 #else 132 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 133 #endif 134 135 #ifdef DM9000_TX_DEBUG 136 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 137 #else 138 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 139 #endif 140 141 #ifdef DM9000_RX_DEBUG 142 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 143 #else 144 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 145 #endif 146 147 #ifdef DM9000_RX_DATA_DEBUG 148 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 149 #else 150 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 151 #endif 152 153 #ifdef DM9000_TX_DATA_DEBUG 154 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 155 #else 156 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 157 #endif 158 159 static void dme_reset(struct dme_softc *); 160 static int dme_init(struct ifnet *); 161 static void dme_stop(struct ifnet *, int); 162 static void dme_start(struct ifnet *); 163 static int dme_ioctl(struct ifnet *, u_long, void *); 164 165 static void dme_set_rcvfilt(struct dme_softc *); 166 static void mii_statchg(struct ifnet *); 167 static void lnkchg(struct dme_softc *); 168 static void phy_tick(void *); 169 static int mii_readreg(device_t, int, int, uint16_t *); 170 static int mii_writereg(device_t, int, int, uint16_t); 171 172 static void dme_prepare(struct ifnet *); 173 static void dme_transmit(struct ifnet *); 174 static void dme_receive(struct ifnet *); 175 176 static int pkt_read_2(struct dme_softc *, struct mbuf **); 177 static int pkt_write_2(struct dme_softc *, struct mbuf *); 178 static int pkt_read_1(struct dme_softc *, struct mbuf **); 179 static int pkt_write_1(struct dme_softc *, struct mbuf *); 180 #define PKT_READ(ii,m) (*(ii)->sc_pkt_read)((ii),(m)) 181 #define PKT_WRITE(ii,m) (*(ii)->sc_pkt_write)((ii),(m)) 182 183 #define ETHER_IS_ONE(x) \ 184 (((x)[0] & (x)[1] & (x)[2] & (x)[3] & (x)[4] & (x)[5]) == 255) 185 #define ETHER_IS_ZERO(x) \ 186 (((x)[0] | (x)[1] | (x)[2] | (x)[3] | (x)[4] | (x)[5]) == 0) 187 188 int 189 dme_attach(struct dme_softc *sc, const uint8_t *notusedanymore) 190 { 191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 192 struct mii_data *mii = &sc->sc_mii; 193 struct ifmedia *ifm = &mii->mii_media; 194 uint8_t b[2]; 195 uint16_t io_mode; 196 uint8_t enaddr[ETHER_ADDR_LEN]; 197 prop_dictionary_t dict; 198 prop_data_t ea; 199 200 dme_read_c(sc, DM9000_VID0, b, 2); 201 sc->sc_vendor_id = le16toh((uint16_t)b[1] << 8 | b[0]); 202 dme_read_c(sc, DM9000_PID0, b, 2); 203 sc->sc_product_id = le16toh((uint16_t)b[1] << 8 | b[0]); 204 205 /* TODO: Check the vendor ID as well */ 206 if (sc->sc_product_id != 0x9000) { 207 panic("dme_attach: product id mismatch (0x%hx != 0x9000)", 208 sc->sc_product_id); 209 } 210 #if 1 || DM9000_DEBUG 211 { 212 dme_read_c(sc, DM9000_PAB0, enaddr, 6); 213 aprint_normal_dev(sc->sc_dev, 214 "DM9000 was configured with MAC address: %s\n", 215 ether_sprintf(enaddr)); 216 } 217 #endif 218 dict = device_properties(sc->sc_dev); 219 ea = (dict) ? prop_dictionary_get(dict, "mac-address") : NULL; 220 if (ea != NULL) { 221 /* 222 * If the MAC address is overriden by a device property, 223 * use that. 224 */ 225 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 226 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 227 memcpy(enaddr, prop_data_value(ea), ETHER_ADDR_LEN); 228 aprint_debug_dev(sc->sc_dev, "got MAC address!\n"); 229 } else { 230 /* 231 * If we did not get an externaly configure address, 232 * try to read one from the current setup, before 233 * resetting the chip. 234 */ 235 dme_read_c(sc, DM9000_PAB0, enaddr, 6); 236 if (ETHER_IS_ONE(enaddr) || ETHER_IS_ZERO(enaddr)) { 237 /* make a random MAC address */ 238 uint32_t maclo = 0x00f2 | (cprng_strong32() << 16); 239 uint32_t machi = cprng_strong32(); 240 enaddr[0] = maclo; 241 enaddr[1] = maclo >> 8; 242 enaddr[2] = maclo >> 16; 243 enaddr[3] = maclo >> 26; 244 enaddr[4] = machi; 245 enaddr[5] = machi >> 8; 246 } 247 } 248 /* TODO: perform explicit EEPROM read op if it's availble */ 249 250 dme_reset(sc); 251 252 mii->mii_ifp = ifp; 253 mii->mii_readreg = mii_readreg; 254 mii->mii_writereg = mii_writereg; 255 mii->mii_statchg = mii_statchg; 256 257 /* assume davicom PHY at 1. ext PHY could be hooked but only at 0-3 */ 258 sc->sc_ethercom.ec_mii = mii; 259 ifmedia_init(ifm, 0, ether_mediachange, ether_mediastatus); 260 mii_attach(sc->sc_dev, mii, 0xffffffff, 1 /* PHY 1 */, 261 MII_OFFSET_ANY, 0); 262 if (LIST_FIRST(&mii->mii_phys) == NULL) { 263 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 264 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 265 } else 266 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 267 ifm->ifm_media = ifm->ifm_cur->ifm_media; 268 269 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 270 ifp->if_softc = sc; 271 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 272 ifp->if_init = dme_init; 273 ifp->if_start = dme_start; 274 ifp->if_stop = dme_stop; 275 ifp->if_ioctl = dme_ioctl; 276 ifp->if_watchdog = NULL; /* no watchdog used */ 277 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 278 IFQ_SET_READY(&ifp->if_snd); 279 280 if_attach(ifp); 281 ether_ifattach(ifp, enaddr); 282 if_deferred_start_init(ifp, NULL); 283 284 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 285 RND_TYPE_NET, RND_FLAG_DEFAULT); 286 287 /* might be unnecessary as link change interrupt works well */ 288 callout_init(&sc->sc_link_callout, 0); 289 callout_setfunc(&sc->sc_link_callout, phy_tick, sc); 290 291 io_mode = (dme_read(sc, DM9000_ISR) & 292 DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT; 293 294 /* frame body read/write ops in 2 byte quantity or byte-wise. */ 295 DPRINTF(("DM9000 Operation Mode: ")); 296 switch (io_mode) { 297 case DM9000_MODE_8BIT: 298 DPRINTF(("8-bit mode")); 299 sc->sc_data_width = 1; 300 sc->sc_pkt_write = pkt_write_1; 301 sc->sc_pkt_read = pkt_read_1; 302 break; 303 case DM9000_MODE_16BIT: 304 DPRINTF(("16-bit mode")); 305 sc->sc_data_width = 2; 306 sc->sc_pkt_write = pkt_write_2; 307 sc->sc_pkt_read = pkt_read_2; 308 break; 309 case DM9000_MODE_32BIT: 310 DPRINTF(("32-bit mode")); 311 sc->sc_data_width = 4; 312 panic("32bit mode is unsupported\n"); 313 break; 314 default: 315 DPRINTF(("Invalid mode")); 316 break; 317 } 318 DPRINTF(("\n")); 319 320 return 0; 321 } 322 323 int 324 dme_detach(struct dme_softc *sc) 325 { 326 return 0; 327 } 328 329 /* Software Initialize/Reset of the DM9000 */ 330 static void 331 dme_reset(struct dme_softc *sc) 332 { 333 uint8_t misc; 334 335 /* We only re-initialized the PHY in this function the first time it is 336 * called. */ 337 if (!sc->sc_phy_initialized) { 338 /* PHY Reset */ 339 mii_writereg(sc->sc_dev, 1, MII_BMCR, BMCR_RESET); 340 341 /* PHY Power Down */ 342 misc = dme_read(sc, DM9000_GPR); 343 dme_write(sc, DM9000_GPR, misc | DM9000_GPR_PHY_PWROFF); 344 } 345 346 /* Reset the DM9000 twice, as described in section 2 of the Programming 347 * Guide. 348 * The PHY is initialized and enabled between those two resets. 349 */ 350 351 /* Software Reset */ 352 dme_write(sc, DM9000_NCR, 353 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 354 delay(20); 355 dme_write(sc, DM9000_NCR, 0x0); 356 357 if (!sc->sc_phy_initialized) { 358 /* PHY Enable */ 359 misc = dme_read(sc, DM9000_GPR); 360 dme_write(sc, DM9000_GPR, misc & ~DM9000_GPR_PHY_PWROFF); 361 misc = dme_read(sc, DM9000_GPCR); 362 dme_write(sc, DM9000_GPCR, misc | DM9000_GPCR_GPIO0_OUT); 363 364 dme_write(sc, DM9000_NCR, 365 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 366 delay(20); 367 dme_write(sc, DM9000_NCR, 0x0); 368 } 369 370 /* Select internal PHY, no wakeup event, no collosion mode, 371 * normal loopback mode. 372 */ 373 dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL); 374 375 /* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/ 376 dme_read(sc, DM9000_NSR); 377 378 /* Enable wraparound of read/write pointer, frame received latch, 379 * and frame transmitted latch. 380 */ 381 dme_write(sc, DM9000_IMR, 382 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 383 384 dme_write(sc, DM9000_RCR, 385 DM9000_RCR_DIS_CRC | DM9000_RCR_DIS_LONG | DM9000_RCR_WTDIS); 386 387 sc->sc_phy_initialized = 1; 388 } 389 390 static int 391 dme_init(struct ifnet *ifp) 392 { 393 struct dme_softc *sc = ifp->if_softc; 394 395 dme_stop(ifp, 0); 396 dme_reset(sc); 397 dme_write_c(sc, DM9000_PAB0, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 398 dme_set_rcvfilt(sc); 399 (void)ether_mediachange(ifp); 400 401 sc->txbusy = sc->txready = 0; 402 403 ifp->if_flags |= IFF_RUNNING; 404 ifp->if_flags &= ~IFF_OACTIVE; 405 callout_schedule(&sc->sc_link_callout, hz); 406 407 return 0; 408 } 409 410 /* Configure multicast filter */ 411 static void 412 dme_set_rcvfilt(struct dme_softc *sc) 413 { 414 struct ethercom *ec = &sc->sc_ethercom; 415 struct ifnet *ifp = &ec->ec_if; 416 struct ether_multi *enm; 417 struct ether_multistep step; 418 uint8_t mchash[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* 64bit mchash */ 419 uint32_t h = 0; 420 int rcr; 421 422 rcr = dme_read(sc, DM9000_RCR); 423 rcr &= ~(DM9000_RCR_PRMSC | DM9000_RCR_ALL); 424 dme_write(sc, DM9000_RCR, rcr &~ DM9000_RCR_RXEN); 425 426 ETHER_LOCK(ec); 427 if (ifp->if_flags & IFF_PROMISC) { 428 ec->ec_flags |= ETHER_F_ALLMULTI; 429 ETHER_UNLOCK(ec); 430 /* run promisc. mode */ 431 rcr |= DM9000_RCR_PRMSC; 432 goto update; 433 } 434 ec->ec_flags &= ~ETHER_F_ALLMULTI; 435 ETHER_FIRST_MULTI(step, ec, enm); 436 while (enm != NULL) { 437 if (memcpy(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 438 /* 439 * We must listen to a range of multicast addresses. 440 * For now, just accept all multicasts, rather than 441 * trying to set only those filter bits needed to match 442 * the range. (At this time, the only use of address 443 * ranges is for IP multicast routing, for which the 444 * range is big enough to require all bits set.) 445 */ 446 ec->ec_flags |= ETHER_F_ALLMULTI; 447 ETHER_UNLOCK(ec); 448 memset(mchash, 0xff, sizeof(mchash)); /* necessary? */ 449 /* accept all mulicast frame */ 450 rcr |= DM9000_RCR_ALL; 451 break; 452 } 453 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 454 /* 3(5:3) and 3(2:0) sampling to have uint8_t[8] */ 455 mchash[h / 8] |= 1 << (h % 8); 456 ETHER_NEXT_MULTI(step, enm); 457 } 458 ETHER_UNLOCK(ec); 459 /* DM9000 receive filter is always on */ 460 mchash[7] |= 0x80; /* to catch bcast frame */ 461 update: 462 dme_write_c(sc, DM9000_MAB0, mchash, sizeof(mchash)); 463 dme_write(sc, DM9000_RCR, rcr | DM9000_RCR_RXEN); 464 return; 465 } 466 467 void 468 lnkchg(struct dme_softc *sc) 469 { 470 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 471 struct ifmediareq ifmr; 472 473 ether_mediastatus(ifp, &ifmr); 474 } 475 476 static void 477 mii_statchg(struct ifnet *ifp) 478 { 479 struct dme_softc *sc = ifp->if_softc; 480 struct mii_data *mii = &sc->sc_mii; 481 uint8_t fcr, ncr; 482 483 #if 0 484 const uint8_t Mbps[2] = { 10, 100 }; 485 uint8_t nsr = dme_read(sc, DM9000_NSR); 486 int spd = Mbps[!!(nsr & DM9000_NSR_SPEED)]; 487 /* speed/duplexity available also in reg 0x11 of internal PHY */ 488 if (nsr & DM9000_NSR_LINKST) 489 printf("link up,spd%d", spd); 490 else 491 printf("link down"); 492 493 /* show resolved mii(4) parameters */ 494 printf("MII spd%d", 495 (int)(sc->sc_ethercom.ec_if.if_baudrate / IF_Mbps(1))); 496 if (mii->mii_media_active & IFM_FDX) 497 printf(",full-duplex"); 498 printf("\n"); 499 #endif 500 501 /* Adjust duplexity and PAUSE flow control. */ 502 fcr = dme_read(sc, DM9000_FCR) &~ DM9000_FCR_FLCE; 503 ncr = dme_read(sc, DM9000_NCR) &~ DM9000_NCR_FDX; 504 if ((mii->mii_media_active & IFM_FDX) 505 && (mii->mii_media_active & IFM_FLOW)) { 506 fcr |= DM9000_FCR_FLCE; 507 ncr |= DM9000_NCR_FDX; 508 } 509 dme_write(sc, DM9000_FCR, fcr); 510 dme_write(sc, DM9000_NCR, ncr); 511 } 512 513 static void 514 phy_tick(void *arg) 515 { 516 struct dme_softc *sc = arg; 517 struct mii_data *mii = &sc->sc_mii; 518 int s; 519 520 s = splnet(); 521 mii_tick(mii); 522 splx(s); 523 524 callout_schedule(&sc->sc_link_callout, hz); 525 } 526 527 static int 528 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 529 { 530 struct dme_softc *sc = device_private(self); 531 532 if (phy != 1) 533 return EINVAL; 534 535 /* Select Register to read*/ 536 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 537 (reg & DM9000_EPAR_EROA_MASK)); 538 /* Select read operation (DM9000_EPCR_ERPRR) from the PHY */ 539 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY); 540 541 /* Wait until access to PHY has completed */ 542 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 543 ; 544 545 /* Reset ERPRR-bit */ 546 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 547 548 *val = dme_read(sc, DM9000_EPDRL) | (dme_read(sc, DM9000_EPDRH) << 8); 549 return 0; 550 } 551 552 static int 553 mii_writereg(device_t self, int phy, int reg, uint16_t val) 554 { 555 struct dme_softc *sc = device_private(self); 556 557 if (phy != 1) 558 return EINVAL; 559 560 /* Select Register to write */ 561 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 562 (reg & DM9000_EPAR_EROA_MASK)); 563 564 /* Write data to the two data registers */ 565 dme_write(sc, DM9000_EPDRL, val & 0xFF); 566 dme_write(sc, DM9000_EPDRH, (val >> 8) & 0xFF); 567 568 /* Select write operation (DM9000_EPCR_ERPRW) from the PHY */ 569 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY); 570 571 /* Wait until access to PHY has completed */ 572 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 573 ; 574 575 /* Reset ERPRR-bit */ 576 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 577 578 return 0; 579 } 580 581 void 582 dme_stop(struct ifnet *ifp, int disable) 583 { 584 struct dme_softc *sc = ifp->if_softc; 585 586 /* Not quite sure what to do when called with disable == 0 */ 587 if (disable) { 588 /* Disable RX */ 589 dme_write(sc, DM9000_RCR, 0x0); 590 } 591 mii_down(&sc->sc_mii); 592 callout_stop(&sc->sc_link_callout); 593 594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 595 ifp->if_timer = 0; 596 } 597 598 static void 599 dme_start(struct ifnet *ifp) 600 { 601 struct dme_softc *sc = ifp->if_softc; 602 603 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 604 printf("No output\n"); 605 return; 606 } 607 if (sc->txbusy && sc->txready) 608 panic("DM9000: Internal error, trying to send without" 609 " any empty queue\n"); 610 611 dme_prepare(ifp); 612 if (sc->txbusy) { 613 /* We need to wait until the current frame has 614 * been transmitted. 615 */ 616 ifp->if_flags |= IFF_OACTIVE; 617 return; 618 } 619 /* We are ready to transmit right away */ 620 dme_transmit(ifp); 621 dme_prepare(ifp); /* Prepare next one */ 622 } 623 624 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */ 625 static void 626 dme_prepare(struct ifnet *ifp) 627 { 628 struct dme_softc *sc = ifp->if_softc; 629 uint16_t length; 630 struct mbuf *m; 631 632 if (sc->txready) 633 panic("dme_prepare: Someone called us with txready set\n"); 634 635 IFQ_DEQUEUE(&ifp->if_snd, m); 636 if (m == NULL) { 637 TX_DPRINTF(("dme_prepare: Nothing to transmit\n")); 638 ifp->if_flags &= ~IFF_OACTIVE; /* Clear OACTIVE bit */ 639 return; /* Nothing to transmit */ 640 } 641 642 /* Element has now been removed from the queue, so we better send it */ 643 644 bpf_mtap(ifp, m, BPF_D_OUT); 645 646 /* Setup the DM9000 to accept the writes, and then write each buf in 647 the chain. */ 648 649 TX_DATA_DPRINTF(("dme_prepare: Writing data: ")); 650 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD); 651 length = PKT_WRITE(sc, m); 652 bpf_mtap(ifp, m, BPF_D_OUT); 653 TX_DATA_DPRINTF(("\n")); 654 655 if (length % sc->sc_data_width != 0) 656 panic("dme_prepare: length is not compatible with IO_MODE"); 657 658 sc->txready_length = length; 659 sc->txready = 1; 660 m_freem(m); 661 } 662 663 /* Transmit prepared data */ 664 static void 665 dme_transmit(struct ifnet *ifp) 666 { 667 struct dme_softc *sc = ifp->if_softc; 668 669 TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n", 670 sc->txready, sc->txbusy)); 671 672 /* prime frame length first */ 673 dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff); 674 dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff); 675 /* read isr next */ 676 dme_read(sc, DM9000_ISR); 677 /* finally issue a request to send */ 678 dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ); 679 sc->txready = 0; 680 sc->txbusy = 1; 681 sc->txready_length = 0; 682 } 683 684 /* Receive data */ 685 static void 686 dme_receive(struct ifnet *ifp) 687 { 688 struct dme_softc *sc = ifp->if_softc; 689 struct mbuf *m; 690 uint8_t avail, rsr; 691 692 DPRINTF(("inside dme_receive\n")); 693 694 /* frame has just arrived, retrieve it */ 695 /* called right after Rx frame available interrupt */ 696 do { 697 /* "no increment" read to get the avail byte without 698 moving past it. */ 699 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, 700 DM9000_MRCMDX); 701 /* Read twice */ 702 avail = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 703 avail = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 704 avail &= 03; /* 1:0 we only want these bits */ 705 if (avail == 01) { 706 /* Read with address increment. */ 707 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, 708 DM9000_MRCMD); 709 rsr = PKT_READ(sc, &m); 710 if (m == NULL) { 711 /* failed to allocate a receive buffer */ 712 RX_DPRINTF(("dme_receive: " 713 "Error allocating buffer\n")); 714 if_statinc(ifp, if_ierrors); 715 continue; 716 } 717 if (rsr & (DM9000_RSR_CE | DM9000_RSR_PLE)) { 718 /* Error while receiving the frame, 719 * discard it and keep track of counters 720 */ 721 RX_DPRINTF(("dme_receive: " 722 "Error reciving frame\n")); 723 if_statinc(ifp, if_ierrors); 724 continue; 725 } 726 if (rsr & DM9000_RSR_LCS) { 727 if_statinc(ifp, if_collisions); 728 continue; 729 } 730 /* pick and forward this frame to ifq */ 731 if_percpuq_enqueue(ifp->if_percpuq, m); 732 } else if (avail != 00) { 733 /* Should this be logged somehow? */ 734 printf("%s: Resetting chip\n", 735 device_xname(sc->sc_dev)); 736 dme_reset(sc); 737 break; 738 } 739 } while (avail == 01); 740 /* frame receieved successfully */ 741 } 742 743 int 744 dme_intr(void *arg) 745 { 746 struct dme_softc *sc = arg; 747 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 748 uint8_t isr, nsr, tsr; 749 750 DPRINTF(("dme_intr: Begin\n")); 751 752 /* Disable interrupts */ 753 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR); 754 755 isr = dme_read(sc, DM9000_ISR); 756 dme_write(sc, DM9000_ISR, isr); /* write to clear */ 757 758 if (isr & DM9000_ISR_PRS) { 759 KASSERT(ifp->if_flags & IFF_RUNNING); 760 dme_receive(ifp); 761 } 762 if (isr & DM9000_ISR_LNKCHNG) 763 lnkchg(sc); 764 if (isr & DM9000_ISR_PTS) { 765 tsr = 0x01; /* Initialize to an error value */ 766 767 /* A frame has been transmitted */ 768 sc->txbusy = 0; 769 770 nsr = dme_read(sc, DM9000_NSR); 771 if (nsr & DM9000_NSR_TX1END) { 772 tsr = dme_read(sc, DM9000_TSR1); 773 TX_DPRINTF(("dme_intr: Sent using channel 0\n")); 774 } else if (nsr & DM9000_NSR_TX2END) { 775 tsr = dme_read(sc, DM9000_TSR2); 776 TX_DPRINTF(("dme_intr: Sent using channel 1\n")); 777 } 778 779 if (tsr == 0x0) { 780 /* Frame successfully sent */ 781 if_statinc(ifp, if_opackets); 782 } else { 783 if_statinc(ifp, if_oerrors); 784 } 785 786 /* If we have nothing ready to transmit, prepare something */ 787 if (!sc->txready) 788 dme_prepare(ifp); 789 790 if (sc->txready) 791 dme_transmit(ifp); 792 793 /* Prepare the next frame */ 794 dme_prepare(ifp); 795 796 if_schedule_deferred_start(ifp); 797 } 798 799 /* Enable interrupts again */ 800 dme_write(sc, DM9000_IMR, 801 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 802 803 DPRINTF(("dme_intr: End\n")); 804 805 return (isr != 0); 806 } 807 808 static int 809 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data) 810 { 811 struct dme_softc *sc = ifp->if_softc; 812 struct ifreq *ifr = (struct ifreq *)data; 813 struct ifmedia *ifm = &sc->sc_mii.mii_media; 814 int s, error; 815 816 s = splnet(); 817 switch (cmd) { 818 case SIOCSIFMEDIA: 819 /* Flow control requires full-duplex mode. */ 820 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 821 (ifr->ifr_media & IFM_FDX) == 0) 822 ifr->ifr_media &= ~IFM_ETH_FMASK; 823 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 824 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 825 ifr->ifr_media |= 826 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 827 } 828 } 829 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 830 break; 831 default: 832 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 833 break; 834 error = 0; 835 if (cmd == SIOCSIFCAP) 836 error = (*ifp->if_init)(ifp); 837 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 838 ; 839 else if (ifp->if_flags && IFF_RUNNING) { 840 /* Address list has changed, reconfigure filter */ 841 dme_set_rcvfilt(sc); 842 } 843 break; 844 } 845 splx(s); 846 return error; 847 } 848 849 static struct mbuf * 850 dme_alloc_receive_buffer(struct ifnet *ifp, unsigned int frame_length) 851 { 852 struct dme_softc *sc = ifp->if_softc; 853 struct mbuf *m; 854 int pad, quantum; 855 856 quantum = sc->sc_data_width; 857 MGETHDR(m, M_DONTWAIT, MT_DATA); 858 if (m == NULL) 859 return NULL; 860 861 m_set_rcvif(m, ifp); 862 /* Ensure that we always allocate an even number of 863 * bytes in order to avoid writing beyond the buffer 864 */ 865 m->m_pkthdr.len = frame_length + (frame_length % quantum); 866 pad = ALIGN(sizeof(struct ether_header)) - 867 sizeof(struct ether_header); 868 /* All our frames have the CRC attached */ 869 m->m_flags |= M_HASFCS; 870 if (m->m_pkthdr.len + pad > MHLEN) { 871 MCLGET(m, M_DONTWAIT); 872 if ((m->m_flags & M_EXT) == 0) { 873 m_freem(m); 874 return NULL; 875 } 876 } 877 878 m->m_data += pad; 879 m->m_len = frame_length + (frame_length % quantum); 880 881 return m; 882 } 883 884 static int 885 pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain) 886 { 887 int left_over_count = 0; /* Number of bytes from previous mbuf, which 888 need to be written with the next.*/ 889 uint16_t left_over_buf = 0; 890 int length = 0; 891 struct mbuf *buf; 892 uint8_t *write_ptr; 893 894 /* We expect that the DM9000 has been setup to accept writes before 895 this function is called. */ 896 897 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 898 int to_write = buf->m_len; 899 900 length += to_write; 901 902 write_ptr = buf->m_data; 903 while (to_write > 0 || 904 (buf->m_next == NULL && left_over_count > 0)) { 905 if (left_over_count > 0) { 906 uint8_t b = 0; 907 DPRINTF(("pkt_write_16: " 908 "Writing left over byte\n")); 909 910 if (to_write > 0) { 911 b = *write_ptr; 912 to_write--; 913 write_ptr++; 914 915 DPRINTF(("Took single byte\n")); 916 } else { 917 DPRINTF(("Leftover in last run\n")); 918 length++; 919 } 920 921 /* Does shift direction depend on endianess? */ 922 left_over_buf = left_over_buf | (b << 8); 923 924 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 925 sc->dme_data, left_over_buf); 926 TX_DATA_DPRINTF(("%02X ", left_over_buf)); 927 left_over_count = 0; 928 } else if ((long)write_ptr % 2 != 0) { 929 /* Misaligned data */ 930 DPRINTF(("pkt_write_16: " 931 "Detected misaligned data\n")); 932 left_over_buf = *write_ptr; 933 left_over_count = 1; 934 write_ptr++; 935 to_write--; 936 } else { 937 int i; 938 uint16_t *dptr = (uint16_t *)write_ptr; 939 940 /* A block of aligned data. */ 941 for (i = 0; i < to_write / 2; i++) { 942 /* buf will be half-word aligned 943 * all the time 944 */ 945 bus_space_write_2(sc->sc_iot, 946 sc->sc_ioh, sc->dme_data, *dptr); 947 TX_DATA_DPRINTF(("%02X %02X ", 948 *dptr & 0xFF, (*dptr >> 8) & 0xFF)); 949 dptr++; 950 } 951 952 write_ptr += i * 2; 953 if (to_write % 2 != 0) { 954 DPRINTF(("pkt_write_16: " 955 "to_write %% 2: %d\n", 956 to_write % 2)); 957 left_over_count = 1; 958 /* XXX: Does this depend on 959 * the endianess? 960 */ 961 left_over_buf = *write_ptr; 962 963 write_ptr++; 964 to_write--; 965 DPRINTF(("pkt_write_16: " 966 "to_write (after): %d\n", 967 to_write)); 968 DPRINTF(("pkt_write_16: i * 2: %d\n", 969 i*2)); 970 } 971 to_write -= i * 2; 972 } 973 } /* while (...) */ 974 } /* for (...) */ 975 976 return length; 977 } 978 979 static int 980 pkt_read_2(struct dme_softc *sc, struct mbuf **outBuf) 981 { 982 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 983 uint8_t rx_status; 984 struct mbuf *m; 985 uint16_t data; 986 uint16_t frame_length; 987 uint16_t i; 988 uint16_t *buf; 989 990 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->dme_data); 991 rx_status = data & 0xFF; 992 993 frame_length = bus_space_read_2(sc->sc_iot, 994 sc->sc_ioh, sc->dme_data); 995 if (frame_length > ETHER_MAX_LEN) { 996 printf("Got frame of length: %d\n", frame_length); 997 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 998 panic("Something is rotten"); 999 } 1000 RX_DPRINTF(("dme_receive: rx_statux: 0x%x, frame_length: %d\n", 1001 rx_status, frame_length)); 1002 1003 m = dme_alloc_receive_buffer(ifp, frame_length); 1004 if (m == NULL) { 1005 /* 1006 * didn't get a receive buffer, so we read the rest of the 1007 * frame, throw it away and return an error 1008 */ 1009 for (i = 0; i < frame_length; i += 2) { 1010 data = bus_space_read_2(sc->sc_iot, 1011 sc->sc_ioh, sc->dme_data); 1012 } 1013 *outBuf = NULL; 1014 return 0; 1015 } 1016 1017 buf = mtod(m, uint16_t*); 1018 1019 RX_DPRINTF(("dme_receive: ")); 1020 1021 for (i = 0; i < frame_length; i += 2) { 1022 data = bus_space_read_2(sc->sc_iot, 1023 sc->sc_ioh, sc->dme_data); 1024 if ( (frame_length % 2 != 0) && 1025 (i == frame_length - 1) ) { 1026 data = data & 0xff; 1027 RX_DPRINTF((" L ")); 1028 } 1029 *buf = data; 1030 buf++; 1031 RX_DATA_DPRINTF(("%02X %02X ", data & 0xff, 1032 (data >> 8) & 0xff)); 1033 } 1034 1035 RX_DATA_DPRINTF(("\n")); 1036 RX_DPRINTF(("Read %d bytes\n", i)); 1037 1038 *outBuf = m; 1039 return rx_status; 1040 } 1041 1042 static int 1043 pkt_write_1(struct dme_softc *sc, struct mbuf *bufChain) 1044 { 1045 int length = 0, i; 1046 struct mbuf *buf; 1047 uint8_t *write_ptr; 1048 1049 /* 1050 * We expect that the DM9000 has been setup to accept writes before 1051 * this function is called. 1052 */ 1053 1054 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 1055 int to_write = buf->m_len; 1056 1057 length += to_write; 1058 1059 write_ptr = buf->m_data; 1060 for (i = 0; i < to_write; i++) { 1061 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1062 sc->dme_data, *write_ptr); 1063 write_ptr++; 1064 } 1065 } /* for (...) */ 1066 1067 return length; 1068 } 1069 1070 static int 1071 pkt_read_1(struct dme_softc *sc, struct mbuf **outBuf) 1072 { 1073 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1074 uint8_t rx_status; 1075 struct mbuf *m; 1076 uint8_t *buf; 1077 uint16_t frame_length; 1078 uint16_t i, reg; 1079 uint8_t data; 1080 1081 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1082 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1083 rx_status = reg & 0xFF; 1084 1085 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1086 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1087 frame_length = reg; 1088 1089 if (frame_length > ETHER_MAX_LEN) { 1090 printf("Got frame of length: %d\n", frame_length); 1091 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1092 panic("Something is rotten"); 1093 } 1094 RX_DPRINTF(("dme_receive: " 1095 "rx_statux: 0x%x, frame_length: %d\n", 1096 rx_status, frame_length)); 1097 1098 m = dme_alloc_receive_buffer(ifp, frame_length); 1099 if (m == NULL) { 1100 /* 1101 * didn't get a receive buffer, so we read the rest of the 1102 * frame, throw it away and return an error 1103 */ 1104 for (i = 0; i < frame_length; i++ ) { 1105 data = bus_space_read_2(sc->sc_iot, 1106 sc->sc_ioh, sc->dme_data); 1107 } 1108 *outBuf = NULL; 1109 return 0; 1110 } 1111 1112 buf = mtod(m, uint8_t *); 1113 1114 RX_DPRINTF(("dme_receive: ")); 1115 for (i = 0; i< frame_length; i += 1) { 1116 data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1117 *buf = data; 1118 buf++; 1119 RX_DATA_DPRINTF(("%02X ", data)); 1120 } 1121 1122 RX_DATA_DPRINTF(("\n")); 1123 RX_DPRINTF(("Read %d bytes\n", i)); 1124 1125 *outBuf = m; 1126 return rx_status; 1127 } 1128
Indexes created Fri Sep 26 08:10:20 GMT 2025