dm9000.c revision 1.4
1 /* $NetBSD: dm9000.c,v 1.4 2012/01/28 08:29:55 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* based on sys/dev/ic/cs89x0.c */ 30 /* 31 * Copyright (c) 2004 Christopher Gilbert 32 * All rights reserved. 33 * 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The name of the company nor the name of the author may be used to 40 * endorse or promote products derived from this software without specific 41 * prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright 1997 58 * Digital Equipment Corporation. All rights reserved. 59 * 60 * This software is furnished under license and may be used and 61 * copied only in accordance with the following terms and conditions. 62 * Subject to these conditions, you may download, copy, install, 63 * use, modify and distribute this software in source and/or binary 64 * form. No title or ownership is transferred hereby. 65 * 66 * 1) Any source code used, modified or distributed must reproduce 67 * and retain this copyright notice and list of conditions as 68 * they appear in the source file. 69 * 70 * 2) No right is granted to use any trade name, trademark, or logo of 71 * Digital Equipment Corporation. Neither the "Digital Equipment 72 * Corporation" name nor any trademark or logo of Digital Equipment 73 * Corporation may be used to endorse or promote products derived 74 * from this software without the prior written permission of 75 * Digital Equipment Corporation. 76 * 77 * 3) This software is provided "AS-IS" and any express or implied 78 * warranties, including but not limited to, any implied warranties 79 * of merchantability, fitness for a particular purpose, or 80 * non-infringement are disclaimed. In no event shall DIGITAL be 81 * liable for any damages whatsoever, and in particular, DIGITAL 82 * shall not be liable for special, indirect, consequential, or 83 * incidental damages or damages for lost profits, loss of 84 * revenue or loss of use, whether such damages arise in contract, 85 * negligence, tort, under statute, in equity, at law or otherwise, 86 * even if advised of the possibility of such damage. 87 */ 88 89 #include <sys/cdefs.h> 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/mbuf.h> 95 #include <sys/syslog.h> 96 #include <sys/socket.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 #include <sys/ioctl.h> 100 #include <sys/errno.h> 101 102 #include <net/if.h> 103 #include <net/if_ether.h> 104 #include <net/if_media.h> 105 #ifdef INET 106 #include <netinet/in.h> 107 #include <netinet/if_inarp.h> 108 #endif 109 110 #include <net/bpf.h> 111 #include <net/bpfdesc.h> 112 113 #include <sys/bus.h> 114 #include <sys/intr.h> 115 116 #include <dev/ic/dm9000var.h> 117 #include <dev/ic/dm9000reg.h> 118 119 #if 1 120 #undef DM9000_DEBUG 121 #undef DM9000_TX_DEBUG 122 #undef DM9000_TX_DATA_DEBUG 123 #undef DM9000_RX_DEBUG 124 #undef DM9000_RX_DATA_DEBUG 125 #else 126 #define DM9000_DEBUG 127 #define DM9000_TX_DEBUG 128 #define DM9000_TX_DATA_DEBUG 129 #define DM9000_RX_DEBUG 130 #define DM9000_RX_DATA_DEBUG 131 #endif 132 133 #ifdef DM9000_DEBUG 134 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 135 #else 136 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 137 #endif 138 139 #ifdef DM9000_TX_DEBUG 140 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 141 #else 142 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 143 #endif 144 145 #ifdef DM9000_RX_DEBUG 146 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 147 #else 148 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 149 #endif 150 151 #ifdef DM9000_RX_DATA_DEBUG 152 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 153 #else 154 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 155 #endif 156 157 #ifdef DM9000_TX_DATA_DEBUG 158 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 159 #else 160 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 161 #endif 162 163 /*** Internal PHY functions ***/ 164 uint16_t dme_phy_read(struct dme_softc *sc, int reg); 165 void dme_phy_write(struct dme_softc *sc, int reg, uint16_t value); 166 void dme_phy_init(struct dme_softc *sc); 167 void dme_phy_reset(struct dme_softc *sc); 168 void dme_phy_update_media(struct dme_softc *sc); 169 void dme_phy_check_link(void *arg); 170 171 /*** Methods registered in struct ifnet ***/ 172 void dme_start_output(struct ifnet *ifp); 173 int dme_init(struct ifnet *ifp); 174 int dme_ioctl(struct ifnet *ifp, u_long cmd, void *data); 175 void dme_stop(struct ifnet *ifp, int disable); 176 177 int dme_mediachange(struct ifnet *ifp); 178 void dme_mediastatus(struct ifnet *ufp, struct ifmediareq *ifmr); 179 180 /*** Internal methods ***/ 181 182 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */ 183 void dme_prepare(struct dme_softc *sc, struct ifnet *ifp); 184 185 /* Transmit prepared data */ 186 void dme_transmit(struct dme_softc *sc); 187 188 /* Receive data */ 189 void dme_receive(struct dme_softc *sc, struct ifnet *ifp); 190 191 /* Software Initialize/Reset of the DM9000 */ 192 void dme_reset(struct dme_softc *sc); 193 194 /* Configure multicast filter */ 195 void dme_set_addr_filter(struct dme_softc *sc); 196 197 /* Set media */ 198 int dme_set_media(struct dme_softc *sc, int media); 199 200 /* Read/write packet data from/to DM9000 IC in various transfer sizes */ 201 int dme_pkt_read_2(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf); 202 int dme_pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain); 203 /* TODO: Implement 8 and 32 bit read/write functions */ 204 205 uint16_t 206 dme_phy_read(struct dme_softc *sc, int reg) 207 { 208 uint16_t val; 209 /* Select Register to read*/ 210 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 211 (reg & DM9000_EPAR_EROA_MASK)); 212 /* Select read operation (DM9000_EPCR_ERPRR) from the PHY */ 213 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY); 214 215 /* Wait until access to PHY has completed */ 216 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE); 217 218 /* Reset ERPRR-bit */ 219 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 220 221 val = dme_read(sc, DM9000_EPDRL); 222 val += dme_read(sc, DM9000_EPDRH) << 8; 223 224 return val; 225 } 226 227 void 228 dme_phy_write(struct dme_softc *sc, int reg, uint16_t value) 229 { 230 /* Select Register to write*/ 231 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 232 (reg & DM9000_EPAR_EROA_MASK)); 233 234 /* Write data to the two data registers */ 235 dme_write(sc, DM9000_EPDRL, value & 0xFF); 236 dme_write(sc, DM9000_EPDRH, (value >> 8) & 0xFF); 237 238 /* Select write operation (DM9000_EPCR_ERPRW) from the PHY */ 239 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY); 240 241 /* Wait until access to PHY has completed */ 242 while(dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE); 243 244 /* Reset ERPRR-bit */ 245 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 246 } 247 248 void 249 dme_phy_init(struct dme_softc *sc) 250 { 251 u_int ifm_media = sc->sc_media.ifm_media; 252 uint32_t bmcr, anar; 253 254 bmcr = dme_phy_read(sc, DM9000_PHY_BMCR); 255 anar = dme_phy_read(sc, DM9000_PHY_ANAR); 256 257 anar = anar & ~DM9000_PHY_ANAR_10_HDX 258 & ~DM9000_PHY_ANAR_10_FDX 259 & ~DM9000_PHY_ANAR_TX_HDX 260 & ~DM9000_PHY_ANAR_TX_FDX; 261 262 switch (IFM_SUBTYPE(ifm_media)) { 263 case IFM_AUTO: 264 bmcr |= DM9000_PHY_BMCR_AUTO_NEG_EN; 265 anar |= DM9000_PHY_ANAR_10_HDX | 266 DM9000_PHY_ANAR_10_FDX | 267 DM9000_PHY_ANAR_TX_HDX | 268 DM9000_PHY_ANAR_TX_FDX; 269 break; 270 case IFM_10_T: 271 //bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 272 bmcr &= ~DM9000_PHY_BMCR_SPEED_SELECT; 273 if (ifm_media & IFM_FDX) 274 anar |= DM9000_PHY_ANAR_10_FDX; 275 else 276 anar |= DM9000_PHY_ANAR_10_HDX; 277 break; 278 case IFM_100_TX: 279 //bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 280 bmcr |= DM9000_PHY_BMCR_SPEED_SELECT; 281 if (ifm_media & IFM_FDX) 282 anar |= DM9000_PHY_ANAR_TX_FDX; 283 else 284 anar |= DM9000_PHY_ANAR_TX_HDX; 285 286 break; 287 } 288 289 if(ifm_media & IFM_FDX) { 290 bmcr |= DM9000_PHY_BMCR_DUPLEX_MODE; 291 } else { 292 bmcr &= ~DM9000_PHY_BMCR_DUPLEX_MODE; 293 } 294 295 dme_phy_write(sc, DM9000_PHY_BMCR, bmcr); 296 dme_phy_write(sc, DM9000_PHY_ANAR, anar); 297 } 298 299 void 300 dme_phy_reset(struct dme_softc *sc) 301 { 302 uint32_t reg; 303 304 /* PHY Reset */ 305 dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET); 306 307 reg = dme_read(sc, DM9000_GPCR); 308 dme_write(sc, DM9000_GPCR, reg & ~DM9000_GPCR_GPIO0_OUT); 309 reg = dme_read(sc, DM9000_GPR); 310 dme_write(sc, DM9000_GPR, reg | DM9000_GPR_PHY_PWROFF); 311 312 dme_phy_init(sc); 313 314 reg = dme_read(sc, DM9000_GPR); 315 dme_write(sc, DM9000_GPR, reg & ~DM9000_GPR_PHY_PWROFF); 316 reg = dme_read(sc, DM9000_GPCR); 317 dme_write(sc, DM9000_GPCR, reg | DM9000_GPCR_GPIO0_OUT); 318 319 dme_phy_update_media(sc); 320 } 321 322 void 323 dme_phy_update_media(struct dme_softc *sc) 324 { 325 u_int ifm_media = sc->sc_media.ifm_media; 326 uint32_t reg; 327 328 if (IFM_SUBTYPE(ifm_media) == IFM_AUTO) { 329 /* If auto-negotiation is used, ensures that it is completed 330 before trying to extract any media information. */ 331 reg = dme_phy_read(sc, DM9000_PHY_BMSR); 332 if ((reg & DM9000_PHY_BMSR_AUTO_NEG_AB) == 0) { 333 /* Auto-negotation not possible, therefore there is no 334 reason to try obtain any media information. */ 335 return; 336 } 337 338 /* Then loop until the negotiation is completed. */ 339 while ((reg & DM9000_PHY_BMSR_AUTO_NEG_COM) == 0) { 340 /* TODO: Bail out after a finite number of attempts 341 in case something goes wrong. */ 342 preempt(); 343 reg = dme_phy_read(sc, DM9000_PHY_BMSR); 344 } 345 } 346 347 348 sc->sc_media_active = IFM_ETHER; 349 reg = dme_phy_read(sc, DM9000_PHY_BMCR); 350 351 if (reg & DM9000_PHY_BMCR_SPEED_SELECT) { 352 sc->sc_media_active |= IFM_100_TX; 353 } else { 354 sc->sc_media_active |= IFM_10_T; 355 } 356 357 if (reg & DM9000_PHY_BMCR_DUPLEX_MODE) { 358 sc->sc_media_active |= IFM_FDX; 359 } 360 } 361 362 void 363 dme_phy_check_link(void *arg) 364 { 365 struct dme_softc *sc = arg; 366 uint32_t reg; 367 int s; 368 369 s = splnet(); 370 371 reg = dme_read(sc, DM9000_NSR) & DM9000_NSR_LINKST; 372 373 if( reg ) 374 reg = IFM_ETHER | IFM_AVALID | IFM_ACTIVE; 375 else { 376 reg = IFM_ETHER | IFM_AVALID; 377 sc->sc_media_active = IFM_NONE; 378 } 379 380 if ( (sc->sc_media_status != reg) && (reg & IFM_ACTIVE)) { 381 dme_phy_reset(sc); 382 } 383 384 sc->sc_media_status = reg; 385 386 callout_schedule(&sc->sc_link_callout, mstohz(2000)); 387 splx(s); 388 } 389 390 int 391 dme_set_media(struct dme_softc *sc, int media) 392 { 393 int s; 394 395 s = splnet(); 396 sc->sc_media.ifm_media = media; 397 dme_phy_reset(sc); 398 399 splx(s); 400 401 return 0; 402 } 403 404 int 405 dme_attach(struct dme_softc *sc, const uint8_t *enaddr) 406 { 407 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 408 uint8_t b[2]; 409 uint16_t io_mode; 410 411 dme_read_c(sc, DM9000_VID0, b, 2); 412 #if BYTE_ORDER == BIG_ENDIAN 413 sc->sc_vendor_id = (b[0] << 8) | b[1]; 414 #else 415 sc->sc_vendor_id = b[0] | (b[1] << 8); 416 #endif 417 dme_read_c(sc, DM9000_PID0, b, 2); 418 #if BYTE_ORDER == BIG_ENDIAN 419 sc->sc_product_id = (b[0] << 8) | b[1]; 420 #else 421 sc->sc_product_id = b[0] | (b[1] << 8); 422 #endif 423 /* TODO: Check the vendor ID as well */ 424 if (sc->sc_product_id != 0x9000) { 425 panic("dme_attach: product id mismatch (0x%hx != 0x9000)", 426 sc->sc_product_id); 427 } 428 429 /* Initialize ifnet structure. */ 430 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 431 ifp->if_softc = sc; 432 ifp->if_start = dme_start_output; 433 ifp->if_init = dme_init; 434 ifp->if_ioctl = dme_ioctl; 435 ifp->if_stop = dme_stop; 436 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 437 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | IFF_BROADCAST | 438 IFF_MULTICAST; 439 IFQ_SET_READY(&ifp->if_snd); 440 441 /* Initialize ifmedia structures. */ 442 ifmedia_init(&sc->sc_media, 0, dme_mediachange, dme_mediastatus); 443 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_AUTO, 0, NULL); 444 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 445 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T, 0, NULL); 446 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 447 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX, 0, NULL); 448 449 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 450 451 if (enaddr != NULL) 452 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 453 /* TODO: Support an EEPROM attached to the DM9000 chip */ 454 455 callout_init(&sc->sc_link_callout, 0); 456 callout_setfunc(&sc->sc_link_callout, dme_phy_check_link, sc); 457 458 sc->sc_media_status = 0; 459 460 /* Configure DM9000 with the MAC address */ 461 dme_write_c(sc, DM9000_PAB0, sc->sc_enaddr, 6); 462 463 #ifdef DM9000_DEBUG 464 { 465 uint8_t macAddr[6]; 466 dme_read_c(sc, DM9000_PAB0, macAddr, 6); 467 printf("DM9000 configured with MAC address: "); 468 for (int i = 0; i < 6; i++) { 469 printf("%02X:", macAddr[i]); 470 } 471 printf("\n"); 472 } 473 #endif 474 475 if_attach(ifp); 476 ether_ifattach(ifp, sc->sc_enaddr); 477 478 #ifdef DM9000_DEBUG 479 { 480 uint8_t network_state; 481 network_state = dme_read(sc, DM9000_NSR); 482 printf("DM9000 Link status: "); 483 if (network_state & DM9000_NSR_LINKST) { 484 if (network_state & DM9000_NSR_SPEED) 485 printf("10Mbps"); 486 else 487 printf("100Mbps"); 488 } else { 489 printf("Down"); 490 } 491 printf("\n"); 492 } 493 #endif 494 495 io_mode = (dme_read(sc, DM9000_ISR) & 496 DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT; 497 if (io_mode != DM9000_MODE_16BIT ) 498 panic("DM9000: Only 16-bit mode is supported!\n"); 499 500 DPRINTF(("DM9000 Operation Mode: ")); 501 switch( io_mode) { 502 case DM9000_MODE_16BIT: 503 DPRINTF(("16-bit mode")); 504 sc->sc_data_width = 2; 505 sc->sc_pkt_write = dme_pkt_write_2; 506 sc->sc_pkt_read = dme_pkt_read_2; 507 break; 508 case DM9000_MODE_32BIT: 509 DPRINTF(("32-bit mode")); 510 sc->sc_data_width = 4; 511 break; 512 case DM9000_MODE_8BIT: 513 DPRINTF(("8-bit mode")); 514 sc->sc_data_width = 1; 515 break; 516 default: 517 DPRINTF(("Invalid mode")); 518 break; 519 } 520 DPRINTF(("\n")); 521 522 callout_schedule(&sc->sc_link_callout, mstohz(2000)); 523 524 return 0; 525 } 526 527 int dme_intr(void *arg) 528 { 529 struct dme_softc *sc = arg; 530 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 531 uint8_t status; 532 533 534 DPRINTF(("dme_intr: Begin\n")); 535 536 /* Disable interrupts */ 537 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR ); 538 539 status = dme_read(sc, DM9000_ISR); 540 dme_write(sc, DM9000_ISR, status); 541 542 if (status & DM9000_ISR_PRS) { 543 if (ifp->if_flags & IFF_RUNNING ) 544 dme_receive(sc, ifp); 545 } 546 if (status & DM9000_ISR_PTS) { 547 uint8_t nsr; 548 uint8_t tx_status = 0x01; /* Initialize to an error value */ 549 550 /* A packet has been transmitted */ 551 sc->txbusy = 0; 552 553 nsr = dme_read(sc, DM9000_NSR); 554 555 if (nsr & DM9000_NSR_TX1END) { 556 tx_status = dme_read(sc, DM9000_TSR1); 557 TX_DPRINTF(("dme_intr: Sent using channel 0\n")); 558 } else if (nsr & DM9000_NSR_TX2END) { 559 tx_status = dme_read(sc, DM9000_TSR2); 560 TX_DPRINTF(("dme_intr: Sent using channel 1\n")); 561 } 562 563 if (tx_status == 0x0) { 564 /* Frame successfully sent */ 565 ifp->if_opackets++; 566 } else { 567 ifp->if_oerrors++; 568 } 569 570 /* If we have nothing ready to transmit, prepare something */ 571 if (!sc->txready) { 572 dme_prepare(sc, ifp); 573 } 574 575 if (sc->txready) 576 dme_transmit(sc); 577 578 /* Prepare the next frame */ 579 dme_prepare(sc, ifp); 580 581 } 582 #ifdef notyet 583 if (status & DM9000_ISR_LNKCHNG) { 584 } 585 #endif 586 587 /* Enable interrupts again */ 588 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR | DM9000_IMR_PRM | 589 DM9000_IMR_PTM); 590 591 DPRINTF(("dme_intr: End\n")); 592 593 return 1; 594 } 595 596 void 597 dme_start_output(struct ifnet *ifp) 598 { 599 struct dme_softc *sc; 600 601 sc = ifp->if_softc; 602 603 DPRINTF(("dme_start_output: Begin\n")); 604 605 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 606 printf("No output\n"); 607 return; 608 } 609 610 if (sc->txbusy && sc->txready) { 611 panic("DM9000: Internal error, trying to send without" 612 " any empty queue\n"); 613 } 614 615 dme_prepare(sc, ifp); 616 617 if (sc->txbusy == 0) { 618 /* We are ready to transmit right away */ 619 dme_transmit(sc); 620 dme_prepare(sc, ifp); /* Prepare next one */ 621 } else { 622 /* We need to wait until the current packet has 623 * been transmitted. 624 */ 625 ifp->if_flags |= IFF_OACTIVE; 626 } 627 628 DPRINTF(("dme_start_output: End\n")); 629 } 630 631 void 632 dme_prepare(struct dme_softc *sc, struct ifnet *ifp) 633 { 634 struct mbuf *bufChain; 635 uint16_t length; 636 637 TX_DPRINTF(("dme_prepare: Entering\n")); 638 639 if (sc->txready) 640 panic("dme_prepare: Someone called us with txready set\n"); 641 642 IFQ_DEQUEUE(&ifp->if_snd, bufChain); 643 if (bufChain == NULL) { 644 TX_DPRINTF(("dme_prepare: Nothing to transmit\n")); 645 ifp->if_flags &= ~IFF_OACTIVE; /* Clear OACTIVE bit */ 646 return; /* Nothing to transmit */ 647 } 648 649 /* Element has now been removed from the queue, so we better send it */ 650 651 if (ifp->if_bpf) 652 bpf_mtap(ifp, bufChain); 653 654 /* Setup the DM9000 to accept the writes, and then write each buf in 655 the chain. */ 656 657 TX_DATA_DPRINTF(("dme_prepare: Writing data: ")); 658 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD); 659 length = sc->sc_pkt_write(sc, bufChain); 660 TX_DATA_DPRINTF(("\n")); 661 662 if (length % sc->sc_data_width != 0) { 663 panic("dme_prepare: length is not compatible with IO_MODE"); 664 } 665 666 sc->txready_length = length; 667 sc->txready = 1; 668 669 TX_DPRINTF(("dme_prepare: txbusy: %d\ndme_prepare: " 670 "txready: %d, txready_length: %d\n", 671 sc->txbusy, sc->txready, sc->txready_length)); 672 673 m_freem(bufChain); 674 675 TX_DPRINTF(("dme_prepare: Leaving\n")); 676 } 677 678 int 679 dme_init(struct ifnet *ifp) 680 { 681 int s; 682 struct dme_softc *sc = ifp->if_softc; 683 684 dme_stop(ifp, 0); 685 686 s = splnet(); 687 688 dme_reset(sc); 689 690 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 691 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 692 sc->sc_ethercom.ec_if.if_timer = 0; 693 694 splx(s); 695 696 return 0; 697 } 698 699 int 700 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data) 701 { 702 struct dme_softc *sc = ifp->if_softc; 703 struct ifreq *ifr = data; 704 int s, error = 0; 705 706 s = splnet(); 707 708 switch(cmd) { 709 case SIOCGIFMEDIA: 710 case SIOCSIFMEDIA: 711 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 712 break; 713 default: 714 error = ether_ioctl(ifp, cmd, data); 715 if (error == ENETRESET) { 716 if (ifp->if_flags && IFF_RUNNING) { 717 /* Address list has changed, reconfigure 718 filter */ 719 dme_set_addr_filter(sc); 720 } 721 error = 0; 722 } 723 break; 724 } 725 726 splx(s); 727 return error; 728 } 729 730 void 731 dme_stop(struct ifnet *ifp, int disable) 732 { 733 struct dme_softc *sc = ifp->if_softc; 734 735 /* Not quite sure what to do when called with disable == 0 */ 736 if (disable) { 737 /* Disable RX */ 738 dme_write(sc, DM9000_RCR, 0x0); 739 } 740 741 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 742 ifp->if_timer = 0; 743 } 744 745 int 746 dme_mediachange(struct ifnet *ifp) 747 { 748 struct dme_softc *sc = ifp->if_softc; 749 750 return dme_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 751 } 752 753 void 754 dme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 755 { 756 struct dme_softc *sc = ifp->if_softc; 757 758 ifmr->ifm_active = sc->sc_media_active; 759 ifmr->ifm_status = sc->sc_media_status; 760 } 761 762 void 763 dme_transmit(struct dme_softc *sc) 764 { 765 uint8_t status; 766 767 TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n", 768 sc->txready, sc->txbusy)); 769 770 dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff); 771 dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff ); 772 773 /* Request to send the packet */ 774 status = dme_read(sc, DM9000_ISR); 775 776 dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ); 777 778 sc->txready = 0; 779 sc->txbusy = 1; 780 sc->txready_length = 0; 781 } 782 783 void 784 dme_receive(struct dme_softc *sc, struct ifnet *ifp) 785 { 786 uint8_t ready = 0x01; 787 788 DPRINTF(("inside dme_receive\n")); 789 790 while (ready == 0x01) { 791 /* Packet received, retrieve it */ 792 793 /* Read without address increment to get the ready byte without moving past it. */ 794 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 795 sc->dme_io, DM9000_MRCMDX); 796 /* Dummy ready */ 797 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 798 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 799 ready &= 0x03; /* we only want bits 1:0 */ 800 if (ready == 0x01) { 801 uint8_t rx_status; 802 struct mbuf *m; 803 804 /* Read with address increment. */ 805 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 806 sc->dme_io, DM9000_MRCMD); 807 808 rx_status = sc->sc_pkt_read(sc, ifp, &m); 809 810 if (rx_status & (DM9000_RSR_CE | DM9000_RSR_PLE)) { 811 /* Error while receiving the packet, 812 * discard it and keep track of counters 813 */ 814 ifp->if_ierrors++; 815 RX_DPRINTF(("dme_receive: " 816 "Error reciving packet\n")); 817 } else if (rx_status & DM9000_RSR_LCS) { 818 ifp->if_collisions++; 819 } else { 820 if (ifp->if_bpf) 821 bpf_mtap(ifp, m); 822 ifp->if_ipackets++; 823 (*ifp->if_input)(ifp, m); 824 } 825 826 } else if (ready != 0x00) { 827 /* Should this be logged somehow? */ 828 printf("%s: Resetting chip\n", 829 device_xname(sc->sc_dev)); 830 dme_reset(sc); 831 } 832 } 833 } 834 835 void 836 dme_reset(struct dme_softc *sc) 837 { 838 uint8_t var; 839 840 /* We only re-initialized the PHY in this function the first time it is 841 called. */ 842 if( !sc->sc_phy_initialized) { 843 /* PHY Reset */ 844 dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET); 845 846 /* PHY Power Down */ 847 var = dme_read(sc, DM9000_GPR); 848 dme_write(sc, DM9000_GPR, var | DM9000_GPR_PHY_PWROFF); 849 } 850 851 /* Reset the DM9000 twice, as described in section 2 of the Programming 852 Guide. 853 The PHY is initialized and enabled between those two resets. 854 */ 855 856 /* Software Reset*/ 857 dme_write(sc, DM9000_NCR, 858 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 859 delay(20); 860 dme_write(sc, DM9000_NCR, 0x0); 861 862 if( !sc->sc_phy_initialized) { 863 /* PHY Initialization */ 864 dme_phy_init(sc); 865 866 /* PHY Enable */ 867 var = dme_read(sc, DM9000_GPR); 868 dme_write(sc, DM9000_GPR, var & ~DM9000_GPR_PHY_PWROFF); 869 var = dme_read(sc, DM9000_GPCR); 870 dme_write(sc, DM9000_GPCR, var | DM9000_GPCR_GPIO0_OUT); 871 872 dme_write(sc, DM9000_NCR, 873 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 874 delay(20); 875 dme_write(sc, DM9000_NCR, 0x0); 876 } 877 878 /* Select internal PHY, no wakeup event, no collosion mode, 879 * normal loopback mode. 880 */ 881 dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL ); 882 883 /* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/ 884 dme_read(sc, DM9000_NSR); 885 886 /* Enable wraparound of read/write pointer, packet received latch, 887 * and packet transmitted latch. 888 */ 889 dme_write(sc, DM9000_IMR, 890 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 891 892 /* Setup multicast address filter, and enable RX. */ 893 dme_set_addr_filter(sc); 894 895 /* Obtain media information from PHY */ 896 dme_phy_update_media(sc); 897 898 sc->txbusy = 0; 899 sc->txready = 0; 900 sc->sc_phy_initialized = 1; 901 } 902 903 void 904 dme_set_addr_filter(struct dme_softc *sc) 905 { 906 struct ether_multi *enm; 907 struct ether_multistep step; 908 struct ethercom *ec; 909 struct ifnet *ifp; 910 uint16_t af[4]; 911 int i; 912 913 ec = &sc->sc_ethercom; 914 ifp = &ec->ec_if; 915 916 if (ifp->if_flags & IFF_PROMISC) { 917 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | 918 DM9000_RCR_WTDIS | 919 DM9000_RCR_PRMSC); 920 ifp->if_flags |= IFF_ALLMULTI; 921 return; 922 } 923 924 af[0] = af[1] = af[2] = af[3] = 0x0000; 925 ifp->if_flags &= ~IFF_ALLMULTI; 926 927 ETHER_FIRST_MULTI(step, ec, enm); 928 while (enm != NULL) { 929 uint16_t hash; 930 if (memcpy(enm->enm_addrlo, enm->enm_addrhi, 931 sizeof(enm->enm_addrlo))) { 932 /* 933 * We must listen to a range of multicast addresses. 934 * For now, just accept all multicasts, rather than 935 * trying to set only those filter bits needed to match 936 * the range. (At this time, the only use of address 937 * ranges is for IP multicast routing, for which the 938 * range is big enough to require all bits set.) 939 */ 940 ifp->if_flags |= IFF_ALLMULTI; 941 af[0] = af[1] = af[2] = af[3] = 0xffff; 942 break; 943 } else { 944 hash = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3F; 945 af[(uint16_t)(hash>>4)] |= (uint16_t)(1 << (hash % 16)); 946 ETHER_NEXT_MULTI(step, enm); 947 } 948 } 949 950 /* Write the multicast address filter */ 951 for(i=0; i<4; i++) { 952 dme_write(sc, DM9000_MAB0+i*2, af[i] & 0xFF); 953 dme_write(sc, DM9000_MAB0+i*2+1, (af[i] >> 8) & 0xFF); 954 } 955 956 /* Setup RX controls */ 957 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | DM9000_RCR_WTDIS); 958 } 959 960 int 961 dme_pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain) 962 { 963 int left_over_count = 0; /* Number of bytes from previous mbuf, which 964 need to be written with the next.*/ 965 uint16_t left_over_buf = 0; 966 int length = 0; 967 struct mbuf *buf; 968 uint8_t *write_ptr; 969 970 /* We expect that the DM9000 has been setup to accept writes before 971 this function is called. */ 972 973 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 974 int to_write = buf->m_len; 975 976 length += to_write; 977 978 write_ptr = buf->m_data; 979 while (to_write > 0 || 980 (buf->m_next == NULL && left_over_count > 0) 981 ) { 982 if (left_over_count > 0) { 983 uint8_t b = 0; 984 DPRINTF(("dme_pkt_write_16: " 985 "Writing left over byte\n")); 986 987 if (to_write > 0) { 988 b = *write_ptr; 989 to_write--; 990 write_ptr++; 991 992 DPRINTF(("Took single byte\n")); 993 } else { 994 DPRINTF(("Leftover in last run\n")); 995 length++; 996 } 997 998 /* Does shift direction depend on endianess? */ 999 left_over_buf = left_over_buf | (b << 8); 1000 1001 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 1002 sc->dme_data, left_over_buf); 1003 TX_DATA_DPRINTF(("%02X ", left_over_buf)); 1004 left_over_count = 0; 1005 } else if ((long)write_ptr % 2 != 0) { 1006 /* Misaligned data */ 1007 DPRINTF(("dme_pkt_write_16: " 1008 "Detected misaligned data\n")); 1009 left_over_buf = *write_ptr; 1010 left_over_count = 1; 1011 write_ptr++; 1012 to_write--; 1013 } else { 1014 int i; 1015 uint16_t *dptr = (uint16_t*)write_ptr; 1016 1017 /* A block of aligned data. */ 1018 for(i = 0; i < to_write/2; i++) { 1019 /* buf will be half-word aligned 1020 * all the time 1021 */ 1022 bus_space_write_2(sc->sc_iot, 1023 sc->sc_ioh, sc->dme_data, *dptr); 1024 TX_DATA_DPRINTF(("%02X %02X ", 1025 *dptr & 0xFF, (*dptr>>8) & 0xFF)); 1026 dptr++; 1027 } 1028 1029 write_ptr += i*2; 1030 if (to_write % 2 != 0) { 1031 DPRINTF(("dme_pkt_write_16: " 1032 "to_write %% 2: %d\n", 1033 to_write % 2)); 1034 left_over_count = 1; 1035 /* XXX: Does this depend on 1036 * the endianess? 1037 */ 1038 left_over_buf = *write_ptr; 1039 1040 write_ptr++; 1041 to_write--; 1042 DPRINTF(("dme_pkt_write_16: " 1043 "to_write (after): %d\n", 1044 to_write)); 1045 DPRINTF(("dme_pkt_write_16: i*2: %d\n", 1046 i*2)); 1047 } 1048 to_write -= i*2; 1049 } 1050 } /* while(...) */ 1051 } /* for(...) */ 1052 1053 return length; 1054 } 1055 1056 int 1057 dme_pkt_read_2(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf) 1058 { 1059 uint8_t rx_status; 1060 struct mbuf *m; 1061 uint16_t data; 1062 uint16_t frame_length; 1063 uint16_t i; 1064 uint16_t *buf; 1065 1066 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 1067 sc->dme_data); 1068 1069 rx_status = data & 0xFF; 1070 frame_length = bus_space_read_2(sc->sc_iot, 1071 sc->sc_ioh, sc->dme_data); 1072 if (frame_length > ETHER_MAX_LEN) { 1073 printf("Got frame of length: %d\n", frame_length); 1074 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1075 panic("Something is rotten"); 1076 } 1077 RX_DPRINTF(("dme_receive: " 1078 "rx_statux: 0x%x, frame_length: %d\n", 1079 rx_status, frame_length)); 1080 1081 1082 m = dme_alloc_receive_buffer(ifp, frame_length); 1083 1084 buf = mtod(m, uint16_t*); 1085 1086 RX_DPRINTF(("dme_receive: ")); 1087 1088 for(i=0; i< frame_length; i+=2 ) { 1089 data = bus_space_read_2(sc->sc_iot, 1090 sc->sc_ioh, sc->dme_data); 1091 if ( (frame_length % 2 != 0) && 1092 (i == frame_length-1) ) { 1093 data = data & 0xff; 1094 RX_DPRINTF((" L ")); 1095 } 1096 *buf = data; 1097 buf++; 1098 RX_DATA_DPRINTF(("%02X %02X ", data & 0xff, 1099 (data>>8) & 0xff)); 1100 } 1101 1102 RX_DATA_DPRINTF(("\n")); 1103 RX_DPRINTF(("Read %d bytes\n", i)); 1104 1105 *outBuf = m; 1106 return rx_status; 1107 } 1108 1109 struct mbuf* 1110 dme_alloc_receive_buffer(struct ifnet *ifp, unsigned int frame_length) 1111 { 1112 struct dme_softc *sc = ifp->if_softc; 1113 struct mbuf *m; 1114 int pad; 1115 1116 MGETHDR(m, M_DONTWAIT, MT_DATA); 1117 m->m_pkthdr.rcvif = ifp; 1118 /* Ensure that we always allocate an even number of 1119 * bytes in order to avoid writing beyond the buffer 1120 */ 1121 m->m_pkthdr.len = frame_length + (frame_length % sc->sc_data_width); 1122 pad = ALIGN(sizeof(struct ether_header)) - 1123 sizeof(struct ether_header); 1124 /* All our frames have the CRC attached */ 1125 m->m_flags |= M_HASFCS; 1126 if (m->m_pkthdr.len + pad > MHLEN ) 1127 MCLGET(m, M_DONTWAIT); 1128 1129 m->m_data += pad; 1130 m->m_len = frame_length + (frame_length % sc->sc_data_width); 1131 1132 return m; 1133 } 1134
Indexes created Fri Sep 26 08:10:20 GMT 2025