dm9000.c revision 1.7
1 /* $NetBSD: dm9000.c,v 1.7 2015/03/14 13:45:43 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* based on sys/dev/ic/cs89x0.c */ 30 /* 31 * Copyright (c) 2004 Christopher Gilbert 32 * All rights reserved. 33 * 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The name of the company nor the name of the author may be used to 40 * endorse or promote products derived from this software without specific 41 * prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright 1997 58 * Digital Equipment Corporation. All rights reserved. 59 * 60 * This software is furnished under license and may be used and 61 * copied only in accordance with the following terms and conditions. 62 * Subject to these conditions, you may download, copy, install, 63 * use, modify and distribute this software in source and/or binary 64 * form. No title or ownership is transferred hereby. 65 * 66 * 1) Any source code used, modified or distributed must reproduce 67 * and retain this copyright notice and list of conditions as 68 * they appear in the source file. 69 * 70 * 2) No right is granted to use any trade name, trademark, or logo of 71 * Digital Equipment Corporation. Neither the "Digital Equipment 72 * Corporation" name nor any trademark or logo of Digital Equipment 73 * Corporation may be used to endorse or promote products derived 74 * from this software without the prior written permission of 75 * Digital Equipment Corporation. 76 * 77 * 3) This software is provided "AS-IS" and any express or implied 78 * warranties, including but not limited to, any implied warranties 79 * of merchantability, fitness for a particular purpose, or 80 * non-infringement are disclaimed. In no event shall DIGITAL be 81 * liable for any damages whatsoever, and in particular, DIGITAL 82 * shall not be liable for special, indirect, consequential, or 83 * incidental damages or damages for lost profits, loss of 84 * revenue or loss of use, whether such damages arise in contract, 85 * negligence, tort, under statute, in equity, at law or otherwise, 86 * even if advised of the possibility of such damage. 87 */ 88 89 #include <sys/cdefs.h> 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/mbuf.h> 95 #include <sys/syslog.h> 96 #include <sys/socket.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 #include <sys/ioctl.h> 100 #include <sys/errno.h> 101 102 #include <net/if.h> 103 #include <net/if_ether.h> 104 #include <net/if_media.h> 105 #ifdef INET 106 #include <netinet/in.h> 107 #include <netinet/if_inarp.h> 108 #endif 109 110 #include <net/bpf.h> 111 #include <net/bpfdesc.h> 112 113 #include <sys/bus.h> 114 #include <sys/intr.h> 115 116 #include <dev/ic/dm9000var.h> 117 #include <dev/ic/dm9000reg.h> 118 119 #if 1 120 #undef DM9000_DEBUG 121 #undef DM9000_TX_DEBUG 122 #undef DM9000_TX_DATA_DEBUG 123 #undef DM9000_RX_DEBUG 124 #undef DM9000_RX_DATA_DEBUG 125 #else 126 #define DM9000_DEBUG 127 #define DM9000_TX_DEBUG 128 #define DM9000_TX_DATA_DEBUG 129 #define DM9000_RX_DEBUG 130 #define DM9000_RX_DATA_DEBUG 131 #endif 132 133 #ifdef DM9000_DEBUG 134 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 135 #else 136 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 137 #endif 138 139 #ifdef DM9000_TX_DEBUG 140 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 141 #else 142 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 143 #endif 144 145 #ifdef DM9000_RX_DEBUG 146 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 147 #else 148 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 149 #endif 150 151 #ifdef DM9000_RX_DATA_DEBUG 152 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 153 #else 154 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 155 #endif 156 157 #ifdef DM9000_TX_DATA_DEBUG 158 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 159 #else 160 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 161 #endif 162 163 /*** Internal PHY functions ***/ 164 uint16_t dme_phy_read(struct dme_softc *, int ); 165 void dme_phy_write(struct dme_softc *, int, uint16_t); 166 void dme_phy_init(struct dme_softc *); 167 void dme_phy_reset(struct dme_softc *); 168 void dme_phy_update_media(struct dme_softc *); 169 void dme_phy_check_link(void *); 170 171 /*** Methods registered in struct ifnet ***/ 172 void dme_start_output(struct ifnet *); 173 int dme_init(struct ifnet *); 174 int dme_ioctl(struct ifnet *, u_long, void *); 175 void dme_stop(struct ifnet *, int); 176 177 int dme_mediachange(struct ifnet *); 178 void dme_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 /*** Internal methods ***/ 181 182 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */ 183 void dme_prepare(struct dme_softc *, struct ifnet *); 184 185 /* Transmit prepared data */ 186 void dme_transmit(struct dme_softc *); 187 188 /* Receive data */ 189 void dme_receive(struct dme_softc *, struct ifnet *); 190 191 /* Software Initialize/Reset of the DM9000 */ 192 void dme_reset(struct dme_softc *); 193 194 /* Configure multicast filter */ 195 void dme_set_addr_filter(struct dme_softc *); 196 197 /* Set media */ 198 int dme_set_media(struct dme_softc *, int ); 199 200 /* Read/write packet data from/to DM9000 IC in various transfer sizes */ 201 int dme_pkt_read_2(struct dme_softc *, struct ifnet *, struct mbuf **); 202 int dme_pkt_write_2(struct dme_softc *, struct mbuf *); 203 int dme_pkt_read_1(struct dme_softc *, struct ifnet *, struct mbuf **); 204 int dme_pkt_write_1(struct dme_softc *, struct mbuf *); 205 /* TODO: Implement 32 bit read/write functions */ 206 207 uint16_t 208 dme_phy_read(struct dme_softc *sc, int reg) 209 { 210 uint16_t val; 211 /* Select Register to read*/ 212 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 213 (reg & DM9000_EPAR_EROA_MASK)); 214 /* Select read operation (DM9000_EPCR_ERPRR) from the PHY */ 215 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY); 216 217 /* Wait until access to PHY has completed */ 218 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE); 219 220 /* Reset ERPRR-bit */ 221 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 222 223 val = dme_read(sc, DM9000_EPDRL); 224 val += dme_read(sc, DM9000_EPDRH) << 8; 225 226 return val; 227 } 228 229 void 230 dme_phy_write(struct dme_softc *sc, int reg, uint16_t value) 231 { 232 /* Select Register to write*/ 233 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 234 (reg & DM9000_EPAR_EROA_MASK)); 235 236 /* Write data to the two data registers */ 237 dme_write(sc, DM9000_EPDRL, value & 0xFF); 238 dme_write(sc, DM9000_EPDRH, (value >> 8) & 0xFF); 239 240 /* Select write operation (DM9000_EPCR_ERPRW) from the PHY */ 241 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY); 242 243 /* Wait until access to PHY has completed */ 244 while(dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE); 245 246 /* Reset ERPRR-bit */ 247 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 248 } 249 250 void 251 dme_phy_init(struct dme_softc *sc) 252 { 253 u_int ifm_media = sc->sc_media.ifm_media; 254 uint32_t bmcr, anar; 255 256 bmcr = dme_phy_read(sc, DM9000_PHY_BMCR); 257 anar = dme_phy_read(sc, DM9000_PHY_ANAR); 258 259 anar = anar & ~DM9000_PHY_ANAR_10_HDX 260 & ~DM9000_PHY_ANAR_10_FDX 261 & ~DM9000_PHY_ANAR_TX_HDX 262 & ~DM9000_PHY_ANAR_TX_FDX; 263 264 switch (IFM_SUBTYPE(ifm_media)) { 265 case IFM_AUTO: 266 bmcr |= DM9000_PHY_BMCR_AUTO_NEG_EN; 267 anar |= DM9000_PHY_ANAR_10_HDX | 268 DM9000_PHY_ANAR_10_FDX | 269 DM9000_PHY_ANAR_TX_HDX | 270 DM9000_PHY_ANAR_TX_FDX; 271 break; 272 case IFM_10_T: 273 //bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 274 bmcr &= ~DM9000_PHY_BMCR_SPEED_SELECT; 275 if (ifm_media & IFM_FDX) 276 anar |= DM9000_PHY_ANAR_10_FDX; 277 else 278 anar |= DM9000_PHY_ANAR_10_HDX; 279 break; 280 case IFM_100_TX: 281 //bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN; 282 bmcr |= DM9000_PHY_BMCR_SPEED_SELECT; 283 if (ifm_media & IFM_FDX) 284 anar |= DM9000_PHY_ANAR_TX_FDX; 285 else 286 anar |= DM9000_PHY_ANAR_TX_HDX; 287 288 break; 289 } 290 291 if(ifm_media & IFM_FDX) { 292 bmcr |= DM9000_PHY_BMCR_DUPLEX_MODE; 293 } else { 294 bmcr &= ~DM9000_PHY_BMCR_DUPLEX_MODE; 295 } 296 297 dme_phy_write(sc, DM9000_PHY_BMCR, bmcr); 298 dme_phy_write(sc, DM9000_PHY_ANAR, anar); 299 } 300 301 void 302 dme_phy_reset(struct dme_softc *sc) 303 { 304 uint32_t reg; 305 306 /* PHY Reset */ 307 dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET); 308 309 reg = dme_read(sc, DM9000_GPCR); 310 dme_write(sc, DM9000_GPCR, reg & ~DM9000_GPCR_GPIO0_OUT); 311 reg = dme_read(sc, DM9000_GPR); 312 dme_write(sc, DM9000_GPR, reg | DM9000_GPR_PHY_PWROFF); 313 314 dme_phy_init(sc); 315 316 reg = dme_read(sc, DM9000_GPR); 317 dme_write(sc, DM9000_GPR, reg & ~DM9000_GPR_PHY_PWROFF); 318 reg = dme_read(sc, DM9000_GPCR); 319 dme_write(sc, DM9000_GPCR, reg | DM9000_GPCR_GPIO0_OUT); 320 321 dme_phy_update_media(sc); 322 } 323 324 void 325 dme_phy_update_media(struct dme_softc *sc) 326 { 327 u_int ifm_media = sc->sc_media.ifm_media; 328 uint32_t reg; 329 330 if (IFM_SUBTYPE(ifm_media) == IFM_AUTO) { 331 /* If auto-negotiation is used, ensures that it is completed 332 before trying to extract any media information. */ 333 reg = dme_phy_read(sc, DM9000_PHY_BMSR); 334 if ((reg & DM9000_PHY_BMSR_AUTO_NEG_AB) == 0) { 335 /* Auto-negotation not possible, therefore there is no 336 reason to try obtain any media information. */ 337 return; 338 } 339 340 /* Then loop until the negotiation is completed. */ 341 while ((reg & DM9000_PHY_BMSR_AUTO_NEG_COM) == 0) { 342 /* TODO: Bail out after a finite number of attempts 343 in case something goes wrong. */ 344 preempt(); 345 reg = dme_phy_read(sc, DM9000_PHY_BMSR); 346 } 347 } 348 349 350 sc->sc_media_active = IFM_ETHER; 351 reg = dme_phy_read(sc, DM9000_PHY_BMCR); 352 353 if (reg & DM9000_PHY_BMCR_SPEED_SELECT) { 354 sc->sc_media_active |= IFM_100_TX; 355 } else { 356 sc->sc_media_active |= IFM_10_T; 357 } 358 359 if (reg & DM9000_PHY_BMCR_DUPLEX_MODE) { 360 sc->sc_media_active |= IFM_FDX; 361 } 362 } 363 364 void 365 dme_phy_check_link(void *arg) 366 { 367 struct dme_softc *sc = arg; 368 uint32_t reg; 369 int s; 370 371 s = splnet(); 372 373 reg = dme_read(sc, DM9000_NSR) & DM9000_NSR_LINKST; 374 375 if( reg ) 376 reg = IFM_ETHER | IFM_AVALID | IFM_ACTIVE; 377 else { 378 reg = IFM_ETHER | IFM_AVALID; 379 sc->sc_media_active = IFM_NONE; 380 } 381 382 if ( (sc->sc_media_status != reg) && (reg & IFM_ACTIVE)) { 383 dme_phy_reset(sc); 384 } 385 386 sc->sc_media_status = reg; 387 388 callout_schedule(&sc->sc_link_callout, mstohz(2000)); 389 splx(s); 390 } 391 392 int 393 dme_set_media(struct dme_softc *sc, int media) 394 { 395 int s; 396 397 s = splnet(); 398 sc->sc_media.ifm_media = media; 399 dme_phy_reset(sc); 400 401 splx(s); 402 403 return 0; 404 } 405 406 int 407 dme_attach(struct dme_softc *sc, const uint8_t *enaddr) 408 { 409 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 410 uint8_t b[2]; 411 uint16_t io_mode; 412 413 dme_read_c(sc, DM9000_VID0, b, 2); 414 #if BYTE_ORDER == BIG_ENDIAN 415 sc->sc_vendor_id = (b[0] << 8) | b[1]; 416 #else 417 sc->sc_vendor_id = b[0] | (b[1] << 8); 418 #endif 419 dme_read_c(sc, DM9000_PID0, b, 2); 420 #if BYTE_ORDER == BIG_ENDIAN 421 sc->sc_product_id = (b[0] << 8) | b[1]; 422 #else 423 sc->sc_product_id = b[0] | (b[1] << 8); 424 #endif 425 /* TODO: Check the vendor ID as well */ 426 if (sc->sc_product_id != 0x9000) { 427 panic("dme_attach: product id mismatch (0x%hx != 0x9000)", 428 sc->sc_product_id); 429 } 430 431 /* Initialize ifnet structure. */ 432 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 433 ifp->if_softc = sc; 434 ifp->if_start = dme_start_output; 435 ifp->if_init = dme_init; 436 ifp->if_ioctl = dme_ioctl; 437 ifp->if_stop = dme_stop; 438 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 439 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | IFF_BROADCAST | 440 IFF_MULTICAST; 441 IFQ_SET_READY(&ifp->if_snd); 442 443 /* Initialize ifmedia structures. */ 444 ifmedia_init(&sc->sc_media, 0, dme_mediachange, dme_mediastatus); 445 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_AUTO, 0, NULL); 446 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 447 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T, 0, NULL); 448 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 449 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX, 0, NULL); 450 451 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 452 453 if (enaddr != NULL) 454 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 455 /* TODO: Support an EEPROM attached to the DM9000 chip */ 456 457 callout_init(&sc->sc_link_callout, 0); 458 callout_setfunc(&sc->sc_link_callout, dme_phy_check_link, sc); 459 460 sc->sc_media_status = 0; 461 462 /* Configure DM9000 with the MAC address */ 463 dme_write_c(sc, DM9000_PAB0, sc->sc_enaddr, 6); 464 465 #ifdef DM9000_DEBUG 466 { 467 uint8_t macAddr[6]; 468 dme_read_c(sc, DM9000_PAB0, macAddr, 6); 469 printf("DM9000 configured with MAC address: "); 470 for (int i = 0; i < 6; i++) { 471 printf("%02X:", macAddr[i]); 472 } 473 printf("\n"); 474 } 475 #endif 476 477 if_attach(ifp); 478 ether_ifattach(ifp, sc->sc_enaddr); 479 480 #ifdef DM9000_DEBUG 481 { 482 uint8_t network_state; 483 network_state = dme_read(sc, DM9000_NSR); 484 printf("DM9000 Link status: "); 485 if (network_state & DM9000_NSR_LINKST) { 486 if (network_state & DM9000_NSR_SPEED) 487 printf("10Mbps"); 488 else 489 printf("100Mbps"); 490 } else { 491 printf("Down"); 492 } 493 printf("\n"); 494 } 495 #endif 496 497 io_mode = (dme_read(sc, DM9000_ISR) & 498 DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT; 499 500 DPRINTF(("DM9000 Operation Mode: ")); 501 switch( io_mode) { 502 case DM9000_MODE_16BIT: 503 DPRINTF(("16-bit mode")); 504 sc->sc_data_width = 2; 505 sc->sc_pkt_write = dme_pkt_write_2; 506 sc->sc_pkt_read = dme_pkt_read_2; 507 break; 508 case DM9000_MODE_32BIT: 509 DPRINTF(("32-bit mode")); 510 sc->sc_data_width = 4; 511 panic("32bit mode is unsupported\n"); 512 break; 513 case DM9000_MODE_8BIT: 514 DPRINTF(("8-bit mode")); 515 sc->sc_data_width = 1; 516 sc->sc_pkt_write = dme_pkt_write_1; 517 sc->sc_pkt_read = dme_pkt_read_1; 518 break; 519 default: 520 DPRINTF(("Invalid mode")); 521 break; 522 } 523 DPRINTF(("\n")); 524 525 callout_schedule(&sc->sc_link_callout, mstohz(2000)); 526 527 return 0; 528 } 529 530 int dme_intr(void *arg) 531 { 532 struct dme_softc *sc = arg; 533 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 534 uint8_t status; 535 536 537 DPRINTF(("dme_intr: Begin\n")); 538 539 /* Disable interrupts */ 540 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR ); 541 542 status = dme_read(sc, DM9000_ISR); 543 dme_write(sc, DM9000_ISR, status); 544 545 if (status & DM9000_ISR_PRS) { 546 if (ifp->if_flags & IFF_RUNNING ) 547 dme_receive(sc, ifp); 548 } 549 if (status & DM9000_ISR_PTS) { 550 uint8_t nsr; 551 uint8_t tx_status = 0x01; /* Initialize to an error value */ 552 553 /* A packet has been transmitted */ 554 sc->txbusy = 0; 555 556 nsr = dme_read(sc, DM9000_NSR); 557 558 if (nsr & DM9000_NSR_TX1END) { 559 tx_status = dme_read(sc, DM9000_TSR1); 560 TX_DPRINTF(("dme_intr: Sent using channel 0\n")); 561 } else if (nsr & DM9000_NSR_TX2END) { 562 tx_status = dme_read(sc, DM9000_TSR2); 563 TX_DPRINTF(("dme_intr: Sent using channel 1\n")); 564 } 565 566 if (tx_status == 0x0) { 567 /* Frame successfully sent */ 568 ifp->if_opackets++; 569 } else { 570 ifp->if_oerrors++; 571 } 572 573 /* If we have nothing ready to transmit, prepare something */ 574 if (!sc->txready) { 575 dme_prepare(sc, ifp); 576 } 577 578 if (sc->txready) 579 dme_transmit(sc); 580 581 /* Prepare the next frame */ 582 dme_prepare(sc, ifp); 583 584 } 585 #ifdef notyet 586 if (status & DM9000_ISR_LNKCHNG) { 587 } 588 #endif 589 590 /* Enable interrupts again */ 591 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR | DM9000_IMR_PRM | 592 DM9000_IMR_PTM); 593 594 DPRINTF(("dme_intr: End\n")); 595 596 return 1; 597 } 598 599 void 600 dme_start_output(struct ifnet *ifp) 601 { 602 struct dme_softc *sc; 603 604 sc = ifp->if_softc; 605 606 DPRINTF(("dme_start_output: Begin\n")); 607 608 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 609 printf("No output\n"); 610 return; 611 } 612 613 if (sc->txbusy && sc->txready) { 614 panic("DM9000: Internal error, trying to send without" 615 " any empty queue\n"); 616 } 617 618 dme_prepare(sc, ifp); 619 620 if (sc->txbusy == 0) { 621 /* We are ready to transmit right away */ 622 dme_transmit(sc); 623 dme_prepare(sc, ifp); /* Prepare next one */ 624 } else { 625 /* We need to wait until the current packet has 626 * been transmitted. 627 */ 628 ifp->if_flags |= IFF_OACTIVE; 629 } 630 631 DPRINTF(("dme_start_output: End\n")); 632 } 633 634 void 635 dme_prepare(struct dme_softc *sc, struct ifnet *ifp) 636 { 637 struct mbuf *bufChain; 638 uint16_t length; 639 640 TX_DPRINTF(("dme_prepare: Entering\n")); 641 642 if (sc->txready) 643 panic("dme_prepare: Someone called us with txready set\n"); 644 645 IFQ_DEQUEUE(&ifp->if_snd, bufChain); 646 if (bufChain == NULL) { 647 TX_DPRINTF(("dme_prepare: Nothing to transmit\n")); 648 ifp->if_flags &= ~IFF_OACTIVE; /* Clear OACTIVE bit */ 649 return; /* Nothing to transmit */ 650 } 651 652 /* Element has now been removed from the queue, so we better send it */ 653 654 if (ifp->if_bpf) 655 bpf_mtap(ifp, bufChain); 656 657 /* Setup the DM9000 to accept the writes, and then write each buf in 658 the chain. */ 659 660 TX_DATA_DPRINTF(("dme_prepare: Writing data: ")); 661 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD); 662 length = sc->sc_pkt_write(sc, bufChain); 663 TX_DATA_DPRINTF(("\n")); 664 665 if (length % sc->sc_data_width != 0) { 666 panic("dme_prepare: length is not compatible with IO_MODE"); 667 } 668 669 sc->txready_length = length; 670 sc->txready = 1; 671 672 TX_DPRINTF(("dme_prepare: txbusy: %d\ndme_prepare: " 673 "txready: %d, txready_length: %d\n", 674 sc->txbusy, sc->txready, sc->txready_length)); 675 676 m_freem(bufChain); 677 678 TX_DPRINTF(("dme_prepare: Leaving\n")); 679 } 680 681 int 682 dme_init(struct ifnet *ifp) 683 { 684 int s; 685 struct dme_softc *sc = ifp->if_softc; 686 687 dme_stop(ifp, 0); 688 689 s = splnet(); 690 691 dme_reset(sc); 692 693 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 694 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 695 sc->sc_ethercom.ec_if.if_timer = 0; 696 697 splx(s); 698 699 return 0; 700 } 701 702 int 703 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data) 704 { 705 struct dme_softc *sc = ifp->if_softc; 706 struct ifreq *ifr = data; 707 int s, error = 0; 708 709 s = splnet(); 710 711 switch(cmd) { 712 case SIOCGIFMEDIA: 713 case SIOCSIFMEDIA: 714 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 715 break; 716 default: 717 error = ether_ioctl(ifp, cmd, data); 718 if (error == ENETRESET) { 719 if (ifp->if_flags && IFF_RUNNING) { 720 /* Address list has changed, reconfigure 721 filter */ 722 dme_set_addr_filter(sc); 723 } 724 error = 0; 725 } 726 break; 727 } 728 729 splx(s); 730 return error; 731 } 732 733 void 734 dme_stop(struct ifnet *ifp, int disable) 735 { 736 struct dme_softc *sc = ifp->if_softc; 737 738 /* Not quite sure what to do when called with disable == 0 */ 739 if (disable) { 740 /* Disable RX */ 741 dme_write(sc, DM9000_RCR, 0x0); 742 } 743 744 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 745 ifp->if_timer = 0; 746 } 747 748 int 749 dme_mediachange(struct ifnet *ifp) 750 { 751 struct dme_softc *sc = ifp->if_softc; 752 753 return dme_set_media(sc, sc->sc_media.ifm_cur->ifm_media); 754 } 755 756 void 757 dme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 758 { 759 struct dme_softc *sc = ifp->if_softc; 760 761 ifmr->ifm_active = sc->sc_media_active; 762 ifmr->ifm_status = sc->sc_media_status; 763 } 764 765 void 766 dme_transmit(struct dme_softc *sc) 767 { 768 769 TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n", 770 sc->txready, sc->txbusy)); 771 772 dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff); 773 dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff ); 774 775 /* Request to send the packet */ 776 dme_read(sc, DM9000_ISR); 777 778 dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ); 779 780 sc->txready = 0; 781 sc->txbusy = 1; 782 sc->txready_length = 0; 783 } 784 785 void 786 dme_receive(struct dme_softc *sc, struct ifnet *ifp) 787 { 788 uint8_t ready = 0x01; 789 790 DPRINTF(("inside dme_receive\n")); 791 792 while (ready == 0x01) { 793 /* Packet received, retrieve it */ 794 795 /* Read without address increment to get the ready byte without 796 moving past it. */ 797 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 798 sc->dme_io, DM9000_MRCMDX); 799 /* Dummy ready */ 800 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 801 ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 802 ready &= 0x03; /* we only want bits 1:0 */ 803 if (ready == 0x01) { 804 uint8_t rx_status; 805 struct mbuf *m; 806 807 /* Read with address increment. */ 808 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 809 sc->dme_io, DM9000_MRCMD); 810 811 rx_status = sc->sc_pkt_read(sc, ifp, &m); 812 813 if (rx_status & (DM9000_RSR_CE | DM9000_RSR_PLE)) { 814 /* Error while receiving the packet, 815 * discard it and keep track of counters 816 */ 817 ifp->if_ierrors++; 818 RX_DPRINTF(("dme_receive: " 819 "Error reciving packet\n")); 820 } else if (rx_status & DM9000_RSR_LCS) { 821 ifp->if_collisions++; 822 } else { 823 if (ifp->if_bpf) 824 bpf_mtap(ifp, m); 825 ifp->if_ipackets++; 826 (*ifp->if_input)(ifp, m); 827 } 828 829 } else if (ready != 0x00) { 830 /* Should this be logged somehow? */ 831 printf("%s: Resetting chip\n", 832 device_xname(sc->sc_dev)); 833 dme_reset(sc); 834 } 835 } 836 } 837 838 void 839 dme_reset(struct dme_softc *sc) 840 { 841 uint8_t var; 842 843 /* We only re-initialized the PHY in this function the first time it is 844 called. */ 845 if( !sc->sc_phy_initialized) { 846 /* PHY Reset */ 847 dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET); 848 849 /* PHY Power Down */ 850 var = dme_read(sc, DM9000_GPR); 851 dme_write(sc, DM9000_GPR, var | DM9000_GPR_PHY_PWROFF); 852 } 853 854 /* Reset the DM9000 twice, as described in section 2 of the Programming 855 Guide. 856 The PHY is initialized and enabled between those two resets. 857 */ 858 859 /* Software Reset*/ 860 dme_write(sc, DM9000_NCR, 861 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 862 delay(20); 863 dme_write(sc, DM9000_NCR, 0x0); 864 865 if( !sc->sc_phy_initialized) { 866 /* PHY Initialization */ 867 dme_phy_init(sc); 868 869 /* PHY Enable */ 870 var = dme_read(sc, DM9000_GPR); 871 dme_write(sc, DM9000_GPR, var & ~DM9000_GPR_PHY_PWROFF); 872 var = dme_read(sc, DM9000_GPCR); 873 dme_write(sc, DM9000_GPCR, var | DM9000_GPCR_GPIO0_OUT); 874 875 dme_write(sc, DM9000_NCR, 876 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 877 delay(20); 878 dme_write(sc, DM9000_NCR, 0x0); 879 } 880 881 /* Select internal PHY, no wakeup event, no collosion mode, 882 * normal loopback mode. 883 */ 884 dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL ); 885 886 /* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/ 887 dme_read(sc, DM9000_NSR); 888 889 /* Enable wraparound of read/write pointer, packet received latch, 890 * and packet transmitted latch. 891 */ 892 dme_write(sc, DM9000_IMR, 893 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 894 895 /* Setup multicast address filter, and enable RX. */ 896 dme_set_addr_filter(sc); 897 898 /* Obtain media information from PHY */ 899 dme_phy_update_media(sc); 900 901 sc->txbusy = 0; 902 sc->txready = 0; 903 sc->sc_phy_initialized = 1; 904 } 905 906 void 907 dme_set_addr_filter(struct dme_softc *sc) 908 { 909 struct ether_multi *enm; 910 struct ether_multistep step; 911 struct ethercom *ec; 912 struct ifnet *ifp; 913 uint16_t af[4]; 914 int i; 915 916 ec = &sc->sc_ethercom; 917 ifp = &ec->ec_if; 918 919 if (ifp->if_flags & IFF_PROMISC) { 920 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | 921 DM9000_RCR_WTDIS | 922 DM9000_RCR_PRMSC); 923 ifp->if_flags |= IFF_ALLMULTI; 924 return; 925 } 926 927 af[0] = af[1] = af[2] = af[3] = 0x0000; 928 ifp->if_flags &= ~IFF_ALLMULTI; 929 930 ETHER_FIRST_MULTI(step, ec, enm); 931 while (enm != NULL) { 932 uint16_t hash; 933 if (memcpy(enm->enm_addrlo, enm->enm_addrhi, 934 sizeof(enm->enm_addrlo))) { 935 /* 936 * We must listen to a range of multicast addresses. 937 * For now, just accept all multicasts, rather than 938 * trying to set only those filter bits needed to match 939 * the range. (At this time, the only use of address 940 * ranges is for IP multicast routing, for which the 941 * range is big enough to require all bits set.) 942 */ 943 ifp->if_flags |= IFF_ALLMULTI; 944 af[0] = af[1] = af[2] = af[3] = 0xffff; 945 break; 946 } else { 947 hash = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3F; 948 af[(uint16_t)(hash>>4)] |= (uint16_t)(1 << (hash % 16)); 949 ETHER_NEXT_MULTI(step, enm); 950 } 951 } 952 953 /* Write the multicast address filter */ 954 for(i=0; i<4; i++) { 955 dme_write(sc, DM9000_MAB0+i*2, af[i] & 0xFF); 956 dme_write(sc, DM9000_MAB0+i*2+1, (af[i] >> 8) & 0xFF); 957 } 958 959 /* Setup RX controls */ 960 dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | DM9000_RCR_WTDIS); 961 } 962 963 int 964 dme_pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain) 965 { 966 int left_over_count = 0; /* Number of bytes from previous mbuf, which 967 need to be written with the next.*/ 968 uint16_t left_over_buf = 0; 969 int length = 0; 970 struct mbuf *buf; 971 uint8_t *write_ptr; 972 973 /* We expect that the DM9000 has been setup to accept writes before 974 this function is called. */ 975 976 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 977 int to_write = buf->m_len; 978 979 length += to_write; 980 981 write_ptr = buf->m_data; 982 while (to_write > 0 || 983 (buf->m_next == NULL && left_over_count > 0) 984 ) { 985 if (left_over_count > 0) { 986 uint8_t b = 0; 987 DPRINTF(("dme_pkt_write_16: " 988 "Writing left over byte\n")); 989 990 if (to_write > 0) { 991 b = *write_ptr; 992 to_write--; 993 write_ptr++; 994 995 DPRINTF(("Took single byte\n")); 996 } else { 997 DPRINTF(("Leftover in last run\n")); 998 length++; 999 } 1000 1001 /* Does shift direction depend on endianess? */ 1002 left_over_buf = left_over_buf | (b << 8); 1003 1004 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 1005 sc->dme_data, left_over_buf); 1006 TX_DATA_DPRINTF(("%02X ", left_over_buf)); 1007 left_over_count = 0; 1008 } else if ((long)write_ptr % 2 != 0) { 1009 /* Misaligned data */ 1010 DPRINTF(("dme_pkt_write_16: " 1011 "Detected misaligned data\n")); 1012 left_over_buf = *write_ptr; 1013 left_over_count = 1; 1014 write_ptr++; 1015 to_write--; 1016 } else { 1017 int i; 1018 uint16_t *dptr = (uint16_t *)write_ptr; 1019 1020 /* A block of aligned data. */ 1021 for(i = 0; i < to_write / 2; i++) { 1022 /* buf will be half-word aligned 1023 * all the time 1024 */ 1025 bus_space_write_2(sc->sc_iot, 1026 sc->sc_ioh, sc->dme_data, *dptr); 1027 TX_DATA_DPRINTF(("%02X %02X ", 1028 *dptr & 0xFF, (*dptr >> 8) & 0xFF)); 1029 dptr++; 1030 } 1031 1032 write_ptr += i * 2; 1033 if (to_write % 2 != 0) { 1034 DPRINTF(("dme_pkt_write_16: " 1035 "to_write %% 2: %d\n", 1036 to_write % 2)); 1037 left_over_count = 1; 1038 /* XXX: Does this depend on 1039 * the endianess? 1040 */ 1041 left_over_buf = *write_ptr; 1042 1043 write_ptr++; 1044 to_write--; 1045 DPRINTF(("dme_pkt_write_16: " 1046 "to_write (after): %d\n", 1047 to_write)); 1048 DPRINTF(("dme_pkt_write_16: i * 2: %d\n", 1049 i*2)); 1050 } 1051 to_write -= i * 2; 1052 } 1053 } /* while(...) */ 1054 } /* for(...) */ 1055 1056 return length; 1057 } 1058 1059 int 1060 dme_pkt_read_2(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf) 1061 { 1062 uint8_t rx_status; 1063 struct mbuf *m; 1064 uint16_t data; 1065 uint16_t frame_length; 1066 uint16_t i; 1067 uint16_t *buf; 1068 1069 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1070 1071 rx_status = data & 0xFF; 1072 frame_length = bus_space_read_2(sc->sc_iot, 1073 sc->sc_ioh, sc->dme_data); 1074 if (frame_length > ETHER_MAX_LEN) { 1075 printf("Got frame of length: %d\n", frame_length); 1076 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1077 panic("Something is rotten"); 1078 } 1079 RX_DPRINTF(("dme_receive: " 1080 "rx_statux: 0x%x, frame_length: %d\n", 1081 rx_status, frame_length)); 1082 1083 1084 m = dme_alloc_receive_buffer(ifp, frame_length); 1085 1086 buf = mtod(m, uint16_t*); 1087 1088 RX_DPRINTF(("dme_receive: ")); 1089 1090 for (i = 0; i < frame_length; i += 2 ) { 1091 data = bus_space_read_2(sc->sc_iot, 1092 sc->sc_ioh, sc->dme_data); 1093 if ( (frame_length % 2 != 0) && 1094 (i == frame_length - 1) ) { 1095 data = data & 0xff; 1096 RX_DPRINTF((" L ")); 1097 } 1098 *buf = data; 1099 buf++; 1100 RX_DATA_DPRINTF(("%02X %02X ", data & 0xff, 1101 (data >> 8) & 0xff)); 1102 } 1103 1104 RX_DATA_DPRINTF(("\n")); 1105 RX_DPRINTF(("Read %d bytes\n", i)); 1106 1107 *outBuf = m; 1108 return rx_status; 1109 } 1110 1111 int 1112 dme_pkt_write_1(struct dme_softc *sc, struct mbuf *bufChain) 1113 { 1114 int length = 0, i; 1115 struct mbuf *buf; 1116 uint8_t *write_ptr; 1117 1118 /* We expect that the DM9000 has been setup to accept writes before 1119 this function is called. */ 1120 1121 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 1122 int to_write = buf->m_len; 1123 1124 length += to_write; 1125 1126 write_ptr = buf->m_data; 1127 for (i = 0; i < to_write; i++) { 1128 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1129 sc->dme_data, *write_ptr); 1130 write_ptr++; 1131 } 1132 } /* for(...) */ 1133 1134 return length; 1135 } 1136 1137 int 1138 dme_pkt_read_1(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf) 1139 { 1140 uint8_t rx_status; 1141 struct mbuf *m; 1142 uint8_t *buf; 1143 uint16_t frame_length; 1144 uint16_t i, reg; 1145 uint8_t data; 1146 1147 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1148 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1149 rx_status = reg & 0xFF; 1150 1151 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1152 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1153 frame_length = reg; 1154 1155 if (frame_length > ETHER_MAX_LEN) { 1156 printf("Got frame of length: %d\n", frame_length); 1157 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1158 panic("Something is rotten"); 1159 } 1160 RX_DPRINTF(("dme_receive: " 1161 "rx_statux: 0x%x, frame_length: %d\n", 1162 rx_status, frame_length)); 1163 1164 1165 m = dme_alloc_receive_buffer(ifp, frame_length); 1166 1167 buf = mtod(m, uint8_t *); 1168 1169 RX_DPRINTF(("dme_receive: ")); 1170 1171 for (i = 0; i< frame_length; i += 1 ) { 1172 data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1173 *buf = data; 1174 buf++; 1175 RX_DATA_DPRINTF(("%02X ", data)); 1176 } 1177 1178 RX_DATA_DPRINTF(("\n")); 1179 RX_DPRINTF(("Read %d bytes\n", i)); 1180 1181 *outBuf = m; 1182 return rx_status; 1183 } 1184 1185 struct mbuf* 1186 dme_alloc_receive_buffer(struct ifnet *ifp, unsigned int frame_length) 1187 { 1188 struct dme_softc *sc = ifp->if_softc; 1189 struct mbuf *m; 1190 int pad; 1191 1192 MGETHDR(m, M_DONTWAIT, MT_DATA); 1193 m->m_pkthdr.rcvif = ifp; 1194 /* Ensure that we always allocate an even number of 1195 * bytes in order to avoid writing beyond the buffer 1196 */ 1197 m->m_pkthdr.len = frame_length + (frame_length % sc->sc_data_width); 1198 pad = ALIGN(sizeof(struct ether_header)) - 1199 sizeof(struct ether_header); 1200 /* All our frames have the CRC attached */ 1201 m->m_flags |= M_HASFCS; 1202 if (m->m_pkthdr.len + pad > MHLEN ) 1203 MCLGET(m, M_DONTWAIT); 1204 1205 m->m_data += pad; 1206 m->m_len = frame_length + (frame_length % sc->sc_data_width); 1207 1208 return m; 1209 } 1210
Indexes created Fri Sep 26 20:09:58 GMT 2025