dp8390reg.h revision 1.3
1 /* $NetBSD: dp8390reg.h,v 1.3 1997/04/29 04:32:08 scottr Exp $ */ 2 3 /* 4 * National Semiconductor DS8390 NIC register definitions. 5 * 6 * Copyright (C) 1993, David Greenman. This software may be used, modified, 7 * copied, distributed, and sold, in both source and binary form provided that 8 * the above copyright and these terms are retained. Under no circumstances is 9 * the author responsible for the proper functioning of this software, nor does 10 * the author assume any responsibility for damages incurred with its use. 11 */ 12 13 /* 14 * Page 0 register offsets 15 */ 16 #define ED_P0_CR 0x00 /* Command Register */ 17 18 #define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 19 #define ED_P0_PSTART 0x01 /* Page Start register (write) */ 20 21 #define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 22 #define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 23 24 #define ED_P0_BNRY 0x03 /* Boundary Pointer */ 25 26 #define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 27 #define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 28 29 #define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 30 #define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 31 32 #define ED_P0_FIFO 0x06 /* FIFO register (read) */ 33 #define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 34 35 #define ED_P0_ISR 0x07 /* Interrupt Status Register */ 36 37 #define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 38 #define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 39 40 #define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 41 #define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 42 43 #define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 44 45 #define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 46 47 #define ED_P0_RSR 0x0c /* Receive Status (read) */ 48 #define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 49 50 #define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 51 #define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 52 53 #define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 54 #define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 55 56 #define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 57 #define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 58 59 /* 60 * Page 1 register offsets 61 */ 62 #define ED_P1_CR 0x00 /* Command Register */ 63 #define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 64 #define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 65 #define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 66 #define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 67 #define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 68 #define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 69 #define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 70 #define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 71 #define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 72 #define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 73 #define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 74 #define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 75 #define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 76 #define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 77 #define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 78 79 /* 80 * Page 2 register offsets 81 */ 82 #define ED_P2_CR 0x00 /* Command Register */ 83 #define ED_P2_PSTART 0x01 /* Page Start (read) */ 84 #define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 85 #define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 86 #define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 87 #define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 88 #define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 89 #define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 90 #define ED_P2_ACU 0x06 /* Address Counter Upper */ 91 #define ED_P2_ACL 0x07 /* Address Counter Lower */ 92 #define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 93 #define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 94 #define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 95 #define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 96 97 /* 98 * Command Register (CR) definitions 99 */ 100 101 /* 102 * STP: SToP. Software reset command. Takes the controller offline. No 103 * packets will be received or transmitted. Any reception or transmission in 104 * progress will continue to completion before entering reset state. To exit 105 * this state, the STP bit must reset and the STA bit must be set. The 106 * software reset has executed only when indicated by the RST bit in the ISR 107 * being set. 108 */ 109 #define ED_CR_STP 0x01 110 111 /* 112 * STA: STArt. This bit is used to activate the NIC after either power-up, or 113 * when the NIC has been put in reset mode by software command or error. 114 */ 115 #define ED_CR_STA 0x02 116 117 /* 118 * TXP: Transmit Packet. This bit must be set to indicate transmission of a 119 * packet. TXP is internally reset either after the transmission is completed 120 * or aborted. This bit should be set only after the Transmit Byte Count and 121 * Transmit Page Start register have been programmed. 122 */ 123 #define ED_CR_TXP 0x04 124 125 /* 126 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 127 * of the remote DMA channel. RD2 can be set to abort any remote DMA command 128 * in progress. The Remote Byte Count registers should be cleared when a 129 * remote DMA has been aborted. The Remote Start Addresses are not restored 130 * to the starting address if the remote DMA is aborted. 131 * 132 * RD2 RD1 RD0 function 133 * 0 0 0 not allowed 134 * 0 0 1 remote read 135 * 0 1 0 remote write 136 * 0 1 1 send packet 137 * 1 X X abort 138 */ 139 #define ED_CR_RD0 0x08 140 #define ED_CR_RD1 0x10 141 #define ED_CR_RD2 0x20 142 143 /* 144 * PS0, PS1: Page Select. The two bits select which register set or 'page' to 145 * access. 146 * 147 * PS1 PS0 page 148 * 0 0 0 149 * 0 1 1 150 * 1 0 2 151 * 1 1 reserved 152 */ 153 #define ED_CR_PS0 0x40 154 #define ED_CR_PS1 0x80 155 /* bit encoded aliases */ 156 #define ED_CR_PAGE_0 0x00 /* (for consistency) */ 157 #define ED_CR_PAGE_1 0x40 158 #define ED_CR_PAGE_2 0x80 159 160 /* 161 * Interrupt Status Register (ISR) definitions 162 */ 163 164 /* 165 * PRX: Packet Received. Indicates packet received with no errors. 166 */ 167 #define ED_ISR_PRX 0x01 168 169 /* 170 * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 171 */ 172 #define ED_ISR_PTX 0x02 173 174 /* 175 * RXE: Receive Error. Indicates that a packet was received with one or more 176 * the following errors: CRC error, frame alignment error, FIFO overrun, 177 * missed packet. 178 */ 179 #define ED_ISR_RXE 0x04 180 181 /* 182 * TXE: Transmission Error. Indicates that an attempt to transmit a packet 183 * resulted in one or more of the following errors: excessive collisions, FIFO 184 * underrun. 185 */ 186 #define ED_ISR_TXE 0x08 187 188 /* 189 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 190 * would exceed (has exceeded?) the boundary pointer, resulting in data that 191 * was previously received and not yet read from the buffer to be overwritten. 192 */ 193 #define ED_ISR_OVW 0x10 194 195 /* 196 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Tally 197 * Counters has been set. 198 */ 199 #define ED_ISR_CNT 0x20 200 201 /* 202 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has 203 * completed. 204 */ 205 #define ED_ISR_RDC 0x40 206 207 /* 208 * RST: Reset status. Set when the NIC enters the reset state and cleared when 209 * a Start Command is issued to the CR. This bit is also set when a receive 210 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 211 * packets have been removed from the ring. This is a read-only bit. 212 */ 213 #define ED_ISR_RST 0x80 214 215 /* 216 * Interrupt Mask Register (IMR) definitions 217 */ 218 219 /* 220 * PRXE: Packet Received interrupt Enable. If set, a received packet will 221 * cause an interrupt. 222 */ 223 #define ED_IMR_PRXE 0x01 224 225 /* 226 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated 227 * when a packet transmission completes. 228 */ 229 #define ED_IMR_PTXE 0x02 230 231 /* 232 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur 233 * whenever a packet is received with an error. 234 */ 235 #define ED_IMR_RXEE 0x04 236 237 /* 238 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur 239 * whenever a transmission results in an error. 240 */ 241 #define ED_IMR_TXEE 0x08 242 243 /* 244 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated 245 * whenever the receive ring-buffer is overrun. i.e. when the boundary pointer 246 * is exceeded. 247 */ 248 #define ED_IMR_OVWE 0x10 249 250 /* 251 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated 252 * whenever the MSB of one or more of the Network Statistics counters has been 253 * set. 254 */ 255 #define ED_IMR_CNTE 0x20 256 257 /* 258 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is 259 * generated when a remote DMA transfer has completed. 260 */ 261 #define ED_IMR_RDCE 0x40 262 263 /* 264 * Bit 7 is unused/reserved. 265 */ 266 267 /* 268 * Data Configuration Register (DCR) definitions 269 */ 270 271 /* 272 * WTS: Word Transfer Select. WTS establishes byte or word transfers for both 273 * remote and local DMA transfers 274 */ 275 #define ED_DCR_WTS 0x01 276 277 /* 278 * BOS: Byte Order Select. BOS sets the byte order for the host. Should be 0 279 * for 80x86, and 1 for 68000 series processors 280 */ 281 #define ED_DCR_BOS 0x02 282 283 /* 284 * LAS: Long Address Select. When LAS is 1, the contents of the remote DMA 285 * registers RSAR0 and RSAR1 are used to provide A16-A31. 286 */ 287 #define ED_DCR_LAS 0x04 288 289 /* 290 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 of 291 * the TCR must also be programmed for loopback operation. When 1, normal 292 * operation is selected. 293 */ 294 #define ED_DCR_LS 0x08 295 296 /* 297 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 298 * under program control. When 1, remote DMA is automatically initiated and 299 * the boundary pointer is automatically updated. 300 */ 301 #define ED_DCR_AR 0x10 302 303 /* 304 * FT0, FT1: Fifo Threshold select. 305 * 306 * FT1 FT0 Word-width Byte-width 307 * 0 0 1 word 2 bytes 308 * 0 1 2 words 4 bytes 309 * 1 0 4 words 8 bytes 310 * 1 1 8 words 12 bytes 311 * 312 * During transmission, the FIFO threshold indicates the number of bytes or 313 * words that the FIFO has filled from the local DMA before BREQ is asserted. 314 * The transmission threshold is 16 bytes minus the receiver threshold. 315 */ 316 #define ED_DCR_FT0 0x20 317 #define ED_DCR_FT1 0x40 318 319 /* 320 * bit 7 (0x80) is unused/reserved 321 */ 322 323 /* 324 * Transmit Configuration Register (TCR) definitions 325 */ 326 327 /* 328 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 329 * is not appended by the transmitter. 330 */ 331 #define ED_TCR_CRC 0x01 332 333 /* 334 * LB0, LB1: Loopback control. These two bits set the type of loopback that is 335 * to be performed. 336 * 337 * LB1 LB0 mode 338 * 0 0 0 - normal operation (DCR_LS = 0) 339 * 0 1 1 - internal loopback (DCR_LS = 0) 340 * 1 0 2 - external loopback (DCR_LS = 1) 341 * 1 1 3 - external loopback (DCR_LS = 0) 342 */ 343 #define ED_TCR_LB0 0x02 344 #define ED_TCR_LB1 0x04 345 346 /* 347 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 348 * another station to disable the NIC's transmitter by transmitting to a 349 * multicast address hashing to bit 62. Reception of a multicast address 350 * hashing to bit 63 enables the transmitter. 351 */ 352 #define ED_TCR_ATD 0x08 353 354 /* 355 * OFST: Collision Offset enable. This bit when set modifies the backoff 356 * algorithm to allow prioritization of nodes. 357 */ 358 #define ED_TCR_OFST 0x10 359 360 /* 361 * bits 5, 6, and 7 are unused/reserved 362 */ 363 364 /* 365 * Transmit Status Register (TSR) definitions 366 */ 367 368 /* 369 * PTX: Packet Transmitted. Indicates successful transmission of packet. 370 */ 371 #define ED_TSR_PTX 0x01 372 373 /* 374 * bit 1 (0x02) is unused/reserved 375 */ 376 377 /* 378 * COL: Transmit Collided. Indicates that the transmission collided at least 379 * once with another station on the network. 380 */ 381 #define ED_TSR_COL 0x04 382 383 /* 384 * ABT: Transmit aborted. Indicates that the transmission was aborted due to 385 * excessive collisions. 386 */ 387 #define ED_TSR_ABT 0x08 388 389 /* 390 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 391 * transmission of the packet. (Transmission is not aborted because of a loss 392 * of carrier). 393 */ 394 #define ED_TSR_CRS 0x10 395 396 /* 397 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 398 * transmission memory before the FIFO emptied. Transmission of the packet was 399 * aborted. 400 */ 401 #define ED_TSR_FU 0x20 402 403 /* 404 * CDH: CD Heartbeat. Indicates that the collision detection circuitry isn't 405 * working correctly during a collision heartbeat test. 406 */ 407 #define ED_TSR_CDH 0x40 408 409 /* 410 * OWC: Out of Window Collision: Indicates that a collision occurred after a 411 * slot time (51.2us). The transmission is rescheduled just as in normal 412 * collisions. 413 */ 414 #define ED_TSR_OWC 0x80 415 416 /* 417 * Receiver Configuration Register (RCR) definitions 418 */ 419 420 /* 421 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 422 * packets with CRC and frame errors are not discarded. 423 */ 424 #define ED_RCR_SEP 0x01 425 426 /* 427 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 428 * If set to 1, packets with less than 64 byte are not discarded. 429 */ 430 #define ED_RCR_AR 0x02 431 432 /* 433 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 434 * accepted. 435 */ 436 #define ED_RCR_AB 0x04 437 438 /* 439 * AM: Accept Multicast. If set, packets sent to a multicast address are 440 * checked for a match in the hashing array. If clear, multicast packets are 441 * ignored. 442 */ 443 #define ED_RCR_AM 0x08 444 445 /* 446 * PRO: Promiscuous Physical. If set, all packets with a physical addresses 447 * are accepted. If clear, a physical destination address must match this 448 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM must 449 * also be set. In addition, the multicast hashing array must be set to all 450 * 1's so that all multicast addresses are accepted. 451 */ 452 #define ED_RCR_PRO 0x10 453 454 /* 455 * MON: Monitor Mode. If set, packets will be checked for good CRC and 456 * framing, but are not stored in the ring-buffer. If clear, packets are 457 * stored (normal operation). 458 */ 459 #define ED_RCR_MON 0x20 460 461 /* 462 * Bits 6 and 7 are unused/reserved. 463 */ 464 465 /* 466 * Receiver Status Register (RSR) definitions 467 */ 468 469 /* 470 * PRX: Packet Received without error. 471 */ 472 #define ED_RSR_PRX 0x01 473 474 /* 475 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for 476 * frame alignment errors. 477 */ 478 #define ED_RSR_CRC 0x02 479 480 /* 481 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end 482 * on a byte boundary and the CRC did not match at the last byte boundary. 483 */ 484 #define ED_RSR_FAE 0x04 485 486 /* 487 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local 488 * DMA) causing it to overrun. Reception of the packet is aborted. 489 */ 490 #define ED_RSR_FO 0x08 491 492 /* 493 * MPA: Missed Packet. Indicates that the received packet couldn't be stored 494 * in the ring-buffer because of insufficient buffer space (exceeding the 495 * boundary pointer), or because the transfer to the ring-buffer was inhibited 496 * by RCR_MON - monitor mode. 497 */ 498 #define ED_RSR_MPA 0x10 499 500 /* 501 * PHY: Physical address. If 0, the packet received was sent to a physical 502 * address. If 1, the packet was accepted because of a multicast/broadcast 503 * address match. 504 */ 505 #define ED_RSR_PHY 0x20 506 507 /* 508 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered 509 * monitor mode. Cleared when the receiver exits monitor mode. 510 */ 511 #define ED_RSR_DIS 0x40 512 513 /* 514 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL 515 * inputs are active, and the transceiver has set the CD line as a result of 516 * the jabber. 517 */ 518 #define ED_RSR_DFR 0x80 519 520 /* 521 * receive ring descriptor 522 * 523 * The National Semiconductor DS8390 Network interface controller uses the 524 * following receive ring headers. The way this works is that the memory on 525 * the interface card is chopped up into 256 bytes blocks. A contiguous 526 * portion of those blocks are marked for receive packets by setting start and 527 * end block #'s in the NIC. For each packet that is put into the receive 528 * ring, one of these headers (4 bytes each) is tacked onto the front. The 529 * first byte is a copy of the receiver status register at the time the packet 530 * was received. 531 */ 532 struct dp8390_ring { 533 u_int8_t rsr; /* receiver status */ 534 u_int8_t next_packet; /* pointer to next packet */ 535 u_int16_t count; /* bytes in packet (length + 4) */ 536 }; 537 538 /* 539 * XXX For compatibility only! This needs to die when all drivers have 540 * been converted to be front ends to the MI driver. 541 */ 542 struct ed_ring { 543 #if BYTE_ORDER == BIG_ENDIAN 544 u_char next_packet; /* pointer to next packet */ 545 u_char rsr; /* receiver status */ 546 #else 547 u_char rsr; /* receiver status */ 548 u_char next_packet; /* pointer to next packet */ 549 #endif 550 u_short count; /* bytes in packet (length + 4) */ 551 }; 552 553 /* 554 * Common constants 555 */ 556 #define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 557 #define ED_PAGE_MASK 255 558 #define ED_PAGE_SHIFT 8 559 560 #define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 561
Indexes created Mon Sep 29 21:09:56 GMT 2025