dp83932.c revision 1.21
1 /* $NetBSD: dp83932.c,v 1.21 2008/03/12 18:13:15 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the National Semiconductor DP83932 41 * Systems-Oriented Network Interface Controller (SONIC). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dp83932.c,v 1.21 2008/03/12 18:13:15 dyoung Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <sys/bus.h> 70 #include <sys/intr.h> 71 72 #include <dev/ic/dp83932reg.h> 73 #include <dev/ic/dp83932var.h> 74 75 void sonic_start(struct ifnet *); 76 void sonic_watchdog(struct ifnet *); 77 int sonic_ioctl(struct ifnet *, u_long, void *); 78 int sonic_init(struct ifnet *); 79 void sonic_stop(struct ifnet *, int); 80 81 void sonic_shutdown(void *); 82 83 void sonic_reset(struct sonic_softc *); 84 void sonic_rxdrain(struct sonic_softc *); 85 int sonic_add_rxbuf(struct sonic_softc *, int); 86 void sonic_set_filter(struct sonic_softc *); 87 88 uint16_t sonic_txintr(struct sonic_softc *); 89 void sonic_rxintr(struct sonic_softc *); 90 91 int sonic_copy_small = 0; 92 93 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 94 95 /* 96 * sonic_attach: 97 * 98 * Attach a SONIC interface to the system. 99 */ 100 void 101 sonic_attach(struct sonic_softc *sc, const uint8_t *enaddr) 102 { 103 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 104 int i, rseg, error; 105 bus_dma_segment_t seg; 106 size_t cdatasize; 107 char *nullbuf; 108 109 /* 110 * Allocate the control data structures, and create and load the 111 * DMA map for it. 112 */ 113 if (sc->sc_32bit) 114 cdatasize = sizeof(struct sonic_control_data32); 115 else 116 cdatasize = sizeof(struct sonic_control_data16); 117 118 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdatasize + ETHER_PAD_LEN, 119 PAGE_SIZE, (64 * 1024), &seg, 1, &rseg, 120 BUS_DMA_NOWAIT)) != 0) { 121 printf("%s: unable to allocate control data, error = %d\n", 122 sc->sc_dev.dv_xname, error); 123 goto fail_0; 124 } 125 126 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 127 cdatasize + ETHER_PAD_LEN, (void **) &sc->sc_cdata16, 128 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 129 printf("%s: unable to map control data, error = %d\n", 130 sc->sc_dev.dv_xname, error); 131 goto fail_1; 132 } 133 nullbuf = (char *)sc->sc_cdata16 + cdatasize; 134 memset(nullbuf, 0, ETHER_PAD_LEN); 135 136 if ((error = bus_dmamap_create(sc->sc_dmat, 137 cdatasize, 1, cdatasize, 0, BUS_DMA_NOWAIT, 138 &sc->sc_cddmamap)) != 0) { 139 printf("%s: unable to create control data DMA map, " 140 "error = %d\n", sc->sc_dev.dv_xname, error); 141 goto fail_2; 142 } 143 144 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 145 sc->sc_cdata16, cdatasize, NULL, BUS_DMA_NOWAIT)) != 0) { 146 printf("%s: unable to load control data DMA map, error = %d\n", 147 sc->sc_dev.dv_xname, error); 148 goto fail_3; 149 } 150 151 /* 152 * Create the transmit buffer DMA maps. 153 */ 154 for (i = 0; i < SONIC_NTXDESC; i++) { 155 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 156 SONIC_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 157 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 158 printf("%s: unable to create tx DMA map %d, " 159 "error = %d\n", sc->sc_dev.dv_xname, i, error); 160 goto fail_4; 161 } 162 } 163 164 /* 165 * Create the receive buffer DMA maps. 166 */ 167 for (i = 0; i < SONIC_NRXDESC; i++) { 168 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 169 MCLBYTES, 0, BUS_DMA_NOWAIT, 170 &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 171 printf("%s: unable to create rx DMA map %d, " 172 "error = %d\n", sc->sc_dev.dv_xname, i, error); 173 goto fail_5; 174 } 175 sc->sc_rxsoft[i].ds_mbuf = NULL; 176 } 177 178 /* 179 * create and map the pad buffer 180 */ 181 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 182 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT, &sc->sc_nulldmamap)) != 0) { 183 printf("%s: unable to create pad buffer DMA map, " 184 "error = %d\n", sc->sc_dev.dv_xname, error); 185 goto fail_5; 186 } 187 188 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 189 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 190 printf("%s: unable to load pad buffer DMA map, " 191 "error = %d\n", sc->sc_dev.dv_xname, error); 192 goto fail_6; 193 } 194 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 195 BUS_DMASYNC_PREWRITE); 196 197 /* 198 * Reset the chip to a known state. 199 */ 200 sonic_reset(sc); 201 202 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 203 ether_sprintf(enaddr)); 204 205 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 206 ifp->if_softc = sc; 207 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 208 ifp->if_ioctl = sonic_ioctl; 209 ifp->if_start = sonic_start; 210 ifp->if_watchdog = sonic_watchdog; 211 ifp->if_init = sonic_init; 212 ifp->if_stop = sonic_stop; 213 IFQ_SET_READY(&ifp->if_snd); 214 215 /* 216 * Attach the interface. 217 */ 218 if_attach(ifp); 219 ether_ifattach(ifp, enaddr); 220 221 /* 222 * Make sure the interface is shutdown during reboot. 223 */ 224 sc->sc_sdhook = shutdownhook_establish(sonic_shutdown, sc); 225 if (sc->sc_sdhook == NULL) 226 printf("%s: WARNING: unable to establish shutdown hook\n", 227 sc->sc_dev.dv_xname); 228 return; 229 230 /* 231 * Free any resources we've allocated during the failed attach 232 * attempt. Do this in reverse order and fall through. 233 */ 234 fail_6: 235 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 236 fail_5: 237 for (i = 0; i < SONIC_NRXDESC; i++) { 238 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 239 bus_dmamap_destroy(sc->sc_dmat, 240 sc->sc_rxsoft[i].ds_dmamap); 241 } 242 fail_4: 243 for (i = 0; i < SONIC_NTXDESC; i++) { 244 if (sc->sc_txsoft[i].ds_dmamap != NULL) 245 bus_dmamap_destroy(sc->sc_dmat, 246 sc->sc_txsoft[i].ds_dmamap); 247 } 248 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 249 fail_3: 250 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 251 fail_2: 252 bus_dmamem_unmap(sc->sc_dmat, (void *) sc->sc_cdata16, cdatasize); 253 fail_1: 254 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 255 fail_0: 256 return; 257 } 258 259 /* 260 * sonic_shutdown: 261 * 262 * Make sure the interface is stopped at reboot. 263 */ 264 void 265 sonic_shutdown(void *arg) 266 { 267 struct sonic_softc *sc = arg; 268 269 sonic_stop(&sc->sc_ethercom.ec_if, 1); 270 } 271 272 /* 273 * sonic_start: [ifnet interface function] 274 * 275 * Start packet transmission on the interface. 276 */ 277 void 278 sonic_start(struct ifnet *ifp) 279 { 280 struct sonic_softc *sc = ifp->if_softc; 281 struct mbuf *m0, *m; 282 struct sonic_tda16 *tda16; 283 struct sonic_tda32 *tda32; 284 struct sonic_descsoft *ds; 285 bus_dmamap_t dmamap; 286 int error, olasttx, nexttx, opending, totlen, olseg; 287 int seg = 0; /* XXX: gcc */ 288 289 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 290 return; 291 292 /* 293 * Remember the previous txpending and the current "last txdesc 294 * used" index. 295 */ 296 opending = sc->sc_txpending; 297 olasttx = sc->sc_txlast; 298 299 /* 300 * Loop through the send queue, setting up transmit descriptors 301 * until we drain the queue, or use up all available transmit 302 * descriptors. Leave one at the end for sanity's sake. 303 */ 304 while (sc->sc_txpending < (SONIC_NTXDESC - 1)) { 305 /* 306 * Grab a packet off the queue. 307 */ 308 IFQ_POLL(&ifp->if_snd, m0); 309 if (m0 == NULL) 310 break; 311 m = NULL; 312 313 /* 314 * Get the next available transmit descriptor. 315 */ 316 nexttx = SONIC_NEXTTX(sc->sc_txlast); 317 ds = &sc->sc_txsoft[nexttx]; 318 dmamap = ds->ds_dmamap; 319 320 /* 321 * Load the DMA map. If this fails, the packet either 322 * didn't fit in the allotted number of frags, or we were 323 * short on resources. In this case, we'll copy and try 324 * again. 325 */ 326 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 327 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 328 (m0->m_pkthdr.len < ETHER_PAD_LEN && 329 dmamap->dm_nsegs == SONIC_NTXFRAGS)) { 330 if (error == 0) 331 bus_dmamap_unload(sc->sc_dmat, dmamap); 332 MGETHDR(m, M_DONTWAIT, MT_DATA); 333 if (m == NULL) { 334 printf("%s: unable to allocate Tx mbuf\n", 335 sc->sc_dev.dv_xname); 336 break; 337 } 338 if (m0->m_pkthdr.len > MHLEN) { 339 MCLGET(m, M_DONTWAIT); 340 if ((m->m_flags & M_EXT) == 0) { 341 printf("%s: unable to allocate Tx " 342 "cluster\n", sc->sc_dev.dv_xname); 343 m_freem(m); 344 break; 345 } 346 } 347 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 348 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 349 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 350 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 351 if (error) { 352 printf("%s: unable to load Tx buffer, " 353 "error = %d\n", sc->sc_dev.dv_xname, error); 354 m_freem(m); 355 break; 356 } 357 } 358 IFQ_DEQUEUE(&ifp->if_snd, m0); 359 if (m != NULL) { 360 m_freem(m0); 361 m0 = m; 362 } 363 364 /* 365 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 366 */ 367 368 /* Sync the DMA map. */ 369 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 370 BUS_DMASYNC_PREWRITE); 371 372 /* 373 * Store a pointer to the packet so we can free it later. 374 */ 375 ds->ds_mbuf = m0; 376 377 /* 378 * Initialize the transmit descriptor. 379 */ 380 totlen = 0; 381 if (sc->sc_32bit) { 382 tda32 = &sc->sc_tda32[nexttx]; 383 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 384 tda32->tda_frags[seg].frag_ptr1 = 385 htosonic32(sc, 386 (dmamap->dm_segs[seg].ds_addr >> 16) & 387 0xffff); 388 tda32->tda_frags[seg].frag_ptr0 = 389 htosonic32(sc, 390 dmamap->dm_segs[seg].ds_addr & 0xffff); 391 tda32->tda_frags[seg].frag_size = 392 htosonic32(sc, dmamap->dm_segs[seg].ds_len); 393 totlen += dmamap->dm_segs[seg].ds_len; 394 } 395 if (totlen < ETHER_PAD_LEN) { 396 tda32->tda_frags[seg].frag_ptr1 = 397 htosonic32(sc, 398 (sc->sc_nulldma >> 16) & 0xffff); 399 tda32->tda_frags[seg].frag_ptr0 = 400 htosonic32(sc, sc->sc_nulldma & 0xffff); 401 tda32->tda_frags[seg].frag_size = 402 htosonic32(sc, ETHER_PAD_LEN - totlen); 403 totlen = ETHER_PAD_LEN; 404 seg++; 405 } 406 407 tda32->tda_status = 0; 408 tda32->tda_pktconfig = 0; 409 tda32->tda_pktsize = htosonic32(sc, totlen); 410 tda32->tda_fragcnt = htosonic32(sc, seg); 411 412 /* Link it up. */ 413 tda32->tda_frags[seg].frag_ptr0 = 414 htosonic32(sc, SONIC_CDTXADDR32(sc, 415 SONIC_NEXTTX(nexttx)) & 0xffff); 416 417 /* Sync the Tx descriptor. */ 418 SONIC_CDTXSYNC32(sc, nexttx, 419 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 420 } else { 421 tda16 = &sc->sc_tda16[nexttx]; 422 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 423 tda16->tda_frags[seg].frag_ptr1 = 424 htosonic16(sc, 425 (dmamap->dm_segs[seg].ds_addr >> 16) & 426 0xffff); 427 tda16->tda_frags[seg].frag_ptr0 = 428 htosonic16(sc, 429 dmamap->dm_segs[seg].ds_addr & 0xffff); 430 tda16->tda_frags[seg].frag_size = 431 htosonic16(sc, dmamap->dm_segs[seg].ds_len); 432 totlen += dmamap->dm_segs[seg].ds_len; 433 } 434 if (totlen < ETHER_PAD_LEN) { 435 tda16->tda_frags[seg].frag_ptr1 = 436 htosonic16(sc, 437 (sc->sc_nulldma >> 16) & 0xffff); 438 tda16->tda_frags[seg].frag_ptr0 = 439 htosonic16(sc, sc->sc_nulldma & 0xffff); 440 tda16->tda_frags[seg].frag_size = 441 htosonic16(sc, ETHER_PAD_LEN - totlen); 442 totlen = ETHER_PAD_LEN; 443 seg++; 444 } 445 446 tda16->tda_status = 0; 447 tda16->tda_pktconfig = 0; 448 tda16->tda_pktsize = htosonic16(sc, totlen); 449 tda16->tda_fragcnt = htosonic16(sc, seg); 450 451 /* Link it up. */ 452 tda16->tda_frags[seg].frag_ptr0 = 453 htosonic16(sc, SONIC_CDTXADDR16(sc, 454 SONIC_NEXTTX(nexttx)) & 0xffff); 455 456 /* Sync the Tx descriptor. */ 457 SONIC_CDTXSYNC16(sc, nexttx, 458 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 459 } 460 461 /* Advance the Tx pointer. */ 462 sc->sc_txpending++; 463 sc->sc_txlast = nexttx; 464 465 #if NBPFILTER > 0 466 /* 467 * Pass the packet to any BPF listeners. 468 */ 469 if (ifp->if_bpf) 470 bpf_mtap(ifp->if_bpf, m0); 471 #endif 472 } 473 474 if (sc->sc_txpending == (SONIC_NTXDESC - 1)) { 475 /* No more slots left; notify upper layer. */ 476 ifp->if_flags |= IFF_OACTIVE; 477 } 478 479 if (sc->sc_txpending != opending) { 480 /* 481 * We enqueued packets. If the transmitter was idle, 482 * reset the txdirty pointer. 483 */ 484 if (opending == 0) 485 sc->sc_txdirty = SONIC_NEXTTX(olasttx); 486 487 /* 488 * Stop the SONIC on the last packet we've set up, 489 * and clear end-of-list on the descriptor previous 490 * to our new chain. 491 * 492 * NOTE: our `seg' variable should still be valid! 493 */ 494 if (sc->sc_32bit) { 495 olseg = 496 sonic32toh(sc, sc->sc_tda32[olasttx].tda_fragcnt); 497 sc->sc_tda32[sc->sc_txlast].tda_frags[seg].frag_ptr0 |= 498 htosonic32(sc, TDA_LINK_EOL); 499 SONIC_CDTXSYNC32(sc, sc->sc_txlast, 500 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 501 sc->sc_tda32[olasttx].tda_frags[olseg].frag_ptr0 &= 502 htosonic32(sc, ~TDA_LINK_EOL); 503 SONIC_CDTXSYNC32(sc, olasttx, 504 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 505 } else { 506 olseg = 507 sonic16toh(sc, sc->sc_tda16[olasttx].tda_fragcnt); 508 sc->sc_tda16[sc->sc_txlast].tda_frags[seg].frag_ptr0 |= 509 htosonic16(sc, TDA_LINK_EOL); 510 SONIC_CDTXSYNC16(sc, sc->sc_txlast, 511 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 512 sc->sc_tda16[olasttx].tda_frags[olseg].frag_ptr0 &= 513 htosonic16(sc, ~TDA_LINK_EOL); 514 SONIC_CDTXSYNC16(sc, olasttx, 515 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 516 } 517 518 /* Start the transmitter. */ 519 CSR_WRITE(sc, SONIC_CR, CR_TXP); 520 521 /* Set a watchdog timer in case the chip flakes out. */ 522 ifp->if_timer = 5; 523 } 524 } 525 526 /* 527 * sonic_watchdog: [ifnet interface function] 528 * 529 * Watchdog timer handler. 530 */ 531 void 532 sonic_watchdog(struct ifnet *ifp) 533 { 534 struct sonic_softc *sc = ifp->if_softc; 535 536 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 537 ifp->if_oerrors++; 538 539 (void) sonic_init(ifp); 540 } 541 542 /* 543 * sonic_ioctl: [ifnet interface function] 544 * 545 * Handle control requests from the operator. 546 */ 547 int 548 sonic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 549 { 550 int s, error; 551 552 s = splnet(); 553 554 error = ether_ioctl(ifp, cmd, data); 555 if (error == ENETRESET) { 556 /* 557 * Multicast list has changed; set the hardware 558 * filter accordingly. 559 */ 560 if (ifp->if_flags & IFF_RUNNING) 561 (void) sonic_init(ifp); 562 error = 0; 563 } 564 565 splx(s); 566 return (error); 567 } 568 569 /* 570 * sonic_intr: 571 * 572 * Interrupt service routine. 573 */ 574 int 575 sonic_intr(void *arg) 576 { 577 struct sonic_softc *sc = arg; 578 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 579 uint16_t isr; 580 int handled = 0, wantinit; 581 582 for (wantinit = 0; wantinit == 0;) { 583 isr = CSR_READ(sc, SONIC_ISR) & sc->sc_imr; 584 if (isr == 0) 585 break; 586 CSR_WRITE(sc, SONIC_ISR, isr); /* ACK */ 587 588 handled = 1; 589 590 if (isr & IMR_PRX) 591 sonic_rxintr(sc); 592 593 if (isr & (IMR_PTX|IMR_TXER)) { 594 if (sonic_txintr(sc) & TCR_FU) { 595 printf("%s: transmit FIFO underrun\n", 596 sc->sc_dev.dv_xname); 597 wantinit = 1; 598 } 599 } 600 601 if (isr & (IMR_RFO|IMR_RBA|IMR_RBE|IMR_RDE)) { 602 #define PRINTERR(bit, str) \ 603 if (isr & (bit)) \ 604 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 605 PRINTERR(IMR_RFO, "receive FIFO overrun"); 606 PRINTERR(IMR_RBA, "receive buffer exceeded"); 607 PRINTERR(IMR_RBE, "receive buffers exhausted"); 608 PRINTERR(IMR_RDE, "receive descriptors exhausted"); 609 wantinit = 1; 610 } 611 } 612 613 if (handled) { 614 if (wantinit) 615 (void) sonic_init(ifp); 616 sonic_start(ifp); 617 } 618 619 return (handled); 620 } 621 622 /* 623 * sonic_txintr: 624 * 625 * Helper; handle transmit complete interrupts. 626 */ 627 uint16_t 628 sonic_txintr(struct sonic_softc *sc) 629 { 630 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 631 struct sonic_descsoft *ds; 632 struct sonic_tda32 *tda32; 633 struct sonic_tda16 *tda16; 634 uint16_t status, totstat = 0; 635 int i; 636 637 ifp->if_flags &= ~IFF_OACTIVE; 638 639 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 640 i = SONIC_NEXTTX(i), sc->sc_txpending--) { 641 ds = &sc->sc_txsoft[i]; 642 643 if (sc->sc_32bit) { 644 SONIC_CDTXSYNC32(sc, i, 645 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 646 tda32 = &sc->sc_tda32[i]; 647 status = sonic32toh(sc, tda32->tda_status); 648 SONIC_CDTXSYNC32(sc, i, BUS_DMASYNC_PREREAD); 649 } else { 650 SONIC_CDTXSYNC16(sc, i, 651 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 652 tda16 = &sc->sc_tda16[i]; 653 status = sonic16toh(sc, tda16->tda_status); 654 SONIC_CDTXSYNC16(sc, i, BUS_DMASYNC_PREREAD); 655 } 656 657 if ((status & ~(TCR_EXDIS|TCR_CRCI|TCR_POWC|TCR_PINT)) == 0) 658 break; 659 660 totstat |= status; 661 662 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 663 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 664 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 665 m_freem(ds->ds_mbuf); 666 ds->ds_mbuf = NULL; 667 668 /* 669 * Check for errors and collisions. 670 */ 671 if (status & TCR_PTX) 672 ifp->if_opackets++; 673 else 674 ifp->if_oerrors++; 675 ifp->if_collisions += TDA_STATUS_NCOL(status); 676 } 677 678 /* Update the dirty transmit buffer pointer. */ 679 sc->sc_txdirty = i; 680 681 /* 682 * Cancel the watchdog timer if there are no pending 683 * transmissions. 684 */ 685 if (sc->sc_txpending == 0) 686 ifp->if_timer = 0; 687 688 return (totstat); 689 } 690 691 /* 692 * sonic_rxintr: 693 * 694 * Helper; handle receive interrupts. 695 */ 696 void 697 sonic_rxintr(struct sonic_softc *sc) 698 { 699 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 700 struct sonic_descsoft *ds; 701 struct sonic_rda32 *rda32; 702 struct sonic_rda16 *rda16; 703 struct mbuf *m; 704 int i, len; 705 uint16_t status, bytecount, ptr0, ptr1, seqno; 706 707 for (i = sc->sc_rxptr;; i = SONIC_NEXTRX(i)) { 708 ds = &sc->sc_rxsoft[i]; 709 710 if (sc->sc_32bit) { 711 SONIC_CDRXSYNC32(sc, i, 712 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 713 rda32 = &sc->sc_rda32[i]; 714 SONIC_CDRXSYNC32(sc, i, BUS_DMASYNC_PREREAD); 715 if (rda32->rda_inuse != 0) 716 break; 717 status = sonic32toh(sc, rda32->rda_status); 718 bytecount = sonic32toh(sc, rda32->rda_bytecount); 719 ptr0 = sonic32toh(sc, rda32->rda_pkt_ptr0); 720 ptr1 = sonic32toh(sc, rda32->rda_pkt_ptr1); 721 seqno = sonic32toh(sc, rda32->rda_seqno); 722 } else { 723 SONIC_CDRXSYNC16(sc, i, 724 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 725 rda16 = &sc->sc_rda16[i]; 726 SONIC_CDRXSYNC16(sc, i, BUS_DMASYNC_PREREAD); 727 if (rda16->rda_inuse != 0) 728 break; 729 status = sonic16toh(sc, rda16->rda_status); 730 bytecount = sonic16toh(sc, rda16->rda_bytecount); 731 ptr0 = sonic16toh(sc, rda16->rda_pkt_ptr0); 732 ptr1 = sonic16toh(sc, rda16->rda_pkt_ptr1); 733 seqno = sonic16toh(sc, rda16->rda_seqno); 734 } 735 736 /* 737 * Make absolutely sure this is the only packet 738 * in this receive buffer. Our entire Rx buffer 739 * management scheme depends on this, and if the 740 * SONIC didn't follow our rule, it means we've 741 * misconfigured it. 742 */ 743 KASSERT(status & RCR_LPKT); 744 745 /* 746 * Make sure the packet arrived OK. If an error occurred, 747 * update stats and reset the descriptor. The buffer will 748 * be reused the next time the descriptor comes up in the 749 * ring. 750 */ 751 if ((status & RCR_PRX) == 0) { 752 if (status & RCR_FAER) 753 printf("%s: Rx frame alignment error\n", 754 sc->sc_dev.dv_xname); 755 else if (status & RCR_CRCR) 756 printf("%s: Rx CRC error\n", 757 sc->sc_dev.dv_xname); 758 ifp->if_ierrors++; 759 SONIC_INIT_RXDESC(sc, i); 760 continue; 761 } 762 763 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 764 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 765 766 /* 767 * The SONIC includes the CRC with every packet. 768 */ 769 len = bytecount - ETHER_CRC_LEN; 770 771 /* 772 * Ok, if the chip is in 32-bit mode, then receive 773 * buffers must be aligned to 32-bit boundaries, 774 * which means the payload is misaligned. In this 775 * case, we must allocate a new mbuf, and copy the 776 * packet into it, scooted forward 2 bytes to ensure 777 * proper alignment. 778 * 779 * Note, in 16-bit mode, we can configure the SONIC 780 * to do what we want, and we have. 781 */ 782 #ifndef __NO_STRICT_ALIGNMENT 783 if (sc->sc_32bit) { 784 MGETHDR(m, M_DONTWAIT, MT_DATA); 785 if (m == NULL) 786 goto dropit; 787 if (len > (MHLEN - 2)) { 788 MCLGET(m, M_DONTWAIT); 789 if ((m->m_flags & M_EXT) == 0) 790 goto dropit; 791 } 792 m->m_data += 2; 793 /* 794 * Note that we use a cluster for incoming frames, 795 * so the buffer is virtually contiguous. 796 */ 797 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 798 len); 799 SONIC_INIT_RXDESC(sc, i); 800 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 801 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 802 } else 803 #endif /* ! __NO_STRICT_ALIGNMENT */ 804 /* 805 * If the packet is small enough to fit in a single 806 * header mbuf, allocate one and copy the data into 807 * it. This greatly reduces memory consumption when 808 * we receive lots of small packets. 809 */ 810 if (sonic_copy_small != 0 && len <= (MHLEN - 2)) { 811 MGETHDR(m, M_DONTWAIT, MT_DATA); 812 if (m == NULL) 813 goto dropit; 814 m->m_data += 2; 815 /* 816 * Note that we use a cluster for incoming frames, 817 * so the buffer is virtually contiguous. 818 */ 819 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 820 len); 821 SONIC_INIT_RXDESC(sc, i); 822 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 823 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 824 } else { 825 m = ds->ds_mbuf; 826 if (sonic_add_rxbuf(sc, i) != 0) { 827 dropit: 828 ifp->if_ierrors++; 829 SONIC_INIT_RXDESC(sc, i); 830 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 831 ds->ds_dmamap->dm_mapsize, 832 BUS_DMASYNC_PREREAD); 833 continue; 834 } 835 } 836 837 ifp->if_ipackets++; 838 m->m_pkthdr.rcvif = ifp; 839 m->m_pkthdr.len = m->m_len = len; 840 841 #if NBPFILTER > 0 842 /* 843 * Pass this up to any BPF listeners. 844 */ 845 if (ifp->if_bpf) 846 bpf_mtap(ifp->if_bpf, m); 847 #endif /* NBPFILTER > 0 */ 848 849 /* Pass it on. */ 850 (*ifp->if_input)(ifp, m); 851 } 852 853 /* Update the receive pointer. */ 854 sc->sc_rxptr = i; 855 CSR_WRITE(sc, SONIC_RWR, SONIC_CDRRADDR(sc, SONIC_PREVRX(i))); 856 } 857 858 /* 859 * sonic_reset: 860 * 861 * Perform a soft reset on the SONIC. 862 */ 863 void 864 sonic_reset(struct sonic_softc *sc) 865 { 866 867 /* stop TX, RX and timer, and ensure RST is clear */ 868 CSR_WRITE(sc, SONIC_CR, CR_STP | CR_RXDIS | CR_HTX); 869 delay(1000); 870 871 CSR_WRITE(sc, SONIC_CR, CR_RST); 872 delay(1000); 873 874 /* clear all interrupts */ 875 CSR_WRITE(sc, SONIC_IMR, 0); 876 CSR_WRITE(sc, SONIC_ISR, IMR_ALL); 877 878 CSR_WRITE(sc, SONIC_CR, 0); 879 delay(1000); 880 } 881 882 /* 883 * sonic_init: [ifnet interface function] 884 * 885 * Initialize the interface. Must be called at splnet(). 886 */ 887 int 888 sonic_init(struct ifnet *ifp) 889 { 890 struct sonic_softc *sc = ifp->if_softc; 891 struct sonic_descsoft *ds; 892 int i, error = 0; 893 uint16_t reg; 894 895 /* 896 * Cancel any pending I/O. 897 */ 898 sonic_stop(ifp, 0); 899 900 /* 901 * Reset the SONIC to a known state. 902 */ 903 sonic_reset(sc); 904 905 /* 906 * Bring the SONIC into reset state, and program the DCR. 907 * 908 * Note: We don't bother optimizing the transmit and receive 909 * thresholds, here. TFT/RFT values should be set in MD attachments. 910 */ 911 reg = sc->sc_dcr; 912 if (sc->sc_32bit) 913 reg |= DCR_DW; 914 CSR_WRITE(sc, SONIC_CR, CR_RST); 915 CSR_WRITE(sc, SONIC_DCR, reg); 916 CSR_WRITE(sc, SONIC_DCR2, sc->sc_dcr2); 917 CSR_WRITE(sc, SONIC_CR, 0); 918 919 /* 920 * Initialize the transmit descriptors. 921 */ 922 if (sc->sc_32bit) { 923 for (i = 0; i < SONIC_NTXDESC; i++) { 924 memset(&sc->sc_tda32[i], 0, sizeof(struct sonic_tda32)); 925 SONIC_CDTXSYNC32(sc, i, 926 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 927 } 928 } else { 929 for (i = 0; i < SONIC_NTXDESC; i++) { 930 memset(&sc->sc_tda16[i], 0, sizeof(struct sonic_tda16)); 931 SONIC_CDTXSYNC16(sc, i, 932 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 933 } 934 } 935 sc->sc_txpending = 0; 936 sc->sc_txdirty = 0; 937 sc->sc_txlast = SONIC_NTXDESC - 1; 938 939 /* 940 * Initialize the receive descriptor ring. 941 */ 942 for (i = 0; i < SONIC_NRXDESC; i++) { 943 ds = &sc->sc_rxsoft[i]; 944 if (ds->ds_mbuf == NULL) { 945 if ((error = sonic_add_rxbuf(sc, i)) != 0) { 946 printf("%s: unable to allocate or map Rx " 947 "buffer %d, error = %d\n", 948 sc->sc_dev.dv_xname, i, error); 949 /* 950 * XXX Should attempt to run with fewer receive 951 * XXX buffers instead of just failing. 952 */ 953 sonic_rxdrain(sc); 954 goto out; 955 } 956 } else 957 SONIC_INIT_RXDESC(sc, i); 958 } 959 sc->sc_rxptr = 0; 960 961 /* Give the transmit ring to the SONIC. */ 962 CSR_WRITE(sc, SONIC_UTDAR, (SONIC_CDTXADDR(sc, 0) >> 16) & 0xffff); 963 CSR_WRITE(sc, SONIC_CTDAR, SONIC_CDTXADDR(sc, 0) & 0xffff); 964 965 /* Give the receive descriptor ring to the SONIC. */ 966 CSR_WRITE(sc, SONIC_URDAR, (SONIC_CDRXADDR(sc, 0) >> 16) & 0xffff); 967 CSR_WRITE(sc, SONIC_CRDAR, SONIC_CDRXADDR(sc, 0) & 0xffff); 968 969 /* Give the receive buffer ring to the SONIC. */ 970 CSR_WRITE(sc, SONIC_URRAR, (SONIC_CDRRADDR(sc, 0) >> 16) & 0xffff); 971 CSR_WRITE(sc, SONIC_RSAR, SONIC_CDRRADDR(sc, 0) & 0xffff); 972 if (sc->sc_32bit) 973 CSR_WRITE(sc, SONIC_REAR, 974 (SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1) + 975 sizeof(struct sonic_rra32)) & 0xffff); 976 else 977 CSR_WRITE(sc, SONIC_REAR, 978 (SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1) + 979 sizeof(struct sonic_rra16)) & 0xffff); 980 CSR_WRITE(sc, SONIC_RRR, SONIC_CDRRADDR(sc, 0) & 0xffff); 981 CSR_WRITE(sc, SONIC_RWR, SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1)); 982 983 /* 984 * Set the End-Of-Buffer counter such that only one packet 985 * will be placed into each buffer we provide. Note we are 986 * following the recommendation of section 3.4.4 of the manual 987 * here, and have "lengthened" the receive buffers accordingly. 988 */ 989 if (sc->sc_32bit) 990 CSR_WRITE(sc, SONIC_EOBC, (ETHER_MAX_LEN + 2) / 2); 991 else 992 CSR_WRITE(sc, SONIC_EOBC, (ETHER_MAX_LEN / 2)); 993 994 /* Reset the receive sequence counter. */ 995 CSR_WRITE(sc, SONIC_RSC, 0); 996 997 /* Clear the tally registers. */ 998 CSR_WRITE(sc, SONIC_CRCETC, 0xffff); 999 CSR_WRITE(sc, SONIC_FAET, 0xffff); 1000 CSR_WRITE(sc, SONIC_MPT, 0xffff); 1001 1002 /* Set the receive filter. */ 1003 sonic_set_filter(sc); 1004 1005 /* 1006 * Set the interrupt mask register. 1007 */ 1008 sc->sc_imr = IMR_RFO | IMR_RBA | IMR_RBE | IMR_RDE | 1009 IMR_TXER | IMR_PTX | IMR_PRX; 1010 CSR_WRITE(sc, SONIC_IMR, sc->sc_imr); 1011 1012 /* 1013 * Start the receive process in motion. Note, we don't 1014 * start the transmit process until we actually try to 1015 * transmit packets. 1016 */ 1017 CSR_WRITE(sc, SONIC_CR, CR_RXEN | CR_RRRA); 1018 1019 /* 1020 * ...all done! 1021 */ 1022 ifp->if_flags |= IFF_RUNNING; 1023 ifp->if_flags &= ~IFF_OACTIVE; 1024 1025 out: 1026 if (error) 1027 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1028 return (error); 1029 } 1030 1031 /* 1032 * sonic_rxdrain: 1033 * 1034 * Drain the receive queue. 1035 */ 1036 void 1037 sonic_rxdrain(struct sonic_softc *sc) 1038 { 1039 struct sonic_descsoft *ds; 1040 int i; 1041 1042 for (i = 0; i < SONIC_NRXDESC; i++) { 1043 ds = &sc->sc_rxsoft[i]; 1044 if (ds->ds_mbuf != NULL) { 1045 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1046 m_freem(ds->ds_mbuf); 1047 ds->ds_mbuf = NULL; 1048 } 1049 } 1050 } 1051 1052 /* 1053 * sonic_stop: [ifnet interface function] 1054 * 1055 * Stop transmission on the interface. 1056 */ 1057 void 1058 sonic_stop(struct ifnet *ifp, int disable) 1059 { 1060 struct sonic_softc *sc = ifp->if_softc; 1061 struct sonic_descsoft *ds; 1062 int i; 1063 1064 /* 1065 * Disable interrupts. 1066 */ 1067 CSR_WRITE(sc, SONIC_IMR, 0); 1068 1069 /* 1070 * Stop the transmitter, receiver, and timer. 1071 */ 1072 CSR_WRITE(sc, SONIC_CR, CR_HTX|CR_RXDIS|CR_STP); 1073 for (i = 0; i < 1000; i++) { 1074 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP|CR_RXEN|CR_ST)) == 0) 1075 break; 1076 delay(2); 1077 } 1078 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP|CR_RXEN|CR_ST)) != 0) 1079 printf("%s: SONIC failed to stop\n", sc->sc_dev.dv_xname); 1080 1081 /* 1082 * Release any queued transmit buffers. 1083 */ 1084 for (i = 0; i < SONIC_NTXDESC; i++) { 1085 ds = &sc->sc_txsoft[i]; 1086 if (ds->ds_mbuf != NULL) { 1087 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1088 m_freem(ds->ds_mbuf); 1089 ds->ds_mbuf = NULL; 1090 } 1091 } 1092 1093 /* 1094 * Mark the interface down and cancel the watchdog timer. 1095 */ 1096 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1097 ifp->if_timer = 0; 1098 1099 if (disable) 1100 sonic_rxdrain(sc); 1101 } 1102 1103 /* 1104 * sonic_add_rxbuf: 1105 * 1106 * Add a receive buffer to the indicated descriptor. 1107 */ 1108 int 1109 sonic_add_rxbuf(struct sonic_softc *sc, int idx) 1110 { 1111 struct sonic_descsoft *ds = &sc->sc_rxsoft[idx]; 1112 struct mbuf *m; 1113 int error; 1114 1115 MGETHDR(m, M_DONTWAIT, MT_DATA); 1116 if (m == NULL) 1117 return (ENOBUFS); 1118 1119 MCLGET(m, M_DONTWAIT); 1120 if ((m->m_flags & M_EXT) == 0) { 1121 m_freem(m); 1122 return (ENOBUFS); 1123 } 1124 1125 if (ds->ds_mbuf != NULL) 1126 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1127 1128 ds->ds_mbuf = m; 1129 1130 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1131 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1132 BUS_DMA_READ|BUS_DMA_NOWAIT); 1133 if (error) { 1134 printf("%s: can't load rx DMA map %d, error = %d\n", 1135 sc->sc_dev.dv_xname, idx, error); 1136 panic("sonic_add_rxbuf"); /* XXX */ 1137 } 1138 1139 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1140 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1141 1142 SONIC_INIT_RXDESC(sc, idx); 1143 1144 return (0); 1145 } 1146 1147 static void 1148 sonic_set_camentry(struct sonic_softc *sc, int entry, const uint8_t *enaddr) 1149 { 1150 1151 if (sc->sc_32bit) { 1152 struct sonic_cda32 *cda = &sc->sc_cda32[entry]; 1153 1154 cda->cda_entry = htosonic32(sc, entry); 1155 cda->cda_addr0 = htosonic32(sc, enaddr[0] | (enaddr[1] << 8)); 1156 cda->cda_addr1 = htosonic32(sc, enaddr[2] | (enaddr[3] << 8)); 1157 cda->cda_addr2 = htosonic32(sc, enaddr[4] | (enaddr[5] << 8)); 1158 } else { 1159 struct sonic_cda16 *cda = &sc->sc_cda16[entry]; 1160 1161 cda->cda_entry = htosonic16(sc, entry); 1162 cda->cda_addr0 = htosonic16(sc, enaddr[0] | (enaddr[1] << 8)); 1163 cda->cda_addr1 = htosonic16(sc, enaddr[2] | (enaddr[3] << 8)); 1164 cda->cda_addr2 = htosonic16(sc, enaddr[4] | (enaddr[5] << 8)); 1165 } 1166 } 1167 1168 /* 1169 * sonic_set_filter: 1170 * 1171 * Set the SONIC receive filter. 1172 */ 1173 void 1174 sonic_set_filter(struct sonic_softc *sc) 1175 { 1176 struct ethercom *ec = &sc->sc_ethercom; 1177 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1178 struct ether_multi *enm; 1179 struct ether_multistep step; 1180 int i, entry = 0; 1181 uint16_t camvalid = 0; 1182 uint16_t rcr = 0; 1183 1184 if (ifp->if_flags & IFF_BROADCAST) 1185 rcr |= RCR_BRD; 1186 1187 if (ifp->if_flags & IFF_PROMISC) { 1188 rcr |= RCR_PRO; 1189 goto allmulti; 1190 } 1191 1192 /* Put our station address in the first CAM slot. */ 1193 sonic_set_camentry(sc, entry, CLLADDR(ifp->if_sadl)); 1194 camvalid |= (1U << entry); 1195 entry++; 1196 1197 /* Add the multicast addresses to the CAM. */ 1198 ETHER_FIRST_MULTI(step, ec, enm); 1199 while (enm != NULL) { 1200 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1201 /* 1202 * We must listen to a range of multicast addresses. 1203 * The only way to do this on the SONIC is to enable 1204 * reception of all multicast packets. 1205 */ 1206 goto allmulti; 1207 } 1208 1209 if (entry == 16) { 1210 /* 1211 * Out of CAM slots. Have to enable reception 1212 * of all multicast addresses. 1213 */ 1214 goto allmulti; 1215 } 1216 1217 sonic_set_camentry(sc, entry, enm->enm_addrlo); 1218 camvalid |= (1U << entry); 1219 entry++; 1220 1221 ETHER_NEXT_MULTI(step, enm); 1222 } 1223 1224 ifp->if_flags &= ~IFF_ALLMULTI; 1225 goto setit; 1226 1227 allmulti: 1228 /* Use only the first CAM slot (station address). */ 1229 camvalid = 0x0001; 1230 entry = 1; 1231 rcr |= RCR_AMC; 1232 1233 setit: 1234 /* Load the CAM. */ 1235 SONIC_CDCAMSYNC(sc, BUS_DMASYNC_PREWRITE); 1236 CSR_WRITE(sc, SONIC_CDP, SONIC_CDCAMADDR(sc) & 0xffff); 1237 CSR_WRITE(sc, SONIC_CDC, entry); 1238 CSR_WRITE(sc, SONIC_CR, CR_LCAM); 1239 for (i = 0; i < 10000; i++) { 1240 if ((CSR_READ(sc, SONIC_CR) & CR_LCAM) == 0) 1241 break; 1242 delay(2); 1243 } 1244 if (CSR_READ(sc, SONIC_CR) & CR_LCAM) 1245 printf("%s: CAM load failed\n", sc->sc_dev.dv_xname); 1246 SONIC_CDCAMSYNC(sc, BUS_DMASYNC_POSTWRITE); 1247 1248 /* Set the CAM enable resgiter. */ 1249 CSR_WRITE(sc, SONIC_CER, camvalid); 1250 1251 /* Set the receive control register. */ 1252 CSR_WRITE(sc, SONIC_RCR, rcr); 1253 } 1254
Indexes created Thu Sep 25 16:09:42 GMT 2025