dp83932reg.h revision 1.2
1 /* $NetBSD: dp83932reg.h,v 1.2 2002/05/03 00:07:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_IC_DP83932REG_H_ 40 #define _DEV_IC_DP83932REG_H_ 41 42 /* 43 * Register description for the National Semiconductor DP83932 44 * Systems-Oriented Network Interface Controller (SONIC). 45 */ 46 47 /* 48 * SONIC Receive Descriptor Area. 49 */ 50 struct sonic_rda16 { 51 uint16_t rda_status; 52 uint16_t rda_bytecount; 53 uint16_t rda_pkt_ptr0; 54 uint16_t rda_pkt_ptr1; 55 uint16_t rda_seqno; 56 uint16_t rda_link; 57 uint16_t rda_inuse; 58 } __attribute__((__packed__)); 59 60 struct sonic_rda32 { 61 uint32_t rda_status; 62 uint32_t rda_bytecount; 63 uint32_t rda_pkt_ptr0; 64 uint32_t rda_pkt_ptr1; 65 uint32_t rda_seqno; 66 uint32_t rda_link; 67 uint32_t rda_inuse; 68 } __attribute__((__packed__)); 69 70 #define RDA_SEQNO_RBA(x) (((x) >> 8) & 0xff) 71 #define RDA_SEQNO_RSN(x) ((x) & 0xff) 72 73 #define RDA_LINK_EOL 0x01 /* end-of-list */ 74 75 /* 76 * SONIC Receive Resource Area. 77 * 78 * Note, in 32-bit mode, Rx buffers must be aligned to 32-bit 79 * boundaries, and in 16-bit mode, to 16-bit boundaries. 80 * 81 * Also note the `word count' is always in units of 16-bit words. 82 */ 83 struct sonic_rra16 { 84 uint16_t rra_ptr0; 85 uint16_t rra_ptr1; 86 uint16_t rra_wc0; 87 uint16_t rra_wc1; 88 } __attribute__((__packed__)); 89 90 struct sonic_rra32 { 91 uint32_t rra_ptr0; 92 uint32_t rra_ptr1; 93 uint32_t rra_wc0; 94 uint32_t rra_wc1; 95 } __attribute__((__packed__)); 96 97 /* 98 * SONIC Transmit Descriptor Area 99 * 100 * Note the number of fragments defined here is arbitrary. 101 */ 102 #define SONIC_NTXFRAGS 16 103 104 struct sonic_frag16 { 105 uint16_t frag_ptr0; 106 uint16_t frag_ptr1; 107 uint16_t frag_size; 108 } __attribute__((__packed__)); 109 110 struct sonic_frag32 { 111 uint32_t frag_ptr0; 112 uint32_t frag_ptr1; 113 uint32_t frag_size; 114 } __attribute__((__packed__)); 115 116 /* 117 * Note the frag after the last frag is used to link up to the 118 * next descriptor. 119 */ 120 121 struct sonic_tda16 { 122 uint16_t tda_status; 123 uint16_t tda_pktconfig; 124 uint16_t tda_pktsize; 125 uint16_t tda_fragcnt; 126 struct sonic_frag16 tda_frags[SONIC_NTXFRAGS + 1]; 127 #if 0 128 uint16_t tda_link; 129 #endif 130 } __attribute__((__packed__)); 131 132 struct sonic_tda32 { 133 uint32_t tda_status; 134 uint32_t tda_pktconfig; 135 uint32_t tda_pktsize; 136 uint32_t tda_fragcnt; 137 struct sonic_frag32 tda_frags[SONIC_NTXFRAGS + 1]; 138 #if 0 139 uint32_t tda_link; 140 #endif 141 } __attribute__((__packed__)); 142 143 #define TDA_STATUS_NCOL(x) (((x) >> 11) & 0x1f) 144 145 #define TDA_LINK_EOL 0x01 /* end-of-list */ 146 147 /* 148 * SONIC CAM Descriptor Area. 149 */ 150 struct sonic_cda16 { 151 uint16_t cda_entry; 152 uint16_t cda_addr0; 153 uint16_t cda_addr1; 154 uint16_t cda_addr2; 155 } __attribute__((__packed__)); 156 157 struct sonic_cda32 { 158 uint32_t cda_entry; 159 uint32_t cda_addr0; 160 uint32_t cda_addr1; 161 uint32_t cda_addr2; 162 } __attribute__((__packed__)); 163 164 /* 165 * SONIC register file. 166 * 167 * NOTE: We define these as indices, and use a register map to deal 168 * with different address strides. 169 */ 170 171 #define SONIC_CR 0x00 /* Command Register */ 172 #define CR_HTX (1U << 0) /* Halt Transmission */ 173 #define CR_TXP (1U << 1) /* Transmit Packets */ 174 #define CR_RXDIS (1U << 2) /* Receiver Disable */ 175 #define CR_RXEN (1U << 3) /* Receiver Enable */ 176 #define CR_STP (1U << 4) /* Stop Timer */ 177 #define CR_ST (1U << 5) /* Start Timer */ 178 #define CR_RST (1U << 7) /* Software Reset */ 179 #define CR_RRRA (1U << 8) /* Read RRA */ 180 #define CR_LCAM (1U << 9) /* Load CAM */ 181 182 #define SONIC_DCR 0x01 /* Data Configuration Register */ 183 #define DCR_TFT0 (1U << 0) /* Transmit FIFO Threshold (lo) */ 184 #define DCR_TFT1 (1U << 1) /* Transmit FIFO Threshold (hi) */ 185 #define DCR_RFT0 (1U << 2) /* Receive FIFO Threshold (lo) */ 186 #define DCR_RFT1 (1U << 3) /* Receive FIFO Threshold (hi) */ 187 #define DCR_BMS (1U << 4) /* Block Mode Select for DMA */ 188 #define DCR_DW (1U << 5) /* Data Width Select */ 189 #define DCR_WC0 (1U << 6) /* Wait State Control (lo) */ 190 #define DCR_WC1 (1U << 7) /* Wait State Control (hi) */ 191 #define DCR_USR0 (1U << 8) /* User Definable Pin 0 */ 192 #define DCR_USR1 (1U << 9) /* User Definable Pin 1 */ 193 #define DCR_SBUS (1U << 10) /* Synchronous Bus Mode */ 194 #define DCR_PO0 (1U << 11) /* Programmable Output 0 */ 195 #define DCR_PO1 (1U << 12) /* Programmable Output 1 */ 196 #define DCR_LBR (1U << 13) /* Latched Bus Retry */ 197 #define DCR_EXBUS (1U << 15) /* Extended Bus Mode */ 198 199 #define SONIC_RCR 0x02 /* Receive Control Register */ 200 #define RCR_PRX (1U << 0) /* Packet Received OK */ 201 #define RCR_LBK (1U << 1) /* Loopback Packet Received */ 202 #define RCR_FAER (1U << 2) /* Frame Alignment Error */ 203 #define RCR_CRCR (1U << 3) /* CRC Error */ 204 #define RCR_COL (1U << 4) /* Collision Activity */ 205 #define RCR_CRS (1U << 5) /* Carrier Sense Activity */ 206 #define RCR_LPKT (1U << 6) /* Last Packet in RBA */ 207 #define RCR_BC (1U << 7) /* Broadcast Packet Received */ 208 #define RCR_MC (1U << 8) /* Multicast Packet Received */ 209 #define RCR_LB0 (1U << 9) /* Loopback Control 0 */ 210 #define RCR_LB1 (1U << 10) /* Loopback Control 1 */ 211 #define RCR_AMC (1U << 11) /* Accept All Multicast Packets */ 212 #define RCR_PRO (1U << 12) /* Physical Promiscuous Packets */ 213 #define RCR_BRD (1U << 13) /* Accept Broadcast Packets */ 214 #define RCR_RNT (1U << 14) /* Accept Runt Packets */ 215 #define RCR_ERR (1U << 15) /* Accept Packets with Errors */ 216 217 #define SONIC_TCR 0x03 /* Transmit Control Register */ 218 #define TCR_PTX (1U << 0) /* Packet Transmitted OK */ 219 #define TCR_BCM (1U << 1) /* Byte Count Mismatch */ 220 #define TCR_FU (1U << 2) /* FIFO Underrun */ 221 #define TCR_PMB (1U << 3) /* Packet Monitored Bad */ 222 #define TCR_OWC (1U << 5) /* Out of Window Collision */ 223 #define TCR_EXC (1U << 6) /* Excessive Collisions */ 224 #define TCR_CRSL (1U << 7) /* Carrier Sense Lost */ 225 #define TCR_NCRS (1U << 8) /* No Carrier Sense */ 226 #define TCR_DEF (1U << 9) /* Deferred Transmission */ 227 #define TCR_EXD (1U << 10) /* Excessive Deferral */ 228 #define TCR_EXDIS (1U << 12) /* Disable Excessive Deferral Timer */ 229 #define TCR_CRCI (1U << 13) /* CRC Inhibit */ 230 #define TCR_POWC (1U << 14) /* Programmed Out of Window Col. Tmr */ 231 #define TCR_PINT (1U << 15) /* Programmable Interrupt */ 232 233 #define SONIC_IMR 0x04 /* Interrupt Mask Register */ 234 #define IMR_RFO (1U << 0) /* Rx FIFO Overrun */ 235 #define IMR_MP (1U << 1) /* Missed Packet Tally */ 236 #define IMR_FAE (1U << 2) /* Frame Alignment Error Tally */ 237 #define IMR_CRC (1U << 3) /* CRC Tally */ 238 #define IMR_RBA (1U << 4) /* RBA Exceeded */ 239 #define IMR_RBE (1U << 5) /* Rx Buffers Exhausted */ 240 #define IMR_RDE (1U << 6) /* Rx Descriptors Exhausted */ 241 #define IMR_TC (1U << 7) /* Timer Complete */ 242 #define IMR_TXER (1U << 8) /* Transmit Error */ 243 #define IMR_PTX (1U << 9) /* Transmit OK */ 244 #define IMR_PRX (1U << 10) /* Packet Received */ 245 #define IMR_PINT (1U << 11) /* Programmable Interrupt */ 246 #define IMR_LCD (1U << 12) /* Load CAM Done */ 247 #define IMR_HBL (1U << 13) /* Heartbeat Lost */ 248 #define IMR_BR (1U << 14) /* Bus Retry Occurred */ 249 250 #define SONIC_ISR 0x05 /* Interrupt Status Register */ 251 /* See IMR bits. */ 252 253 #define SONIC_UTDAR 0x06 /* Upper Tx Descriptor Adress Register */ 254 255 #define SONIC_CTDAR 0x07 /* Current Tx Descriptor Address Register */ 256 257 #define SONIC_TPS 0x08 /* Transmit Packet Size */ 258 259 #define SONIC_TFC 0x09 /* Transmit Fragment Count */ 260 261 #define SONIC_TSA0 0x0a /* Transmit Start Address (lo) */ 262 263 #define SONIC_TSA1 0x0b /* Transmit Start Address (hi) */ 264 265 #define SONIC_TFS 0x0c /* Transmit Fragment Size */ 266 267 #define SONIC_URDAR 0x0d /* Upper Rx Descriptor Address Register */ 268 269 #define SONIC_CRDAR 0x0e /* Current Rx Descriptor Address Register */ 270 271 #define SONIC_CRBA0 0x0f /* Current Receive Buffer Address (lo) */ 272 273 #define SONIC_CRBA1 0x10 /* Current Receive Buffer Address (hi) */ 274 275 #define SONIC_RBWC0 0x11 /* Remaining Buffer Word Count 0 */ 276 277 #define SONIC_RBWC1 0x12 /* Remaining Buffer Word Count 1 */ 278 279 #define SONIC_EOBC 0x13 /* End Of Buffer Word Count */ 280 281 #define SONIC_URRAR 0x14 /* Upper Rx Resource Address Register */ 282 283 #define SONIC_RSAR 0x15 /* Resource Start Address Register */ 284 285 #define SONIC_REAR 0x16 /* Resource End Address Register */ 286 287 #define SONIC_RRR 0x17 /* Resource Read Register */ 288 289 #define SONIC_RWR 0x18 /* Resource Write Register */ 290 291 #define SONIC_TRBA0 0x19 /* Temporary Receive Buffer Address (lo) */ 292 293 #define SONIC_TRBA1 0x1a /* Temporary Receive Buffer Address (hi) */ 294 295 #define SONIC_TBWC0 0x1b /* Temporary Buffer Word Count 0 */ 296 297 #define SONIC_TBWC1 0x1c /* Temporary Buffer Word Count 1 */ 298 299 #define SONIC_ADDR0 0x1d /* Address Generator 0 */ 300 301 #define SONIC_ADDR1 0x1e /* Address Generator 1 */ 302 303 #define SONIC_LLFA 0x1f /* Last Link Field Address */ 304 305 #define SONIC_TTDA 0x20 /* Temporary Tx Descriptor Address */ 306 307 #define SONIC_CEP 0x21 /* CAM Entry Pointer */ 308 309 #define SONIC_CAP2 0x22 /* CAM Address Port 2 */ 310 311 #define SONIC_CAP1 0x23 /* CAM Address Port 1 */ 312 313 #define SONIC_CAP0 0x24 /* CAM Address Port 0 */ 314 315 #define SONIC_CER 0x25 /* CAM Enable Register */ 316 317 #define SONIC_CDP 0x26 /* CAM Descriptor Pointer */ 318 319 #define SONIC_CDC 0x27 /* CAM Descriptor Count */ 320 321 #define SONIC_SRR 0x28 /* Silicon Revision Register */ 322 323 #define SONIC_WT0 0x29 /* Watchdog Timer 0 */ 324 325 #define SONIC_WT1 0x2a /* Watchdog Timer 1 */ 326 327 #define SONIC_RSC 0x2b /* Receive Sequence Counter */ 328 329 #define SONIC_CRCETC 0x2c /* CRC Error Tally Count */ 330 331 #define SONIC_FAET 0x2d /* Frame Alignment Error Tally */ 332 333 #define SONIC_MPT 0x2e /* Missed Packet Tally */ 334 335 #define SONIC_DCR2 0x3f /* Data Configuration Register 2 */ 336 #define DCR2_RJCM (1U << 0) /* Reject on CAM Match */ 337 #define DCR2_PCNM (1U << 1) /* Packet Compress When not Matched */ 338 #define DCR2_PCM (1U << 2) /* Packet Compress When Matched */ 339 #define DCR2_PH (1U << 4) /* Program Hold */ 340 #define DCR2_EXPO0 (1U << 12) /* Extended Programmable Output 0 */ 341 #define DCR2_EXPO1 (1U << 13) /* Extended Programmable Output 1 */ 342 #define DCR2_EXPO2 (1U << 14) /* Extended Programmable Output 2 */ 343 #define DCR2_EXPO3 (1U << 15) /* Extended Programmable Output 3 */ 344 345 #define SONIC_NREGS 0x40 346 347 #endif /* _DEV_IC_DP83932REG_H_ */ 348
Indexes created Mon Sep 29 21:09:56 GMT 2025