dptreg.h revision 1.5.2.2
1 1.5.2.2 he /* $NetBSD: dptreg.h,v 1.5.2.2 2000/01/17 18:34:32 he Exp $ */ 2 1.5.2.2 he 3 1.5.2.2 he /* 4 1.5.2.2 he * Copyright (c) 1999 Andy Doran <ad (at) NetBSD.org> 5 1.5.2.2 he * All rights reserved. 6 1.5.2.2 he * 7 1.5.2.2 he * Redistribution and use in source and binary forms, with or without 8 1.5.2.2 he * modification, are permitted provided that the following conditions 9 1.5.2.2 he * are met: 10 1.5.2.2 he * 1. Redistributions of source code must retain the above copyright 11 1.5.2.2 he * notice, this list of conditions and the following disclaimer. 12 1.5.2.2 he * 2. Redistributions in binary form must reproduce the above copyright 13 1.5.2.2 he * notice, this list of conditions and the following disclaimer in the 14 1.5.2.2 he * documentation and/or other materials provided with the distribution. 15 1.5.2.2 he * 16 1.5.2.2 he * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 1.5.2.2 he * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.5.2.2 he * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.5.2.2 he * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 1.5.2.2 he * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.5.2.2 he * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.5.2.2 he * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.5.2.2 he * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.5.2.2 he * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.5.2.2 he * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.5.2.2 he * SUCH DAMAGE. 27 1.5.2.2 he * 28 1.5.2.2 he */ 29 1.5.2.2 he 30 1.5.2.2 he #ifndef _IC_DPTREG_H_ 31 1.5.2.2 he #define _IC_DPTREG_H_ 1 32 1.5.2.2 he 33 1.5.2.2 he /* Hardware limits */ 34 1.5.2.2 he #define DPT_MAX_TARGETS 16 35 1.5.2.2 he #define DPT_MAX_LUNS 8 36 1.5.2.2 he #define DPT_MAX_CHANNELS 3 37 1.5.2.2 he 38 1.5.2.2 he /* Software parameters */ 39 1.5.2.2 he #define DPT_MAX_XFER ((DPT_SG_SIZE - 1) << PGSHIFT) 40 1.5.2.2 he #define DPT_MAX_CCBS 256 41 1.5.2.2 he #define DPT_SG_SIZE 64 42 1.5.2.2 he #define DPT_ABORT_TIMEOUT 2000 /* milliseconds */ 43 1.5.2.2 he #define DPT_MORE_TIMEOUT 1000 /* microseconds */ 44 1.5.2.2 he 45 1.5.2.2 he #ifdef _KERNEL 46 1.5.2.2 he 47 1.5.2.2 he #if BYTE_ORDER == LITTLE_ENDIAN 48 1.5.2.2 he #define SWAP32(x) bswap32((x)) 49 1.5.2.2 he #define SWAP16(x) bswap16((x)) 50 1.5.2.2 he #define RSWAP32(x) (x) 51 1.5.2.2 he #define RSWAP16(x) (x) 52 1.5.2.2 he #else 53 1.5.2.2 he #define SWAP32(x) (x) 54 1.5.2.2 he #define SWAP16(x) (x) 55 1.5.2.2 he #define RSWAP32(x) bswap32((x)) 56 1.5.2.2 he #define RSWAP16(x) bswap16((x)) 57 1.5.2.2 he #endif 58 1.5.2.2 he 59 1.5.2.2 he #define dpt_inb(x, o) \ 60 1.5.2.2 he bus_space_read_1((x)->sc_iot, (x)->sc_ioh, (o)) 61 1.5.2.2 he 62 1.5.2.2 he #define dpt_inw(x, o) \ 63 1.5.2.2 he RSWAP16(bus_space_read_2((x)->sc_iot, (x)->sc_ioh, (o))) 64 1.5.2.2 he 65 1.5.2.2 he #define dpt_inl(x, o) \ 66 1.5.2.2 he RSWAP32(bus_space_read_4((x)->sc_iot, (x)->sc_ioh, (o))) 67 1.5.2.2 he 68 1.5.2.2 he #define dpt_outb(x, o, d) \ 69 1.5.2.2 he bus_space_write_1((x)->sc_iot, (x)->sc_ioh, (o), (d)) 70 1.5.2.2 he 71 1.5.2.2 he #define dpt_outw(x, o, d) \ 72 1.5.2.2 he bus_space_write_2((x)->sc_iot, (x)->sc_ioh, (o), RSWAP16(d)) 73 1.5.2.2 he 74 1.5.2.2 he #define dpt_outl(x, o, d) \ 75 1.5.2.2 he bus_space_write_4((x)->sc_iot, (x)->sc_ioh, (o), RSWAP32(d)) 76 1.5.2.2 he 77 1.5.2.2 he #endif /* _KERNEL */ 78 1.5.2.2 he 79 1.5.2.2 he /* 80 1.5.2.2 he * HBA registers 81 1.5.2.2 he */ 82 1.5.2.2 he #define HA_BASE 0x10 83 1.5.2.2 he #define HA_DATA (HA_BASE + 0) 84 1.5.2.2 he #define HA_ERROR (HA_BASE + 1) 85 1.5.2.2 he #define HA_DMA_BASE (HA_BASE + 2) 86 1.5.2.2 he #define HA_ICMD_CODE2 (HA_BASE + 4) 87 1.5.2.2 he #define HA_ICMD_CODE1 (HA_BASE + 5) 88 1.5.2.2 he #define HA_ICMD (HA_BASE + 6) 89 1.5.2.2 he 90 1.5.2.2 he /* EATA commands. There are many more that we don't define or use. */ 91 1.5.2.2 he #define HA_COMMAND (HA_BASE + 7) 92 1.5.2.2 he #define CP_PIO_GETCFG 0xf0 /* Read configuration data, PIO */ 93 1.5.2.2 he #define CP_PIO_CMD 0xf2 /* Execute command, PIO */ 94 1.5.2.2 he #define CP_DMA_GETCFG 0xfd /* Read configuration data, DMA */ 95 1.5.2.2 he #define CP_DMA_CMD 0xff /* Execute command, DMA */ 96 1.5.2.2 he #define CP_PIO_TRUNCATE 0xf4 /* Truncate transfer command, PIO */ 97 1.5.2.2 he #define CP_RESET 0xf9 /* Reset controller and SCSI bus */ 98 1.5.2.2 he #define CP_REBOOT 0x06 /* Reboot controller (last resort) */ 99 1.5.2.2 he #define CP_IMMEDIATE 0xfa /* EATA immediate command */ 100 1.5.2.2 he #define CPI_GEN_ABORT 0x00 /* Generic abort */ 101 1.5.2.2 he #define CPI_SPEC_RESET 0x01 /* Specific reset */ 102 1.5.2.2 he #define CPI_BUS_RESET 0x02 /* Bus reset */ 103 1.5.2.2 he #define CPI_SPEC_ABORT 0x03 /* Specific abort */ 104 1.5.2.2 he #define CPI_QUIET_INTR 0x04 /* ?? */ 105 1.5.2.2 he #define CPI_ROM_DL_EN 0x05 /* ?? */ 106 1.5.2.2 he #define CPI_COLD_BOOT 0x06 /* Cold boot HBA */ 107 1.5.2.2 he #define CPI_FORCE_IO 0x07 /* ?? */ 108 1.5.2.2 he #define CPI_BUS_OFFLINE 0x08 /* Set SCSI bus offline */ 109 1.5.2.2 he #define CPI_RESET_MSKD_BUS 0x09 /* Reset masked bus */ 110 1.5.2.2 he #define CPI_POWEROFF_WARN 0x0a /* Power about to fail */ 111 1.5.2.2 he 112 1.5.2.2 he #define HA_STATUS (HA_BASE + 7) 113 1.5.2.2 he #define HA_ST_ERROR 0x01 114 1.5.2.2 he #define HA_ST_MORE 0x02 115 1.5.2.2 he #define HA_ST_CORRECTD 0x04 116 1.5.2.2 he #define HA_ST_DRQ 0x08 117 1.5.2.2 he #define HA_ST_SEEK_COMPLETE 0x10 118 1.5.2.2 he #define HA_ST_WRT_FLT 0x20 119 1.5.2.2 he #define HA_ST_READY 0x40 120 1.5.2.2 he #define HA_ST_BUSY 0x80 121 1.5.2.2 he #define HA_ST_DATA_RDY (HA_ST_SEEK_COMPLETE|HA_ST_READY|HA_ST_DRQ) 122 1.5.2.2 he 123 1.5.2.2 he #define HA_AUX_STATUS (HA_BASE + 8) 124 1.5.2.2 he #define HA_AUX_BUSY 0x01 125 1.5.2.2 he #define HA_AUX_INTR 0x02 126 1.5.2.2 he 127 1.5.2.2 he /* 128 1.5.2.2 he * Structure of an EATA command packet. 129 1.5.2.2 he */ 130 1.5.2.2 he struct eata_cp { 131 1.5.2.2 he u_int8_t cp_scsireset :1; /* cause a bus reset */ 132 1.5.2.2 he u_int8_t cp_hbainit :1; /* cause HBA to reinitialize */ 133 1.5.2.2 he u_int8_t cp_autosense :1; /* auto request sense on err */ 134 1.5.2.2 he u_int8_t cp_scatter :1; /* doing SG I/O */ 135 1.5.2.2 he u_int8_t cp_quick :1; /* return no status packet */ 136 1.5.2.2 he u_int8_t cp_interpret :1; /* HBA interprets SCSI CDB */ 137 1.5.2.2 he u_int8_t cp_dataout :1; /* data out phase */ 138 1.5.2.2 he u_int8_t cp_datain :1; /* data in phase */ 139 1.5.2.2 he u_int8_t cp_senselen; /* request sense length */ 140 1.5.2.2 he u_int8_t cp_unused0[3]; /* unused */ 141 1.5.2.2 he u_int8_t cp_tophys :1; /* send to RAID component */ 142 1.5.2.2 he u_int8_t cp_unused1 :7; /* unused */ 143 1.5.2.2 he u_int8_t cp_physunit :1; /* phys unit on mirrored pair */ 144 1.5.2.2 he u_int8_t cp_noat :1; /* no address translation */ 145 1.5.2.2 he u_int8_t cp_nocache :1; /* no HBA caching */ 146 1.5.2.2 he u_int8_t cp_unused2 :5; /* unused */ 147 1.5.2.2 he u_int8_t cp_id :5; /* SCSI device id of target */ 148 1.5.2.2 he u_int8_t cp_channel :3; /* SCSI channel id */ 149 1.5.2.2 he u_int8_t cp_lun :3; /* SCSI LUN id */ 150 1.5.2.2 he u_int8_t cp_unused3 :2; /* unused */ 151 1.5.2.2 he u_int8_t cp_luntar :1; /* CP is for target ROUTINE */ 152 1.5.2.2 he u_int8_t cp_dispri :1; /* give disconnect privilege */ 153 1.5.2.2 he u_int8_t cp_identify :1; /* always true */ 154 1.5.2.2 he u_int8_t cp_msg[3]; /* message bytes 0-3 */ 155 1.5.2.2 he 156 1.5.2.2 he /* Partial SCSI CDB ref */ 157 1.5.2.2 he u_int8_t cp_scsi_cmd; 158 1.5.2.2 he u_int8_t cp_extent :1; 159 1.5.2.2 he u_int8_t cp_bytchk :1; 160 1.5.2.2 he u_int8_t cp_reladr :1; 161 1.5.2.2 he u_int8_t cp_cmplst :1; 162 1.5.2.2 he u_int8_t cp_fmtdata :1; 163 1.5.2.2 he u_int8_t cp_cdblun :3; 164 1.5.2.2 he u_int8_t cp_page; 165 1.5.2.2 he u_int8_t cp_unused4; 166 1.5.2.2 he u_int8_t cp_len; 167 1.5.2.2 he u_int8_t cp_link :1; 168 1.5.2.2 he u_int8_t cp_flag :1; 169 1.5.2.2 he u_int8_t cp_unused5 :4; 170 1.5.2.2 he u_int8_t cp_vendor :2; 171 1.5.2.2 he u_int8_t cp_cdbmore[6]; 172 1.5.2.2 he 173 1.5.2.2 he u_int32_t cp_datalen; /* length in bytes of data/SG list */ 174 1.5.2.2 he u_int32_t cp_ccbid; /* ID of software CCB */ 175 1.5.2.2 he u_int32_t cp_dataaddr; /* address of data/SG list */ 176 1.5.2.2 he u_int32_t cp_stataddr; /* addr for status packet */ 177 1.5.2.2 he u_int32_t cp_senseaddr; /* addr of req. sense (err only) */ 178 1.5.2.2 he }; 179 1.5.2.2 he 180 1.5.2.2 he /* 181 1.5.2.2 he * EATA status packet as returned by controller upon command completion. It 182 1.5.2.2 he * contains status, message info and a handle on the initiating CCB. 183 1.5.2.2 he */ 184 1.5.2.2 he struct eata_sp { 185 1.5.2.2 he u_int8_t sp_hba_status; /* host adapter status */ 186 1.5.2.2 he u_int8_t sp_scsi_status; /* SCSI bus status */ 187 1.5.2.2 he u_int8_t sp_reserved[2]; /* reserved */ 188 1.5.2.2 he u_int32_t sp_inv_residue; /* bytes not transfered */ 189 1.5.2.2 he u_int32_t sp_ccbid; /* ID of software CCB */ 190 1.5.2.2 he u_int8_t sp_id_message; 191 1.5.2.2 he u_int8_t sp_que_message; 192 1.5.2.2 he u_int8_t sp_tag_message; 193 1.5.2.2 he u_int8_t sp_messages[9]; 194 1.5.2.2 he }; 195 1.5.2.2 he 196 1.5.2.2 he /* 197 1.5.2.2 he * HBA status as returned by status packet. Bit 7 signals end of command. 198 1.5.2.2 he */ 199 1.5.2.2 he #define HA_NO_ERROR 0x00 /* No error on command */ 200 1.5.2.2 he #define HA_ERROR_SEL_TO 0x01 /* Device selection timeout */ 201 1.5.2.2 he #define HA_ERROR_CMD_TO 0x02 /* Device command timeout */ 202 1.5.2.2 he #define HA_ERROR_RESET 0x03 /* SCSI bus was reset */ 203 1.5.2.2 he #define HA_INIT_POWERUP 0x04 /* Initial controller power up */ 204 1.5.2.2 he #define HA_UNX_BUSPHASE 0x05 /* Unexpected bus phase */ 205 1.5.2.2 he #define HA_UNX_BUS_FREE 0x06 /* Unexpected bus free */ 206 1.5.2.2 he #define HA_BUS_PARITY 0x07 /* SCSI bus parity error */ 207 1.5.2.2 he #define HA_SCSI_HUNG 0x08 /* SCSI bus hung */ 208 1.5.2.2 he #define HA_UNX_MSGRJCT 0x09 /* Unexpected message reject */ 209 1.5.2.2 he #define HA_RESET_STUCK 0x0A /* SCSI bus reset stuck */ 210 1.5.2.2 he #define HA_RSENSE_FAIL 0x0B /* Auto-request sense failed */ 211 1.5.2.2 he #define HA_PARITY 0x0C /* HBA memory parity error */ 212 1.5.2.2 he #define HA_ABORT_NA 0x0D /* CP aborted - not on bus */ 213 1.5.2.2 he #define HA_ABORTED 0x0E /* CP aborted - was on bus */ 214 1.5.2.2 he #define HA_RESET_NA 0x0F /* CP reset - not on bus */ 215 1.5.2.2 he #define HA_RESET 0x10 /* CP reset - was on bus */ 216 1.5.2.2 he #define HA_ECC 0x11 /* HBA memory ECC error */ 217 1.5.2.2 he #define HA_PCI_PARITY 0x12 /* PCI parity error */ 218 1.5.2.2 he #define HA_PCI_MASTER 0x13 /* PCI master abort */ 219 1.5.2.2 he #define HA_PCI_TARGET 0x14 /* PCI target abort */ 220 1.5.2.2 he #define HA_PCI_SIGNAL_TARGET 0x15 /* PCI signalled target abort */ 221 1.5.2.2 he #define HA_ABORT 0x20 /* Software abort (too many retries) */ 222 1.5.2.2 he 223 1.5.2.2 he /* 224 1.5.2.2 he * Scatter-gather list element. 225 1.5.2.2 he */ 226 1.5.2.2 he struct eata_sg { 227 1.5.2.2 he u_int32_t sg_addr; 228 1.5.2.2 he u_int32_t sg_len; 229 1.5.2.2 he }; 230 1.5.2.2 he 231 1.5.2.2 he /* 232 1.5.2.2 he * EATA configuration data as returned by HBA. XXX this is bogus, some fields 233 1.5.2.2 he * don't *seem* to be filled on my SmartCache III. Also, it doesn't sync up 234 1.5.2.2 he * with the structure FreeBSD uses. [ad] 235 1.5.2.2 he */ 236 1.5.2.2 he struct eata_cfg { 237 1.5.2.2 he u_int8_t ec_devtype; 238 1.5.2.2 he u_int8_t ec_pagecode; 239 1.5.2.2 he u_int8_t ec_reserved0; 240 1.5.2.2 he u_int8_t ec_cfglen; /* Length in bytes after this field */ 241 1.5.2.2 he u_int8_t ec_eatasig[4]; /* EATA signature */ 242 1.5.2.2 he u_int8_t ec_eataversion; /* EATA version number */ 243 1.5.2.2 he u_int8_t ec_overlapcmds : 1; /* Overlapped cmds supported */ 244 1.5.2.2 he u_int8_t ec_targetmode : 1; /* Target mode supported */ 245 1.5.2.2 he u_int8_t ec_trunnotrec : 1; /* Truncate cmd not supported */ 246 1.5.2.2 he u_int8_t ec_moresupported:1; /* More cmd supported */ 247 1.5.2.2 he u_int8_t ec_dmasupported : 1; /* DMA mode supported */ 248 1.5.2.2 he u_int8_t ec_dmanumvalid : 1; /* DMA channel field is valid */ 249 1.5.2.2 he u_int8_t ec_atadev : 1; /* This is an ATA device */ 250 1.5.2.2 he u_int8_t ec_hbavalid : 1; /* HBA field is valid */ 251 1.5.2.2 he u_int8_t ec_padlength[2]; /* Pad bytes for PIO cmds */ 252 1.5.2.2 he u_int8_t ec_hba[4]; /* Host adapter SCSI IDs */ 253 1.5.2.2 he u_int8_t ec_cplen[4]; /* Command packet length */ 254 1.5.2.2 he u_int8_t ec_splen[4]; /* Status packet length */ 255 1.5.2.2 he u_int8_t ec_queuedepth[2]; /* Controller queue depth */ 256 1.5.2.2 he u_int8_t ec_reserved1[2]; 257 1.5.2.2 he u_int8_t ec_sglen[2]; /* Maximum scatter gather list size */ 258 1.5.2.2 he u_int8_t ec_irqnum : 4; /* IRQ number */ 259 1.5.2.2 he u_int8_t ec_irqtrigger : 1; /* IRQ trigger: 0 = edge, 1 = level */ 260 1.5.2.2 he u_int8_t ec_secondary : 1; /* Controller not at address 0x170 */ 261 1.5.2.2 he u_int8_t ec_dmanum : 2; /* DMA channel index for ISA */ 262 1.5.2.2 he u_int8_t ec_irq; /* IRQ address */ 263 1.5.2.2 he u_int8_t ec_iodisable : 1; /* ISA I/O address disabled */ 264 1.5.2.2 he u_int8_t ec_forceaddr : 1; /* PCI forced to an EISA/ISA addr */ 265 1.5.2.2 he u_int8_t ec_sg64k : 1; /* 64K of SG space */ 266 1.5.2.2 he u_int8_t ec_sgunaligned : 1; /* Can do unaligned SG, otherwise 4 */ 267 1.5.2.2 he u_int8_t ec_reserved2 : 4; /* Reserved */ 268 1.5.2.2 he u_int8_t ec_maxtarget : 5; /* Maximun SCSI target ID supported */ 269 1.5.2.2 he u_int8_t ec_maxchannel : 3; /* Maximun channel number supported */ 270 1.5.2.2 he u_int8_t ec_maxlun; /* Maximum LUN supported */ 271 1.5.2.2 he u_int8_t ec_reserved3 : 3; /* Reserved field */ 272 1.5.2.2 he u_int8_t ec_autoterm : 1; /* Support auto term (low byte) */ 273 1.5.2.2 he u_int8_t ec_pcim1 : 1; /* PCI M1 chipset */ 274 1.5.2.2 he u_int8_t ec_bogusraidid : 1; /* Raid ID may be questionable */ 275 1.5.2.2 he u_int8_t ec_pci : 1; /* PCI adapter */ 276 1.5.2.2 he u_int8_t ec_eisa : 1; /* EISA adapter */ 277 1.5.2.2 he u_int8_t ec_raidnum; /* RAID host adapter humber */ 278 1.5.2.2 he }; 279 1.5.2.2 he 280 1.5.2.2 he /* 281 1.5.2.2 he * How SCSI inquiry data breaks down for EATA boards. 282 1.5.2.2 he */ 283 1.5.2.2 he struct eata_inquiry_data { 284 1.5.2.2 he u_int8_t ei_device; 285 1.5.2.2 he u_int8_t ei_dev_qual2; 286 1.5.2.2 he u_int8_t ei_version; 287 1.5.2.2 he u_int8_t ei_response_format; 288 1.5.2.2 he u_int8_t ei_additional_length; 289 1.5.2.2 he u_int8_t ei_unused[2]; 290 1.5.2.2 he u_int8_t ei_flags; 291 1.5.2.2 he char ei_vendor[8]; /* Vendor, e.g: DPT, NEC */ 292 1.5.2.2 he char ei_model[7]; /* Model number */ 293 1.5.2.2 he char ei_suffix[9]; /* Model number suffix */ 294 1.5.2.2 he char ei_fw[3]; /* Firmware */ 295 1.5.2.2 he char ei_fwrev[1]; /* Firmware revision */ 296 1.5.2.2 he u_int8_t ei_extra[8]; 297 1.5.2.2 he }; 298 1.5.2.2 he 299 1.5.2.2 he #endif /* !defined _IC_DPTREG_H_ */ 300
Indexes created Mon Oct 27 02:09:54 GMT 2025