dptreg.h revision 1.2
1 /* $NetBSD: dptreg.h,v 1.2 1999/09/29 17:33:02 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Andy Doran <ad (at) NetBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef _IC_DPTREG_H_ 31 #define _IC_DPTREG_H_ 1 32 33 /* Hardware limits */ 34 #define DPT_MAX_TARGETS 16 35 #define DPT_MAX_LUNS 8 36 #define DPT_MAX_CHANNELS 3 37 38 /* Software parameters */ 39 #define DPT_MAX_XFER ((DPT_SG_SIZE - 1) << PGSHIFT) 40 #define DPT_MAX_CCBS 256 41 #define DPT_SG_SIZE 64 42 #define DPT_ABORT_TIMEOUT 2000 43 44 #ifdef _KERNEL 45 46 #if BYTE_ORDER == LITTLE_ENDIAN 47 #define SWAP32(x) bswap32((x)) 48 #define SWAP16(x) bswap16((x)) 49 #define RSWAP32(x) (x) 50 #define RSWAP16(x) (x) 51 #else 52 #define SWAP32(x) (x) 53 #define SWAP16(x) (x) 54 #define RSWAP32(x) bswap32((x)) 55 #define RSWAP16(x) bswap16((x)) 56 #endif 57 58 #define dpt_inb(x, o) \ 59 bus_space_read_1((x)->sc_iot, (x)->sc_ioh, (o)) 60 61 #define dpt_inw(x, o) \ 62 RSWAP16(bus_space_read_2((x)->sc_iot, (x)->sc_ioh, (o))) 63 64 #define dpt_inl(x, o) \ 65 RSWAP32(bus_space_read_4((x)->sc_iot, (x)->sc_ioh, (o))) 66 67 #define dpt_outb(x, o, d) \ 68 bus_space_write_1((x)->sc_iot, (x)->sc_ioh, (o), (d)) 69 70 #define dpt_outw(x, o, d) \ 71 bus_space_write_2((x)->sc_iot, (x)->sc_ioh, (o), RSWAP16(d)) 72 73 #define dpt_outl(x, o, d) \ 74 bus_space_write_4((x)->sc_iot, (x)->sc_ioh, (o), RSWAP32(d)) 75 76 #endif /* _KERNEL */ 77 78 /* 79 * HBA registers 80 */ 81 #define HA_BASE 0x10 82 #define HA_DATA (HA_BASE + 0) 83 #define HA_ERROR (HA_BASE + 1) 84 #define HA_DMA_BASE (HA_BASE + 2) 85 #define HA_ICMD_CODE2 (HA_BASE + 4) 86 #define HA_ICMD_CODE1 (HA_BASE + 5) 87 #define HA_ICMD (HA_BASE + 6) 88 89 /* EATA commands. There are many more the we don't define or use. */ 90 #define HA_COMMAND (HA_BASE + 7) 91 #define CP_PIO_GETCFG 0xf0 /* Read configuration data, PIO */ 92 #define CP_PIO_CMD 0xf2 /* Execute command, PIO */ 93 #define CP_DMA_GETCFG 0xfd /* Read configuration data, DMA */ 94 #define CP_DMA_CMD 0xff /* Execute command, DMA */ 95 #define CP_PIO_TRUNCATE 0xf4 /* Truncate transfer command, PIO */ 96 #define CP_RESET 0xf9 /* Reset controller and SCSI bus */ 97 #define CP_REBOOT 0x06 /* Reboot controller (last resort) */ 98 #define CP_IMMEDIATE 0xfa /* EATA immediate command */ 99 #define CPI_GEN_ABORT 0x00 /* Generic abort */ 100 #define CPI_SPEC_RESET 0x01 /* Specific reset */ 101 #define CPI_BUS_RESET 0x02 /* Bus reset */ 102 #define CPI_SPEC_ABORT 0x03 /* Specific abort */ 103 #define CPI_QUIET_INTR 0x04 /* ?? */ 104 #define CPI_ROM_DL_EN 0x05 /* ?? */ 105 #define CPI_COLD_BOOT 0x06 /* Cold boot HBA */ 106 #define CPI_FORCE_IO 0x07 /* ?? */ 107 #define CPI_BUS_OFFLINE 0x08 /* Set SCSI bus offline */ 108 #define CPI_RESET_MSKD_BUS 0x09 /* Reset masked bus */ 109 #define CPI_POWEROFF_WARN 0x0a /* Power about to fail */ 110 111 #define HA_STATUS (HA_BASE + 7) 112 #define HA_ST_ERROR 0x01 113 #define HA_ST_INDEX 0x02 114 #define HA_ST_CORRECTD 0x04 115 #define HA_ST_DRQ 0x08 116 #define HA_ST_SEEK_COMPLETE 0x10 117 #define HA_ST_WRT_FLT 0x20 118 #define HA_ST_READY 0x40 119 #define HA_ST_BUSY 0x80 120 #define HA_ST_DATA_RDY (HA_ST_SEEK_COMPLETE|HA_ST_READY|HA_ST_DRQ) 121 122 #define HA_AUX_STATUS (HA_BASE + 8) 123 #define HA_AUX_BUSY 0x01 124 #define HA_AUX_INTR 0x02 125 126 /* 127 * Structure of an EATA command packet. 128 */ 129 struct eata_cp { 130 u_int8_t cp_scsireset :1; /* cause a bus reset */ 131 u_int8_t cp_hbainit :1; /* cause HBA to reinitialize */ 132 u_int8_t cp_autosense :1; /* auto request sense on err */ 133 u_int8_t cp_scatter :1; /* doing SG I/O */ 134 u_int8_t cp_quick :1; /* return no status packet */ 135 u_int8_t cp_interpret :1; /* HBA interprets SCSI CDB */ 136 u_int8_t cp_dataout :1; /* data out phase */ 137 u_int8_t cp_datain :1; /* data in phase */ 138 u_int8_t cp_senselen; /* request sense length */ 139 u_int8_t cp_unused0[3]; /* unused */ 140 u_int8_t cp_tophys :1; /* send to RAID component */ 141 u_int8_t cp_unused1 :7; /* unused */ 142 u_int8_t cp_physunit :1; /* phys unit on mirrored pair */ 143 u_int8_t cp_noat :1; /* no address translation */ 144 u_int8_t cp_nocache :1; /* no HBA caching */ 145 u_int8_t cp_unused2 :5; /* unused */ 146 u_int8_t cp_id :5; /* SCSI device id of target */ 147 u_int8_t cp_channel :3; /* SCSI channel id */ 148 u_int8_t cp_lun :3; /* SCSI LUN id */ 149 u_int8_t cp_unused3 :2; /* unused */ 150 u_int8_t cp_luntar :1; /* CP is for target ROUTINE */ 151 u_int8_t cp_dispri :1; /* give disconnect privilege */ 152 u_int8_t cp_identify :1; /* always true */ 153 u_int8_t cp_msg[3]; /* message bytes 0-3 */ 154 155 /* Partial SCSI CDB ref */ 156 u_int8_t cp_scsi_cmd; 157 u_int8_t cp_extent :1; 158 u_int8_t cp_bytchk :1; 159 u_int8_t cp_reladr :1; 160 u_int8_t cp_cmplst :1; 161 u_int8_t cp_fmtdata :1; 162 u_int8_t cp_cdblun :3; 163 u_int8_t cp_page; 164 u_int8_t cp_unused4; 165 u_int8_t cp_len; 166 u_int8_t cp_link :1; 167 u_int8_t cp_flag :1; 168 u_int8_t cp_unused5 :4; 169 u_int8_t cp_vendor :2; 170 u_int8_t cp_cdbmore[6]; 171 172 u_int32_t cp_datalen; /* length in bytes of data/SG list */ 173 u_int32_t cp_ccbid; /* ID of software CCB */ 174 u_int32_t cp_dataaddr; /* address of data/SG list */ 175 u_int32_t cp_stataddr; /* addr for status packet */ 176 u_int32_t cp_senseaddr; /* addr of req. sense (err only) */ 177 }; 178 179 /* 180 * EATA status packet as returned by controller upon command completion. It 181 * contains status, message info and a handle on the initiating CCB. 182 */ 183 struct eata_sp { 184 u_int8_t sp_hba_status : 7; /* host adapter status */ 185 u_int8_t sp_eoc : 1; /* end of command (unsafe) */ 186 u_int8_t sp_scsi_status; /* SCSI bus status */ 187 u_int8_t sp_reserved[2]; /* reserved */ 188 u_int32_t sp_inv_residue; /* bytes not transfered */ 189 u_int32_t sp_ccbid; /* ID of software CCB */ 190 u_int8_t sp_id_message; 191 u_int8_t sp_que_message; 192 u_int8_t sp_tag_message; 193 u_int8_t sp_messages[9]; 194 }; 195 196 /* HBA status as returned by status packet */ 197 #define HA_NO_ERROR 0x00 /* No error on command */ 198 #define HA_ERROR_SEL_TO 0x01 /* Device selection timeout */ 199 #define HA_ERROR_CMD_TO 0x02 /* Device command timeout */ 200 #define HA_ERROR_RESET 0x03 /* SCSI bus was reset */ 201 #define HA_INIT_POWERUP 0x04 /* Initial controller power up */ 202 #define HA_UNX_BUSPHASE 0x05 /* Unexpected bus phase */ 203 #define HA_UNX_BUS_FREE 0x06 /* Unexpected bus free */ 204 #define HA_BUS_PARITY 0x07 /* SCSI bus parity error */ 205 #define HA_SCSI_HUNG 0x08 /* SCSI bus hung */ 206 #define HA_UNX_MSGRJCT 0x09 /* Unexpected message reject */ 207 #define HA_RESET_STUCK 0x0A /* SCSI bus reset stuck */ 208 #define HA_RSENSE_FAIL 0x0B /* Auto-request sense failed */ 209 #define HA_PARITY 0x0C /* HBA memory parity error */ 210 #define HA_ABORT_NA 0x0D /* CP aborted - not on bus */ 211 #define HA_ABORTED 0x0E /* CP aborted - was on bus */ 212 #define HA_RESET_NA 0x0F /* CP reset - not on bus */ 213 #define HA_RESET 0x10 /* CP reset - was on bus */ 214 #define HA_ECC 0x11 /* HBA memory ECC error */ 215 #define HA_PCI_PARITY 0x12 /* PCI parity error */ 216 #define HA_PCI_MASTER 0x13 /* PCI master abort */ 217 #define HA_PCI_TARGET 0x14 /* PCI target abort */ 218 #define HA_PCI_SIGNAL_TARGET 0x15 /* PCI signalled target abort */ 219 #define HA_ABORT 0x20 /* Software abort (too many retries) */ 220 221 /* 222 * Scatter-gather list element. 223 */ 224 struct eata_sg { 225 u_int32_t sg_addr; 226 u_int32_t sg_len; 227 }; 228 229 /* 230 * EATA configuration data as returned by HBA. XXX this is bogus, some fields 231 * don't *seem* to be filled on my SmartCache III. Also, it doesn't sync up 232 * with the structure FreeBSD uses. [ad] 233 */ 234 struct eata_cfg { 235 u_int8_t ec_devtype; 236 u_int8_t ec_pagecode; 237 u_int8_t ec_reserved0; 238 u_int8_t ec_cfglen; /* Length in bytes after this field */ 239 u_int8_t ec_eatasig[4]; /* EATA signature */ 240 u_int8_t ec_eataversion; /* EATA version number */ 241 u_int8_t ec_overlapcmds : 1; /* Overlapped cmds supported */ 242 u_int8_t ec_targetmode : 1; /* Target mode supported */ 243 u_int8_t ec_trunnotrec : 1; /* Truncate cmd not supported */ 244 u_int8_t ec_moresupported:1; /* More cmd supported */ 245 u_int8_t ec_dmasupported : 1; /* DMA mode supported */ 246 u_int8_t ec_dmanumvalid : 1; /* DMA channel field is valid */ 247 u_int8_t ec_atadev : 1; /* This is an ATA device */ 248 u_int8_t ec_hbavalid : 1; /* HBA field is valid */ 249 u_int8_t ec_padlength[2]; /* Pad bytes for PIO cmds */ 250 u_int8_t ec_hba[4]; /* Host adapter SCSI IDs */ 251 u_int8_t ec_cplen[4]; /* Command packet length */ 252 u_int8_t ec_splen[4]; /* Status packet length */ 253 u_int8_t ec_queuedepth[2]; /* Controller queue depth */ 254 u_int8_t ec_reserved1[2]; 255 u_int8_t ec_sglen[2]; /* Maximum scatter gather list size */ 256 u_int8_t ec_irqnum : 4; /* IRQ number */ 257 u_int8_t ec_irqtrigger : 1; /* IRQ trigger: 0 = edge, 1 = level */ 258 u_int8_t ec_secondary : 1; /* Controller not at address 0x170 */ 259 u_int8_t ec_dmanum : 2; /* DMA channel index for ISA */ 260 u_int8_t ec_irq; /* IRQ address */ 261 u_int8_t ec_iodisable : 1; /* ISA I/O address disabled */ 262 u_int8_t ec_forceaddr : 1; /* PCI forced to an EISA/ISA addr */ 263 u_int8_t ec_sg64k : 1; /* 64K of SG space */ 264 u_int8_t ec_sgunaligned : 1; /* Can do unaligned SG, otherwise 4 */ 265 u_int8_t ec_reserved2 : 4; /* Reserved */ 266 u_int8_t ec_maxtarget : 5; /* Maximun SCSI target ID supported */ 267 u_int8_t ec_maxchannel : 3; /* Maximun channel number supported */ 268 u_int8_t ec_maxlun; /* Maximum LUN supported */ 269 u_int8_t ec_reserved3 : 3; /* Reserved field */ 270 u_int8_t ec_autoterm : 1; /* Support auto term (low byte) */ 271 u_int8_t ec_pcim1 : 1; /* PCI M1 chipset */ 272 u_int8_t ec_bogusraidid : 1; /* Raid ID may be questionable */ 273 u_int8_t ec_pci : 1; /* PCI adapter */ 274 u_int8_t ec_eisa : 1; /* EISA adapter */ 275 u_int8_t ec_raidnum; /* RAID host adapter humber */ 276 }; 277 278 /* 279 * How SCSI inquiry data breaks down for EATA boards. 280 */ 281 struct eata_inquiry_data { 282 u_int8_t ei_device; 283 u_int8_t ei_dev_qual2; 284 u_int8_t ei_version; 285 u_int8_t ei_response_format; 286 u_int8_t ei_additional_length; 287 u_int8_t ei_unused[2]; 288 u_int8_t ei_flags; 289 char ei_vendor[8]; /* Vendor, e.g: DPT, NEC */ 290 char ei_model[7]; /* Model number */ 291 char ei_suffix[9]; /* Model number suffix */ 292 char ei_fw[3]; /* Firmware */ 293 char ei_fwrev[1]; /* Firmware revision */ 294 u_int8_t ei_extra[8]; 295 }; 296 297 #endif /* !defined _IC_DPTREG_H_ */ 298
Indexes created Sun Sep 28 16:09:52 GMT 2025