dptreg.h revision 1.7
1 /* $NetBSD: dptreg.h,v 1.7 2000/02/24 18:47:55 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Andy Doran <ad (at) NetBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef _IC_DPTREG_H_ 31 #define _IC_DPTREG_H_ 1 32 33 /* Hardware limits */ 34 #define DPT_MAX_TARGETS 16 35 #define DPT_MAX_LUNS 8 36 #define DPT_MAX_CHANNELS 3 37 38 /* Software parameters */ 39 #define DPT_MAX_XFER ((DPT_SG_SIZE - 1) << PGSHIFT) 40 #define DPT_MAX_CCBS 256 41 #define DPT_SG_SIZE 64 42 #define DPT_ABORT_TIMEOUT 2000 /* milliseconds */ 43 #define DPT_MORE_TIMEOUT 1000 /* microseconds */ 44 #define DPT_SCRATCH_SIZE 256 /* bytes */ 45 46 #ifdef _KERNEL 47 48 #define dpt_inb(x, o) \ 49 bus_space_read_1((x)->sc_iot, (x)->sc_ioh, (o)) 50 #define dpt_inw(x, o) \ 51 le16toh(bus_space_read_2((x)->sc_iot, (x)->sc_ioh, (o))) 52 #define dpt_inl(x, o) \ 53 le32toh(bus_space_read_4((x)->sc_iot, (x)->sc_ioh, (o))) 54 55 #define dpt_outb(x, o, d) \ 56 bus_space_write_1((x)->sc_iot, (x)->sc_ioh, (o), (d)) 57 #define dpt_outw(x, o, d) \ 58 bus_space_write_2((x)->sc_iot, (x)->sc_ioh, (o), htole16(d)) 59 #define dpt_outl(x, o, d) \ 60 bus_space_write_4((x)->sc_iot, (x)->sc_ioh, (o), htole32(d)) 61 62 #endif /* _KERNEL */ 63 64 /* 65 * HBA registers 66 */ 67 #define HA_DATA 0 68 #define HA_ERROR 1 69 #define HA_DMA_BASE 2 70 #define HA_ICMD_CODE2 4 71 #define HA_ICMD_CODE1 5 72 #define HA_ICMD 6 73 74 /* EATA commands. There are many more that we don't define or use. */ 75 #define HA_COMMAND 7 76 #define CP_PIO_GETCFG 0xf0 /* Read configuration data, PIO */ 77 #define CP_PIO_CMD 0xf2 /* Execute command, PIO */ 78 #define CP_DMA_GETCFG 0xfd /* Read configuration data, DMA */ 79 #define CP_DMA_CMD 0xff /* Execute command, DMA */ 80 #define CP_PIO_TRUNCATE 0xf4 /* Truncate transfer command, PIO */ 81 #define CP_RESET 0xf9 /* Reset controller and SCSI bus */ 82 #define CP_REBOOT 0x06 /* Reboot controller (last resort) */ 83 #define CP_IMMEDIATE 0xfa /* EATA immediate command */ 84 #define CPI_GEN_ABORT 0x00 /* Generic abort */ 85 #define CPI_SPEC_RESET 0x01 /* Specific reset */ 86 #define CPI_BUS_RESET 0x02 /* Bus reset */ 87 #define CPI_SPEC_ABORT 0x03 /* Specific abort */ 88 #define CPI_QUIET_INTR 0x04 /* ?? */ 89 #define CPI_ROM_DL_EN 0x05 /* ?? */ 90 #define CPI_COLD_BOOT 0x06 /* Cold boot HBA */ 91 #define CPI_FORCE_IO 0x07 /* ?? */ 92 #define CPI_BUS_OFFLINE 0x08 /* Set SCSI bus offline */ 93 #define CPI_RESET_MSKD_BUS 0x09 /* Reset masked bus */ 94 #define CPI_POWEROFF_WARN 0x0a /* Power about to fail */ 95 96 #define HA_STATUS 7 97 #define HA_ST_ERROR 0x01 98 #define HA_ST_MORE 0x02 99 #define HA_ST_CORRECTD 0x04 100 #define HA_ST_DRQ 0x08 101 #define HA_ST_SEEK_COMPLETE 0x10 102 #define HA_ST_WRT_FLT 0x20 103 #define HA_ST_READY 0x40 104 #define HA_ST_BUSY 0x80 105 #define HA_ST_DATA_RDY (HA_ST_SEEK_COMPLETE|HA_ST_READY|HA_ST_DRQ) 106 107 #define HA_AUX_STATUS 8 108 #define HA_AUX_BUSY 0x01 109 #define HA_AUX_INTR 0x02 110 111 /* 112 * Structure of an EATA command packet. 113 */ 114 struct eata_cp { 115 u_int8_t cp_ctl0; /* Control flags 0 */ 116 u_int8_t cp_senselen; /* Request sense length */ 117 u_int8_t cp_unused0[3]; /* Unused */ 118 u_int8_t cp_ctl1; /* Control flags 1 */ 119 u_int8_t cp_ctl2; /* Control flags 2 */ 120 u_int8_t cp_ctl3; /* Control flags 3 */ 121 u_int8_t cp_ctl4; /* Control flags 4 */ 122 u_int8_t cp_msg[3]; /* Message bytes 0-3 */ 123 u_int8_t cp_cdb_cmd; /* SCSI CDB */ 124 u_int8_t cp_cdb_more0[3]; /* SCSI CDB */ 125 u_int8_t cp_cdb_len; /* SCSI CDB */ 126 u_int8_t cp_cdb_more1[7]; /* SCSI CDB */ 127 u_int32_t cp_datalen; /* Bytes of data/SG list */ 128 u_int32_t cp_ccbid; /* ID of software CCB */ 129 u_int32_t cp_dataaddr; /* Addr of data/SG list */ 130 u_int32_t cp_stataddr; /* Addr of status packet */ 131 u_int32_t cp_senseaddr; /* Addr of req. sense */ 132 }; 133 134 #define CP_C0_SCSI_RESET 0x01 /* Cause a bus reset */ 135 #define CP_C0_HBA_INIT 0x02 /* Reinitialize HBA */ 136 #define CP_C0_AUTO_SENSE 0x04 /* Auto request sense on error */ 137 #define CP_C0_SCATTER 0x08 /* Do scatter/gather I/O */ 138 #define CP_C0_QUICK 0x10 /* Return no status packet */ 139 #define CP_C0_INTERPRET 0x20 /* HBA interprets SCSI CDB */ 140 #define CP_C0_DATA_OUT 0x40 /* Data out phase */ 141 #define CP_C0_DATA_IN 0x80 /* Data in phase */ 142 143 #define CP_C1_TO_PHYS 0x01 /* Send to RAID component */ 144 #define CP_C1_RESERVED 0xfe 145 146 #define CP_C2_PHYS_UNIT 0x01 /* Physical unit on mirrored pair */ 147 #define CP_C2_NO_AT 0x02 /* No address translation */ 148 #define CP_C2_NO_CACHE 0x04 /* No HBA caching */ 149 #define CP_C2_RESERVED 0xf8 150 151 #define CP_C3_ID_MASK 0x1f /* Target ID */ 152 #define CP_C3_ID_SHIFT 0 153 #define CP_C3_CHANNEL_MASK 0xe0 /* Target channel */ 154 #define CP_C3_CHANNEL_SHIFT 5 155 156 #define CP_C4_LUN_MASK 0x07 /* Target LUN */ 157 #define CP_C4_LUN_SHIFT 0 158 #define CP_C4_RESERVED 0x18 159 #define CP_C4_LUN_TAR 0x20 /* CP is for target ROUTINE */ 160 #define CP_C4_DIS_PRI 0x40 /* Give disconnect privilege */ 161 #define CP_C4_IDENTIFY 0x80 /* Always true */ 162 163 /* 164 * EATA status packet as returned by controller upon command completion. It 165 * contains status, message info and a handle on the initiating CCB. 166 */ 167 struct eata_sp { 168 u_int8_t sp_hba_status; /* Host adapter status */ 169 u_int8_t sp_scsi_status; /* SCSI bus status */ 170 u_int8_t sp_reserved[2]; /* Reserved */ 171 u_int32_t sp_inv_residue; /* Bytes not transfered */ 172 u_int32_t sp_ccbid; /* ID of software CCB */ 173 u_int8_t sp_id_message; 174 u_int8_t sp_que_message; 175 u_int8_t sp_tag_message; 176 u_int8_t sp_messages[9]; 177 }; 178 179 /* 180 * HBA status as returned by status packet. Bit 7 signals end of command. 181 */ 182 #define SP_HBA_NO_ERROR 0x00 /* No error on command */ 183 #define SP_HBA_ERROR_SEL_TO 0x01 /* Device selection timeout */ 184 #define SP_HBA_ERROR_CMD_TO 0x02 /* Device command timeout */ 185 #define SP_HBA_ERROR_RESET 0x03 /* SCSI bus was reset */ 186 #define SP_HBA_INIT_POWERUP 0x04 /* Initial controller power up */ 187 #define SP_HBA_UNX_BUSPHASE 0x05 /* Unexpected bus phase */ 188 #define SP_HBA_UNX_BUS_FREE 0x06 /* Unexpected bus free */ 189 #define SP_HBA_BUS_PARITY 0x07 /* SCSI bus parity error */ 190 #define SP_HBA_SCSI_HUNG 0x08 /* SCSI bus hung */ 191 #define SP_HBA_UNX_MSGRJCT 0x09 /* Unexpected message reject */ 192 #define SP_HBA_RESET_STUCK 0x0a /* SCSI bus reset stuck */ 193 #define SP_HBA_RSENSE_FAIL 0x0b /* Auto-request sense failed */ 194 #define SP_HBA_PARITY 0x0c /* HBA memory parity error */ 195 #define SP_HBA_ABORT_NA 0x0d /* CP aborted - not on bus */ 196 #define SP_HBA_ABORTED 0x0e /* CP aborted - was on bus */ 197 #define SP_HBA_RESET_NA 0x0f /* CP reset - not on bus */ 198 #define SP_HBA_RESET 0x10 /* CP reset - was on bus */ 199 #define SP_HBA_ECC 0x11 /* HBA memory ECC error */ 200 #define SP_HBA_PCI_PARITY 0x12 /* PCI parity error */ 201 #define SP_HBA_PCI_MASTER 0x13 /* PCI master abort */ 202 #define SP_HBA_PCI_TARGET 0x14 /* PCI target abort */ 203 #define SP_HBA_PCI_SIG_TARGET 0x15 /* PCI signalled target abort */ 204 #define SP_HBA_ABORT 0x20 /* Software abort (too many retries) */ 205 206 /* 207 * Scatter-gather list element. 208 */ 209 struct eata_sg { 210 u_int32_t sg_addr; 211 u_int32_t sg_len; 212 }; 213 214 /* 215 * EATA configuration data as returned by HBA. XXX this is bogus - it 216 * doesn't sync up with the structure FreeBSD uses. [ad] 217 */ 218 struct eata_cfg { 219 u_int8_t ec_devtype; 220 u_int8_t ec_pagecode; 221 u_int8_t ec_reserved0; 222 u_int8_t ec_cfglen; /* Length in bytes past here */ 223 u_int8_t ec_eatasig[4]; /* EATA signature */ 224 u_int8_t ec_eataversion; /* EATA version number */ 225 u_int8_t ec_feat0; /* First feature byte */ 226 u_int8_t ec_padlength[2]; /* Pad bytes for PIO cmds */ 227 u_int8_t ec_hba[4]; /* Host adapter SCSI IDs */ 228 u_int8_t ec_cplen[4]; /* Command packet length */ 229 u_int8_t ec_splen[4]; /* Status packet length */ 230 u_int8_t ec_queuedepth[2]; /* Controller queue depth */ 231 u_int8_t ec_reserved1[2]; 232 u_int8_t ec_sglen[2]; /* Maximum s/g list size */ 233 u_int8_t ec_feat1; /* 2nd feature byte */ 234 u_int8_t ec_irq; /* IRQ address */ 235 u_int8_t ec_feat2; /* 3rd feature byte */ 236 u_int8_t ec_feat3; /* 4th feature byte */ 237 u_int8_t ec_maxlun; /* Maximum LUN supported */ 238 u_int8_t ec_feat4; /* 5th feature byte */ 239 u_int8_t ec_raidnum; /* RAID host adapter humber */ 240 }; 241 242 #define EC_F0_OVERLAP_CMDS 0x01 /* Overlapped cmds supported */ 243 #define EC_F0_TARGET_MODE 0x02 /* Target mode supported */ 244 #define EC_F0_TRUNC_NOT_REC 0x04 /* Truncate cmd not supported */ 245 #define EC_F0_MORE_SUPPORTED 0x08 /* More cmd supported */ 246 #define EC_F0_DMA_SUPPORTED 0x10 /* DMA mode supported */ 247 #define EC_F0_DMA_NUM_VALID 0x20 /* DMA channel field is valid */ 248 #define EC_F0_ATA_DEV 0x40 /* This is an ATA device */ 249 #define EC_F0_HBA_VALID 0x80 /* HBA field is valid */ 250 251 #define EC_F1_IRQ_NUM_MASK 0x0f /* IRQ number mask */ 252 #define EC_F1_IRQ_NUM_SHIFT 0 253 #define EC_F1_IRQ_TRIGGER 0x10 /* IRQ trigger: 0 = edge, 1 = level */ 254 #define EC_F1_SECONDARY 0x20 /* Controller not at address 0x170 */ 255 #define EC_F1_DMA_NUM_MASK 0xc0 /* DMA channel *index* for ISA */ 256 #define EC_F1_DMA_NUM_SHIFT 6 257 258 #define EC_F2_ISA_IO_DISABLE 0x01 /* ISA I/O address disabled */ 259 #define EC_F2_FORCE_ADDR 0x02 /* HBA forced to EISA/ISA address */ 260 #define EC_F2_SG_64K 0x04 /* 64kB of scatter/gather space */ 261 #define EC_F2_SG_UNALIGNED 0x08 /* Can do unaligned scatter/gather */ 262 #define EC_F2_RESERVED0 0x10 /* Reserved */ 263 #define EC_F2_RESERVED1 0x20 /* Reserved */ 264 #define EC_F2_RESERVED2 0x40 /* Reserved */ 265 #define EC_F2_RESERVED3 0x40 /* Reserved */ 266 267 #define EC_F3_MAX_TARGET_MASK 0x1f /* Maximum target ID supported */ 268 #define EC_F3_MAX_TARGET_SHIFT 0 269 #define EC_F3_MAX_CHANNEL_MASK 0xe0 /* Maximum channel ID supported */ 270 #define EC_F3_MAX_CHANNEL_SHIFT 5 271 272 #define EC_F4_RESERVED0 0x01 /* Reserved */ 273 #define EC_F4_RESERVED1 0x02 /* Reserved */ 274 #define EC_F4_RESERVED2 0x04 /* Reserved */ 275 #define EC_F4_AUTO_TERM 0x08 /* Supports auto termination */ 276 #define EC_F4_PCIM1 0x10 /* PCI M1 chipset */ 277 #define EC_F4_BOGUS_RAID_ID 0x20 /* RAID ID may be questionable */ 278 #define EC_F4_HBA_PCI 0x40 /* PCI adapter */ 279 #define EC_F4_HBA_EISA 0x80 /* EISA adapter */ 280 281 /* 282 * How SCSI inquiry data breaks down for EATA boards. 283 */ 284 struct eata_inquiry_data { 285 u_int8_t ei_device; 286 u_int8_t ei_dev_qual2; 287 u_int8_t ei_version; 288 u_int8_t ei_response_format; 289 u_int8_t ei_additional_length; 290 u_int8_t ei_unused[2]; 291 u_int8_t ei_flags; 292 char ei_vendor[8]; /* Vendor, e.g: DPT, NEC */ 293 char ei_model[7]; /* Model number */ 294 char ei_suffix[9]; /* Model number suffix */ 295 char ei_fw[3]; /* Firmware */ 296 char ei_fwrev[1]; /* Firmware revision */ 297 u_int8_t ei_extra[8]; 298 }; 299 300 #endif /* !defined _IC_DPTREG_H_ */ 301
Indexes created Sun Sep 28 16:09:52 GMT 2025