ds1687reg.h revision 1.13 1 1.13 andvar /* $NetBSD: ds1687reg.h,v 1.13 2022/05/20 19:34:22 andvar Exp $ */
2 1.1 rafal
3 1.1 rafal /*
4 1.1 rafal * Copyright (c) 2003 The NetBSD Foundation, Inc.
5 1.1 rafal * All rights reserved.
6 1.1 rafal *
7 1.1 rafal * This code is derived from software contributed to The NetBSD Foundation
8 1.1 rafal * by Rafal K. Boni.
9 1.7 perry *
10 1.1 rafal * Redistribution and use in source and binary forms, with or without
11 1.1 rafal * modification, are permitted provided that the following conditions
12 1.1 rafal * are met:
13 1.1 rafal * 1. Redistributions of source code must retain the above copyright
14 1.1 rafal * notice, this list of conditions and the following disclaimer.
15 1.1 rafal * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 rafal * notice, this list of conditions and the following disclaimer in the
17 1.1 rafal * documentation and/or other materials provided with the distribution.
18 1.10 martin *
19 1.10 martin * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.10 martin * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.10 martin * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.10 martin * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.10 martin * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.10 martin * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.10 martin * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.10 martin * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.10 martin * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.10 martin * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.10 martin * POSSIBILITY OF SUCH DAMAGE.
30 1.2 rafal */
31 1.2 rafal
32 1.2 rafal /*
33 1.2 rafal * Originally based on mc146818reg.h, with the following license:
34 1.2 rafal *
35 1.2 rafal * Copyright (c) 1995 Carnegie-Mellon University.
36 1.2 rafal * All rights reserved.
37 1.7 perry *
38 1.2 rafal * Permission to use, copy, modify and distribute this software and
39 1.2 rafal * its documentation is hereby granted, provided that both the copyright
40 1.2 rafal * notice and this permission notice appear in all copies of the
41 1.2 rafal * software, derivative works or modified versions, and any portions
42 1.2 rafal * thereof, and that both notices appear in supporting documentation.
43 1.7 perry *
44 1.7 perry * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
45 1.7 perry * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
46 1.2 rafal * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
47 1.7 perry *
48 1.2 rafal * Carnegie Mellon requests users of this software to return to
49 1.2 rafal *
50 1.2 rafal * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
51 1.2 rafal * School of Computer Science
52 1.2 rafal * Carnegie Mellon University
53 1.2 rafal * Pittsburgh PA 15213-3890
54 1.2 rafal *
55 1.2 rafal * any improvements or extensions that they make and grant Carnegie the
56 1.2 rafal * rights to redistribute these changes.
57 1.1 rafal */
58 1.1 rafal
59 1.1 rafal /*
60 1.1 rafal * Definitions for the Dallas Semiconductor DS1687 Real Time Clock.
61 1.1 rafal *
62 1.1 rafal * The DS1687 and follow-on RTC chips are Y2k-compliant successors to the
63 1.1 rafal * DS1287, which in turn is register-compatible with the MC146818 and/or
64 1.1 rafal * MC146818A RTCs.
65 1.1 rafal *
66 1.12 andvar * Plucked right from the Dallas Semiconductor specs available at:
67 1.1 rafal * http://pdfserv.maxim-ic.com/arpdf/DS1685-DS1687.pdf
68 1.1 rafal *
69 1.1 rafal * The DS1686 contains 14 basic clock-related registers and 50 bytes of
70 1.1 rafal * user RAM laid out for compatibility with the register layout of the
71 1.1 rafal * DS1287/MC14818 chips. It also includes an extended mode which allows
72 1.11 msaitoh * access to these same basic registers as well an extended register
73 1.1 rafal * set and NVRAM area; this extended register set includes a century
74 1.1 rafal * register for Y2k compliant date storage.
75 1.1 rafal *
76 1.1 rafal * Since the locations of these ports and the method used to access them
77 1.1 rafal * can be machine-dependent, the low-level details of reading and writing
78 1.1 rafal * writing the RTC's registers are handled by machine-specific functions.
79 1.1 rafal *
80 1.1 rafal * The Dallas chip can store time-of-day and alarm data in BCD or binary;
81 1.1 rafal * this setting applies to *all* values stored in the clock chip and a
82 1.1 rafal * change from one mode to the other requires *all* of the clock data to
83 1.1 rafal * be re-written. The "hours" time-of-year and alarm registers can be
84 1.1 rafal * stored either in an AM/PM or a 24-hour format; the format is set
85 1.1 rafal * globally and changing it requires re-writing both the hours time-of-
86 1.1 rafal * year and alarm registers. In AM/PM mode, the hour must be in the
87 1.1 rafal * range of 1-12 (and stored as either BCD or binary), with the high-
88 1.1 rafal * bit cleared to indicate AM and set to indicate PM. In 24-hour mode,
89 1.1 rafal * hours must be in the range 0-23.
90 1.1 rafal *
91 1.7 perry * In order to support extended features like the century register and
92 1.1 rafal * an embedded silicon serial number while keeping backwards compatibility
93 1.1 rafal * with the DS1287/MC146818, the DS1687 provides a bank-switching method
94 1.1 rafal * which allows the user to switch the RTC between a "compatible" mode in
95 1.1 rafal * bank 0 and an extended mode in bank 1.
96 1.1 rafal *
97 1.1 rafal * Both banks provide access to the 14 timekeeping/alarm registers and
98 1.1 rafal * to 50 bytes of user RAM. In addition, bank 0 provides access to an
99 1.1 rafal * additional 64 bytes of user RAM in the upper half of the RTC address
100 1.1 rafal * space.
101 1.7 perry *
102 1.1 rafal * Bank 1, on the other hand, provides access to an extended register set,
103 1.1 rafal * including a silicon serial number -- including a model ID byte, century
104 1.1 rafal * register for Y2k compatibility and memory address/data registers which
105 1.1 rafal * allow indirect access to a larger extended user RAM address space. It
106 1.1 rafal * is worth noting that the extended user RAM is distinct from the "basic"
107 1.12 andvar * 114 bytes of user RAM which are accessible in bank 0.
108 1.1 rafal */
109 1.1 rafal
110 1.1 rafal /*
111 1.1 rafal * The registers, and the bits within each register.
112 1.1 rafal */
113 1.1 rafal
114 1.1 rafal #define DS1687_SEC 0x00 /* Time of year: seconds (0-59) */
115 1.1 rafal #define DS1687_ASEC 0x01 /* Alarm: seconds */
116 1.1 rafal #define DS1687_MIN 0x02 /* Time of year: minutes (0-59) */
117 1.1 rafal #define DS1687_AMIN 0x03 /* Alarm: minutes */
118 1.1 rafal #define DS1687_HOUR 0x04 /* Time of year: hour (see above) */
119 1.1 rafal #define DS1687_AHOUR 0x05 /* Alarm: hour (see above) */
120 1.1 rafal #define DS1687_DOW 0x06 /* Time of year: day of week (1-7, 1 = Sun) */
121 1.1 rafal #define DS1687_DOM 0x07 /* Time of year: day of month (1-31) */
122 1.1 rafal #define DS1687_MONTH 0x08 /* Time of year: month (1-12) */
123 1.1 rafal #define DS1687_YEAR 0x09 /* Time of year: year in century (0-99) */
124 1.1 rafal
125 1.1 rafal #define DS1687_CONTROLA 0x0a /* Control Register A */
126 1.1 rafal
127 1.1 rafal #define DS1687_UIP 0x80 /* Update in progress: RO */
128 1.1 rafal #define DS1687_DV2 0x40 /* Countdown chain: 0 = on, 1 = reset if DV1 */
129 1.1 rafal #define DS1687_DV1 0x20 /* Oscillator enable */
130 1.1 rafal #define DS1687_BANK1 0x10 /* Bank select: 0 = bank0, 1 = bank1 */
131 1.1 rafal #define DS1687_RATEMASK 0x0f /* Rate select bits for sq. wave and PIE */
132 1.1 rafal
133 1.1 rafal #define DS1687_CONTROLB 0x0b /* Control Register B */
134 1.1 rafal
135 1.1 rafal #define DS1687_SET 0x80 /* Clock update control: 1 = disable update */
136 1.1 rafal #define DS1687_PIE 0x40 /* Periodic interrupt enable */
137 1.1 rafal #define DS1687_AIE 0x20 /* Alarm interrupt enable */
138 1.1 rafal #define DS1687_UIE 0x10 /* Update-ended interrupt enable */
139 1.1 rafal #define DS1687_SQWE 0x08 /* Enable sq. wave output on SQW pin */
140 1.1 rafal #define DS1687_BINARY 0x04 /* Data mode: 0 = BCD, 1 = binary data */
141 1.1 rafal #define DS1687_24HRS 0x02 /* Hour format: 1 = 24hrs, 0 = 12hrs */
142 1.1 rafal #define DS1687_DSE 0x01 /* Daylight savings enable */
143 1.1 rafal
144 1.1 rafal #define DS1687_CONTROLC 0x0c /* Control register C: Read-only */
145 1.1 rafal /* Note: PF, AF, UF cleared on read */
146 1.1 rafal
147 1.1 rafal #define DS1687_IRQF 0x80 /* IRQ present: set when any IRQ is active */
148 1.1 rafal #define DS1687_PF 0x40 /* Periodic interrupt: independent of PIE */
149 1.1 rafal #define DS1687_AF 0x20 /* Alarm reached: independent of AIE */
150 1.1 rafal #define DS1687_UF 0x10 /* Update ended: independent of UIE */
151 1.1 rafal
152 1.1 rafal #define DS1687_CONTROLD 0x0d /* Control register D: Read-only */
153 1.1 rafal
154 1.1 rafal #define DS1687_VRT 0x80 /* Valid RAM and time: battery bad if 0 */
155 1.1 rafal
156 1.1 rafal #define DS1687_NVRAM_START 0x0e /* Start of user ram: offset 14 */
157 1.1 rafal #define DS1687_NVRAM_SIZE 0x72 /* 114 bytes of user RAM */
158 1.1 rafal
159 1.1 rafal #define DS1687_BANK1_START 0x40 /* BANK1: Start of BANK1 registers */
160 1.1 rafal #define DS1687_BANK1_CENTURY 0x48 /* BANK1: Time of yr: Century (0-99) */
161 1.1 rafal #define DS1687_BANK1_ADATE 0x49 /* BANK1: Alarm: Date (1-31) */
162 1.9 macallan #define DS1687_BANK1_XCTRL4A 0x4a
163 1.9 macallan #define DS1687_X4A_VRT 0x80 /* valid RAM / time */
164 1.9 macallan #define DS1687_X4A_INCR 0x40 /* increment status */
165 1.9 macallan #define DS1687_X4A_BME 0x20 /* burst mode enable */
166 1.9 macallan #define DS1687_X4A_PAB 0x08 /* power active bar */
167 1.9 macallan #define DS1687_X4A_RCF 0x04 /* read clear flag */
168 1.9 macallan #define DS1687_X4A_WAF 0x02 /* wakeup alarm flag */
169 1.9 macallan #define DS1687_X4A_KF 0x01 /* kickstart flag */
170 1.9 macallan #define DS1687_BANK1_XCTRL4B 0x4b
171 1.13 andvar #define DS1687_X4B_ABE 0x80 /* auxiliary battery enable */
172 1.9 macallan #define DS1687_X4B_E32K 0x40 /* enable 32.768kHz output */
173 1.9 macallan #define DS1687_X4B_CS 0x20 /* chrystal select */
174 1.9 macallan #define DS1687_X4B_RCE 0x10 /* RAM clear enable */
175 1.9 macallan #define DS1687_X4B_PRS 0x08 /* PAB reset select */
176 1.9 macallan #define DS1687_X4B_RCIE 0x04 /* RAM clear interrupt enable */
177 1.9 macallan #define DS1687_X4B_WIE 0x02 /* wakeup interrupt enable */
178 1.9 macallan #define DS1687_X4B_KIE 0x01 /* kickstart interrupt enable */
179 1.1 rafal
180 1.1 rafal #define DS1687_NBASEREGS 0x0d /* 14 registers; CMOS follows */
181 1.1 rafal
182 1.1 rafal /* Layout of software shadow copy of TOD registers */
183 1.1 rafal #define DS1687_NHDW_TODREGS 0x0a /* 10 basic TOD registers */
184 1.1 rafal #define DS1687_NSOFT_TODREGS 0x0c /* ...plus shadow CENTURY, ADATE */
185 1.1 rafal
186 1.1 rafal #define DS1687_SOFT_SEC 0x00
187 1.1 rafal #define DS1687_SOFT_ASEC 0x01
188 1.1 rafal #define DS1687_SOFT_MIN 0x02
189 1.1 rafal #define DS1687_SOFT_AMIN 0x03
190 1.1 rafal #define DS1687_SOFT_HOUR 0x04
191 1.1 rafal #define DS1687_SOFT_AHOUR 0x05
192 1.1 rafal #define DS1687_SOFT_DOW 0x06
193 1.1 rafal #define DS1687_SOFT_DOM 0x07
194 1.1 rafal #define DS1687_SOFT_MONTH 0x08
195 1.1 rafal #define DS1687_SOFT_YEAR 0x09
196 1.1 rafal #define DS1687_SOFT_CENTURY 0x0a
197 1.1 rafal #define DS1687_SOFT_ADATE 0x0b
198 1.1 rafal
199 1.1 rafal /*
200 1.1 rafal * RTC register/NVRAM read and write functions -- machine-dependent.
201 1.1 rafal * Appropriately manipulate RTC registers to get/put data values.
202 1.1 rafal */
203 1.6 perry u_int ds1687_read(void *, u_int);
204 1.6 perry void ds1687_write(void *, u_int, u_int);
205 1.1 rafal
206 1.1 rafal /*
207 1.1 rafal * A collection of TOD/Alarm registers.
208 1.1 rafal */
209 1.1 rafal typedef u_int ds1687_todregs[DS1687_NSOFT_TODREGS];
210 1.1 rafal
211 1.1 rafal /*
212 1.1 rafal * Get all of the TOD/Alarm registers
213 1.1 rafal * Must be called at splhigh(), and with the RTC properly set up.
214 1.1 rafal */
215 1.1 rafal #define DS1687_GETTOD(sc, regs) \
216 1.1 rafal do { \
217 1.1 rafal int i; \
218 1.1 rafal u_int ctl; \
219 1.1 rafal \
220 1.1 rafal /* turn off update for now */ \
221 1.1 rafal ctl = ds1687_read(sc, DS1687_CONTROLB); \
222 1.1 rafal ds1687_write(sc, DS1687_CONTROLB, ctl | DS1687_SET); \
223 1.1 rafal \
224 1.1 rafal /* read all of the tod/alarm regs */ \
225 1.1 rafal for (i = 0; i < DS1687_NHDW_TODREGS; i++) \
226 1.1 rafal (*regs)[i] = ds1687_read(sc, i); \
227 1.1 rafal \
228 1.1 rafal (*regs)[DS1687_SOFT_CENTURY] = \
229 1.1 rafal ds1687_read(sc, DS1687_BANK1_CENTURY); \
230 1.1 rafal (*regs)[DS1687_SOFT_ADATE] = \
231 1.1 rafal ds1687_read(sc, DS1687_BANK1_ADATE); \
232 1.1 rafal \
233 1.1 rafal /* turn update back on */ \
234 1.1 rafal ds1687_write(sc, DS1687_CONTROLB, ctl); \
235 1.1 rafal } while (0);
236 1.1 rafal
237 1.1 rafal /*
238 1.1 rafal * Set all of the TOD/Alarm registers
239 1.1 rafal * Must be called at splhigh(), and with the RTC properly set up.
240 1.1 rafal */
241 1.1 rafal #define DS1687_PUTTOD(sc, regs) \
242 1.1 rafal do { \
243 1.1 rafal int i; \
244 1.1 rafal u_int ctl; \
245 1.1 rafal \
246 1.1 rafal /* turn off update for now */ \
247 1.1 rafal ctl = ds1687_read(sc, DS1687_CONTROLB); \
248 1.1 rafal ds1687_write(sc, DS1687_CONTROLB, ctl | DS1687_SET); \
249 1.1 rafal \
250 1.1 rafal /* write all of the tod/alarm regs */ \
251 1.1 rafal for (i = 0; i < DS1687_NHDW_TODREGS; i++) \
252 1.1 rafal ds1687_write(sc, i, (*regs)[i]); \
253 1.1 rafal \
254 1.1 rafal ds1687_write(sc, DS1687_BANK1_CENTURY, \
255 1.1 rafal (*regs)[DS1687_SOFT_CENTURY]); \
256 1.1 rafal ds1687_write(sc, DS1687_BANK1_ADATE, \
257 1.1 rafal (*regs)[DS1687_SOFT_ADATE]); \
258 1.1 rafal \
259 1.1 rafal /* turn update back on */ \
260 1.1 rafal ds1687_write(sc, DS1687_CONTROLB, ctl); \
261 1.1 rafal } while (0);
262