dwc_eqos.c revision 1.47
1 /* $NetBSD: dwc_eqos.c,v 1.47 2026/05/30 10:24:04 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2022-2026 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * DesignWare Ethernet Quality-of-Service controller 31 * 32 * TODO: 33 * Multiqueue support. 34 * Add watchdog timer. 35 * Add detach function. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.47 2026/05/30 10:24:04 jmcneill Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/device.h> 44 #include <sys/intr.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mutex.h> 48 #include <sys/callout.h> 49 #include <sys/cprng.h> 50 #include <sys/evcnt.h> 51 #include <sys/sysctl.h> 52 #include <sys/kthread.h> 53 #include <sys/rndsource.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 61 #include <dev/mii/miivar.h> 62 63 #include <dev/ic/dwc_eqos_reg.h> 64 #include <dev/ic/dwc_eqos_var.h> 65 66 #define EQOS_MAX_MTU 9000 /* up to 16364? but not tested */ 67 #define EQOS_TXDMA_SIZE (EQOS_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN) 68 #define EQOS_RXDMA_SIZE 2048 /* Fixed value by hardware */ 69 CTASSERT(MCLBYTES >= EQOS_RXDMA_SIZE); 70 71 #ifdef EQOS_DEBUG 72 #define EDEB_NOTE (1U << 0) 73 #define EDEB_INTR (1U << 1) 74 #define EDEB_RXRING (1U << 2) 75 #define EDEB_TXRING (1U << 3) 76 unsigned int eqos_debug; /* Default value */ 77 #define DPRINTF(FLAG, FORMAT, ...) \ 78 if (sc->sc_debug & FLAG) \ 79 device_printf(sc->sc_dev, "%s: " FORMAT, \ 80 __func__, ##__VA_ARGS__) 81 #else 82 #define DPRINTF(FLAG, FORMAT, ...) ((void)0) 83 #endif 84 85 #define CALLOUT_FLAGS CALLOUT_MPSAFE 86 87 #define DESC_BOUNDARY ((sizeof(bus_size_t) > 4) ? (1ULL << 32) : 0) 88 #define DESC_ALIGN sizeof(struct eqos_dma_desc) 89 #define TX_DESC_COUNT EQOS_DMA_DESC_COUNT 90 #define TX_DESC_SIZE (TX_DESC_COUNT * DESC_ALIGN) 91 #define RX_DESC_COUNT EQOS_DMA_DESC_COUNT 92 #define RX_DESC_SIZE (RX_DESC_COUNT * DESC_ALIGN) 93 #define MII_BUSY_RETRY 1000 94 95 #define DESC_OFF(n) ((n) * sizeof(struct eqos_dma_desc)) 96 #define TX_SKIP(n, o) (((n) + (o)) % TX_DESC_COUNT) 97 #define TX_NEXT(n) TX_SKIP(n, 1) 98 #define RX_NEXT(n) (((n) + 1) % RX_DESC_COUNT) 99 100 #define TX_MAX_SEGS 128 101 102 #define EQOS_LOCK(sc) mutex_enter(&(sc)->sc_lock) 103 #define EQOS_UNLOCK(sc) mutex_exit(&(sc)->sc_lock) 104 #define EQOS_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_lock)) 105 106 #define EQOS_TXLOCK(sc) mutex_enter(&(sc)->sc_txlock) 107 #define EQOS_TXUNLOCK(sc) mutex_exit(&(sc)->sc_txlock) 108 #define EQOS_ASSERT_TXLOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_txlock)) 109 110 #define EQOS_HW_FEATURE_ADDR64_32BIT(sc) \ 111 (((sc)->sc_hw_feature[1] & GMAC_MAC_HW_FEATURE1_ADDR64_MASK) == \ 112 GMAC_MAC_HW_FEATURE1_ADDR64_32BIT) 113 114 115 #define RD4(sc, reg) \ 116 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 117 #define WR4(sc, reg, val) \ 118 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 119 120 /* 121 * Request interrupt on completion for every "rx_batch" # packets. 122 */ 123 int eqos_rx_batch = 16; 124 125 /* 126 * RX interrupt watchdog is triggered after "rx_wdt_count" * 256 system 127 * clock cycles. 128 */ 129 int eqos_rx_wdt_count = 160; 130 131 static void eqos_init_sysctls(struct eqos_softc *); 132 static int eqos_sysctl_tx_cur_handler(SYSCTLFN_PROTO); 133 static int eqos_sysctl_tx_end_handler(SYSCTLFN_PROTO); 134 static int eqos_sysctl_rx_cur_handler(SYSCTLFN_PROTO); 135 static int eqos_sysctl_rx_end_handler(SYSCTLFN_PROTO); 136 #ifdef EQOS_DEBUG 137 static int eqos_sysctl_debug_handler(SYSCTLFN_PROTO); 138 #endif 139 140 static int 141 eqos_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 142 { 143 struct eqos_softc * const sc = device_private(dev); 144 uint32_t addr; 145 int retry; 146 147 addr = sc->sc_clock_range | 148 (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 149 (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | 150 GMAC_MAC_MDIO_ADDRESS_GOC_READ | GMAC_MAC_MDIO_ADDRESS_GB; 151 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 152 153 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 154 delay(10); 155 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); 156 if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { 157 *val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; 158 break; 159 } 160 } 161 if (retry == 0) { 162 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 163 phy, reg); 164 return ETIMEDOUT; 165 } 166 167 return 0; 168 } 169 170 static int 171 eqos_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 172 { 173 struct eqos_softc * const sc = device_private(dev); 174 uint32_t addr; 175 int retry; 176 177 WR4(sc, GMAC_MAC_MDIO_DATA, val); 178 179 addr = sc->sc_clock_range | 180 (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 181 (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | 182 GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | GMAC_MAC_MDIO_ADDRESS_GB; 183 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 184 185 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 186 delay(10); 187 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); 188 if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { 189 break; 190 } 191 } 192 if (retry == 0) { 193 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 194 phy, reg); 195 return ETIMEDOUT; 196 } 197 198 return 0; 199 } 200 201 static void 202 eqos_update_link(struct eqos_softc *sc) 203 { 204 struct mii_data * const mii = &sc->sc_mii; 205 uint64_t baudrate; 206 uint32_t conf, flow; 207 208 baudrate = ifmedia_baudrate(mii->mii_media_active); 209 210 conf = RD4(sc, GMAC_MAC_CONFIGURATION); 211 switch (baudrate) { 212 case IF_Mbps(10): 213 conf |= GMAC_MAC_CONFIGURATION_PS; 214 conf &= ~GMAC_MAC_CONFIGURATION_FES; 215 break; 216 case IF_Mbps(100): 217 conf |= GMAC_MAC_CONFIGURATION_PS; 218 conf |= GMAC_MAC_CONFIGURATION_FES; 219 break; 220 case IF_Gbps(1): 221 conf &= ~GMAC_MAC_CONFIGURATION_PS; 222 conf &= ~GMAC_MAC_CONFIGURATION_FES; 223 break; 224 case IF_Mbps(2500ULL): 225 conf &= ~GMAC_MAC_CONFIGURATION_PS; 226 conf |= GMAC_MAC_CONFIGURATION_FES; 227 break; 228 } 229 230 /* Set duplex. */ 231 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 232 conf |= GMAC_MAC_CONFIGURATION_DM; 233 } else { 234 conf &= ~GMAC_MAC_CONFIGURATION_DM; 235 } 236 WR4(sc, GMAC_MAC_CONFIGURATION, conf); 237 238 /* Set TX flow control. */ 239 if (mii->mii_media_active & IFM_ETH_TXPAUSE) { 240 flow = GMAC_MAC_Q0_TX_FLOW_CTRL_TFE; 241 flow |= 0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT; 242 } else 243 flow = 0; 244 WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, flow); 245 246 /* Set RX flow control. */ 247 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 248 flow = GMAC_MAC_RX_FLOW_CTRL_RFE; 249 else 250 flow = 0; 251 WR4(sc, GMAC_MAC_RX_FLOW_CTRL, flow); 252 } 253 254 static void 255 eqos_mii_statchg(struct ifnet *ifp) 256 { 257 struct eqos_softc * const sc = ifp->if_softc; 258 259 eqos_update_link(sc); 260 } 261 262 static void 263 eqos_dma_sync(struct eqos_softc *sc, bus_dmamap_t map, 264 u_int start, u_int end, u_int total, int flags) 265 { 266 if (end > start) { 267 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(start), 268 DESC_OFF(end) - DESC_OFF(start), flags); 269 } else { 270 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(start), 271 DESC_OFF(total) - DESC_OFF(start), flags); 272 if (end > 0) { 273 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(0), 274 DESC_OFF(end) - DESC_OFF(0), flags); 275 } 276 } 277 } 278 279 static uint32_t 280 eqos_setup_txdesc(struct eqos_softc *sc, int index, int flags, 281 bus_addr_t paddr, u_int len, u_int total_len) 282 { 283 struct eqos_dma_desc desc; 284 uint32_t tdes2, tdes3; 285 286 DPRINTF(EDEB_TXRING, "preparing desc %u\n", index); 287 288 EQOS_ASSERT_TXLOCKED(sc); 289 290 if (paddr == 0 || len == 0) { 291 DPRINTF(EDEB_TXRING, 292 "tx for desc %u done!\n", index); 293 KASSERT(flags == 0); 294 tdes2 = 0; 295 tdes3 = 0; 296 --sc->sc_tx.queued; 297 } else { 298 tdes2 = 0; 299 tdes3 = flags; 300 ++sc->sc_tx.queued; 301 } 302 303 KASSERT(!EQOS_HW_FEATURE_ADDR64_32BIT(sc) || 304 ((uint64_t)paddr >> 32) == 0); 305 306 desc.tdes0 = htole32((uint32_t)paddr); 307 desc.tdes1 = htole32((uint32_t)((uint64_t)paddr >> 32)); 308 desc.tdes2 = htole32(tdes2 | len); 309 desc.tdes3 = htole32(tdes3 | total_len); 310 311 sc->sc_tx.desc_ring[index] = desc; 312 313 return tdes3 | total_len; 314 } 315 316 static int 317 eqos_setup_txbuf(struct eqos_softc *sc, int index, struct mbuf *m, 318 uint32_t *ptdes3) 319 { 320 bus_dma_segment_t *segs; 321 int error, nsegs, cur, i; 322 uint32_t flags, first_tdes3; 323 bool nospace; 324 325 DPRINTF(EDEB_TXRING, "preparing desc %u\n", index); 326 327 /* at least one descriptor free ? */ 328 if (sc->sc_tx.queued >= TX_DESC_COUNT - 1) 329 return -1; 330 331 error = bus_dmamap_load_mbuf(sc->sc_dmat, 332 sc->sc_tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 333 if (error == EFBIG) { 334 device_printf(sc->sc_dev, 335 "TX packet needs too many DMA segments, dropping...\n"); 336 return -2; 337 } 338 if (error != 0) { 339 device_printf(sc->sc_dev, 340 "TX packet cannot be mapped, retried...\n"); 341 return 0; 342 } 343 344 segs = sc->sc_tx.buf_map[index].map->dm_segs; 345 nsegs = sc->sc_tx.buf_map[index].map->dm_nsegs; 346 347 nospace = sc->sc_tx.queued >= TX_DESC_COUNT - nsegs; 348 if (nospace) { 349 bus_dmamap_unload(sc->sc_dmat, 350 sc->sc_tx.buf_map[index].map); 351 /* XXX coalesce and retry ? */ 352 return -1; 353 } 354 355 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.buf_map[index].map, 356 0, sc->sc_tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 357 358 /* stored in same index as loaded map */ 359 sc->sc_tx.buf_map[index].mbuf = m; 360 361 flags = EQOS_TDES3_TX_FD; 362 if (ptdes3 == NULL) { 363 flags |= EQOS_TDES3_TX_OWN; 364 } 365 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) { 366 flags |= EQOS_TDES3_TX_CIC_FULL; 367 } else if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 368 flags |= EQOS_TDES3_TX_CIC_IPHDR; 369 } 370 first_tdes3 = 0; 371 372 for (cur = index, i = 0; i < nsegs; i++) { 373 uint32_t tdes3; 374 375 if (i == nsegs - 1) 376 flags |= EQOS_TDES3_TX_LD; 377 378 tdes3 = eqos_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 379 segs[i].ds_len, m->m_pkthdr.len); 380 cur = TX_NEXT(cur); 381 382 if (i == 0) { 383 first_tdes3 = tdes3; 384 flags &= ~EQOS_TDES3_TX_FD; 385 } 386 flags |= EQOS_TDES3_TX_OWN; 387 } 388 389 if (ptdes3 != NULL) { 390 *ptdes3 = first_tdes3; 391 } 392 393 DPRINTF(EDEB_TXRING, "passing tx desc %u to hardware, cur: %u, " 394 "next: %u, queued: %u, owned: %u\n", 395 index, sc->sc_tx.cur, sc->sc_tx.next, sc->sc_tx.queued, 396 ptdes3 == NULL); 397 398 return nsegs; 399 } 400 401 static void 402 eqos_setup_rxdesc(struct eqos_softc *sc, int index, bus_addr_t paddr) 403 { 404 struct eqos_dma_desc desc; 405 uint32_t tdes3 = EQOS_TDES3_RX_OWN | EQOS_TDES3_RX_BUF1V; 406 407 if ((index % eqos_rx_batch) == 0) { 408 tdes3 |= EQOS_TDES3_RX_IOC; 409 } 410 411 DPRINTF(EDEB_RXRING, "preparing desc %u\n", index); 412 413 desc.tdes0 = htole32((uint32_t)paddr); 414 desc.tdes1 = htole32((uint32_t)((uint64_t)paddr >> 32)); 415 desc.tdes2 = htole32(0); 416 desc.tdes3 = 0; 417 418 sc->sc_rx.desc_ring[index] = desc; 419 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.desc_map, 420 DESC_OFF(index), offsetof(struct eqos_dma_desc, tdes3), 421 BUS_DMASYNC_PREWRITE); 422 sc->sc_rx.desc_ring[index].tdes3 = htole32(tdes3); 423 } 424 425 static int 426 eqos_setup_rxbuf(struct eqos_softc *sc, int index, struct mbuf *m) 427 { 428 int error; 429 430 DPRINTF(EDEB_RXRING, "preparing desc %u\n", index); 431 432 #if MCLBYTES >= (EQOS_RXDMA_SIZE + ETHER_ALIGN) 433 m_adj(m, ETHER_ALIGN); 434 #endif 435 436 error = bus_dmamap_load_mbuf(sc->sc_dmat, 437 sc->sc_rx.buf_map[index].map, m, BUS_DMA_READ | BUS_DMA_NOWAIT); 438 if (error != 0) 439 return error; 440 441 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.buf_map[index].map, 442 0, sc->sc_rx.buf_map[index].map->dm_mapsize, 443 BUS_DMASYNC_PREREAD); 444 445 sc->sc_rx.buf_map[index].mbuf = m; 446 447 return 0; 448 } 449 450 static struct mbuf * 451 eqos_alloc_mbufcl(struct eqos_softc *sc) 452 { 453 struct mbuf *m; 454 455 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 456 if (m != NULL) 457 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 458 MCLAIM(m, &sc->sc_ec.ec_rx_mowner); 459 460 return m; 461 } 462 463 static void 464 eqos_enable_intr(struct eqos_softc *sc) 465 { 466 467 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 468 GMAC_DMA_CHAN0_INTR_ENABLE_NIE | 469 GMAC_DMA_CHAN0_INTR_ENABLE_AIE | 470 GMAC_DMA_CHAN0_INTR_ENABLE_FBE | 471 GMAC_DMA_CHAN0_INTR_ENABLE_RIE); 472 } 473 474 static void 475 eqos_disable_intr(struct eqos_softc *sc) 476 { 477 478 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0); 479 } 480 481 static void 482 eqos_tick(void *softc) 483 { 484 struct eqos_softc * const sc = softc; 485 struct mii_data * const mii = &sc->sc_mii; 486 487 EQOS_LOCK(sc); 488 mii_tick(mii); 489 if ((sc->sc_if_flags & IFF_RUNNING) != 0) 490 callout_schedule(&sc->sc_stat_ch, hz); 491 EQOS_UNLOCK(sc); 492 } 493 494 static uint32_t 495 eqos_bitrev32(uint32_t x) 496 { 497 498 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 499 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 500 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 501 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 502 503 return (x >> 16) | (x << 16); 504 } 505 506 static void 507 eqos_setup_rxfilter(struct eqos_softc *sc) 508 { 509 struct ethercom *ec = &sc->sc_ec; 510 struct ifnet * const ifp = &ec->ec_if; 511 uint32_t pfil, crc, hashreg, hashbit, hash[2]; 512 struct ether_multi *enm; 513 struct ether_multistep step; 514 const uint8_t *eaddr; 515 uint32_t val; 516 517 EQOS_ASSERT_LOCKED(sc); 518 519 pfil = RD4(sc, GMAC_MAC_PACKET_FILTER); 520 521 /* turn off promiscous mode */ 522 /* turn off the receive-all mode */ 523 /* turn off the non-UDP/TCP filter */ 524 /* turn off broadcast filter */ 525 /* turn off pass all multicast mode */ 526 /* turn on hash or perfect mode */ 527 /* turn off source address filter */ 528 /* turn off inverse source address filter */ 529 /* turn off inverse destination address filter */ 530 /* turn off multicast hash table matching */ 531 /* turn off unicast hash table matching */ 532 /* XXX keep IP Layer3+4 filter */ 533 /* XXX keep VLAN tag filter */ 534 /* don't pass control packets */ 535 pfil &= ~(GMAC_MAC_PACKET_FILTER_PR | 536 GMAC_MAC_PACKET_FILTER_RA | 537 GMAC_MAC_PACKET_FILTER_DNTU | 538 GMAC_MAC_PACKET_FILTER_DBF | 539 GMAC_MAC_PACKET_FILTER_PM | 540 GMAC_MAC_PACKET_FILTER_SAF | 541 GMAC_MAC_PACKET_FILTER_SAIF | 542 GMAC_MAC_PACKET_FILTER_DAIF | 543 GMAC_MAC_PACKET_FILTER_HMC | 544 GMAC_MAC_PACKET_FILTER_HUC | 545 GMAC_MAC_PACKET_FILTER_PCF_MASK); 546 pfil |= GMAC_MAC_PACKET_FILTER_HPF; 547 548 ETHER_LOCK(ec); 549 if ((sc->sc_if_flags & IFF_PROMISC) != 0) { 550 ec->ec_flags |= ETHER_F_ALLMULTI; 551 /* enable promiscous mode */ 552 pfil |= GMAC_MAC_PACKET_FILTER_PR; 553 /* also receive control packets */ 554 pfil |= GMAC_MAC_PACKET_FILTER_PCF_ALL; 555 /* ignored */ 556 hash[0] = hash[1] = ~0U; 557 } else { 558 hash[0] = hash[1] = 0U; 559 ec->ec_flags &= ~ETHER_F_ALLMULTI; 560 /* enable multicast hash table matching */ 561 pfil |= GMAC_MAC_PACKET_FILTER_HMC; 562 ETHER_FIRST_MULTI(step, ec, enm); 563 while (enm != NULL) { 564 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 565 ETHER_ADDR_LEN) != 0) { 566 /* disable multicast hash table matching */ 567 pfil &= ~GMAC_MAC_PACKET_FILTER_HMC; 568 /* pass all multicast instead */ 569 pfil |= GMAC_MAC_PACKET_FILTER_PM; 570 /* ignored */ 571 hash[0] = hash[1] = ~0U; 572 break; 573 } 574 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 575 crc &= 0x7f; 576 crc = eqos_bitrev32(~crc) >> 26; 577 hashreg = (crc >> 5); 578 hashbit = (crc & 0x1f); 579 hash[hashreg] |= (1 << hashbit); 580 ETHER_NEXT_MULTI(step, enm); 581 } 582 } 583 ETHER_UNLOCK(ec); 584 585 /* Write our unicast address */ 586 eaddr = CLLADDR(ifp->if_sadl); 587 val = eaddr[4] | (eaddr[5] << 8); 588 val = __SHIFTIN(val, GMAC_MAC_ADDRESS_HIGH_ADDR) 589 | GMAC_MAC_ADDRESS_HIGH_AE; 590 WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val); 591 val = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 592 (eaddr[3] << 24); 593 WR4(sc, GMAC_MAC_ADDRESS0_LOW, val); 594 595 /* Multicast hash filters */ 596 /* XXX assumes 64 bit hashtable size */ 597 WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]); 598 WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]); 599 600 DPRINTF(EDEB_NOTE, "writing new packet filter config " 601 "%08x, hash[1]=%08x, hash[0]=%08x\n", pfil, hash[1], hash[0]); 602 /* Packet filter config */ 603 WR4(sc, GMAC_MAC_PACKET_FILTER, pfil); 604 } 605 606 static int 607 eqos_reset(struct eqos_softc *sc) 608 { 609 uint32_t val; 610 int retry; 611 612 WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR); 613 for (retry = 2000; retry > 0; retry--) { 614 delay(1000); 615 val = RD4(sc, GMAC_DMA_MODE); 616 if ((val & GMAC_DMA_MODE_SWR) == 0) { 617 return 0; 618 } 619 } 620 621 device_printf(sc->sc_dev, "reset timeout!\n"); 622 return ETIMEDOUT; 623 } 624 625 static void 626 eqos_init_rings(struct eqos_softc *sc, int qid) 627 { 628 sc->sc_tx.cur = sc->sc_tx.next = sc->sc_tx.queued = 0; 629 630 sc->sc_rx_discarding = false; 631 m_freem(sc->sc_rx_receiving_m); 632 sc->sc_rx_receiving_m = NULL; 633 sc->sc_rx_receiving_m_last = NULL; 634 635 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI, 636 (uint32_t)((uint64_t)sc->sc_tx.desc_ring_paddr >> 32)); 637 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR, 638 (uint32_t)sc->sc_tx.desc_ring_paddr); 639 WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1); 640 DPRINTF(EDEB_TXRING, "tx ring paddr %lx with %u descriptors\n", 641 sc->sc_tx.desc_ring_paddr, TX_DESC_COUNT); 642 643 sc->sc_rx.cur = sc->sc_rx.next = sc->sc_rx.queued = 0; 644 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI, 645 (uint32_t)((uint64_t)sc->sc_rx.desc_ring_paddr >> 32)); 646 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR, 647 (uint32_t)sc->sc_rx.desc_ring_paddr); 648 WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1); 649 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, 650 (uint32_t)sc->sc_rx.desc_ring_paddr + 651 DESC_OFF((sc->sc_rx.cur - 1) % RX_DESC_COUNT)); 652 DPRINTF(EDEB_RXRING, "rx ring paddr %lx with %u descriptors\n", 653 sc->sc_rx.desc_ring_paddr, RX_DESC_COUNT); 654 } 655 656 static int 657 eqos_init_locked(struct eqos_softc *sc) 658 { 659 struct ifnet * const ifp = &sc->sc_ec.ec_if; 660 struct mii_data * const mii = &sc->sc_mii; 661 uint32_t val, tqs, rqs; 662 663 EQOS_ASSERT_LOCKED(sc); 664 EQOS_ASSERT_TXLOCKED(sc); 665 666 if ((ifp->if_flags & IFF_RUNNING) != 0) { 667 /* Only Setup RX filter */ 668 eqos_setup_rxfilter(sc); 669 return 0; 670 } 671 672 /* Setup TX/RX rings */ 673 eqos_init_rings(sc, 0); 674 675 /* Setup RX filter */ 676 sc->sc_if_flags = ifp->if_flags; 677 eqos_setup_rxfilter(sc); 678 679 WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->sc_csr_clock / 1000000) - 1); 680 681 /* RX interrupt watchdog timer */ 682 WR4(sc, GMAC_DMA_CHAN0_RX_WATCHDOG, 683 GMAC_DMA_CHAN0_RX_WATCHDOG_RWTU_256 | eqos_rx_wdt_count); 684 685 /* Enable transmit and receive DMA */ 686 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); 687 val &= ~GMAC_DMA_CHAN0_CONTROL_DSL_MASK; 688 val |= ((DESC_ALIGN - 16) / 8) << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT; 689 val |= GMAC_DMA_CHAN0_CONTROL_PBLX8; 690 WR4(sc, GMAC_DMA_CHAN0_CONTROL, val); 691 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); 692 val &= ~GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_MASK; 693 val |= (sc->sc_dma_txpbl << GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_SHIFT); 694 val |= GMAC_DMA_CHAN0_TX_CONTROL_OSP; 695 val |= GMAC_DMA_CHAN0_TX_CONTROL_START; 696 WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); 697 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); 698 val &= ~(GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK | 699 GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_MASK); 700 val |= (MCLBYTES << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT); 701 val |= (sc->sc_dma_rxpbl << GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_SHIFT); 702 val |= GMAC_DMA_CHAN0_RX_CONTROL_START; 703 WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); 704 705 /* Disable counters */ 706 WR4(sc, GMAC_MMC_CONTROL, 707 GMAC_MMC_CONTROL_CNTFREEZ | 708 GMAC_MMC_CONTROL_CNTPRST | 709 GMAC_MMC_CONTROL_CNTPRSTLVL); 710 711 /* Configure operation modes */ 712 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, 713 GMAC_MTL_TXQ0_OPERATION_MODE_TSF | 714 GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN); 715 WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, 716 GMAC_MTL_RXQ0_OPERATION_MODE_RSF | 717 GMAC_MTL_RXQ0_OPERATION_MODE_FEP | 718 GMAC_MTL_RXQ0_OPERATION_MODE_FUP); 719 720 /* 721 * TX/RX fifo size in hw_feature[1] are log2(n/128), and 722 * TQS/RQS in TXQ0/RXQ0_OPERATION_MODE are n/256-1. 723 */ 724 tqs = (128 << __SHIFTOUT(sc->sc_hw_feature[1], 725 GMAC_MAC_HW_FEATURE1_TXFIFOSIZE) / 256) - 1; 726 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 727 val &= ~GMAC_MTL_TXQ0_OPERATION_MODE_TQS; 728 val |= __SHIFTIN(tqs, GMAC_MTL_TXQ0_OPERATION_MODE_TQS); 729 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val); 730 731 rqs = (128 << __SHIFTOUT(sc->sc_hw_feature[1], 732 GMAC_MAC_HW_FEATURE1_RXFIFOSIZE) / 256) - 1; 733 val = RD4(sc, GMAC_MTL_RXQ0_OPERATION_MODE); 734 val &= ~GMAC_MTL_RXQ0_OPERATION_MODE_RQS; 735 val |= __SHIFTIN(rqs, GMAC_MTL_RXQ0_OPERATION_MODE_RQS); 736 WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, val); 737 738 /* 739 * Disable flow control. 740 * It'll be configured later from the negotiated result. 741 */ 742 WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, 0); 743 WR4(sc, GMAC_MAC_RX_FLOW_CTRL, 0); 744 745 /* set RX queue mode. must be in DCB mode. */ 746 val = __SHIFTIN(GMAC_RXQ_CTRL0_EN_DCB, GMAC_RXQ_CTRL0_EN_MASK); 747 WR4(sc, GMAC_RXQ_CTRL0, val); 748 749 /* Enable transmitter and receiver */ 750 val = RD4(sc, GMAC_MAC_CONFIGURATION); 751 val |= GMAC_MAC_CONFIGURATION_BE; 752 val |= GMAC_MAC_CONFIGURATION_JD; 753 val |= GMAC_MAC_CONFIGURATION_JE; 754 val |= GMAC_MAC_CONFIGURATION_DCRS; 755 val |= GMAC_MAC_CONFIGURATION_TE; 756 val |= GMAC_MAC_CONFIGURATION_RE; 757 WR4(sc, GMAC_MAC_CONFIGURATION, val); 758 759 /* Enable interrupts */ 760 eqos_enable_intr(sc); 761 762 EQOS_ASSERT_TXLOCKED(sc); 763 sc->sc_txrunning = true; 764 765 ifp->if_flags |= IFF_RUNNING; 766 sc->sc_if_flags |= IFF_RUNNING; 767 768 mii_mediachg(mii); 769 callout_schedule(&sc->sc_stat_ch, hz); 770 771 return 0; 772 } 773 774 static int 775 eqos_init(struct ifnet *ifp) 776 { 777 struct eqos_softc * const sc = ifp->if_softc; 778 int error; 779 780 EQOS_LOCK(sc); 781 EQOS_TXLOCK(sc); 782 error = eqos_init_locked(sc); 783 EQOS_TXUNLOCK(sc); 784 EQOS_UNLOCK(sc); 785 786 return error; 787 } 788 789 static void 790 eqos_stop_locked(struct eqos_softc *sc, int disable) 791 { 792 struct ifnet * const ifp = &sc->sc_ec.ec_if; 793 uint32_t val; 794 int retry; 795 796 EQOS_ASSERT_LOCKED(sc); 797 798 EQOS_TXLOCK(sc); 799 sc->sc_txrunning = false; 800 EQOS_TXUNLOCK(sc); 801 802 callout_halt(&sc->sc_stat_ch, &sc->sc_lock); 803 804 mii_down(&sc->sc_mii); 805 806 /* Disable receiver */ 807 val = RD4(sc, GMAC_MAC_CONFIGURATION); 808 val &= ~GMAC_MAC_CONFIGURATION_RE; 809 WR4(sc, GMAC_MAC_CONFIGURATION, val); 810 811 /* Stop receive DMA */ 812 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); 813 val &= ~GMAC_DMA_CHAN0_RX_CONTROL_START; 814 WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); 815 816 /* Stop transmit DMA */ 817 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); 818 val &= ~GMAC_DMA_CHAN0_TX_CONTROL_START; 819 WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); 820 821 if (disable) { 822 /* Flush data in the TX FIFO */ 823 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 824 val |= GMAC_MTL_TXQ0_OPERATION_MODE_FTQ; 825 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val); 826 /* Wait for flush to complete */ 827 for (retry = 10000; retry > 0; retry--) { 828 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 829 if ((val & GMAC_MTL_TXQ0_OPERATION_MODE_FTQ) == 0) { 830 break; 831 } 832 delay(1); 833 } 834 if (retry == 0) { 835 device_printf(sc->sc_dev, 836 "timeout flushing TX queue\n"); 837 } 838 } 839 840 /* Disable transmitter */ 841 val = RD4(sc, GMAC_MAC_CONFIGURATION); 842 val &= ~GMAC_MAC_CONFIGURATION_TE; 843 WR4(sc, GMAC_MAC_CONFIGURATION, val); 844 845 /* Disable interrupts */ 846 eqos_disable_intr(sc); 847 848 workqueue_wait(sc->sc_wq, &sc->sc_rxwork); 849 850 sc->sc_if_flags &= ~IFF_RUNNING; 851 ifp->if_flags &= ~IFF_RUNNING; 852 } 853 854 static void 855 eqos_stop(struct ifnet *ifp, int disable) 856 { 857 struct eqos_softc * const sc = ifp->if_softc; 858 859 EQOS_LOCK(sc); 860 eqos_stop_locked(sc, disable); 861 EQOS_UNLOCK(sc); 862 } 863 864 static void 865 eqos_rxintr(struct eqos_softc *sc, int qid) 866 { 867 struct ifnet * const ifp = &sc->sc_ec.ec_if; 868 const uint64_t if_capenable = ifp->if_capenable; 869 int error, index, pkts = 0; 870 struct mbuf *m, *m0, *new_m, *mprev; 871 uint32_t tdes3; 872 bool discarding; 873 874 /* restore jumboframe context */ 875 discarding = sc->sc_rx_discarding; 876 m0 = sc->sc_rx_receiving_m; 877 mprev = sc->sc_rx_receiving_m_last; 878 879 DPRINTF(EDEB_INTR, "qid: %u, discarding %u, m0 %p\n", 880 qid, discarding, m0); 881 882 for (index = sc->sc_rx.cur; ; index = RX_NEXT(index)) { 883 eqos_dma_sync(sc, sc->sc_rx.desc_map, 884 index, index + 1, RX_DESC_COUNT, 885 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 886 887 tdes3 = le32toh(sc->sc_rx.desc_ring[index].tdes3); 888 if ((tdes3 & EQOS_TDES3_RX_OWN) != 0) { 889 break; 890 } 891 892 /* now discarding untill the last packet */ 893 if (discarding) 894 goto rx_next; 895 896 if ((tdes3 & EQOS_TDES3_RX_CTXT) != 0) 897 goto rx_next; /* ignore receive context descriptor */ 898 899 /* error packet? */ 900 if ((tdes3 & (EQOS_TDES3_RX_CE | EQOS_TDES3_RX_RWT | 901 EQOS_TDES3_RX_OE | EQOS_TDES3_RX_RE | 902 EQOS_TDES3_RX_DE)) != 0) { 903 #ifdef EQOS_DEBUG 904 char buf[128]; 905 snprintb(buf, sizeof(buf), 906 "\177\020" 907 "b\x1e" "CTXT\0" /* 30 */ 908 "b\x18" "CE\0" /* 24 */ 909 "b\x17" "GP\0" /* 23 */ 910 "b\x16" "WDT\0" /* 22 */ 911 "b\x15" "OE\0" /* 21 */ 912 "b\x14" "RE\0" /* 20 */ 913 "b\x13" "DE\0" /* 19 */ 914 "b\x0f" "ES\0" /* 15 */ 915 "\0", tdes3); 916 DPRINTF(EDEB_NOTE, 917 "rxdesc[%d].tdes3=%s\n", index, buf); 918 #endif 919 if_statinc(ifp, if_ierrors); 920 if (m0 != NULL) { 921 m_freem(m0); 922 m0 = mprev = NULL; 923 } 924 discarding = true; 925 goto rx_next; 926 } 927 928 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.buf_map[index].map, 929 0, sc->sc_rx.buf_map[index].map->dm_mapsize, 930 BUS_DMASYNC_POSTREAD); 931 m = sc->sc_rx.buf_map[index].mbuf; 932 new_m = eqos_alloc_mbufcl(sc); 933 if (new_m == NULL) { 934 /* 935 * cannot allocate new mbuf. discard this received 936 * packet, and reuse the mbuf for next. 937 */ 938 if_statinc(ifp, if_ierrors); 939 if (m0 != NULL) { 940 /* also discard the halfway jumbo packet */ 941 m_freem(m0); 942 m0 = mprev = NULL; 943 } 944 discarding = true; 945 goto rx_next; 946 } 947 bus_dmamap_unload(sc->sc_dmat, 948 sc->sc_rx.buf_map[index].map); 949 error = eqos_setup_rxbuf(sc, index, new_m); 950 if (error) 951 panic("%s: %s: unable to load RX mbuf. error=%d", 952 device_xname(sc->sc_dev), __func__, error); 953 954 if (m0 == NULL) { 955 m0 = m; 956 } else { 957 if (m->m_flags & M_PKTHDR) 958 m_remove_pkthdr(m); 959 mprev->m_next = m; 960 } 961 mprev = m; 962 963 if ((tdes3 & EQOS_TDES3_RX_LD) == 0) { 964 /* to be continued in the next segment */ 965 m->m_len = EQOS_RXDMA_SIZE; 966 } else { 967 /* last segment */ 968 uint32_t totallen = tdes3 & EQOS_TDES3_RX_LENGTH_MASK; 969 uint32_t mlen = totallen % EQOS_RXDMA_SIZE; 970 if (mlen == 0) 971 mlen = EQOS_RXDMA_SIZE; 972 m->m_len = mlen; 973 m0->m_pkthdr.len = totallen; 974 m_set_rcvif(m0, ifp); 975 m0->m_flags |= M_HASFCS; 976 m0->m_nextpkt = NULL; 977 978 if ((tdes3 & EQOS_TDES3_RX_RS1V) != 0 && 979 (if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) { 980 uint32_t tdes1 = 981 le32toh(sc->sc_rx.desc_ring[index].tdes1); 982 983 if ((tdes1 & (EQOS_TDES1_RX_IPCE | 984 EQOS_TDES1_RX_IPCB)) == 0) { 985 if ((tdes1 & EQOS_TDES1_RX_IPV4) != 0) { 986 m0->m_pkthdr.csum_flags |= 987 M_CSUM_IPv4; 988 } 989 switch (tdes1 & EQOS_TDES1_RX_PT_MASK) { 990 case EQOS_TDES1_RX_PT_UDP: 991 m0->m_pkthdr.csum_flags |= 992 M_CSUM_UDPv4; 993 break; 994 case EQOS_TDES1_RX_PT_TCP: 995 m0->m_pkthdr.csum_flags |= 996 M_CSUM_TCPv4; 997 break; 998 } 999 } 1000 } 1001 1002 if_percpuq_enqueue(ifp->if_percpuq, m0); 1003 m0 = mprev = NULL; 1004 1005 ++pkts; 1006 } 1007 1008 rx_next: 1009 if (discarding && (tdes3 & EQOS_TDES3_RX_LD) != 0) 1010 discarding = false; 1011 1012 eqos_setup_rxdesc(sc, index, 1013 sc->sc_rx.buf_map[index].map->dm_segs[0].ds_addr); 1014 eqos_dma_sync(sc, sc->sc_rx.desc_map, 1015 index, index + 1, RX_DESC_COUNT, 1016 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1017 } 1018 /* save jumboframe context */ 1019 sc->sc_rx_discarding = discarding; 1020 sc->sc_rx_receiving_m = m0; 1021 sc->sc_rx_receiving_m_last = mprev; 1022 1023 DPRINTF(EDEB_RXRING, "sc_rx.cur %u -> %u\n", 1024 sc->sc_rx.cur, index); 1025 sc->sc_rx.cur = index; 1026 1027 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, 1028 (uint32_t)sc->sc_rx.desc_ring_paddr + 1029 DESC_OFF(sc->sc_rx.cur)); 1030 1031 if (pkts != 0) { 1032 rnd_add_uint32(&sc->sc_rndsource, pkts); 1033 } 1034 } 1035 1036 static void 1037 eqos_txintr(struct eqos_softc *sc, int qid) 1038 { 1039 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1040 struct eqos_bufmap *bmap; 1041 struct eqos_dma_desc *desc; 1042 uint32_t tdes3; 1043 int i, pkts = 0; 1044 1045 DPRINTF(EDEB_INTR, "qid: %u\n", qid); 1046 1047 EQOS_ASSERT_TXLOCKED(sc); 1048 1049 eqos_dma_sync(sc, sc->sc_tx.desc_map, 1050 sc->sc_tx.next, sc->sc_tx.cur, TX_DESC_COUNT, 1051 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1052 1053 for (i = sc->sc_tx.next; sc->sc_tx.queued > 0; i = TX_NEXT(i)) { 1054 KASSERT(sc->sc_tx.queued > 0); 1055 KASSERT(sc->sc_tx.queued <= TX_DESC_COUNT); 1056 1057 desc = &sc->sc_tx.desc_ring[i]; 1058 tdes3 = le32toh(desc->tdes3); 1059 if ((tdes3 & EQOS_TDES3_TX_OWN) != 0) { 1060 break; 1061 } 1062 bmap = &sc->sc_tx.buf_map[i]; 1063 if (bmap->mbuf != NULL) { 1064 bus_dmamap_sync(sc->sc_dmat, bmap->map, 1065 0, bmap->map->dm_mapsize, 1066 BUS_DMASYNC_POSTWRITE); 1067 bus_dmamap_unload(sc->sc_dmat, bmap->map); 1068 m_freem(bmap->mbuf); 1069 bmap->mbuf = NULL; 1070 ++pkts; 1071 } 1072 1073 --sc->sc_tx.queued; 1074 1075 /* Last descriptor in a packet contains DMA status */ 1076 if ((tdes3 & EQOS_TDES3_TX_LD) != 0) { 1077 if ((tdes3 & EQOS_TDES3_TX_DE) != 0) { 1078 device_printf(sc->sc_dev, 1079 "TX [%u] desc error: 0x%08x\n", 1080 i, tdes3); 1081 if_statinc(ifp, if_oerrors); 1082 } else if ((tdes3 & EQOS_TDES3_TX_ES) != 0) { 1083 device_printf(sc->sc_dev, 1084 "TX [%u] tx error: 0x%08x\n", 1085 i, tdes3); 1086 if_statinc(ifp, if_oerrors); 1087 } else { 1088 if_statinc(ifp, if_opackets); 1089 } 1090 } 1091 1092 } 1093 1094 sc->sc_tx.next = i; 1095 1096 if (pkts != 0) { 1097 rnd_add_uint32(&sc->sc_rndsource, pkts); 1098 } 1099 } 1100 1101 static void 1102 eqos_start_locked(struct eqos_softc *sc) 1103 { 1104 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1105 struct mbuf *m; 1106 int cnt, nsegs, start; 1107 uint32_t first_tdes3 = 0; 1108 uint32_t *ptdes3 = &first_tdes3; 1109 1110 EQOS_ASSERT_TXLOCKED(sc); 1111 1112 if (!sc->sc_txrunning) 1113 return; 1114 1115 for (cnt = 0, start = sc->sc_tx.cur; ; cnt++) { 1116 if (sc->sc_tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 1117 DPRINTF(EDEB_TXRING, "%u sc_tx.queued, ring full\n", 1118 sc->sc_tx.queued); 1119 break; 1120 } 1121 1122 IFQ_POLL(&ifp->if_snd, m); 1123 if (m == NULL) 1124 break; 1125 1126 nsegs = eqos_setup_txbuf(sc, sc->sc_tx.cur, m, ptdes3); 1127 if (nsegs <= 0) { 1128 DPRINTF(EDEB_TXRING, "eqos_setup_txbuf failed " 1129 "with %d\n", nsegs); 1130 if (nsegs == -2) { 1131 IFQ_DEQUEUE(&ifp->if_snd, m); 1132 m_freem(m); 1133 continue; 1134 } 1135 break; 1136 } 1137 1138 IFQ_DEQUEUE(&ifp->if_snd, m); 1139 bpf_mtap(ifp, m, BPF_D_OUT); 1140 1141 sc->sc_tx.cur = TX_SKIP(sc->sc_tx.cur, nsegs); 1142 ptdes3 = NULL; 1143 } 1144 1145 DPRINTF(EDEB_TXRING, "tx loop -> cnt = %u, cur: %u, next: %u, " 1146 "queued: %u\n", cnt, sc->sc_tx.cur, sc->sc_tx.next, 1147 sc->sc_tx.queued); 1148 1149 if (cnt != 0) { 1150 eqos_dma_sync(sc, sc->sc_tx.desc_map, 1151 start, sc->sc_tx.cur, TX_DESC_COUNT, 1152 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1153 1154 /* 1155 * Defer setting OWN bit on the first descriptor until all 1156 * descriptors have been updated. The hardware will not try to 1157 * process any descriptors past the first one still owned by 1158 * software (i.e., with the OWN bit clear). 1159 */ 1160 sc->sc_tx.desc_ring[start].tdes3 = 1161 htole32(first_tdes3 | EQOS_TDES3_TX_OWN); 1162 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.desc_map, 1163 DESC_OFF(start) + offsetof(struct eqos_dma_desc, tdes3), 1164 sizeof(uint32_t), 1165 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1166 1167 /* Start and run TX DMA */ 1168 DPRINTF(EDEB_TXRING, "sending desc %u at %lx upto " 1169 "%u-1 at %lx cur tx desc: %x cur tx buf: %x\n", start, 1170 (uint32_t)sc->sc_tx.desc_ring_paddr + DESC_OFF(start), 1171 sc->sc_tx.cur, 1172 (uint32_t)sc->sc_tx.desc_ring_paddr + 1173 DESC_OFF(sc->sc_tx.cur), 1174 RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC), 1175 RD4(sc, GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR)); 1176 WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR, 1177 (uint32_t)sc->sc_tx.desc_ring_paddr + 1178 DESC_OFF(sc->sc_tx.cur)); 1179 } 1180 } 1181 1182 static void 1183 eqos_start(struct ifnet *ifp) 1184 { 1185 struct eqos_softc * const sc = ifp->if_softc; 1186 1187 EQOS_LOCK(sc); 1188 cv_signal(&sc->sc_startcv); 1189 EQOS_UNLOCK(sc); 1190 } 1191 1192 static void 1193 eqos_receive(struct work *wk, void *arg) 1194 { 1195 struct eqos_softc *sc = arg; 1196 uint32_t dma_intr_enable; 1197 1198 EQOS_LOCK(sc); 1199 1200 eqos_rxintr(sc, 0); 1201 1202 dma_intr_enable = RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE); 1203 dma_intr_enable |= GMAC_DMA_CHAN0_STATUS_RI; 1204 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable); 1205 1206 EQOS_UNLOCK(sc); 1207 } 1208 1209 static void 1210 eqos_transmit(void *arg) 1211 { 1212 struct eqos_softc *sc = arg; 1213 1214 EQOS_TXLOCK(sc); 1215 for (;;) { 1216 cv_wait(&sc->sc_startcv, &sc->sc_txlock); 1217 1218 eqos_txintr(sc, 0); 1219 eqos_start_locked(sc); 1220 } 1221 1222 EQOS_TXUNLOCK(sc); 1223 1224 kthread_exit(0); 1225 } 1226 1227 static void 1228 eqos_intr_mtl(struct eqos_softc *sc, uint32_t mtl_status) 1229 { 1230 uint32_t debug_data __unused = 0, ictrl = 0; 1231 1232 if (mtl_status == 0) 1233 return; 1234 1235 /* Drain the errors reported by MTL_INTERRUPT_STATUS */ 1236 sc->sc_ev_mtl.ev_count++; 1237 1238 if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_DBGIS) != 0) { 1239 debug_data = RD4(sc, GMAC_MTL_FIFO_DEBUG_DATA); 1240 sc->sc_ev_mtl_debugdata.ev_count++; 1241 } 1242 if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_Q0IS) != 0) { 1243 uint32_t new_status = 0; 1244 1245 ictrl = RD4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS); 1246 if ((ictrl & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS) != 0) { 1247 new_status |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS; 1248 sc->sc_ev_mtl_rxovfis.ev_count++; 1249 } 1250 if ((ictrl & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS) != 0) { 1251 new_status |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS; 1252 sc->sc_ev_mtl_txovfis.ev_count++; 1253 } 1254 if (new_status) { 1255 new_status |= (ictrl & 1256 (GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE | 1257 GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE)); 1258 WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, new_status); 1259 } 1260 } 1261 DPRINTF(EDEB_INTR, 1262 "GMAC_MTL_INTERRUPT_STATUS = 0x%08X, " 1263 "GMAC_MTL_FIFO_DEBUG_DATA = 0x%08X, " 1264 "GMAC_MTL_INTERRUPT_STATUS_Q0IS = 0x%08X\n", 1265 mtl_status, debug_data, ictrl); 1266 } 1267 1268 int 1269 eqos_intr(void *arg) 1270 { 1271 struct eqos_softc * const sc = arg; 1272 uint32_t mac_status, mtl_status, dma_status, dma_intr_enable, 1273 rx_tx_status; 1274 1275 EQOS_LOCK(sc); 1276 1277 sc->sc_ev_intr.ev_count++; 1278 1279 mac_status = RD4(sc, GMAC_MAC_INTERRUPT_STATUS); 1280 mac_status &= RD4(sc, GMAC_MAC_INTERRUPT_ENABLE); 1281 1282 if (mac_status) { 1283 sc->sc_ev_mac.ev_count++; 1284 DPRINTF(EDEB_INTR, 1285 "GMAC_MAC_INTERRUPT_STATUS = 0x%08X\n", mac_status); 1286 } 1287 1288 mtl_status = RD4(sc, GMAC_MTL_INTERRUPT_STATUS); 1289 eqos_intr_mtl(sc, mtl_status); 1290 1291 dma_intr_enable = RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE); 1292 dma_status = RD4(sc, GMAC_DMA_CHAN0_STATUS); 1293 dma_status &= dma_intr_enable; 1294 if (dma_status) { 1295 WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status); 1296 } 1297 1298 if ((dma_status & GMAC_DMA_CHAN0_STATUS_RI) != 0) { 1299 dma_intr_enable &= ~GMAC_DMA_CHAN0_STATUS_RI; 1300 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable); 1301 workqueue_enqueue(sc->sc_wq, &sc->sc_rxwork, NULL); 1302 sc->sc_ev_rxintr.ev_count++; 1303 } 1304 1305 rx_tx_status = RD4(sc, GMAC_MAC_RX_TX_STATUS); 1306 1307 EQOS_UNLOCK(sc); 1308 1309 if ((mac_status | mtl_status | dma_status) == 0) { 1310 DPRINTF(EDEB_NOTE, "spurious interrupt?!\n"); 1311 } 1312 1313 if (rx_tx_status) { 1314 sc->sc_ev_status.ev_count++; 1315 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_RWT) != 0) 1316 sc->sc_ev_rwt.ev_count++; 1317 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_EXCOL) != 0) 1318 sc->sc_ev_excol.ev_count++; 1319 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_LCOL) != 0) 1320 sc->sc_ev_lcol.ev_count++; 1321 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_EXDEF) != 0) 1322 sc->sc_ev_exdef.ev_count++; 1323 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_LCARR) != 0) 1324 sc->sc_ev_lcarr.ev_count++; 1325 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_NCARR) != 0) 1326 sc->sc_ev_ncarr.ev_count++; 1327 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_TJT) != 0) 1328 sc->sc_ev_tjt.ev_count++; 1329 1330 DPRINTF(EDEB_INTR, "GMAC_MAC_RX_TX_STATUS = 1x%08x\n", 1331 rx_tx_status); 1332 } 1333 1334 return 1; 1335 } 1336 1337 static int 1338 eqos_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1339 { 1340 struct eqos_softc * const sc = ifp->if_softc; 1341 int error; 1342 1343 switch (cmd) { 1344 case SIOCADDMULTI: 1345 case SIOCDELMULTI: 1346 break; 1347 default: 1348 KASSERT(IFNET_LOCKED(ifp)); 1349 } 1350 1351 switch (cmd) { 1352 case SIOCSIFMTU: { 1353 struct ifreq * const ifr = (struct ifreq *)data; 1354 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > EQOS_MAX_MTU) { 1355 error = EINVAL; 1356 } else { 1357 ifp->if_mtu = ifr->ifr_mtu; 1358 error = 0; /* no need ENETRESET */ 1359 } 1360 break; 1361 } 1362 default: { 1363 const int s = splnet(); 1364 error = ether_ioctl(ifp, cmd, data); 1365 splx(s); 1366 1367 if (error != ENETRESET) 1368 break; 1369 1370 error = 0; 1371 1372 if (cmd == SIOCSIFCAP) 1373 error = (*ifp->if_init)(ifp); 1374 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1375 EQOS_LOCK(sc); 1376 if ((sc->sc_if_flags & IFF_RUNNING) != 0) 1377 eqos_setup_rxfilter(sc); 1378 EQOS_UNLOCK(sc); 1379 } 1380 break; 1381 } 1382 } 1383 1384 return error; 1385 } 1386 1387 static int 1388 eqos_ifflags_cb(struct ethercom *ec) 1389 { 1390 struct ifnet * const ifp = &ec->ec_if; 1391 struct eqos_softc * const sc = ifp->if_softc; 1392 int ret = 0; 1393 1394 KASSERT(IFNET_LOCKED(ifp)); 1395 EQOS_LOCK(sc); 1396 1397 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1398 sc->sc_if_flags = ifp->if_flags; 1399 1400 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 1401 ret = ENETRESET; 1402 } else if ((change & IFF_PROMISC) != 0) { 1403 if ((sc->sc_if_flags & IFF_RUNNING) != 0) 1404 eqos_setup_rxfilter(sc); 1405 } 1406 EQOS_UNLOCK(sc); 1407 1408 return ret; 1409 } 1410 1411 1412 static void 1413 eqos_get_eaddr(struct eqos_softc *sc, uint8_t *eaddr) 1414 { 1415 uint32_t maclo, machi; 1416 1417 if (ether_getaddr(sc->sc_dev, eaddr)) { 1418 return; 1419 } 1420 1421 maclo = RD4(sc, GMAC_MAC_ADDRESS0_LOW); 1422 machi = __SHIFTOUT(RD4(sc, GMAC_MAC_ADDRESS0_HIGH), 1423 GMAC_MAC_ADDRESS_HIGH_ADDR); 1424 if (maclo == 0xFFFFFFFF && machi == 0xFFFF) { 1425 /* Create one */ 1426 maclo = 0x00f2 | (cprng_strong32() << 16); 1427 machi = cprng_strong32() & 0xffff; 1428 } else if (maclo & 0x00000001) { 1429 aprint_error_dev(sc->sc_dev, 1430 "Wrong MAC address. Clearing the multicast bit.\n"); 1431 maclo &= ~0x00000001; 1432 } 1433 1434 eaddr[0] = maclo & 0xff; 1435 eaddr[1] = (maclo >> 8) & 0xff; 1436 eaddr[2] = (maclo >> 16) & 0xff; 1437 eaddr[3] = (maclo >> 24) & 0xff; 1438 eaddr[4] = machi & 0xff; 1439 eaddr[5] = (machi >> 8) & 0xff; 1440 } 1441 1442 static void 1443 eqos_get_dma_pbl(struct eqos_softc *sc) 1444 { 1445 prop_dictionary_t prop = device_properties(sc->sc_dev); 1446 uint32_t pbl; 1447 1448 /* Set default values. */ 1449 sc->sc_dma_txpbl = sc->sc_dma_rxpbl = EQOS_DMA_PBL_DEFAULT; 1450 1451 /* Get values from props. */ 1452 if (prop_dictionary_get_uint32(prop, "snps,pbl", &pbl) && pbl) 1453 sc->sc_dma_txpbl = sc->sc_dma_rxpbl = pbl; 1454 if (prop_dictionary_get_uint32(prop, "snps,txpbl", &pbl) && pbl) 1455 sc->sc_dma_txpbl = pbl; 1456 if (prop_dictionary_get_uint32(prop, "snps,rxpbl", &pbl) && pbl) 1457 sc->sc_dma_rxpbl = pbl; 1458 } 1459 1460 static void 1461 eqos_axi_configure(struct eqos_softc *sc) 1462 { 1463 uint32_t val; 1464 u_int uival; 1465 1466 val = RD4(sc, GMAC_DMA_SYSBUS_MODE); 1467 1468 /* XXX are MB and FB mutually-exclusive? XXX */ 1469 if (device_getprop_bool(sc->sc_dev, "snps,mixed-burst")) { 1470 val |= GMAC_DMA_SYSBUS_MODE_MB; 1471 } 1472 if (device_getprop_bool(sc->sc_dev, "snps,fixed-burst")) { 1473 val |= GMAC_DMA_SYSBUS_MODE_FB; 1474 } 1475 if (device_getprop_uint(sc->sc_dev, "snps,wr_osr_lmt", &uival)) { 1476 val &= ~GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; 1477 val |= (uival << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) & 1478 GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; 1479 } 1480 if (device_getprop_uint(sc->sc_dev, "snps,rd_osr_lmt", &uival)) { 1481 val &= ~GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; 1482 val |= (uival << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) & 1483 GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; 1484 } 1485 1486 if (!EQOS_HW_FEATURE_ADDR64_32BIT(sc)) { 1487 val |= GMAC_DMA_SYSBUS_MODE_EAME; 1488 } 1489 1490 /* XXX snps,kbbe XXX */ 1491 /* XXX snps,blen XXX */ 1492 1493 /* XXX */ 1494 val |= GMAC_DMA_SYSBUS_MODE_BLEN16; 1495 val |= GMAC_DMA_SYSBUS_MODE_BLEN8; 1496 val |= GMAC_DMA_SYSBUS_MODE_BLEN4; 1497 1498 WR4(sc, GMAC_DMA_SYSBUS_MODE, val); 1499 } 1500 1501 static int 1502 eqos_setup_dma(struct eqos_softc *sc, int qid) 1503 { 1504 struct mbuf *m; 1505 int error, nsegs, i; 1506 1507 /* Set back pointer */ 1508 sc->sc_tx.sc = sc; 1509 sc->sc_rx.sc = sc; 1510 1511 /* Setup TX ring */ 1512 error = bus_dmamap_create(sc->sc_dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 1513 DESC_BOUNDARY, BUS_DMA_WAITOK, &sc->sc_tx.desc_map); 1514 if (error) { 1515 return error; 1516 } 1517 error = bus_dmamem_alloc(sc->sc_dmat, TX_DESC_SIZE, DESC_ALIGN, 1518 DESC_BOUNDARY, &sc->sc_tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1519 if (error) { 1520 return error; 1521 } 1522 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_tx.desc_dmaseg, nsegs, 1523 TX_DESC_SIZE, (void *)&sc->sc_tx.desc_ring, 1524 BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1525 if (error) { 1526 return error; 1527 } 1528 error = bus_dmamap_load(sc->sc_dmat, sc->sc_tx.desc_map, 1529 sc->sc_tx.desc_ring, TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1530 if (error) { 1531 return error; 1532 } 1533 sc->sc_tx.desc_ring_paddr = sc->sc_tx.desc_map->dm_segs[0].ds_addr; 1534 1535 memset(sc->sc_tx.desc_ring, 0, TX_DESC_SIZE); 1536 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.desc_map, 0, TX_DESC_SIZE, 1537 BUS_DMASYNC_PREWRITE); 1538 1539 sc->sc_tx.queued = TX_DESC_COUNT; 1540 for (i = 0; i < TX_DESC_COUNT; i++) { 1541 error = bus_dmamap_create(sc->sc_dmat, EQOS_TXDMA_SIZE, 1542 TX_MAX_SEGS, MCLBYTES, 0, 1543 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1544 &sc->sc_tx.buf_map[i].map); 1545 if (error != 0) { 1546 device_printf(sc->sc_dev, 1547 "cannot create TX buffer map\n"); 1548 return error; 1549 } 1550 EQOS_TXLOCK(sc); 1551 eqos_setup_txdesc(sc, i, 0, 0, 0, 0); 1552 EQOS_TXUNLOCK(sc); 1553 } 1554 1555 /* Setup RX ring */ 1556 error = bus_dmamap_create(sc->sc_dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 1557 DESC_BOUNDARY, BUS_DMA_WAITOK, &sc->sc_rx.desc_map); 1558 if (error) { 1559 return error; 1560 } 1561 error = bus_dmamem_alloc(sc->sc_dmat, RX_DESC_SIZE, DESC_ALIGN, 1562 DESC_BOUNDARY, &sc->sc_rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1563 if (error) { 1564 return error; 1565 } 1566 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_rx.desc_dmaseg, nsegs, 1567 RX_DESC_SIZE, (void *)&sc->sc_rx.desc_ring, 1568 BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1569 if (error) { 1570 return error; 1571 } 1572 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rx.desc_map, 1573 sc->sc_rx.desc_ring, RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1574 if (error) { 1575 return error; 1576 } 1577 sc->sc_rx.desc_ring_paddr = sc->sc_rx.desc_map->dm_segs[0].ds_addr; 1578 1579 memset(sc->sc_rx.desc_ring, 0, RX_DESC_SIZE); 1580 1581 for (i = 0; i < RX_DESC_COUNT; i++) { 1582 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1583 RX_DESC_COUNT, MCLBYTES, 0, 1584 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1585 &sc->sc_rx.buf_map[i].map); 1586 if (error != 0) { 1587 device_printf(sc->sc_dev, 1588 "cannot create RX buffer map\n"); 1589 return error; 1590 } 1591 if ((m = eqos_alloc_mbufcl(sc)) == NULL) { 1592 device_printf(sc->sc_dev, "cannot allocate RX mbuf\n"); 1593 return ENOMEM; 1594 } 1595 error = eqos_setup_rxbuf(sc, i, m); 1596 if (error != 0) { 1597 device_printf(sc->sc_dev, "cannot create RX buffer\n"); 1598 return error; 1599 } 1600 eqos_setup_rxdesc(sc, i, 1601 sc->sc_rx.buf_map[i].map->dm_segs[0].ds_addr); 1602 } 1603 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.desc_map, 1604 0, sc->sc_rx.desc_map->dm_mapsize, 1605 BUS_DMASYNC_PREWRITE); 1606 1607 aprint_debug_dev(sc->sc_dev, "TX ring @ 0x%lX, RX ring @ 0x%lX\n", 1608 sc->sc_tx.desc_ring_paddr, sc->sc_rx.desc_ring_paddr); 1609 1610 return 0; 1611 } 1612 1613 int 1614 eqos_attach(struct eqos_softc *sc) 1615 { 1616 struct mii_data * const mii = &sc->sc_mii; 1617 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1618 uint8_t eaddr[ETHER_ADDR_LEN]; 1619 u_int userver, snpsver; 1620 int error; 1621 int n; 1622 1623 #ifdef EQOS_DEBUG 1624 /* Load the default debug flags. */ 1625 sc->sc_debug = eqos_debug; 1626 #endif 1627 1628 const uint32_t ver = RD4(sc, GMAC_MAC_VERSION); 1629 userver = (ver & GMAC_MAC_VERSION_USERVER_MASK) >> 1630 GMAC_MAC_VERSION_USERVER_SHIFT; 1631 snpsver = ver & GMAC_MAC_VERSION_SNPSVER_MASK; 1632 1633 if ((snpsver < 0x51) || (snpsver > 0x52)) { 1634 aprint_error(": EQOS version 0x%02x not supported\n", 1635 snpsver); 1636 return ENXIO; 1637 } 1638 1639 if (sc->sc_csr_clock < 20000000) { 1640 aprint_error(": CSR clock too low\n"); 1641 return EINVAL; 1642 } else if (sc->sc_csr_clock < 35000000) { 1643 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_20_35; 1644 } else if (sc->sc_csr_clock < 60000000) { 1645 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_35_60; 1646 } else if (sc->sc_csr_clock < 100000000) { 1647 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_60_100; 1648 } else if (sc->sc_csr_clock < 150000000) { 1649 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_100_150; 1650 } else if (sc->sc_csr_clock < 250000000) { 1651 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_150_250; 1652 } else if (sc->sc_csr_clock < 300000000) { 1653 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_250_300; 1654 } else if (sc->sc_csr_clock < 500000000) { 1655 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_300_500; 1656 } else if (sc->sc_csr_clock < 800000000) { 1657 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_500_800; 1658 } else { 1659 aprint_error(": CSR clock too high\n"); 1660 return EINVAL; 1661 } 1662 1663 for (n = 0; n < 4; n++) { 1664 sc->sc_hw_feature[n] = RD4(sc, GMAC_MAC_HW_FEATURE(n)); 1665 } 1666 1667 aprint_naive("\n"); 1668 aprint_normal(": DesignWare EQOS ver 0x%02x (0x%02x)\n", 1669 snpsver, userver); 1670 aprint_verbose_dev(sc->sc_dev, "hw features %08x %08x %08x %08x\n", 1671 sc->sc_hw_feature[0], sc->sc_hw_feature[1], 1672 sc->sc_hw_feature[2], sc->sc_hw_feature[3]); 1673 1674 if (EQOS_HW_FEATURE_ADDR64_32BIT(sc)) { 1675 bus_dma_tag_t ntag; 1676 1677 error = bus_dmatag_subregion(sc->sc_dmat, 0, UINT32_MAX, 1678 &ntag, 0); 1679 if (error) { 1680 aprint_error_dev(sc->sc_dev, 1681 "failed to restrict DMA: %d\n", error); 1682 return error; 1683 } 1684 aprint_verbose_dev(sc->sc_dev, "using 32-bit DMA\n"); 1685 sc->sc_dmat = ntag; 1686 } 1687 1688 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET); 1689 mutex_init(&sc->sc_txlock, MUTEX_DEFAULT, IPL_NET); 1690 callout_init(&sc->sc_stat_ch, CALLOUT_MPSAFE); 1691 callout_setfunc(&sc->sc_stat_ch, eqos_tick, sc); 1692 1693 eqos_get_eaddr(sc, eaddr); 1694 aprint_normal_dev(sc->sc_dev, 1695 "Ethernet address %s\n", ether_sprintf(eaddr)); 1696 1697 /* Soft reset EMAC core */ 1698 error = eqos_reset(sc); 1699 if (error != 0) { 1700 return error; 1701 } 1702 1703 /* Get DMA burst length */ 1704 eqos_get_dma_pbl(sc); 1705 1706 /* Configure AXI Bus mode parameters */ 1707 eqos_axi_configure(sc); 1708 1709 /* Setup DMA descriptors */ 1710 if (eqos_setup_dma(sc, 0) != 0) { 1711 aprint_error_dev(sc->sc_dev, 1712 "failed to setup DMA descriptors\n"); 1713 return EINVAL; 1714 } 1715 1716 /* Receive workers */ 1717 error = workqueue_create(&sc->sc_wq, device_xname(sc->sc_dev), 1718 eqos_receive, sc, PRI_SOFTNET, IPL_NET, WQ_MPSAFE | WQ_PERCPU); 1719 if (error != 0) { 1720 aprint_error_dev(sc->sc_dev, 1721 "failed to create receive workqueue: %d\n", error); 1722 return error; 1723 } 1724 1725 /* Transmit thread */ 1726 cv_init(&sc->sc_startcv, "idle"); 1727 error = kthread_create(PRI_SOFTNET, KTHREAD_MPSAFE, NULL, 1728 eqos_transmit, sc, &sc->sc_startlwp, "%s-tx", 1729 device_xname(sc->sc_dev)); 1730 if (error != 0) { 1731 aprint_error_dev(sc->sc_dev, 1732 "failed to create transmit thread: %d\n", error); 1733 return error; 1734 } 1735 1736 /* Setup ethernet interface */ 1737 ifp->if_softc = sc; 1738 snprintf(ifp->if_xname, IFNAMSIZ, "%s", device_xname(sc->sc_dev)); 1739 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1740 ifp->if_extflags = IFEF_MPSAFE; 1741 ifp->if_start = eqos_start; 1742 ifp->if_ioctl = eqos_ioctl; 1743 ifp->if_init = eqos_init; 1744 ifp->if_stop = eqos_stop; 1745 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1746 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1747 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1748 ifp->if_capenable = 0; 1749 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1750 IFQ_SET_READY(&ifp->if_snd); 1751 1752 /* 802.1Q VLAN-sized frames, and jumbo frame are supported */ 1753 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1754 sc->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1755 1756 /* Attach MII driver */ 1757 sc->sc_ec.ec_mii = mii; 1758 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1759 mii->mii_ifp = ifp; 1760 mii->mii_readreg = eqos_mii_readreg; 1761 mii->mii_writereg = eqos_mii_writereg; 1762 mii->mii_statchg = eqos_mii_statchg; 1763 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, MII_OFFSET_ANY, 1764 MIIF_DOPAUSE); 1765 1766 if (LIST_EMPTY(&mii->mii_phys)) { 1767 aprint_error_dev(sc->sc_dev, "no PHY found!\n"); 1768 return ENOENT; 1769 } 1770 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1771 1772 /* Master interrupt evcnt */ 1773 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 1774 NULL, device_xname(sc->sc_dev), "interrupts"); 1775 1776 /* Per-interrupt type, using main interrupt */ 1777 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1778 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rxintr"); 1779 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 1780 &sc->sc_ev_intr, device_xname(sc->sc_dev), "txintr"); 1781 evcnt_attach_dynamic(&sc->sc_ev_mac, EVCNT_TYPE_INTR, 1782 &sc->sc_ev_intr, device_xname(sc->sc_dev), "macstatus"); 1783 evcnt_attach_dynamic(&sc->sc_ev_mtl, EVCNT_TYPE_INTR, 1784 &sc->sc_ev_intr, device_xname(sc->sc_dev), "intrstatus"); 1785 evcnt_attach_dynamic(&sc->sc_ev_status, EVCNT_TYPE_INTR, 1786 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rxtxstatus"); 1787 1788 /* MAC Status specific type, using macstatus interrupt */ 1789 evcnt_attach_dynamic(&sc->sc_ev_mtl_debugdata, EVCNT_TYPE_INTR, 1790 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "debugdata"); 1791 evcnt_attach_dynamic(&sc->sc_ev_mtl_rxovfis, EVCNT_TYPE_INTR, 1792 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "rxovfis"); 1793 evcnt_attach_dynamic(&sc->sc_ev_mtl_txovfis, EVCNT_TYPE_INTR, 1794 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "txovfis"); 1795 1796 /* RX/TX Status specific type, using rxtxstatus interrupt */ 1797 evcnt_attach_dynamic(&sc->sc_ev_rwt, EVCNT_TYPE_INTR, 1798 &sc->sc_ev_status, device_xname(sc->sc_dev), "rwt"); 1799 evcnt_attach_dynamic(&sc->sc_ev_excol, EVCNT_TYPE_INTR, 1800 &sc->sc_ev_status, device_xname(sc->sc_dev), "excol"); 1801 evcnt_attach_dynamic(&sc->sc_ev_lcol, EVCNT_TYPE_INTR, 1802 &sc->sc_ev_status, device_xname(sc->sc_dev), "lcol"); 1803 evcnt_attach_dynamic(&sc->sc_ev_exdef, EVCNT_TYPE_INTR, 1804 &sc->sc_ev_status, device_xname(sc->sc_dev), "exdef"); 1805 evcnt_attach_dynamic(&sc->sc_ev_lcarr, EVCNT_TYPE_INTR, 1806 &sc->sc_ev_status, device_xname(sc->sc_dev), "lcarr"); 1807 evcnt_attach_dynamic(&sc->sc_ev_ncarr, EVCNT_TYPE_INTR, 1808 &sc->sc_ev_status, device_xname(sc->sc_dev), "ncarr"); 1809 evcnt_attach_dynamic(&sc->sc_ev_tjt, EVCNT_TYPE_INTR, 1810 &sc->sc_ev_status, device_xname(sc->sc_dev), "tjt"); 1811 1812 /* Attach interface */ 1813 if_attach(ifp); 1814 if_deferred_start_init(ifp, NULL); 1815 1816 /* Attach ethernet interface */ 1817 ether_ifattach(ifp, eaddr); 1818 ether_set_ifflags_cb(&sc->sc_ec, eqos_ifflags_cb); 1819 1820 eqos_init_sysctls(sc); 1821 1822 rnd_attach_source(&sc->sc_rndsource, ifp->if_xname, RND_TYPE_NET, 1823 RND_FLAG_DEFAULT); 1824 1825 return 0; 1826 } 1827 1828 static void 1829 eqos_init_sysctls(struct eqos_softc *sc) 1830 { 1831 struct sysctllog **log; 1832 const struct sysctlnode *rnode, *qnode, *cnode; 1833 const char *dvname; 1834 int i, rv; 1835 1836 log = &sc->sc_sysctllog; 1837 dvname = device_xname(sc->sc_dev); 1838 1839 rv = sysctl_createv(log, 0, NULL, &rnode, 1840 0, CTLTYPE_NODE, dvname, 1841 SYSCTL_DESCR("eqos information and settings"), 1842 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 1843 if (rv != 0) 1844 goto err; 1845 1846 for (i = 0; i < 1; i++) { 1847 struct eqos_ring *txr = &sc->sc_tx; 1848 struct eqos_ring *rxr = &sc->sc_rx; 1849 const unsigned char *name = "q0"; 1850 1851 if (sysctl_createv(log, 0, &rnode, &qnode, 1852 0, CTLTYPE_NODE, 1853 name, SYSCTL_DESCR("Queue Name"), 1854 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL) != 0) 1855 break; 1856 1857 if (sysctl_createv(log, 0, &qnode, &cnode, 1858 CTLFLAG_READONLY, CTLTYPE_INT, 1859 "txs_cur", SYSCTL_DESCR("TX cur"), 1860 NULL, 0, &txr->cur, 1861 0, CTL_CREATE, CTL_EOL) != 0) 1862 break; 1863 if (sysctl_createv(log, 0, &qnode, &cnode, 1864 CTLFLAG_READONLY, CTLTYPE_INT, 1865 "txs_next", SYSCTL_DESCR("TX next"), 1866 NULL, 0, &txr->next, 1867 0, CTL_CREATE, CTL_EOL) != 0) 1868 break; 1869 if (sysctl_createv(log, 0, &qnode, &cnode, 1870 CTLFLAG_READONLY, CTLTYPE_INT, 1871 "txs_queued", SYSCTL_DESCR("TX queued"), 1872 NULL, 0, &txr->queued, 1873 0, CTL_CREATE, CTL_EOL) != 0) 1874 break; 1875 if (sysctl_createv(log, 0, &qnode, &cnode, 1876 CTLFLAG_READONLY, CTLTYPE_INT, 1877 "txr_cur", SYSCTL_DESCR("TX descriptor cur"), 1878 eqos_sysctl_tx_cur_handler, 0, (void *)txr, 1879 0, CTL_CREATE, CTL_EOL) != 0) 1880 break; 1881 if (sysctl_createv(log, 0, &qnode, &cnode, 1882 CTLFLAG_READONLY, CTLTYPE_INT, 1883 "txr_end", SYSCTL_DESCR("TX descriptor end"), 1884 eqos_sysctl_tx_end_handler, 0, (void *)txr, 1885 0, CTL_CREATE, CTL_EOL) != 0) 1886 break; 1887 if (sysctl_createv(log, 0, &qnode, &cnode, 1888 CTLFLAG_READONLY, CTLTYPE_INT, 1889 "rxs_cur", SYSCTL_DESCR("RX cur"), 1890 NULL, 0, &rxr->cur, 1891 0, CTL_CREATE, CTL_EOL) != 0) 1892 break; 1893 if (sysctl_createv(log, 0, &qnode, &cnode, 1894 CTLFLAG_READONLY, CTLTYPE_INT, 1895 "rxs_next", SYSCTL_DESCR("RX next"), 1896 NULL, 0, &rxr->next, 1897 0, CTL_CREATE, CTL_EOL) != 0) 1898 break; 1899 if (sysctl_createv(log, 0, &qnode, &cnode, 1900 CTLFLAG_READONLY, CTLTYPE_INT, 1901 "rxs_queued", SYSCTL_DESCR("RX queued"), 1902 NULL, 0, &rxr->queued, 1903 0, CTL_CREATE, CTL_EOL) != 0) 1904 break; 1905 if (sysctl_createv(log, 0, &qnode, &cnode, 1906 CTLFLAG_READONLY, CTLTYPE_INT, 1907 "rxr_cur", SYSCTL_DESCR("RX descriptor cur"), 1908 eqos_sysctl_rx_cur_handler, 0, (void *)rxr, 1909 0, CTL_CREATE, CTL_EOL) != 0) 1910 break; 1911 if (sysctl_createv(log, 0, &qnode, &cnode, 1912 CTLFLAG_READONLY, CTLTYPE_INT, 1913 "rxr_end", SYSCTL_DESCR("RX descriptor end"), 1914 eqos_sysctl_rx_end_handler, 0, (void *)rxr, 1915 0, CTL_CREATE, CTL_EOL) != 0) 1916 break; 1917 } 1918 1919 #ifdef EQOS_DEBUG 1920 rv = sysctl_createv(log, 0, &rnode, &cnode, CTLFLAG_READWRITE, 1921 CTLTYPE_INT, "debug_flags", 1922 SYSCTL_DESCR( 1923 "Debug flags:\n" \ 1924 "\t0x01 NOTE\n" \ 1925 "\t0x02 INTR\n" \ 1926 "\t0x04 RX RING\n" \ 1927 "\t0x08 TX RING\n"), 1928 eqos_sysctl_debug_handler, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL); 1929 #endif 1930 1931 return; 1932 1933 err: 1934 sc->sc_sysctllog = NULL; 1935 device_printf(sc->sc_dev, "%s: sysctl_createv failed, rv = %d\n", 1936 __func__, rv); 1937 } 1938 1939 static int 1940 eqos_sysctl_tx_cur_handler(SYSCTLFN_ARGS) 1941 { 1942 struct sysctlnode node = *rnode; 1943 struct eqos_ring *txq = (struct eqos_ring *)node.sysctl_data; 1944 struct eqos_softc *sc = txq->sc; 1945 uint32_t reg, index; 1946 1947 reg = RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC); 1948 #if 0 1949 printf("head = %08x\n", (uint32_t)sc->sc_tx.desc_ring_paddr); 1950 printf("cdesc = %08x\n", reg); 1951 printf("index = %zu\n", 1952 (reg - (uint32_t)sc->sc_tx.desc_ring_paddr) / 1953 sizeof(struct eqos_dma_desc)); 1954 #endif 1955 if (reg == 0) 1956 index = 0; 1957 else { 1958 index = (reg - (uint32_t)sc->sc_tx.desc_ring_paddr) / 1959 sizeof(struct eqos_dma_desc); 1960 } 1961 node.sysctl_data = &index; 1962 return sysctl_lookup(SYSCTLFN_CALL(&node)); 1963 } 1964 1965 static int 1966 eqos_sysctl_tx_end_handler(SYSCTLFN_ARGS) 1967 { 1968 struct sysctlnode node = *rnode; 1969 struct eqos_ring *txq = (struct eqos_ring *)node.sysctl_data; 1970 struct eqos_softc *sc = txq->sc; 1971 uint32_t reg, index; 1972 1973 reg = RD4(sc, GMAC_DMA_CHAN0_TX_END_ADDR); 1974 if (reg == 0) 1975 index = 0; 1976 else { 1977 index = (reg - (uint32_t)sc->sc_tx.desc_ring_paddr) / 1978 sizeof(struct eqos_dma_desc); 1979 } 1980 node.sysctl_data = &index; 1981 return sysctl_lookup(SYSCTLFN_CALL(&node)); 1982 } 1983 1984 static int 1985 eqos_sysctl_rx_cur_handler(SYSCTLFN_ARGS) 1986 { 1987 struct sysctlnode node = *rnode; 1988 struct eqos_ring *rxq = (struct eqos_ring *)node.sysctl_data; 1989 struct eqos_softc *sc = rxq->sc; 1990 uint32_t reg, index; 1991 1992 reg = RD4(sc, GMAC_DMA_CHAN0_CUR_RX_DESC); 1993 if (reg == 0) 1994 index = 0; 1995 else { 1996 index = (reg - (uint32_t)sc->sc_rx.desc_ring_paddr) / 1997 sizeof(struct eqos_dma_desc); 1998 } 1999 node.sysctl_data = &index; 2000 return sysctl_lookup(SYSCTLFN_CALL(&node)); 2001 } 2002 2003 static int 2004 eqos_sysctl_rx_end_handler(SYSCTLFN_ARGS) 2005 { 2006 struct sysctlnode node = *rnode; 2007 struct eqos_ring *rxq = (struct eqos_ring *)node.sysctl_data; 2008 struct eqos_softc *sc = rxq->sc; 2009 uint32_t reg, index; 2010 2011 reg = RD4(sc, GMAC_DMA_CHAN0_RX_END_ADDR); 2012 if (reg == 0) 2013 index = 0; 2014 else { 2015 index = (reg - (uint32_t)sc->sc_rx.desc_ring_paddr) / 2016 sizeof(struct eqos_dma_desc); 2017 } 2018 node.sysctl_data = &index; 2019 return sysctl_lookup(SYSCTLFN_CALL(&node)); 2020 } 2021 2022 #ifdef EQOS_DEBUG 2023 static int 2024 eqos_sysctl_debug_handler(SYSCTLFN_ARGS) 2025 { 2026 struct sysctlnode node = *rnode; 2027 struct eqos_softc *sc = (struct eqos_softc *)node.sysctl_data; 2028 uint32_t dflags; 2029 int error; 2030 2031 dflags = sc->sc_debug; 2032 node.sysctl_data = &dflags; 2033 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2034 2035 if (error || newp == NULL) 2036 return error; 2037 2038 sc->sc_debug = dflags; 2039 #if 0 2040 /* Addd debug code here if you want. */ 2041 #endif 2042 2043 return 0; 2044 } 2045 #endif 2046
Indexes created Sun Nov 01 00:25:34 UTC 2026