dwc_eqos.c revision 1.52
1 /* $NetBSD: dwc_eqos.c,v 1.52 2026/06/13 12:03:13 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2022-2026 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * DesignWare Ethernet Quality-of-Service controller 31 * 32 * TODO: 33 * Multiqueue support. 34 * Add watchdog timer. 35 * Add detach function. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.52 2026/06/13 12:03:13 jmcneill Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/device.h> 44 #include <sys/intr.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mutex.h> 48 #include <sys/callout.h> 49 #include <sys/cprng.h> 50 #include <sys/evcnt.h> 51 #include <sys/sysctl.h> 52 #include <sys/rndsource.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_ether.h> 57 #include <net/if_media.h> 58 #include <net/bpf.h> 59 60 #include <dev/mii/miivar.h> 61 62 #include <dev/ic/dwc_eqos_reg.h> 63 #include <dev/ic/dwc_eqos_var.h> 64 65 #define EQOS_MAX_MTU 9000 /* up to 16364? but not tested */ 66 #define EQOS_TXDMA_SIZE (EQOS_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN) 67 #define EQOS_RXDMA_SIZE 2048 /* Fixed value by hardware */ 68 CTASSERT(MCLBYTES >= EQOS_RXDMA_SIZE); 69 70 #ifdef EQOS_DEBUG 71 #define EDEB_NOTE (1U << 0) 72 #define EDEB_INTR (1U << 1) 73 #define EDEB_RXRING (1U << 2) 74 #define EDEB_TXRING (1U << 3) 75 unsigned int eqos_debug; /* Default value */ 76 #define DPRINTF(FLAG, FORMAT, ...) \ 77 if (sc->sc_debug & FLAG) \ 78 device_printf(sc->sc_dev, "%s: " FORMAT, \ 79 __func__, ##__VA_ARGS__) 80 #else 81 #define DPRINTF(FLAG, FORMAT, ...) ((void)0) 82 #endif 83 84 #define CALLOUT_FLAGS CALLOUT_MPSAFE 85 86 #define DESC_BOUNDARY ((sizeof(bus_size_t) > 4) ? (1ULL << 32) : 0) 87 #define DESC_ALIGN sizeof(struct eqos_dma_desc) 88 #define TX_DESC_COUNT EQOS_DMA_DESC_COUNT 89 #define TX_DESC_SIZE (TX_DESC_COUNT * DESC_ALIGN) 90 #define RX_DESC_COUNT EQOS_DMA_DESC_COUNT 91 #define RX_DESC_SIZE (RX_DESC_COUNT * DESC_ALIGN) 92 #define MII_BUSY_RETRY 1000 93 94 #define DESC_OFF(n) ((n) * sizeof(struct eqos_dma_desc)) 95 #define TX_SKIP(n, o) (((n) + (o)) % TX_DESC_COUNT) 96 #define TX_NEXT(n) TX_SKIP(n, 1) 97 #define RX_NEXT(n) (((n) + 1) % RX_DESC_COUNT) 98 99 #define TX_MAX_SEGS 128 100 101 #define EQOS_LOCK(sc) mutex_enter(&(sc)->sc_lock) 102 #define EQOS_UNLOCK(sc) mutex_exit(&(sc)->sc_lock) 103 #define EQOS_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_lock)) 104 105 #define EQOS_TXLOCK(sc) mutex_enter(&(sc)->sc_txlock) 106 #define EQOS_TXUNLOCK(sc) mutex_exit(&(sc)->sc_txlock) 107 #define EQOS_ASSERT_TXLOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_txlock)) 108 109 #define EQOS_HW_FEATURE_ADDR64_32BIT(sc) \ 110 (((sc)->sc_hw_feature[1] & GMAC_MAC_HW_FEATURE1_ADDR64_MASK) == \ 111 GMAC_MAC_HW_FEATURE1_ADDR64_32BIT) 112 113 114 #define RD4(sc, reg) \ 115 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 116 #define WR4(sc, reg, val) \ 117 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 118 119 /* 120 * Request interrupt on completion for every "rx_batch" # packets. 121 */ 122 int eqos_rx_batch = 16; 123 124 /* 125 * RX interrupt watchdog is triggered after "rx_wdt_count" * 256 system 126 * clock cycles. 127 */ 128 int eqos_rx_wdt_count = 160; 129 130 static void eqos_init_sysctls(struct eqos_softc *); 131 static int eqos_sysctl_tx_cur_handler(SYSCTLFN_PROTO); 132 static int eqos_sysctl_tx_end_handler(SYSCTLFN_PROTO); 133 static int eqos_sysctl_rx_cur_handler(SYSCTLFN_PROTO); 134 static int eqos_sysctl_rx_end_handler(SYSCTLFN_PROTO); 135 #ifdef EQOS_DEBUG 136 static int eqos_sysctl_debug_handler(SYSCTLFN_PROTO); 137 #endif 138 139 static int 140 eqos_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 141 { 142 struct eqos_softc * const sc = device_private(dev); 143 uint32_t addr; 144 int retry; 145 146 addr = sc->sc_clock_range | 147 (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 148 (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | 149 GMAC_MAC_MDIO_ADDRESS_GOC_READ | GMAC_MAC_MDIO_ADDRESS_GB; 150 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 151 152 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 153 delay(10); 154 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); 155 if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { 156 *val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; 157 break; 158 } 159 } 160 if (retry == 0) { 161 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 162 phy, reg); 163 return ETIMEDOUT; 164 } 165 166 return 0; 167 } 168 169 static int 170 eqos_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 171 { 172 struct eqos_softc * const sc = device_private(dev); 173 uint32_t addr; 174 int retry; 175 176 WR4(sc, GMAC_MAC_MDIO_DATA, val); 177 178 addr = sc->sc_clock_range | 179 (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 180 (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | 181 GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | GMAC_MAC_MDIO_ADDRESS_GB; 182 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 183 184 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 185 delay(10); 186 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); 187 if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { 188 break; 189 } 190 } 191 if (retry == 0) { 192 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 193 phy, reg); 194 return ETIMEDOUT; 195 } 196 197 return 0; 198 } 199 200 static void 201 eqos_update_link(struct eqos_softc *sc) 202 { 203 struct mii_data * const mii = &sc->sc_mii; 204 uint64_t baudrate; 205 uint32_t conf, flow; 206 207 baudrate = ifmedia_baudrate(mii->mii_media_active); 208 209 conf = RD4(sc, GMAC_MAC_CONFIGURATION); 210 switch (baudrate) { 211 case IF_Mbps(10): 212 conf |= GMAC_MAC_CONFIGURATION_PS; 213 conf &= ~GMAC_MAC_CONFIGURATION_FES; 214 break; 215 case IF_Mbps(100): 216 conf |= GMAC_MAC_CONFIGURATION_PS; 217 conf |= GMAC_MAC_CONFIGURATION_FES; 218 break; 219 case IF_Gbps(1): 220 conf &= ~GMAC_MAC_CONFIGURATION_PS; 221 conf &= ~GMAC_MAC_CONFIGURATION_FES; 222 break; 223 case IF_Mbps(2500ULL): 224 conf &= ~GMAC_MAC_CONFIGURATION_PS; 225 conf |= GMAC_MAC_CONFIGURATION_FES; 226 break; 227 } 228 229 /* Set duplex. */ 230 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 231 conf |= GMAC_MAC_CONFIGURATION_DM; 232 } else { 233 conf &= ~GMAC_MAC_CONFIGURATION_DM; 234 } 235 WR4(sc, GMAC_MAC_CONFIGURATION, conf); 236 237 /* Set TX flow control. */ 238 if (mii->mii_media_active & IFM_ETH_TXPAUSE) { 239 flow = GMAC_MAC_Q0_TX_FLOW_CTRL_TFE; 240 flow |= 0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT; 241 } else 242 flow = 0; 243 WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, flow); 244 245 /* Set RX flow control. */ 246 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 247 flow = GMAC_MAC_RX_FLOW_CTRL_RFE; 248 else 249 flow = 0; 250 WR4(sc, GMAC_MAC_RX_FLOW_CTRL, flow); 251 } 252 253 static void 254 eqos_mii_statchg(struct ifnet *ifp) 255 { 256 struct eqos_softc * const sc = ifp->if_softc; 257 258 eqos_update_link(sc); 259 } 260 261 static void 262 eqos_dma_sync(struct eqos_softc *sc, bus_dmamap_t map, 263 u_int start, u_int end, u_int total, int flags) 264 { 265 if (end > start) { 266 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(start), 267 DESC_OFF(end) - DESC_OFF(start), flags); 268 } else { 269 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(start), 270 DESC_OFF(total) - DESC_OFF(start), flags); 271 if (end > 0) { 272 bus_dmamap_sync(sc->sc_dmat, map, DESC_OFF(0), 273 DESC_OFF(end) - DESC_OFF(0), flags); 274 } 275 } 276 } 277 278 static uint32_t 279 eqos_setup_txdesc(struct eqos_softc *sc, int index, int flags, 280 bus_addr_t paddr, u_int len, u_int total_len) 281 { 282 struct eqos_dma_desc desc; 283 uint32_t tdes2, tdes3; 284 285 DPRINTF(EDEB_TXRING, "preparing desc %u\n", index); 286 287 EQOS_ASSERT_TXLOCKED(sc); 288 289 if (paddr == 0 || len == 0) { 290 DPRINTF(EDEB_TXRING, 291 "tx for desc %u done!\n", index); 292 KASSERT(flags == 0); 293 tdes2 = 0; 294 tdes3 = 0; 295 --sc->sc_tx.queued; 296 } else { 297 tdes2 = (flags & EQOS_TDES3_TX_LD) ? EQOS_TDES2_TX_IOC : 0; 298 tdes3 = flags; 299 ++sc->sc_tx.queued; 300 } 301 302 KASSERT(!EQOS_HW_FEATURE_ADDR64_32BIT(sc) || 303 ((uint64_t)paddr >> 32) == 0); 304 305 desc.tdes0 = htole32((uint32_t)paddr); 306 desc.tdes1 = htole32((uint32_t)((uint64_t)paddr >> 32)); 307 desc.tdes2 = htole32(tdes2 | len); 308 desc.tdes3 = htole32(tdes3 | total_len); 309 310 sc->sc_tx.desc_ring[index] = desc; 311 312 return tdes3 | total_len; 313 } 314 315 static int 316 eqos_setup_txbuf(struct eqos_softc *sc, int index, struct mbuf *m, 317 uint32_t *ptdes3) 318 { 319 bus_dma_segment_t *segs; 320 int error, nsegs, cur, i; 321 uint32_t flags, first_tdes3; 322 bool nospace; 323 324 DPRINTF(EDEB_TXRING, "preparing desc %u\n", index); 325 326 /* at least one descriptor free ? */ 327 if (sc->sc_tx.queued >= TX_DESC_COUNT - 1) 328 return -1; 329 330 error = bus_dmamap_load_mbuf(sc->sc_dmat, 331 sc->sc_tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 332 if (error == EFBIG) { 333 device_printf(sc->sc_dev, 334 "TX packet needs too many DMA segments, dropping...\n"); 335 return -2; 336 } 337 if (error != 0) { 338 device_printf(sc->sc_dev, 339 "TX packet cannot be mapped, retried...\n"); 340 return 0; 341 } 342 343 segs = sc->sc_tx.buf_map[index].map->dm_segs; 344 nsegs = sc->sc_tx.buf_map[index].map->dm_nsegs; 345 346 nospace = sc->sc_tx.queued >= TX_DESC_COUNT - nsegs; 347 if (nospace) { 348 bus_dmamap_unload(sc->sc_dmat, 349 sc->sc_tx.buf_map[index].map); 350 /* XXX coalesce and retry ? */ 351 return -1; 352 } 353 354 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.buf_map[index].map, 355 0, sc->sc_tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 356 357 /* stored in same index as loaded map */ 358 sc->sc_tx.buf_map[index].mbuf = m; 359 360 flags = EQOS_TDES3_TX_FD; 361 if (ptdes3 == NULL) { 362 flags |= EQOS_TDES3_TX_OWN; 363 } 364 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) { 365 flags |= EQOS_TDES3_TX_CIC_FULL; 366 } else if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 367 flags |= EQOS_TDES3_TX_CIC_IPHDR; 368 } 369 first_tdes3 = 0; 370 371 for (cur = index, i = 0; i < nsegs; i++) { 372 uint32_t tdes3; 373 374 if (i == nsegs - 1) 375 flags |= EQOS_TDES3_TX_LD; 376 377 tdes3 = eqos_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 378 segs[i].ds_len, m->m_pkthdr.len); 379 cur = TX_NEXT(cur); 380 381 if (i == 0) { 382 first_tdes3 = tdes3; 383 flags &= ~EQOS_TDES3_TX_FD; 384 } 385 flags |= EQOS_TDES3_TX_OWN; 386 } 387 388 if (ptdes3 != NULL) { 389 *ptdes3 = first_tdes3; 390 } 391 392 DPRINTF(EDEB_TXRING, "passing tx desc %u to hardware, cur: %u, " 393 "next: %u, queued: %u, owned: %u\n", 394 index, sc->sc_tx.cur, sc->sc_tx.next, sc->sc_tx.queued, 395 ptdes3 == NULL); 396 397 return nsegs; 398 } 399 400 static void 401 eqos_setup_rxdesc(struct eqos_softc *sc, int index, bus_addr_t paddr) 402 { 403 struct eqos_dma_desc desc; 404 uint32_t tdes3 = EQOS_TDES3_RX_OWN | EQOS_TDES3_RX_BUF1V; 405 406 if ((index % eqos_rx_batch) == 0) { 407 tdes3 |= EQOS_TDES3_RX_IOC; 408 } 409 410 DPRINTF(EDEB_RXRING, "preparing desc %u\n", index); 411 412 desc.tdes0 = htole32((uint32_t)paddr); 413 desc.tdes1 = htole32((uint32_t)((uint64_t)paddr >> 32)); 414 desc.tdes2 = htole32(0); 415 desc.tdes3 = 0; 416 417 sc->sc_rx.desc_ring[index] = desc; 418 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.desc_map, 419 DESC_OFF(index), offsetof(struct eqos_dma_desc, tdes3), 420 BUS_DMASYNC_PREWRITE); 421 sc->sc_rx.desc_ring[index].tdes3 = htole32(tdes3); 422 } 423 424 static int 425 eqos_setup_rxbuf(struct eqos_softc *sc, int index, struct mbuf *m) 426 { 427 int error; 428 429 DPRINTF(EDEB_RXRING, "preparing desc %u\n", index); 430 431 #if MCLBYTES >= (EQOS_RXDMA_SIZE + ETHER_ALIGN) 432 m_adj(m, ETHER_ALIGN); 433 #endif 434 435 error = bus_dmamap_load_mbuf(sc->sc_dmat, 436 sc->sc_rx.buf_map[index].map, m, BUS_DMA_READ | BUS_DMA_NOWAIT); 437 if (error != 0) 438 return error; 439 440 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.buf_map[index].map, 441 0, sc->sc_rx.buf_map[index].map->dm_mapsize, 442 BUS_DMASYNC_PREREAD); 443 444 sc->sc_rx.buf_map[index].mbuf = m; 445 446 return 0; 447 } 448 449 static struct mbuf * 450 eqos_alloc_mbufcl(struct eqos_softc *sc) 451 { 452 struct mbuf *m; 453 454 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 455 if (m != NULL) 456 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 457 MCLAIM(m, &sc->sc_ec.ec_rx_mowner); 458 459 return m; 460 } 461 462 static void 463 eqos_enable_intr(struct eqos_softc *sc) 464 { 465 466 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 467 GMAC_DMA_CHAN0_INTR_ENABLE_NIE | 468 GMAC_DMA_CHAN0_INTR_ENABLE_AIE | 469 GMAC_DMA_CHAN0_INTR_ENABLE_FBE | 470 GMAC_DMA_CHAN0_INTR_ENABLE_RIE | 471 GMAC_DMA_CHAN0_INTR_ENABLE_TIE); 472 } 473 474 static void 475 eqos_disable_intr(struct eqos_softc *sc) 476 { 477 478 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0); 479 } 480 481 static void 482 eqos_tick(void *softc) 483 { 484 struct eqos_softc * const sc = softc; 485 struct mii_data * const mii = &sc->sc_mii; 486 487 EQOS_LOCK(sc); 488 mii_tick(mii); 489 if ((sc->sc_if_flags & IFF_RUNNING) != 0) 490 callout_schedule(&sc->sc_stat_ch, hz); 491 EQOS_UNLOCK(sc); 492 } 493 494 static uint32_t 495 eqos_bitrev32(uint32_t x) 496 { 497 498 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 499 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 500 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 501 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 502 503 return (x >> 16) | (x << 16); 504 } 505 506 static void 507 eqos_setup_rxfilter(struct eqos_softc *sc) 508 { 509 struct ethercom *ec = &sc->sc_ec; 510 struct ifnet * const ifp = &ec->ec_if; 511 uint32_t pfil, crc, hashreg, hashbit, hash[2]; 512 struct ether_multi *enm; 513 struct ether_multistep step; 514 const uint8_t *eaddr; 515 uint32_t val; 516 517 EQOS_ASSERT_LOCKED(sc); 518 519 pfil = RD4(sc, GMAC_MAC_PACKET_FILTER); 520 521 /* turn off promiscous mode */ 522 /* turn off the receive-all mode */ 523 /* turn off the non-UDP/TCP filter */ 524 /* turn off broadcast filter */ 525 /* turn off pass all multicast mode */ 526 /* turn on hash or perfect mode */ 527 /* turn off source address filter */ 528 /* turn off inverse source address filter */ 529 /* turn off inverse destination address filter */ 530 /* turn off multicast hash table matching */ 531 /* turn off unicast hash table matching */ 532 /* XXX keep IP Layer3+4 filter */ 533 /* XXX keep VLAN tag filter */ 534 /* don't pass control packets */ 535 pfil &= ~(GMAC_MAC_PACKET_FILTER_PR | 536 GMAC_MAC_PACKET_FILTER_RA | 537 GMAC_MAC_PACKET_FILTER_DNTU | 538 GMAC_MAC_PACKET_FILTER_DBF | 539 GMAC_MAC_PACKET_FILTER_PM | 540 GMAC_MAC_PACKET_FILTER_SAF | 541 GMAC_MAC_PACKET_FILTER_SAIF | 542 GMAC_MAC_PACKET_FILTER_DAIF | 543 GMAC_MAC_PACKET_FILTER_HMC | 544 GMAC_MAC_PACKET_FILTER_HUC | 545 GMAC_MAC_PACKET_FILTER_PCF_MASK); 546 pfil |= GMAC_MAC_PACKET_FILTER_HPF; 547 548 ETHER_LOCK(ec); 549 if ((sc->sc_if_flags & IFF_PROMISC) != 0) { 550 ec->ec_flags |= ETHER_F_ALLMULTI; 551 /* enable promiscous mode */ 552 pfil |= GMAC_MAC_PACKET_FILTER_PR; 553 /* also receive control packets */ 554 pfil |= GMAC_MAC_PACKET_FILTER_PCF_ALL; 555 /* ignored */ 556 hash[0] = hash[1] = ~0U; 557 } else { 558 hash[0] = hash[1] = 0U; 559 ec->ec_flags &= ~ETHER_F_ALLMULTI; 560 /* enable multicast hash table matching */ 561 pfil |= GMAC_MAC_PACKET_FILTER_HMC; 562 ETHER_FIRST_MULTI(step, ec, enm); 563 while (enm != NULL) { 564 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 565 ETHER_ADDR_LEN) != 0) { 566 /* disable multicast hash table matching */ 567 pfil &= ~GMAC_MAC_PACKET_FILTER_HMC; 568 /* pass all multicast instead */ 569 pfil |= GMAC_MAC_PACKET_FILTER_PM; 570 /* ignored */ 571 hash[0] = hash[1] = ~0U; 572 break; 573 } 574 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 575 crc &= 0x7f; 576 crc = eqos_bitrev32(~crc) >> 26; 577 hashreg = (crc >> 5); 578 hashbit = (crc & 0x1f); 579 hash[hashreg] |= (1 << hashbit); 580 ETHER_NEXT_MULTI(step, enm); 581 } 582 } 583 ETHER_UNLOCK(ec); 584 585 /* Write our unicast address */ 586 eaddr = CLLADDR(ifp->if_sadl); 587 val = eaddr[4] | (eaddr[5] << 8); 588 val = __SHIFTIN(val, GMAC_MAC_ADDRESS_HIGH_ADDR) 589 | GMAC_MAC_ADDRESS_HIGH_AE; 590 WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val); 591 val = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | 592 (eaddr[3] << 24); 593 WR4(sc, GMAC_MAC_ADDRESS0_LOW, val); 594 595 /* Multicast hash filters */ 596 /* XXX assumes 64 bit hashtable size */ 597 WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]); 598 WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]); 599 600 DPRINTF(EDEB_NOTE, "writing new packet filter config " 601 "%08x, hash[1]=%08x, hash[0]=%08x\n", pfil, hash[1], hash[0]); 602 /* Packet filter config */ 603 WR4(sc, GMAC_MAC_PACKET_FILTER, pfil); 604 } 605 606 static void 607 eqos_setup_coe(struct eqos_softc *sc) 608 { 609 struct ifnet * const ifp = &sc->sc_ec.ec_if; 610 const uint64_t if_capenable = ifp->if_capenable; 611 uint32_t val; 612 613 EQOS_ASSERT_LOCKED(sc); 614 615 val = RD4(sc, GMAC_MAC_CONFIGURATION); 616 if ((if_capenable & (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 617 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 618 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx)) != 0) { 619 val |= GMAC_MAC_CONFIGURATION_IPC; 620 } else { 621 val &= ~GMAC_MAC_CONFIGURATION_IPC; 622 } 623 WR4(sc, GMAC_MAC_CONFIGURATION, val); 624 } 625 626 static int 627 eqos_reset(struct eqos_softc *sc) 628 { 629 uint32_t val; 630 int retry; 631 632 WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR); 633 for (retry = 2000; retry > 0; retry--) { 634 delay(1000); 635 val = RD4(sc, GMAC_DMA_MODE); 636 if ((val & GMAC_DMA_MODE_SWR) == 0) { 637 return 0; 638 } 639 } 640 641 device_printf(sc->sc_dev, "reset timeout!\n"); 642 return ETIMEDOUT; 643 } 644 645 static void 646 eqos_init_rings(struct eqos_softc *sc, int qid) 647 { 648 sc->sc_tx.cur = sc->sc_tx.next = sc->sc_tx.queued = 0; 649 650 sc->sc_rx_discarding = false; 651 m_freem(sc->sc_rx_receiving_m); 652 sc->sc_rx_receiving_m = NULL; 653 sc->sc_rx_receiving_m_last = NULL; 654 655 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI, 656 (uint32_t)((uint64_t)sc->sc_tx.desc_ring_paddr >> 32)); 657 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR, 658 (uint32_t)sc->sc_tx.desc_ring_paddr); 659 WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1); 660 DPRINTF(EDEB_TXRING, "tx ring paddr %lx with %u descriptors\n", 661 sc->sc_tx.desc_ring_paddr, TX_DESC_COUNT); 662 663 sc->sc_rx.cur = sc->sc_rx.next = sc->sc_rx.queued = 0; 664 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI, 665 (uint32_t)((uint64_t)sc->sc_rx.desc_ring_paddr >> 32)); 666 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR, 667 (uint32_t)sc->sc_rx.desc_ring_paddr); 668 WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1); 669 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, 670 (uint32_t)sc->sc_rx.desc_ring_paddr + 671 DESC_OFF((sc->sc_rx.cur - 1) % RX_DESC_COUNT)); 672 DPRINTF(EDEB_RXRING, "rx ring paddr %lx with %u descriptors\n", 673 sc->sc_rx.desc_ring_paddr, RX_DESC_COUNT); 674 } 675 676 static int 677 eqos_init_locked(struct eqos_softc *sc) 678 { 679 struct ifnet * const ifp = &sc->sc_ec.ec_if; 680 struct mii_data * const mii = &sc->sc_mii; 681 uint32_t val, tqs, rqs; 682 683 EQOS_ASSERT_LOCKED(sc); 684 EQOS_ASSERT_TXLOCKED(sc); 685 686 if ((ifp->if_flags & IFF_RUNNING) != 0) { 687 /* Only Setup RX filter and checksum offload */ 688 eqos_setup_rxfilter(sc); 689 eqos_setup_coe(sc); 690 return 0; 691 } 692 693 /* Setup TX/RX rings */ 694 eqos_init_rings(sc, 0); 695 696 /* Setup RX filter */ 697 sc->sc_if_flags = ifp->if_flags; 698 eqos_setup_rxfilter(sc); 699 700 /* Setup checksum offload */ 701 eqos_setup_coe(sc); 702 703 WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->sc_csr_clock / 1000000) - 1); 704 705 /* RX interrupt watchdog timer */ 706 WR4(sc, GMAC_DMA_CHAN0_RX_WATCHDOG, 707 GMAC_DMA_CHAN0_RX_WATCHDOG_RWTU_256 | eqos_rx_wdt_count); 708 709 /* Enable transmit and receive DMA */ 710 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); 711 val &= ~GMAC_DMA_CHAN0_CONTROL_DSL_MASK; 712 val |= ((DESC_ALIGN - 16) / 8) << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT; 713 val |= GMAC_DMA_CHAN0_CONTROL_PBLX8; 714 WR4(sc, GMAC_DMA_CHAN0_CONTROL, val); 715 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); 716 val &= ~GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_MASK; 717 val |= (sc->sc_dma_txpbl << GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_SHIFT); 718 val |= GMAC_DMA_CHAN0_TX_CONTROL_OSP; 719 val |= GMAC_DMA_CHAN0_TX_CONTROL_START; 720 WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); 721 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); 722 val &= ~(GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK | 723 GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_MASK); 724 val |= (MCLBYTES << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT); 725 val |= (sc->sc_dma_rxpbl << GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_SHIFT); 726 val |= GMAC_DMA_CHAN0_RX_CONTROL_START; 727 WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); 728 729 /* Disable counters */ 730 WR4(sc, GMAC_MMC_CONTROL, 731 GMAC_MMC_CONTROL_CNTFREEZ | 732 GMAC_MMC_CONTROL_CNTPRST | 733 GMAC_MMC_CONTROL_CNTPRSTLVL); 734 735 /* Configure operation modes */ 736 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, 737 GMAC_MTL_TXQ0_OPERATION_MODE_TSF | 738 GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN); 739 WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, 740 GMAC_MTL_RXQ0_OPERATION_MODE_RSF | 741 GMAC_MTL_RXQ0_OPERATION_MODE_FEP | 742 GMAC_MTL_RXQ0_OPERATION_MODE_FUP); 743 744 /* 745 * TX/RX fifo size in hw_feature[1] are log2(n/128), and 746 * TQS/RQS in TXQ0/RXQ0_OPERATION_MODE are n/256-1. 747 */ 748 tqs = (128 << __SHIFTOUT(sc->sc_hw_feature[1], 749 GMAC_MAC_HW_FEATURE1_TXFIFOSIZE) / 256) - 1; 750 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 751 val &= ~GMAC_MTL_TXQ0_OPERATION_MODE_TQS; 752 val |= __SHIFTIN(tqs, GMAC_MTL_TXQ0_OPERATION_MODE_TQS); 753 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val); 754 755 rqs = (128 << __SHIFTOUT(sc->sc_hw_feature[1], 756 GMAC_MAC_HW_FEATURE1_RXFIFOSIZE) / 256) - 1; 757 val = RD4(sc, GMAC_MTL_RXQ0_OPERATION_MODE); 758 val &= ~GMAC_MTL_RXQ0_OPERATION_MODE_RQS; 759 val |= __SHIFTIN(rqs, GMAC_MTL_RXQ0_OPERATION_MODE_RQS); 760 WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, val); 761 762 /* 763 * Disable flow control. 764 * It'll be configured later from the negotiated result. 765 */ 766 WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, 0); 767 WR4(sc, GMAC_MAC_RX_FLOW_CTRL, 0); 768 769 /* set RX queue mode. must be in DCB mode. */ 770 val = __SHIFTIN(GMAC_RXQ_CTRL0_EN_DCB, GMAC_RXQ_CTRL0_EN_MASK); 771 WR4(sc, GMAC_RXQ_CTRL0, val); 772 773 /* Enable transmitter and receiver */ 774 val = RD4(sc, GMAC_MAC_CONFIGURATION); 775 val |= GMAC_MAC_CONFIGURATION_BE; 776 val |= GMAC_MAC_CONFIGURATION_JD; 777 val |= GMAC_MAC_CONFIGURATION_JE; 778 val |= GMAC_MAC_CONFIGURATION_DCRS; 779 val |= GMAC_MAC_CONFIGURATION_TE; 780 val |= GMAC_MAC_CONFIGURATION_RE; 781 WR4(sc, GMAC_MAC_CONFIGURATION, val); 782 783 /* Enable interrupts */ 784 eqos_enable_intr(sc); 785 786 EQOS_ASSERT_TXLOCKED(sc); 787 sc->sc_txrunning = true; 788 789 ifp->if_flags |= IFF_RUNNING; 790 sc->sc_if_flags |= IFF_RUNNING; 791 792 mii_mediachg(mii); 793 callout_schedule(&sc->sc_stat_ch, hz); 794 795 return 0; 796 } 797 798 static int 799 eqos_init(struct ifnet *ifp) 800 { 801 struct eqos_softc * const sc = ifp->if_softc; 802 int error; 803 804 EQOS_LOCK(sc); 805 EQOS_TXLOCK(sc); 806 error = eqos_init_locked(sc); 807 EQOS_TXUNLOCK(sc); 808 EQOS_UNLOCK(sc); 809 810 return error; 811 } 812 813 static void 814 eqos_stop_locked(struct eqos_softc *sc, int disable) 815 { 816 struct ifnet * const ifp = &sc->sc_ec.ec_if; 817 uint32_t val; 818 int retry; 819 820 EQOS_ASSERT_LOCKED(sc); 821 822 EQOS_TXLOCK(sc); 823 sc->sc_txrunning = false; 824 EQOS_TXUNLOCK(sc); 825 826 callout_halt(&sc->sc_stat_ch, &sc->sc_lock); 827 828 mii_down(&sc->sc_mii); 829 830 /* Disable receiver */ 831 val = RD4(sc, GMAC_MAC_CONFIGURATION); 832 val &= ~GMAC_MAC_CONFIGURATION_RE; 833 WR4(sc, GMAC_MAC_CONFIGURATION, val); 834 835 /* Stop receive DMA */ 836 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); 837 val &= ~GMAC_DMA_CHAN0_RX_CONTROL_START; 838 WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); 839 840 /* Stop transmit DMA */ 841 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); 842 val &= ~GMAC_DMA_CHAN0_TX_CONTROL_START; 843 WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); 844 845 if (disable) { 846 /* Flush data in the TX FIFO */ 847 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 848 val |= GMAC_MTL_TXQ0_OPERATION_MODE_FTQ; 849 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val); 850 /* Wait for flush to complete */ 851 for (retry = 10000; retry > 0; retry--) { 852 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 853 if ((val & GMAC_MTL_TXQ0_OPERATION_MODE_FTQ) == 0) { 854 break; 855 } 856 delay(1); 857 } 858 if (retry == 0) { 859 device_printf(sc->sc_dev, 860 "timeout flushing TX queue\n"); 861 } 862 } 863 864 /* Disable transmitter */ 865 val = RD4(sc, GMAC_MAC_CONFIGURATION); 866 val &= ~GMAC_MAC_CONFIGURATION_TE; 867 WR4(sc, GMAC_MAC_CONFIGURATION, val); 868 869 /* Disable interrupts */ 870 eqos_disable_intr(sc); 871 872 workqueue_wait(sc->sc_wq, &sc->sc_rxwork); 873 874 sc->sc_if_flags &= ~IFF_RUNNING; 875 ifp->if_flags &= ~IFF_RUNNING; 876 } 877 878 static void 879 eqos_stop(struct ifnet *ifp, int disable) 880 { 881 struct eqos_softc * const sc = ifp->if_softc; 882 883 EQOS_LOCK(sc); 884 eqos_stop_locked(sc, disable); 885 EQOS_UNLOCK(sc); 886 } 887 888 static void 889 eqos_rxintr(struct eqos_softc *sc, int qid) 890 { 891 struct ifnet * const ifp = &sc->sc_ec.ec_if; 892 const uint64_t if_capenable = ifp->if_capenable; 893 int error, index, pkts = 0; 894 struct mbuf *m, *m0, *new_m, *mprev; 895 uint32_t tdes3; 896 bool discarding; 897 898 /* restore jumboframe context */ 899 discarding = sc->sc_rx_discarding; 900 m0 = sc->sc_rx_receiving_m; 901 mprev = sc->sc_rx_receiving_m_last; 902 903 DPRINTF(EDEB_INTR, "qid: %u, discarding %u, m0 %p\n", 904 qid, discarding, m0); 905 906 for (index = sc->sc_rx.cur; ; index = RX_NEXT(index)) { 907 eqos_dma_sync(sc, sc->sc_rx.desc_map, 908 index, index + 1, RX_DESC_COUNT, 909 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 910 911 tdes3 = le32toh(sc->sc_rx.desc_ring[index].tdes3); 912 if ((tdes3 & EQOS_TDES3_RX_OWN) != 0) { 913 break; 914 } 915 916 /* now discarding untill the last packet */ 917 if (discarding) 918 goto rx_next; 919 920 if ((tdes3 & EQOS_TDES3_RX_CTXT) != 0) 921 goto rx_next; /* ignore receive context descriptor */ 922 923 /* error packet? */ 924 if ((tdes3 & (EQOS_TDES3_RX_CE | EQOS_TDES3_RX_RWT | 925 EQOS_TDES3_RX_OE | EQOS_TDES3_RX_RE | 926 EQOS_TDES3_RX_DE)) != 0) { 927 #ifdef EQOS_DEBUG 928 char buf[128]; 929 snprintb(buf, sizeof(buf), 930 "\177\020" 931 "b\x1e" "CTXT\0" /* 30 */ 932 "b\x18" "CE\0" /* 24 */ 933 "b\x17" "GP\0" /* 23 */ 934 "b\x16" "WDT\0" /* 22 */ 935 "b\x15" "OE\0" /* 21 */ 936 "b\x14" "RE\0" /* 20 */ 937 "b\x13" "DE\0" /* 19 */ 938 "b\x0f" "ES\0" /* 15 */ 939 "\0", tdes3); 940 DPRINTF(EDEB_NOTE, 941 "rxdesc[%d].tdes3=%s\n", index, buf); 942 #endif 943 if_statinc(ifp, if_ierrors); 944 if (m0 != NULL) { 945 m_freem(m0); 946 m0 = mprev = NULL; 947 } 948 discarding = true; 949 goto rx_next; 950 } 951 952 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.buf_map[index].map, 953 0, sc->sc_rx.buf_map[index].map->dm_mapsize, 954 BUS_DMASYNC_POSTREAD); 955 m = sc->sc_rx.buf_map[index].mbuf; 956 new_m = eqos_alloc_mbufcl(sc); 957 if (new_m == NULL) { 958 /* 959 * cannot allocate new mbuf. discard this received 960 * packet, and reuse the mbuf for next. 961 */ 962 if_statinc(ifp, if_ierrors); 963 if (m0 != NULL) { 964 /* also discard the halfway jumbo packet */ 965 m_freem(m0); 966 m0 = mprev = NULL; 967 } 968 discarding = true; 969 goto rx_next; 970 } 971 bus_dmamap_unload(sc->sc_dmat, 972 sc->sc_rx.buf_map[index].map); 973 error = eqos_setup_rxbuf(sc, index, new_m); 974 if (error) 975 panic("%s: %s: unable to load RX mbuf. error=%d", 976 device_xname(sc->sc_dev), __func__, error); 977 978 if (m0 == NULL) { 979 m0 = m; 980 } else { 981 if (m->m_flags & M_PKTHDR) 982 m_remove_pkthdr(m); 983 mprev->m_next = m; 984 } 985 mprev = m; 986 987 if ((tdes3 & EQOS_TDES3_RX_LD) == 0) { 988 /* to be continued in the next segment */ 989 m->m_len = EQOS_RXDMA_SIZE; 990 } else { 991 /* last segment */ 992 uint32_t totallen = tdes3 & EQOS_TDES3_RX_LENGTH_MASK; 993 uint32_t mlen = totallen % EQOS_RXDMA_SIZE; 994 if (mlen == 0) 995 mlen = EQOS_RXDMA_SIZE; 996 m->m_len = mlen; 997 m0->m_pkthdr.len = totallen; 998 m_set_rcvif(m0, ifp); 999 m0->m_flags |= M_HASFCS; 1000 m0->m_nextpkt = NULL; 1001 1002 if ((tdes3 & EQOS_TDES3_RX_RS1V) != 0 && 1003 (if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) { 1004 uint32_t tdes1 = 1005 le32toh(sc->sc_rx.desc_ring[index].tdes1); 1006 1007 if ((tdes1 & (EQOS_TDES1_RX_IPCE | 1008 EQOS_TDES1_RX_IPCB)) == 0) { 1009 if ((tdes1 & EQOS_TDES1_RX_IPV4) != 0) { 1010 m0->m_pkthdr.csum_flags |= 1011 M_CSUM_IPv4; 1012 } 1013 switch (tdes1 & EQOS_TDES1_RX_PT_MASK) { 1014 case EQOS_TDES1_RX_PT_UDP: 1015 m0->m_pkthdr.csum_flags |= 1016 M_CSUM_UDPv4; 1017 break; 1018 case EQOS_TDES1_RX_PT_TCP: 1019 m0->m_pkthdr.csum_flags |= 1020 M_CSUM_TCPv4; 1021 break; 1022 } 1023 } 1024 } 1025 1026 if_percpuq_enqueue(ifp->if_percpuq, m0); 1027 m0 = mprev = NULL; 1028 1029 ++pkts; 1030 } 1031 1032 rx_next: 1033 if (discarding && (tdes3 & EQOS_TDES3_RX_LD) != 0) 1034 discarding = false; 1035 1036 eqos_setup_rxdesc(sc, index, 1037 sc->sc_rx.buf_map[index].map->dm_segs[0].ds_addr); 1038 eqos_dma_sync(sc, sc->sc_rx.desc_map, 1039 index, index + 1, RX_DESC_COUNT, 1040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1041 1042 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, 1043 (uint32_t)sc->sc_rx.desc_ring_paddr + DESC_OFF(index)); 1044 } 1045 /* save jumboframe context */ 1046 sc->sc_rx_discarding = discarding; 1047 sc->sc_rx_receiving_m = m0; 1048 sc->sc_rx_receiving_m_last = mprev; 1049 1050 DPRINTF(EDEB_RXRING, "sc_rx.cur %u -> %u\n", 1051 sc->sc_rx.cur, index); 1052 sc->sc_rx.cur = index; 1053 1054 if (pkts != 0) { 1055 rnd_add_uint32(&sc->sc_rndsource, pkts); 1056 } 1057 } 1058 1059 static void 1060 eqos_txintr(struct eqos_softc *sc, int qid) 1061 { 1062 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1063 struct eqos_bufmap *bmap; 1064 struct eqos_dma_desc *desc; 1065 uint32_t tdes3; 1066 int i, pkts = 0; 1067 1068 DPRINTF(EDEB_INTR, "qid: %u\n", qid); 1069 1070 EQOS_ASSERT_TXLOCKED(sc); 1071 1072 eqos_dma_sync(sc, sc->sc_tx.desc_map, 1073 sc->sc_tx.next, sc->sc_tx.cur, TX_DESC_COUNT, 1074 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1075 1076 for (i = sc->sc_tx.next; sc->sc_tx.queued > 0; i = TX_NEXT(i)) { 1077 KASSERT(sc->sc_tx.queued > 0); 1078 KASSERT(sc->sc_tx.queued <= TX_DESC_COUNT); 1079 1080 desc = &sc->sc_tx.desc_ring[i]; 1081 tdes3 = le32toh(desc->tdes3); 1082 if ((tdes3 & EQOS_TDES3_TX_OWN) != 0) { 1083 break; 1084 } 1085 bmap = &sc->sc_tx.buf_map[i]; 1086 if (bmap->mbuf != NULL) { 1087 bus_dmamap_sync(sc->sc_dmat, bmap->map, 1088 0, bmap->map->dm_mapsize, 1089 BUS_DMASYNC_POSTWRITE); 1090 bus_dmamap_unload(sc->sc_dmat, bmap->map); 1091 m_freem(bmap->mbuf); 1092 bmap->mbuf = NULL; 1093 ++pkts; 1094 } 1095 1096 --sc->sc_tx.queued; 1097 1098 /* Last descriptor in a packet contains DMA status */ 1099 if ((tdes3 & EQOS_TDES3_TX_LD) != 0) { 1100 if ((tdes3 & EQOS_TDES3_TX_DE) != 0) { 1101 device_printf(sc->sc_dev, 1102 "TX [%u] desc error: 0x%08x\n", 1103 i, tdes3); 1104 if_statinc(ifp, if_oerrors); 1105 } else if ((tdes3 & EQOS_TDES3_TX_ES) != 0) { 1106 device_printf(sc->sc_dev, 1107 "TX [%u] tx error: 0x%08x\n", 1108 i, tdes3); 1109 if_statinc(ifp, if_oerrors); 1110 } else { 1111 if_statinc(ifp, if_opackets); 1112 } 1113 } 1114 1115 } 1116 1117 sc->sc_tx.next = i; 1118 1119 if (pkts != 0) { 1120 rnd_add_uint32(&sc->sc_rndsource, pkts); 1121 } 1122 } 1123 1124 static void 1125 eqos_start_locked(struct eqos_softc *sc) 1126 { 1127 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1128 struct mbuf *m; 1129 int cnt, nsegs, start; 1130 uint32_t first_tdes3 = 0; 1131 uint32_t *ptdes3 = &first_tdes3; 1132 1133 EQOS_ASSERT_TXLOCKED(sc); 1134 1135 if (!sc->sc_txrunning) 1136 return; 1137 1138 for (cnt = 0, start = sc->sc_tx.cur; ; cnt++) { 1139 if (sc->sc_tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 1140 DPRINTF(EDEB_TXRING, "%u sc_tx.queued, ring full\n", 1141 sc->sc_tx.queued); 1142 break; 1143 } 1144 1145 IFQ_POLL(&ifp->if_snd, m); 1146 if (m == NULL) 1147 break; 1148 1149 nsegs = eqos_setup_txbuf(sc, sc->sc_tx.cur, m, ptdes3); 1150 if (nsegs <= 0) { 1151 DPRINTF(EDEB_TXRING, "eqos_setup_txbuf failed " 1152 "with %d\n", nsegs); 1153 if (nsegs == -2) { 1154 IFQ_DEQUEUE(&ifp->if_snd, m); 1155 m_freem(m); 1156 continue; 1157 } 1158 break; 1159 } 1160 1161 IFQ_DEQUEUE(&ifp->if_snd, m); 1162 bpf_mtap(ifp, m, BPF_D_OUT); 1163 1164 sc->sc_tx.cur = TX_SKIP(sc->sc_tx.cur, nsegs); 1165 ptdes3 = NULL; 1166 } 1167 1168 DPRINTF(EDEB_TXRING, "tx loop -> cnt = %u, cur: %u, next: %u, " 1169 "queued: %u\n", cnt, sc->sc_tx.cur, sc->sc_tx.next, 1170 sc->sc_tx.queued); 1171 1172 if (cnt != 0) { 1173 eqos_dma_sync(sc, sc->sc_tx.desc_map, 1174 start, sc->sc_tx.cur, TX_DESC_COUNT, 1175 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1176 1177 /* 1178 * Defer setting OWN bit on the first descriptor until all 1179 * descriptors have been updated. The hardware will not try to 1180 * process any descriptors past the first one still owned by 1181 * software (i.e., with the OWN bit clear). 1182 */ 1183 sc->sc_tx.desc_ring[start].tdes3 = 1184 htole32(first_tdes3 | EQOS_TDES3_TX_OWN); 1185 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.desc_map, 1186 DESC_OFF(start) + offsetof(struct eqos_dma_desc, tdes3), 1187 sizeof(uint32_t), 1188 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1189 1190 /* Start and run TX DMA */ 1191 DPRINTF(EDEB_TXRING, "sending desc %u at %lx upto " 1192 "%u-1 at %lx cur tx desc: %x cur tx buf: %x\n", start, 1193 (uint32_t)sc->sc_tx.desc_ring_paddr + DESC_OFF(start), 1194 sc->sc_tx.cur, 1195 (uint32_t)sc->sc_tx.desc_ring_paddr + 1196 DESC_OFF(sc->sc_tx.cur), 1197 RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC), 1198 RD4(sc, GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR)); 1199 WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR, 1200 (uint32_t)sc->sc_tx.desc_ring_paddr + 1201 DESC_OFF(sc->sc_tx.cur)); 1202 } 1203 } 1204 1205 static void 1206 eqos_start(struct ifnet *ifp) 1207 { 1208 struct eqos_softc * const sc = ifp->if_softc; 1209 1210 EQOS_TXLOCK(sc); 1211 eqos_start_locked(sc); 1212 EQOS_TXUNLOCK(sc); 1213 } 1214 1215 static void 1216 eqos_receive(struct work *wk, void *arg) 1217 { 1218 struct eqos_softc *sc = arg; 1219 uint32_t dma_intr_enable; 1220 1221 EQOS_LOCK(sc); 1222 1223 eqos_rxintr(sc, 0); 1224 1225 dma_intr_enable = RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE); 1226 dma_intr_enable |= GMAC_DMA_CHAN0_INTR_ENABLE_RIE; 1227 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable); 1228 1229 EQOS_UNLOCK(sc); 1230 } 1231 1232 static void 1233 eqos_txsoftintr(void *arg) 1234 { 1235 struct eqos_softc *sc = arg; 1236 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1237 uint32_t dma_intr_enable; 1238 1239 EQOS_TXLOCK(sc); 1240 eqos_txintr(sc, 0); 1241 EQOS_TXUNLOCK(sc); 1242 1243 if_schedule_deferred_start(ifp); 1244 1245 EQOS_LOCK(sc); 1246 dma_intr_enable = RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE); 1247 dma_intr_enable |= GMAC_DMA_CHAN0_INTR_ENABLE_TIE; 1248 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable); 1249 EQOS_UNLOCK(sc); 1250 } 1251 1252 static void 1253 eqos_intr_mtl(struct eqos_softc *sc, uint32_t mtl_status) 1254 { 1255 uint32_t debug_data __unused = 0, ictrl = 0; 1256 1257 if (mtl_status == 0) 1258 return; 1259 1260 /* Drain the errors reported by MTL_INTERRUPT_STATUS */ 1261 sc->sc_ev_mtl.ev_count++; 1262 1263 if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_DBGIS) != 0) { 1264 debug_data = RD4(sc, GMAC_MTL_FIFO_DEBUG_DATA); 1265 sc->sc_ev_mtl_debugdata.ev_count++; 1266 } 1267 if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_Q0IS) != 0) { 1268 uint32_t new_status = 0; 1269 1270 ictrl = RD4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS); 1271 if ((ictrl & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS) != 0) { 1272 new_status |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS; 1273 sc->sc_ev_mtl_rxovfis.ev_count++; 1274 } 1275 if ((ictrl & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS) != 0) { 1276 new_status |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS; 1277 sc->sc_ev_mtl_txovfis.ev_count++; 1278 } 1279 if (new_status) { 1280 new_status |= (ictrl & 1281 (GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE | 1282 GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE)); 1283 WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, new_status); 1284 } 1285 } 1286 DPRINTF(EDEB_INTR, 1287 "GMAC_MTL_INTERRUPT_STATUS = 0x%08X, " 1288 "GMAC_MTL_FIFO_DEBUG_DATA = 0x%08X, " 1289 "GMAC_MTL_INTERRUPT_STATUS_Q0IS = 0x%08X\n", 1290 mtl_status, debug_data, ictrl); 1291 } 1292 1293 int 1294 eqos_intr(void *arg) 1295 { 1296 struct eqos_softc * const sc = arg; 1297 uint32_t mac_status, mtl_status, dma_status, dma_intr_enable, 1298 rx_tx_status; 1299 bool do_txintr = false; 1300 1301 EQOS_LOCK(sc); 1302 1303 sc->sc_ev_intr.ev_count++; 1304 1305 mac_status = RD4(sc, GMAC_MAC_INTERRUPT_STATUS); 1306 mac_status &= RD4(sc, GMAC_MAC_INTERRUPT_ENABLE); 1307 1308 if (mac_status) { 1309 sc->sc_ev_mac.ev_count++; 1310 DPRINTF(EDEB_INTR, 1311 "GMAC_MAC_INTERRUPT_STATUS = 0x%08X\n", mac_status); 1312 } 1313 1314 mtl_status = RD4(sc, GMAC_MTL_INTERRUPT_STATUS); 1315 eqos_intr_mtl(sc, mtl_status); 1316 1317 dma_intr_enable = RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE); 1318 dma_status = RD4(sc, GMAC_DMA_CHAN0_STATUS); 1319 dma_status &= dma_intr_enable; 1320 if (dma_status) { 1321 WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status); 1322 } 1323 1324 if ((dma_status & GMAC_DMA_CHAN0_STATUS_RI) != 0) { 1325 dma_intr_enable &= ~GMAC_DMA_CHAN0_INTR_ENABLE_RIE; 1326 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable); 1327 workqueue_enqueue(sc->sc_wq, &sc->sc_rxwork, NULL); 1328 sc->sc_ev_rxintr.ev_count++; 1329 } 1330 1331 if ((dma_status & GMAC_DMA_CHAN0_STATUS_TI) != 0) { 1332 do_txintr = true; 1333 dma_intr_enable &= ~GMAC_DMA_CHAN0_INTR_ENABLE_TIE; 1334 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, dma_intr_enable); 1335 sc->sc_ev_txintr.ev_count++; 1336 } 1337 1338 rx_tx_status = RD4(sc, GMAC_MAC_RX_TX_STATUS); 1339 1340 EQOS_UNLOCK(sc); 1341 1342 if ((mac_status | mtl_status | dma_status) == 0) { 1343 DPRINTF(EDEB_NOTE, "spurious interrupt?!\n"); 1344 } 1345 1346 if (rx_tx_status) { 1347 sc->sc_ev_status.ev_count++; 1348 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_RWT) != 0) 1349 sc->sc_ev_rwt.ev_count++; 1350 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_EXCOL) != 0) 1351 sc->sc_ev_excol.ev_count++; 1352 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_LCOL) != 0) 1353 sc->sc_ev_lcol.ev_count++; 1354 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_EXDEF) != 0) 1355 sc->sc_ev_exdef.ev_count++; 1356 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_LCARR) != 0) 1357 sc->sc_ev_lcarr.ev_count++; 1358 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_NCARR) != 0) 1359 sc->sc_ev_ncarr.ev_count++; 1360 if ((rx_tx_status & GMAC_MAC_RX_TX_STATUS_TJT) != 0) 1361 sc->sc_ev_tjt.ev_count++; 1362 1363 DPRINTF(EDEB_INTR, "GMAC_MAC_RX_TX_STATUS = 0x%08x\n", 1364 rx_tx_status); 1365 } 1366 1367 if (do_txintr) { 1368 softint_schedule(sc->sc_tx_si); 1369 } 1370 1371 return 1; 1372 } 1373 1374 static int 1375 eqos_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1376 { 1377 struct eqos_softc * const sc = ifp->if_softc; 1378 int error; 1379 1380 switch (cmd) { 1381 case SIOCADDMULTI: 1382 case SIOCDELMULTI: 1383 break; 1384 default: 1385 KASSERT(IFNET_LOCKED(ifp)); 1386 } 1387 1388 switch (cmd) { 1389 case SIOCSIFMTU: { 1390 struct ifreq * const ifr = (struct ifreq *)data; 1391 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > EQOS_MAX_MTU) { 1392 error = EINVAL; 1393 } else { 1394 ifp->if_mtu = ifr->ifr_mtu; 1395 error = 0; /* no need ENETRESET */ 1396 } 1397 break; 1398 } 1399 default: { 1400 const int s = splnet(); 1401 error = ether_ioctl(ifp, cmd, data); 1402 splx(s); 1403 1404 if (error != ENETRESET) 1405 break; 1406 1407 error = 0; 1408 1409 if (cmd == SIOCSIFCAP) 1410 error = (*ifp->if_init)(ifp); 1411 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1412 EQOS_LOCK(sc); 1413 if ((sc->sc_if_flags & IFF_RUNNING) != 0) 1414 eqos_setup_rxfilter(sc); 1415 EQOS_UNLOCK(sc); 1416 } 1417 break; 1418 } 1419 } 1420 1421 return error; 1422 } 1423 1424 static int 1425 eqos_ifflags_cb(struct ethercom *ec) 1426 { 1427 struct ifnet * const ifp = &ec->ec_if; 1428 struct eqos_softc * const sc = ifp->if_softc; 1429 int ret = 0; 1430 1431 KASSERT(IFNET_LOCKED(ifp)); 1432 EQOS_LOCK(sc); 1433 1434 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1435 sc->sc_if_flags = ifp->if_flags; 1436 1437 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 1438 ret = ENETRESET; 1439 } else if ((change & IFF_PROMISC) != 0) { 1440 if ((sc->sc_if_flags & IFF_RUNNING) != 0) 1441 eqos_setup_rxfilter(sc); 1442 } 1443 EQOS_UNLOCK(sc); 1444 1445 return ret; 1446 } 1447 1448 1449 static void 1450 eqos_get_eaddr(struct eqos_softc *sc, uint8_t *eaddr) 1451 { 1452 uint32_t maclo, machi; 1453 1454 if (ether_getaddr(sc->sc_dev, eaddr)) { 1455 return; 1456 } 1457 1458 maclo = RD4(sc, GMAC_MAC_ADDRESS0_LOW); 1459 machi = __SHIFTOUT(RD4(sc, GMAC_MAC_ADDRESS0_HIGH), 1460 GMAC_MAC_ADDRESS_HIGH_ADDR); 1461 if (maclo == 0xFFFFFFFF && machi == 0xFFFF) { 1462 /* Create one */ 1463 maclo = 0x00f2 | (cprng_strong32() << 16); 1464 machi = cprng_strong32() & 0xffff; 1465 } else if (maclo & 0x00000001) { 1466 aprint_error_dev(sc->sc_dev, 1467 "Wrong MAC address. Clearing the multicast bit.\n"); 1468 maclo &= ~0x00000001; 1469 } 1470 1471 eaddr[0] = maclo & 0xff; 1472 eaddr[1] = (maclo >> 8) & 0xff; 1473 eaddr[2] = (maclo >> 16) & 0xff; 1474 eaddr[3] = (maclo >> 24) & 0xff; 1475 eaddr[4] = machi & 0xff; 1476 eaddr[5] = (machi >> 8) & 0xff; 1477 } 1478 1479 static void 1480 eqos_get_dma_pbl(struct eqos_softc *sc) 1481 { 1482 prop_dictionary_t prop = device_properties(sc->sc_dev); 1483 uint32_t pbl; 1484 1485 /* Set default values. */ 1486 sc->sc_dma_txpbl = sc->sc_dma_rxpbl = EQOS_DMA_PBL_DEFAULT; 1487 1488 /* Get values from props. */ 1489 if (prop_dictionary_get_uint32(prop, "snps,pbl", &pbl) && pbl) 1490 sc->sc_dma_txpbl = sc->sc_dma_rxpbl = pbl; 1491 if (prop_dictionary_get_uint32(prop, "snps,txpbl", &pbl) && pbl) 1492 sc->sc_dma_txpbl = pbl; 1493 if (prop_dictionary_get_uint32(prop, "snps,rxpbl", &pbl) && pbl) 1494 sc->sc_dma_rxpbl = pbl; 1495 } 1496 1497 static void 1498 eqos_axi_configure(struct eqos_softc *sc) 1499 { 1500 uint32_t val; 1501 u_int uival; 1502 1503 val = RD4(sc, GMAC_DMA_SYSBUS_MODE); 1504 1505 /* XXX are MB and FB mutually-exclusive? XXX */ 1506 if (device_getprop_bool(sc->sc_dev, "snps,mixed-burst")) { 1507 val |= GMAC_DMA_SYSBUS_MODE_MB; 1508 } 1509 if (device_getprop_bool(sc->sc_dev, "snps,fixed-burst")) { 1510 val |= GMAC_DMA_SYSBUS_MODE_FB; 1511 } 1512 if (device_getprop_uint(sc->sc_dev, "snps,wr_osr_lmt", &uival)) { 1513 val &= ~GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; 1514 val |= (uival << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) & 1515 GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; 1516 } 1517 if (device_getprop_uint(sc->sc_dev, "snps,rd_osr_lmt", &uival)) { 1518 val &= ~GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; 1519 val |= (uival << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) & 1520 GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; 1521 } 1522 1523 if (!EQOS_HW_FEATURE_ADDR64_32BIT(sc)) { 1524 val |= GMAC_DMA_SYSBUS_MODE_EAME; 1525 } 1526 1527 /* XXX snps,kbbe XXX */ 1528 /* XXX snps,blen XXX */ 1529 1530 /* XXX */ 1531 val |= GMAC_DMA_SYSBUS_MODE_BLEN16; 1532 val |= GMAC_DMA_SYSBUS_MODE_BLEN8; 1533 val |= GMAC_DMA_SYSBUS_MODE_BLEN4; 1534 1535 WR4(sc, GMAC_DMA_SYSBUS_MODE, val); 1536 } 1537 1538 static int 1539 eqos_setup_dma(struct eqos_softc *sc, int qid) 1540 { 1541 struct mbuf *m; 1542 int error, nsegs, i; 1543 1544 /* Set back pointer */ 1545 sc->sc_tx.sc = sc; 1546 sc->sc_rx.sc = sc; 1547 1548 /* Setup TX ring */ 1549 error = bus_dmamap_create(sc->sc_dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 1550 DESC_BOUNDARY, BUS_DMA_WAITOK, &sc->sc_tx.desc_map); 1551 if (error) { 1552 return error; 1553 } 1554 error = bus_dmamem_alloc(sc->sc_dmat, TX_DESC_SIZE, DESC_ALIGN, 1555 DESC_BOUNDARY, &sc->sc_tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1556 if (error) { 1557 return error; 1558 } 1559 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_tx.desc_dmaseg, nsegs, 1560 TX_DESC_SIZE, (void *)&sc->sc_tx.desc_ring, 1561 BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1562 if (error) { 1563 return error; 1564 } 1565 error = bus_dmamap_load(sc->sc_dmat, sc->sc_tx.desc_map, 1566 sc->sc_tx.desc_ring, TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1567 if (error) { 1568 return error; 1569 } 1570 sc->sc_tx.desc_ring_paddr = sc->sc_tx.desc_map->dm_segs[0].ds_addr; 1571 1572 memset(sc->sc_tx.desc_ring, 0, TX_DESC_SIZE); 1573 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx.desc_map, 0, TX_DESC_SIZE, 1574 BUS_DMASYNC_PREWRITE); 1575 1576 sc->sc_tx.queued = TX_DESC_COUNT; 1577 for (i = 0; i < TX_DESC_COUNT; i++) { 1578 error = bus_dmamap_create(sc->sc_dmat, EQOS_TXDMA_SIZE, 1579 TX_MAX_SEGS, MCLBYTES, 0, 1580 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1581 &sc->sc_tx.buf_map[i].map); 1582 if (error != 0) { 1583 device_printf(sc->sc_dev, 1584 "cannot create TX buffer map\n"); 1585 return error; 1586 } 1587 EQOS_TXLOCK(sc); 1588 eqos_setup_txdesc(sc, i, 0, 0, 0, 0); 1589 EQOS_TXUNLOCK(sc); 1590 } 1591 1592 /* Setup RX ring */ 1593 error = bus_dmamap_create(sc->sc_dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 1594 DESC_BOUNDARY, BUS_DMA_WAITOK, &sc->sc_rx.desc_map); 1595 if (error) { 1596 return error; 1597 } 1598 error = bus_dmamem_alloc(sc->sc_dmat, RX_DESC_SIZE, DESC_ALIGN, 1599 DESC_BOUNDARY, &sc->sc_rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1600 if (error) { 1601 return error; 1602 } 1603 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_rx.desc_dmaseg, nsegs, 1604 RX_DESC_SIZE, (void *)&sc->sc_rx.desc_ring, 1605 BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1606 if (error) { 1607 return error; 1608 } 1609 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rx.desc_map, 1610 sc->sc_rx.desc_ring, RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1611 if (error) { 1612 return error; 1613 } 1614 sc->sc_rx.desc_ring_paddr = sc->sc_rx.desc_map->dm_segs[0].ds_addr; 1615 1616 memset(sc->sc_rx.desc_ring, 0, RX_DESC_SIZE); 1617 1618 for (i = 0; i < RX_DESC_COUNT; i++) { 1619 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1620 RX_DESC_COUNT, MCLBYTES, 0, 1621 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1622 &sc->sc_rx.buf_map[i].map); 1623 if (error != 0) { 1624 device_printf(sc->sc_dev, 1625 "cannot create RX buffer map\n"); 1626 return error; 1627 } 1628 if ((m = eqos_alloc_mbufcl(sc)) == NULL) { 1629 device_printf(sc->sc_dev, "cannot allocate RX mbuf\n"); 1630 return ENOMEM; 1631 } 1632 error = eqos_setup_rxbuf(sc, i, m); 1633 if (error != 0) { 1634 device_printf(sc->sc_dev, "cannot create RX buffer\n"); 1635 return error; 1636 } 1637 eqos_setup_rxdesc(sc, i, 1638 sc->sc_rx.buf_map[i].map->dm_segs[0].ds_addr); 1639 } 1640 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.desc_map, 1641 0, sc->sc_rx.desc_map->dm_mapsize, 1642 BUS_DMASYNC_PREWRITE); 1643 1644 aprint_debug_dev(sc->sc_dev, "TX ring @ 0x%lX, RX ring @ 0x%lX\n", 1645 sc->sc_tx.desc_ring_paddr, sc->sc_rx.desc_ring_paddr); 1646 1647 return 0; 1648 } 1649 1650 int 1651 eqos_attach(struct eqos_softc *sc) 1652 { 1653 struct mii_data * const mii = &sc->sc_mii; 1654 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1655 uint8_t eaddr[ETHER_ADDR_LEN]; 1656 u_int userver, snpsver; 1657 int error; 1658 int n; 1659 1660 #ifdef EQOS_DEBUG 1661 /* Load the default debug flags. */ 1662 sc->sc_debug = eqos_debug; 1663 #endif 1664 1665 const uint32_t ver = RD4(sc, GMAC_MAC_VERSION); 1666 userver = (ver & GMAC_MAC_VERSION_USERVER_MASK) >> 1667 GMAC_MAC_VERSION_USERVER_SHIFT; 1668 snpsver = ver & GMAC_MAC_VERSION_SNPSVER_MASK; 1669 1670 if ((snpsver < 0x51) || (snpsver > 0x52)) { 1671 aprint_error(": EQOS version 0x%02x not supported\n", 1672 snpsver); 1673 return ENXIO; 1674 } 1675 1676 if (sc->sc_csr_clock < 20000000) { 1677 aprint_error(": CSR clock too low\n"); 1678 return EINVAL; 1679 } else if (sc->sc_csr_clock < 35000000) { 1680 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_20_35; 1681 } else if (sc->sc_csr_clock < 60000000) { 1682 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_35_60; 1683 } else if (sc->sc_csr_clock < 100000000) { 1684 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_60_100; 1685 } else if (sc->sc_csr_clock < 150000000) { 1686 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_100_150; 1687 } else if (sc->sc_csr_clock < 250000000) { 1688 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_150_250; 1689 } else if (sc->sc_csr_clock < 300000000) { 1690 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_250_300; 1691 } else if (sc->sc_csr_clock < 500000000) { 1692 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_300_500; 1693 } else if (sc->sc_csr_clock < 800000000) { 1694 sc->sc_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_500_800; 1695 } else { 1696 aprint_error(": CSR clock too high\n"); 1697 return EINVAL; 1698 } 1699 1700 for (n = 0; n < 4; n++) { 1701 sc->sc_hw_feature[n] = RD4(sc, GMAC_MAC_HW_FEATURE(n)); 1702 } 1703 1704 aprint_naive("\n"); 1705 aprint_normal(": DesignWare EQOS ver 0x%02x (0x%02x)\n", 1706 snpsver, userver); 1707 aprint_verbose_dev(sc->sc_dev, "hw features %08x %08x %08x %08x\n", 1708 sc->sc_hw_feature[0], sc->sc_hw_feature[1], 1709 sc->sc_hw_feature[2], sc->sc_hw_feature[3]); 1710 1711 if (EQOS_HW_FEATURE_ADDR64_32BIT(sc)) { 1712 bus_dma_tag_t ntag; 1713 1714 error = bus_dmatag_subregion(sc->sc_dmat, 0, UINT32_MAX, 1715 &ntag, 0); 1716 if (error) { 1717 aprint_error_dev(sc->sc_dev, 1718 "failed to restrict DMA: %d\n", error); 1719 return error; 1720 } 1721 aprint_verbose_dev(sc->sc_dev, "using 32-bit DMA\n"); 1722 sc->sc_dmat = ntag; 1723 } 1724 1725 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET); 1726 mutex_init(&sc->sc_txlock, MUTEX_DEFAULT, IPL_NET); 1727 callout_init(&sc->sc_stat_ch, CALLOUT_MPSAFE); 1728 callout_setfunc(&sc->sc_stat_ch, eqos_tick, sc); 1729 1730 eqos_get_eaddr(sc, eaddr); 1731 aprint_normal_dev(sc->sc_dev, 1732 "Ethernet address %s\n", ether_sprintf(eaddr)); 1733 1734 /* Soft reset EMAC core */ 1735 error = eqos_reset(sc); 1736 if (error != 0) { 1737 return error; 1738 } 1739 1740 /* Get DMA burst length */ 1741 eqos_get_dma_pbl(sc); 1742 1743 /* Configure AXI Bus mode parameters */ 1744 eqos_axi_configure(sc); 1745 1746 /* Setup DMA descriptors */ 1747 if (eqos_setup_dma(sc, 0) != 0) { 1748 aprint_error_dev(sc->sc_dev, 1749 "failed to setup DMA descriptors\n"); 1750 return EINVAL; 1751 } 1752 1753 /* Receive workers */ 1754 error = workqueue_create(&sc->sc_wq, device_xname(sc->sc_dev), 1755 eqos_receive, sc, PRI_SOFTNET, IPL_NET, WQ_MPSAFE | WQ_PERCPU); 1756 if (error != 0) { 1757 aprint_error_dev(sc->sc_dev, 1758 "failed to create receive workqueue: %d\n", error); 1759 return error; 1760 } 1761 1762 /* Transmit softint */ 1763 sc->sc_tx_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 1764 eqos_txsoftintr, sc); 1765 1766 /* Setup ethernet interface */ 1767 ifp->if_softc = sc; 1768 snprintf(ifp->if_xname, IFNAMSIZ, "%s", device_xname(sc->sc_dev)); 1769 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1770 ifp->if_extflags = IFEF_MPSAFE; 1771 ifp->if_start = eqos_start; 1772 ifp->if_ioctl = eqos_ioctl; 1773 ifp->if_init = eqos_init; 1774 ifp->if_stop = eqos_stop; 1775 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1776 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1777 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1778 ifp->if_capenable = 0; 1779 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1780 IFQ_SET_READY(&ifp->if_snd); 1781 1782 /* 802.1Q VLAN-sized frames and jumbo frames are supported */ 1783 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1784 sc->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1785 1786 /* Attach MII driver */ 1787 sc->sc_ec.ec_mii = mii; 1788 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1789 mii->mii_ifp = ifp; 1790 mii->mii_readreg = eqos_mii_readreg; 1791 mii->mii_writereg = eqos_mii_writereg; 1792 mii->mii_statchg = eqos_mii_statchg; 1793 mii_attach(sc->sc_dev, mii, 0xffffffff, sc->sc_phy_id, MII_OFFSET_ANY, 1794 MIIF_DOPAUSE); 1795 1796 if (LIST_EMPTY(&mii->mii_phys)) { 1797 aprint_error_dev(sc->sc_dev, "no PHY found!\n"); 1798 return ENOENT; 1799 } 1800 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1801 1802 /* Master interrupt evcnt */ 1803 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 1804 NULL, device_xname(sc->sc_dev), "interrupts"); 1805 1806 /* Per-interrupt type, using main interrupt */ 1807 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1808 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rxintr"); 1809 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 1810 &sc->sc_ev_intr, device_xname(sc->sc_dev), "txintr"); 1811 evcnt_attach_dynamic(&sc->sc_ev_mac, EVCNT_TYPE_INTR, 1812 &sc->sc_ev_intr, device_xname(sc->sc_dev), "macstatus"); 1813 evcnt_attach_dynamic(&sc->sc_ev_mtl, EVCNT_TYPE_INTR, 1814 &sc->sc_ev_intr, device_xname(sc->sc_dev), "intrstatus"); 1815 evcnt_attach_dynamic(&sc->sc_ev_status, EVCNT_TYPE_INTR, 1816 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rxtxstatus"); 1817 1818 /* MAC Status specific type, using macstatus interrupt */ 1819 evcnt_attach_dynamic(&sc->sc_ev_mtl_debugdata, EVCNT_TYPE_INTR, 1820 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "debugdata"); 1821 evcnt_attach_dynamic(&sc->sc_ev_mtl_rxovfis, EVCNT_TYPE_INTR, 1822 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "rxovfis"); 1823 evcnt_attach_dynamic(&sc->sc_ev_mtl_txovfis, EVCNT_TYPE_INTR, 1824 &sc->sc_ev_mtl, device_xname(sc->sc_dev), "txovfis"); 1825 1826 /* RX/TX Status specific type, using rxtxstatus interrupt */ 1827 evcnt_attach_dynamic(&sc->sc_ev_rwt, EVCNT_TYPE_INTR, 1828 &sc->sc_ev_status, device_xname(sc->sc_dev), "rwt"); 1829 evcnt_attach_dynamic(&sc->sc_ev_excol, EVCNT_TYPE_INTR, 1830 &sc->sc_ev_status, device_xname(sc->sc_dev), "excol"); 1831 evcnt_attach_dynamic(&sc->sc_ev_lcol, EVCNT_TYPE_INTR, 1832 &sc->sc_ev_status, device_xname(sc->sc_dev), "lcol"); 1833 evcnt_attach_dynamic(&sc->sc_ev_exdef, EVCNT_TYPE_INTR, 1834 &sc->sc_ev_status, device_xname(sc->sc_dev), "exdef"); 1835 evcnt_attach_dynamic(&sc->sc_ev_lcarr, EVCNT_TYPE_INTR, 1836 &sc->sc_ev_status, device_xname(sc->sc_dev), "lcarr"); 1837 evcnt_attach_dynamic(&sc->sc_ev_ncarr, EVCNT_TYPE_INTR, 1838 &sc->sc_ev_status, device_xname(sc->sc_dev), "ncarr"); 1839 evcnt_attach_dynamic(&sc->sc_ev_tjt, EVCNT_TYPE_INTR, 1840 &sc->sc_ev_status, device_xname(sc->sc_dev), "tjt"); 1841 1842 /* Attach interface */ 1843 if_attach(ifp); 1844 if_deferred_start_init(ifp, NULL); 1845 1846 /* Attach ethernet interface */ 1847 ether_ifattach(ifp, eaddr); 1848 ether_set_ifflags_cb(&sc->sc_ec, eqos_ifflags_cb); 1849 1850 eqos_init_sysctls(sc); 1851 1852 rnd_attach_source(&sc->sc_rndsource, ifp->if_xname, RND_TYPE_NET, 1853 RND_FLAG_DEFAULT); 1854 1855 return 0; 1856 } 1857 1858 static void 1859 eqos_init_sysctls(struct eqos_softc *sc) 1860 { 1861 struct sysctllog **log; 1862 const struct sysctlnode *rnode, *qnode, *cnode; 1863 const char *dvname; 1864 int i, rv; 1865 1866 log = &sc->sc_sysctllog; 1867 dvname = device_xname(sc->sc_dev); 1868 1869 rv = sysctl_createv(log, 0, NULL, &rnode, 1870 0, CTLTYPE_NODE, dvname, 1871 SYSCTL_DESCR("eqos information and settings"), 1872 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 1873 if (rv != 0) 1874 goto err; 1875 1876 for (i = 0; i < 1; i++) { 1877 struct eqos_ring *txr = &sc->sc_tx; 1878 struct eqos_ring *rxr = &sc->sc_rx; 1879 const unsigned char *name = "q0"; 1880 1881 if (sysctl_createv(log, 0, &rnode, &qnode, 1882 0, CTLTYPE_NODE, 1883 name, SYSCTL_DESCR("Queue Name"), 1884 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL) != 0) 1885 break; 1886 1887 if (sysctl_createv(log, 0, &qnode, &cnode, 1888 CTLFLAG_READONLY, CTLTYPE_INT, 1889 "txs_cur", SYSCTL_DESCR("TX cur"), 1890 NULL, 0, &txr->cur, 1891 0, CTL_CREATE, CTL_EOL) != 0) 1892 break; 1893 if (sysctl_createv(log, 0, &qnode, &cnode, 1894 CTLFLAG_READONLY, CTLTYPE_INT, 1895 "txs_next", SYSCTL_DESCR("TX next"), 1896 NULL, 0, &txr->next, 1897 0, CTL_CREATE, CTL_EOL) != 0) 1898 break; 1899 if (sysctl_createv(log, 0, &qnode, &cnode, 1900 CTLFLAG_READONLY, CTLTYPE_INT, 1901 "txs_queued", SYSCTL_DESCR("TX queued"), 1902 NULL, 0, &txr->queued, 1903 0, CTL_CREATE, CTL_EOL) != 0) 1904 break; 1905 if (sysctl_createv(log, 0, &qnode, &cnode, 1906 CTLFLAG_READONLY, CTLTYPE_INT, 1907 "txr_cur", SYSCTL_DESCR("TX descriptor cur"), 1908 eqos_sysctl_tx_cur_handler, 0, (void *)txr, 1909 0, CTL_CREATE, CTL_EOL) != 0) 1910 break; 1911 if (sysctl_createv(log, 0, &qnode, &cnode, 1912 CTLFLAG_READONLY, CTLTYPE_INT, 1913 "txr_end", SYSCTL_DESCR("TX descriptor end"), 1914 eqos_sysctl_tx_end_handler, 0, (void *)txr, 1915 0, CTL_CREATE, CTL_EOL) != 0) 1916 break; 1917 if (sysctl_createv(log, 0, &qnode, &cnode, 1918 CTLFLAG_READONLY, CTLTYPE_INT, 1919 "rxs_cur", SYSCTL_DESCR("RX cur"), 1920 NULL, 0, &rxr->cur, 1921 0, CTL_CREATE, CTL_EOL) != 0) 1922 break; 1923 if (sysctl_createv(log, 0, &qnode, &cnode, 1924 CTLFLAG_READONLY, CTLTYPE_INT, 1925 "rxs_next", SYSCTL_DESCR("RX next"), 1926 NULL, 0, &rxr->next, 1927 0, CTL_CREATE, CTL_EOL) != 0) 1928 break; 1929 if (sysctl_createv(log, 0, &qnode, &cnode, 1930 CTLFLAG_READONLY, CTLTYPE_INT, 1931 "rxs_queued", SYSCTL_DESCR("RX queued"), 1932 NULL, 0, &rxr->queued, 1933 0, CTL_CREATE, CTL_EOL) != 0) 1934 break; 1935 if (sysctl_createv(log, 0, &qnode, &cnode, 1936 CTLFLAG_READONLY, CTLTYPE_INT, 1937 "rxr_cur", SYSCTL_DESCR("RX descriptor cur"), 1938 eqos_sysctl_rx_cur_handler, 0, (void *)rxr, 1939 0, CTL_CREATE, CTL_EOL) != 0) 1940 break; 1941 if (sysctl_createv(log, 0, &qnode, &cnode, 1942 CTLFLAG_READONLY, CTLTYPE_INT, 1943 "rxr_end", SYSCTL_DESCR("RX descriptor end"), 1944 eqos_sysctl_rx_end_handler, 0, (void *)rxr, 1945 0, CTL_CREATE, CTL_EOL) != 0) 1946 break; 1947 } 1948 1949 #ifdef EQOS_DEBUG 1950 rv = sysctl_createv(log, 0, &rnode, &cnode, CTLFLAG_READWRITE, 1951 CTLTYPE_INT, "debug_flags", 1952 SYSCTL_DESCR( 1953 "Debug flags:\n" \ 1954 "\t0x01 NOTE\n" \ 1955 "\t0x02 INTR\n" \ 1956 "\t0x04 RX RING\n" \ 1957 "\t0x08 TX RING\n"), 1958 eqos_sysctl_debug_handler, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL); 1959 #endif 1960 1961 return; 1962 1963 err: 1964 sc->sc_sysctllog = NULL; 1965 device_printf(sc->sc_dev, "%s: sysctl_createv failed, rv = %d\n", 1966 __func__, rv); 1967 } 1968 1969 static int 1970 eqos_sysctl_tx_cur_handler(SYSCTLFN_ARGS) 1971 { 1972 struct sysctlnode node = *rnode; 1973 struct eqos_ring *txq = (struct eqos_ring *)node.sysctl_data; 1974 struct eqos_softc *sc = txq->sc; 1975 uint32_t reg, index; 1976 1977 reg = RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC); 1978 #if 0 1979 printf("head = %08x\n", (uint32_t)sc->sc_tx.desc_ring_paddr); 1980 printf("cdesc = %08x\n", reg); 1981 printf("index = %zu\n", 1982 (reg - (uint32_t)sc->sc_tx.desc_ring_paddr) / 1983 sizeof(struct eqos_dma_desc)); 1984 #endif 1985 if (reg == 0) 1986 index = 0; 1987 else { 1988 index = (reg - (uint32_t)sc->sc_tx.desc_ring_paddr) / 1989 sizeof(struct eqos_dma_desc); 1990 } 1991 node.sysctl_data = &index; 1992 return sysctl_lookup(SYSCTLFN_CALL(&node)); 1993 } 1994 1995 static int 1996 eqos_sysctl_tx_end_handler(SYSCTLFN_ARGS) 1997 { 1998 struct sysctlnode node = *rnode; 1999 struct eqos_ring *txq = (struct eqos_ring *)node.sysctl_data; 2000 struct eqos_softc *sc = txq->sc; 2001 uint32_t reg, index; 2002 2003 reg = RD4(sc, GMAC_DMA_CHAN0_TX_END_ADDR); 2004 if (reg == 0) 2005 index = 0; 2006 else { 2007 index = (reg - (uint32_t)sc->sc_tx.desc_ring_paddr) / 2008 sizeof(struct eqos_dma_desc); 2009 } 2010 node.sysctl_data = &index; 2011 return sysctl_lookup(SYSCTLFN_CALL(&node)); 2012 } 2013 2014 static int 2015 eqos_sysctl_rx_cur_handler(SYSCTLFN_ARGS) 2016 { 2017 struct sysctlnode node = *rnode; 2018 struct eqos_ring *rxq = (struct eqos_ring *)node.sysctl_data; 2019 struct eqos_softc *sc = rxq->sc; 2020 uint32_t reg, index; 2021 2022 reg = RD4(sc, GMAC_DMA_CHAN0_CUR_RX_DESC); 2023 if (reg == 0) 2024 index = 0; 2025 else { 2026 index = (reg - (uint32_t)sc->sc_rx.desc_ring_paddr) / 2027 sizeof(struct eqos_dma_desc); 2028 } 2029 node.sysctl_data = &index; 2030 return sysctl_lookup(SYSCTLFN_CALL(&node)); 2031 } 2032 2033 static int 2034 eqos_sysctl_rx_end_handler(SYSCTLFN_ARGS) 2035 { 2036 struct sysctlnode node = *rnode; 2037 struct eqos_ring *rxq = (struct eqos_ring *)node.sysctl_data; 2038 struct eqos_softc *sc = rxq->sc; 2039 uint32_t reg, index; 2040 2041 reg = RD4(sc, GMAC_DMA_CHAN0_RX_END_ADDR); 2042 if (reg == 0) 2043 index = 0; 2044 else { 2045 index = (reg - (uint32_t)sc->sc_rx.desc_ring_paddr) / 2046 sizeof(struct eqos_dma_desc); 2047 } 2048 node.sysctl_data = &index; 2049 return sysctl_lookup(SYSCTLFN_CALL(&node)); 2050 } 2051 2052 #ifdef EQOS_DEBUG 2053 static int 2054 eqos_sysctl_debug_handler(SYSCTLFN_ARGS) 2055 { 2056 struct sysctlnode node = *rnode; 2057 struct eqos_softc *sc = (struct eqos_softc *)node.sysctl_data; 2058 uint32_t dflags; 2059 int error; 2060 2061 dflags = sc->sc_debug; 2062 node.sysctl_data = &dflags; 2063 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2064 2065 if (error || newp == NULL) 2066 return error; 2067 2068 sc->sc_debug = dflags; 2069 #if 0 2070 /* Addd debug code here if you want. */ 2071 #endif 2072 2073 return 0; 2074 } 2075 #endif 2076
Indexes created Sun Nov 01 00:25:34 UTC 2026