dwc_gmac.c revision 1.92 1 1.92 skrll /* $NetBSD: dwc_gmac.c,v 1.92 2024/08/10 12:11:14 skrll Exp $ */
2 1.18 jmcneill
3 1.1 martin /*-
4 1.1 martin * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
5 1.1 martin * All rights reserved.
6 1.1 martin *
7 1.1 martin * This code is derived from software contributed to The NetBSD Foundation
8 1.1 martin * by Matt Thomas of 3am Software Foundry and Martin Husemann.
9 1.1 martin *
10 1.1 martin * Redistribution and use in source and binary forms, with or without
11 1.1 martin * modification, are permitted provided that the following conditions
12 1.1 martin * are met:
13 1.1 martin * 1. Redistributions of source code must retain the above copyright
14 1.1 martin * notice, this list of conditions and the following disclaimer.
15 1.1 martin * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 martin * notice, this list of conditions and the following disclaimer in the
17 1.1 martin * documentation and/or other materials provided with the distribution.
18 1.1 martin *
19 1.1 martin * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 martin * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 martin * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 martin * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 martin * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 martin * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 martin * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 martin * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 martin * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 martin * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 martin * POSSIBILITY OF SUCH DAMAGE.
30 1.1 martin */
31 1.1 martin
32 1.1 martin /*
33 1.1 martin * This driver supports the Synopsis Designware GMAC core, as found
34 1.1 martin * on Allwinner A20 cores and others.
35 1.1 martin *
36 1.1 martin * Real documentation seems to not be available, the marketing product
37 1.1 martin * documents could be found here:
38 1.1 martin *
39 1.1 martin * http://www.synopsys.com/dw/ipdir.php?ds=dwc_ether_mac10_100_1000_unive
40 1.1 martin */
41 1.1 martin
42 1.1 martin #include <sys/cdefs.h>
43 1.1 martin
44 1.92 skrll __KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.92 2024/08/10 12:11:14 skrll Exp $");
45 1.7 martin
46 1.7 martin /* #define DWC_GMAC_DEBUG 1 */
47 1.1 martin
48 1.38 skrll #ifdef _KERNEL_OPT
49 1.1 martin #include "opt_inet.h"
50 1.38 skrll #endif
51 1.1 martin
52 1.1 martin #include <sys/param.h>
53 1.1 martin #include <sys/bus.h>
54 1.1 martin #include <sys/device.h>
55 1.1 martin #include <sys/intr.h>
56 1.1 martin #include <sys/systm.h>
57 1.1 martin #include <sys/sockio.h>
58 1.29 jmcneill #include <sys/cprng.h>
59 1.63 msaitoh #include <sys/rndsource.h>
60 1.1 martin
61 1.1 martin #include <net/if.h>
62 1.1 martin #include <net/if_ether.h>
63 1.1 martin #include <net/if_media.h>
64 1.1 martin #include <net/bpf.h>
65 1.1 martin #ifdef INET
66 1.1 martin #include <netinet/if_inarp.h>
67 1.1 martin #endif
68 1.1 martin
69 1.1 martin #include <dev/mii/miivar.h>
70 1.1 martin
71 1.1 martin #include <dev/ic/dwc_gmac_reg.h>
72 1.1 martin #include <dev/ic/dwc_gmac_var.h>
73 1.1 martin
74 1.56 msaitoh static int dwc_gmac_miibus_read_reg(device_t, int, int, uint16_t *);
75 1.56 msaitoh static int dwc_gmac_miibus_write_reg(device_t, int, int, uint16_t);
76 1.1 martin static void dwc_gmac_miibus_statchg(struct ifnet *);
77 1.1 martin
78 1.61 msaitoh static int dwc_gmac_reset(struct dwc_gmac_softc *);
79 1.79 mrg static void dwc_gmac_write_hwaddr(struct dwc_gmac_softc *, uint8_t[ETHER_ADDR_LEN]);
80 1.61 msaitoh static int dwc_gmac_alloc_dma_rings(struct dwc_gmac_softc *);
81 1.61 msaitoh static void dwc_gmac_free_dma_rings(struct dwc_gmac_softc *);
82 1.61 msaitoh static int dwc_gmac_alloc_rx_ring(struct dwc_gmac_softc *, struct dwc_gmac_rx_ring *);
83 1.61 msaitoh static void dwc_gmac_reset_rx_ring(struct dwc_gmac_softc *, struct dwc_gmac_rx_ring *);
84 1.61 msaitoh static void dwc_gmac_free_rx_ring(struct dwc_gmac_softc *, struct dwc_gmac_rx_ring *);
85 1.61 msaitoh static int dwc_gmac_alloc_tx_ring(struct dwc_gmac_softc *, struct dwc_gmac_tx_ring *);
86 1.61 msaitoh static void dwc_gmac_reset_tx_ring(struct dwc_gmac_softc *, struct dwc_gmac_tx_ring *);
87 1.61 msaitoh static void dwc_gmac_free_tx_ring(struct dwc_gmac_softc *, struct dwc_gmac_tx_ring *);
88 1.61 msaitoh static void dwc_gmac_txdesc_sync(struct dwc_gmac_softc *, int, int, int);
89 1.61 msaitoh static int dwc_gmac_init(struct ifnet *);
90 1.61 msaitoh static int dwc_gmac_init_locked(struct ifnet *);
91 1.61 msaitoh static void dwc_gmac_stop(struct ifnet *, int);
92 1.61 msaitoh static void dwc_gmac_stop_locked(struct ifnet *, int);
93 1.61 msaitoh static void dwc_gmac_start(struct ifnet *);
94 1.61 msaitoh static void dwc_gmac_start_locked(struct ifnet *);
95 1.61 msaitoh static int dwc_gmac_queue(struct dwc_gmac_softc *, struct mbuf *);
96 1.1 martin static int dwc_gmac_ioctl(struct ifnet *, u_long, void *);
97 1.61 msaitoh static void dwc_gmac_tx_intr(struct dwc_gmac_softc *);
98 1.61 msaitoh static void dwc_gmac_rx_intr(struct dwc_gmac_softc *);
99 1.61 msaitoh static void dwc_gmac_setmulti(struct dwc_gmac_softc *);
100 1.22 martin static int dwc_gmac_ifflags_cb(struct ethercom *);
101 1.55 martin static void dwc_gmac_desc_set_owned_by_dev(struct dwc_gmac_dev_dmadesc *);
102 1.55 martin static int dwc_gmac_desc_is_owned_by_dev(struct dwc_gmac_dev_dmadesc *);
103 1.55 martin static void dwc_gmac_desc_std_set_len(struct dwc_gmac_dev_dmadesc *, int);
104 1.55 martin static uint32_t dwc_gmac_desc_std_get_len(struct dwc_gmac_dev_dmadesc *);
105 1.55 martin static void dwc_gmac_desc_std_tx_init_flags(struct dwc_gmac_dev_dmadesc *);
106 1.55 martin static void dwc_gmac_desc_std_tx_set_first_frag(struct dwc_gmac_dev_dmadesc *);
107 1.55 martin static void dwc_gmac_desc_std_tx_set_last_frag(struct dwc_gmac_dev_dmadesc *);
108 1.55 martin static void dwc_gmac_desc_std_rx_init_flags(struct dwc_gmac_dev_dmadesc *);
109 1.55 martin static int dwc_gmac_desc_std_rx_has_error(struct dwc_gmac_dev_dmadesc *);
110 1.55 martin static void dwc_gmac_desc_enh_set_len(struct dwc_gmac_dev_dmadesc *, int);
111 1.55 martin static uint32_t dwc_gmac_desc_enh_get_len(struct dwc_gmac_dev_dmadesc *);
112 1.55 martin static void dwc_gmac_desc_enh_tx_init_flags(struct dwc_gmac_dev_dmadesc *);
113 1.55 martin static void dwc_gmac_desc_enh_tx_set_first_frag(struct dwc_gmac_dev_dmadesc *);
114 1.55 martin static void dwc_gmac_desc_enh_tx_set_last_frag(struct dwc_gmac_dev_dmadesc *);
115 1.55 martin static void dwc_gmac_desc_enh_rx_init_flags(struct dwc_gmac_dev_dmadesc *);
116 1.55 martin static int dwc_gmac_desc_enh_rx_has_error(struct dwc_gmac_dev_dmadesc *);
117 1.55 martin
118 1.55 martin static const struct dwc_gmac_desc_methods desc_methods_standard = {
119 1.55 martin .tx_init_flags = dwc_gmac_desc_std_tx_init_flags,
120 1.55 martin .tx_set_owned_by_dev = dwc_gmac_desc_set_owned_by_dev,
121 1.55 martin .tx_is_owned_by_dev = dwc_gmac_desc_is_owned_by_dev,
122 1.55 martin .tx_set_len = dwc_gmac_desc_std_set_len,
123 1.55 martin .tx_set_first_frag = dwc_gmac_desc_std_tx_set_first_frag,
124 1.55 martin .tx_set_last_frag = dwc_gmac_desc_std_tx_set_last_frag,
125 1.55 martin .rx_init_flags = dwc_gmac_desc_std_rx_init_flags,
126 1.55 martin .rx_set_owned_by_dev = dwc_gmac_desc_set_owned_by_dev,
127 1.55 martin .rx_is_owned_by_dev = dwc_gmac_desc_is_owned_by_dev,
128 1.55 martin .rx_set_len = dwc_gmac_desc_std_set_len,
129 1.55 martin .rx_get_len = dwc_gmac_desc_std_get_len,
130 1.55 martin .rx_has_error = dwc_gmac_desc_std_rx_has_error
131 1.55 martin };
132 1.55 martin
133 1.55 martin static const struct dwc_gmac_desc_methods desc_methods_enhanced = {
134 1.55 martin .tx_init_flags = dwc_gmac_desc_enh_tx_init_flags,
135 1.55 martin .tx_set_owned_by_dev = dwc_gmac_desc_set_owned_by_dev,
136 1.55 martin .tx_is_owned_by_dev = dwc_gmac_desc_is_owned_by_dev,
137 1.55 martin .tx_set_len = dwc_gmac_desc_enh_set_len,
138 1.55 martin .tx_set_first_frag = dwc_gmac_desc_enh_tx_set_first_frag,
139 1.55 martin .tx_set_last_frag = dwc_gmac_desc_enh_tx_set_last_frag,
140 1.55 martin .rx_init_flags = dwc_gmac_desc_enh_rx_init_flags,
141 1.55 martin .rx_set_owned_by_dev = dwc_gmac_desc_set_owned_by_dev,
142 1.55 martin .rx_is_owned_by_dev = dwc_gmac_desc_is_owned_by_dev,
143 1.55 martin .rx_set_len = dwc_gmac_desc_enh_set_len,
144 1.55 martin .rx_get_len = dwc_gmac_desc_enh_get_len,
145 1.55 martin .rx_has_error = dwc_gmac_desc_enh_rx_has_error
146 1.55 martin };
147 1.55 martin
148 1.1 martin
149 1.82 skrll #define TX_DESC_OFFSET(N) ((AWGE_RX_RING_COUNT + (N)) \
150 1.82 skrll * sizeof(struct dwc_gmac_dev_dmadesc))
151 1.82 skrll #define TX_NEXT(N) (((N) + 1) & (AWGE_TX_RING_COUNT - 1))
152 1.1 martin
153 1.82 skrll #define RX_DESC_OFFSET(N) ((N) * sizeof(struct dwc_gmac_dev_dmadesc))
154 1.82 skrll #define RX_NEXT(N) (((N) + 1) & (AWGE_RX_RING_COUNT - 1))
155 1.8 martin
156 1.8 martin
157 1.8 martin
158 1.61 msaitoh #define GMAC_DEF_DMA_INT_MASK (GMAC_DMA_INT_TIE | GMAC_DMA_INT_RIE | \
159 1.61 msaitoh GMAC_DMA_INT_NIE | GMAC_DMA_INT_AIE | \
160 1.61 msaitoh GMAC_DMA_INT_FBE | GMAC_DMA_INT_UNE)
161 1.61 msaitoh
162 1.61 msaitoh #define GMAC_DMA_INT_ERRORS (GMAC_DMA_INT_AIE | GMAC_DMA_INT_ERE | \
163 1.61 msaitoh GMAC_DMA_INT_FBE | \
164 1.61 msaitoh GMAC_DMA_INT_RWE | GMAC_DMA_INT_RUE | \
165 1.61 msaitoh GMAC_DMA_INT_UNE | GMAC_DMA_INT_OVE | \
166 1.10 martin GMAC_DMA_INT_TJE)
167 1.8 martin
168 1.8 martin #define AWIN_DEF_MAC_INTRMASK \
169 1.8 martin (AWIN_GMAC_MAC_INT_TSI | AWIN_GMAC_MAC_INT_ANEG | \
170 1.55 martin AWIN_GMAC_MAC_INT_LINKCHG)
171 1.1 martin
172 1.7 martin #ifdef DWC_GMAC_DEBUG
173 1.61 msaitoh static void dwc_gmac_dump_dma(struct dwc_gmac_softc *);
174 1.61 msaitoh static void dwc_gmac_dump_tx_desc(struct dwc_gmac_softc *);
175 1.61 msaitoh static void dwc_gmac_dump_rx_desc(struct dwc_gmac_softc *);
176 1.61 msaitoh static void dwc_dump_and_abort(struct dwc_gmac_softc *, const char *);
177 1.61 msaitoh static void dwc_dump_status(struct dwc_gmac_softc *);
178 1.61 msaitoh static void dwc_gmac_dump_ffilt(struct dwc_gmac_softc *, uint32_t);
179 1.7 martin #endif
180 1.7 martin
181 1.51 jmcneill int
182 1.57 martin dwc_gmac_attach(struct dwc_gmac_softc *sc, int phy_id, uint32_t mii_clk)
183 1.1 martin {
184 1.1 martin uint8_t enaddr[ETHER_ADDR_LEN];
185 1.91 skrll uint32_t maclo, machi, hwft;
186 1.1 martin struct mii_data * const mii = &sc->sc_mii;
187 1.1 martin struct ifnet * const ifp = &sc->sc_ec.ec_if;
188 1.5 martin prop_dictionary_t dict;
189 1.1 martin
190 1.1 martin mutex_init(&sc->sc_mdio_lock, MUTEX_DEFAULT, IPL_NET);
191 1.3 martin sc->sc_mii_clk = mii_clk & 7;
192 1.1 martin
193 1.5 martin dict = device_properties(sc->sc_dev);
194 1.5 martin prop_data_t ea = dict ? prop_dictionary_get(dict, "mac-address") : NULL;
195 1.5 martin if (ea != NULL) {
196 1.5 martin /*
197 1.75 andvar * If the MAC address is overridden by a device property,
198 1.5 martin * use that.
199 1.5 martin */
200 1.5 martin KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
201 1.5 martin KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
202 1.71 jmcneill memcpy(enaddr, prop_data_value(ea), ETHER_ADDR_LEN);
203 1.5 martin } else {
204 1.5 martin /*
205 1.5 martin * If we did not get an externaly configure address,
206 1.5 martin * try to read one from the current filter setup,
207 1.5 martin * before resetting the chip.
208 1.5 martin */
209 1.8 martin maclo = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
210 1.8 martin AWIN_GMAC_MAC_ADDR0LO);
211 1.8 martin machi = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
212 1.8 martin AWIN_GMAC_MAC_ADDR0HI);
213 1.14 jmcneill
214 1.14 jmcneill if (maclo == 0xffffffff && (machi & 0xffff) == 0xffff) {
215 1.29 jmcneill /* fake MAC address */
216 1.29 jmcneill maclo = 0x00f2 | (cprng_strong32() << 16);
217 1.29 jmcneill machi = cprng_strong32();
218 1.14 jmcneill }
219 1.14 jmcneill
220 1.1 martin enaddr[0] = maclo & 0x0ff;
221 1.1 martin enaddr[1] = (maclo >> 8) & 0x0ff;
222 1.1 martin enaddr[2] = (maclo >> 16) & 0x0ff;
223 1.1 martin enaddr[3] = (maclo >> 24) & 0x0ff;
224 1.1 martin enaddr[4] = machi & 0x0ff;
225 1.1 martin enaddr[5] = (machi >> 8) & 0x0ff;
226 1.1 martin }
227 1.1 martin
228 1.91 skrll const uint32_t ver =
229 1.91 skrll bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_VERSION);
230 1.91 skrll const uint32_t snpsver =
231 1.91 skrll __SHIFTOUT(ver, AWIN_GMAC_MAC_VERSION_SNPSVER_MASK);
232 1.91 skrll aprint_normal_dev(sc->sc_dev, "Core version: %08x\n", snpsver);
233 1.55 martin
234 1.1 martin /*
235 1.21 joerg * Init chip and do initial setup
236 1.1 martin */
237 1.1 martin if (dwc_gmac_reset(sc) != 0)
238 1.51 jmcneill return ENXIO; /* not much to cleanup, haven't attached yet */
239 1.5 martin dwc_gmac_write_hwaddr(sc, enaddr);
240 1.52 sevan aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
241 1.1 martin ether_sprintf(enaddr));
242 1.1 martin
243 1.55 martin hwft = 0;
244 1.91 skrll if (snpsver >= 0x35) {
245 1.55 martin hwft = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
246 1.55 martin AWIN_GMAC_DMA_HWFEATURES);
247 1.55 martin aprint_normal_dev(sc->sc_dev,
248 1.55 martin "HW feature mask: %x\n", hwft);
249 1.55 martin }
250 1.83 skrll
251 1.83 skrll if (sizeof(bus_addr_t) > 4) {
252 1.83 skrll int error = bus_dmatag_subregion(sc->sc_dmat, 0, __MASK(32),
253 1.83 skrll &sc->sc_dmat, BUS_DMA_WAITOK);
254 1.83 skrll if (error != 0) {
255 1.83 skrll aprint_error_dev(sc->sc_dev,
256 1.83 skrll "failed to create DMA subregion\n");
257 1.83 skrll return ENOMEM;
258 1.83 skrll }
259 1.83 skrll }
260 1.83 skrll
261 1.55 martin if (hwft & GMAC_DMA_FEAT_ENHANCED_DESC) {
262 1.55 martin aprint_normal_dev(sc->sc_dev,
263 1.55 martin "Using enhanced descriptor format\n");
264 1.55 martin sc->sc_descm = &desc_methods_enhanced;
265 1.55 martin } else {
266 1.55 martin sc->sc_descm = &desc_methods_standard;
267 1.55 martin }
268 1.70 chs if (hwft & GMAC_DMA_FEAT_RMON) {
269 1.70 chs uint32_t val;
270 1.70 chs
271 1.70 chs /* Mask all MMC interrupts */
272 1.70 chs val = 0xffffffff;
273 1.70 chs bus_space_write_4(sc->sc_bst, sc->sc_bsh,
274 1.70 chs GMAC_MMC_RX_INT_MSK, val);
275 1.70 chs bus_space_write_4(sc->sc_bst, sc->sc_bsh,
276 1.70 chs GMAC_MMC_TX_INT_MSK, val);
277 1.70 chs }
278 1.55 martin
279 1.1 martin /*
280 1.1 martin * Allocate Tx and Rx rings
281 1.1 martin */
282 1.1 martin if (dwc_gmac_alloc_dma_rings(sc) != 0) {
283 1.1 martin aprint_error_dev(sc->sc_dev, "could not allocate DMA rings\n");
284 1.1 martin goto fail;
285 1.1 martin }
286 1.38 skrll
287 1.1 martin if (dwc_gmac_alloc_tx_ring(sc, &sc->sc_txq) != 0) {
288 1.1 martin aprint_error_dev(sc->sc_dev, "could not allocate Tx ring\n");
289 1.1 martin goto fail;
290 1.1 martin }
291 1.1 martin
292 1.1 martin if (dwc_gmac_alloc_rx_ring(sc, &sc->sc_rxq) != 0) {
293 1.1 martin aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n");
294 1.1 martin goto fail;
295 1.1 martin }
296 1.1 martin
297 1.38 skrll sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
298 1.38 skrll mutex_init(&sc->sc_txq.t_mtx, MUTEX_DEFAULT, IPL_NET);
299 1.38 skrll mutex_init(&sc->sc_rxq.r_mtx, MUTEX_DEFAULT, IPL_NET);
300 1.38 skrll
301 1.1 martin /*
302 1.1 martin * Prepare interface data
303 1.1 martin */
304 1.1 martin ifp->if_softc = sc;
305 1.1 martin strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
306 1.1 martin ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
307 1.44 ozaki #ifdef DWCGMAC_MPSAFE
308 1.43 ozaki ifp->if_extflags = IFEF_MPSAFE;
309 1.44 ozaki #endif
310 1.1 martin ifp->if_ioctl = dwc_gmac_ioctl;
311 1.1 martin ifp->if_start = dwc_gmac_start;
312 1.1 martin ifp->if_init = dwc_gmac_init;
313 1.1 martin ifp->if_stop = dwc_gmac_stop;
314 1.1 martin IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
315 1.1 martin IFQ_SET_READY(&ifp->if_snd);
316 1.1 martin
317 1.1 martin /*
318 1.1 martin * Attach MII subdevices
319 1.1 martin */
320 1.2 martin sc->sc_ec.ec_mii = &sc->sc_mii;
321 1.1 martin ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
322 1.62 msaitoh mii->mii_ifp = ifp;
323 1.62 msaitoh mii->mii_readreg = dwc_gmac_miibus_read_reg;
324 1.62 msaitoh mii->mii_writereg = dwc_gmac_miibus_write_reg;
325 1.62 msaitoh mii->mii_statchg = dwc_gmac_miibus_statchg;
326 1.62 msaitoh mii_attach(sc->sc_dev, mii, 0xffffffff, phy_id, MII_OFFSET_ANY,
327 1.25 jmcneill MIIF_DOPAUSE);
328 1.1 martin
329 1.62 msaitoh if (LIST_EMPTY(&mii->mii_phys)) {
330 1.62 msaitoh aprint_error_dev(sc->sc_dev, "no PHY found!\n");
331 1.62 msaitoh ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL);
332 1.62 msaitoh ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL);
333 1.62 msaitoh } else {
334 1.62 msaitoh ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
335 1.62 msaitoh }
336 1.1 martin
337 1.1 martin /*
338 1.33 tnn * We can support 802.1Q VLAN-sized frames.
339 1.33 tnn */
340 1.33 tnn sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
341 1.33 tnn
342 1.33 tnn /*
343 1.1 martin * Ready, attach interface
344 1.1 martin */
345 1.38 skrll /* Attach the interface. */
346 1.74 riastrad if_initialize(ifp);
347 1.38 skrll sc->sc_ipq = if_percpuq_create(&sc->sc_ec.ec_if);
348 1.40 ozaki if_deferred_start_init(ifp, NULL);
349 1.1 martin ether_ifattach(ifp, enaddr);
350 1.22 martin ether_set_ifflags_cb(&sc->sc_ec, dwc_gmac_ifflags_cb);
351 1.38 skrll if_register(ifp);
352 1.63 msaitoh rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
353 1.63 msaitoh RND_TYPE_NET, RND_FLAG_DEFAULT);
354 1.1 martin
355 1.1 martin /*
356 1.1 martin * Enable interrupts
357 1.1 martin */
358 1.38 skrll mutex_enter(sc->sc_lock);
359 1.25 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTMASK,
360 1.8 martin AWIN_DEF_MAC_INTRMASK);
361 1.8 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_INTENABLE,
362 1.8 martin GMAC_DEF_DMA_INT_MASK);
363 1.38 skrll mutex_exit(sc->sc_lock);
364 1.1 martin
365 1.51 jmcneill return 0;
366 1.51 jmcneill
367 1.1 martin fail:
368 1.1 martin dwc_gmac_free_rx_ring(sc, &sc->sc_rxq);
369 1.1 martin dwc_gmac_free_tx_ring(sc, &sc->sc_txq);
370 1.41 msaitoh dwc_gmac_free_dma_rings(sc);
371 1.41 msaitoh mutex_destroy(&sc->sc_mdio_lock);
372 1.51 jmcneill
373 1.51 jmcneill return ENXIO;
374 1.1 martin }
375 1.1 martin
376 1.1 martin
377 1.1 martin
378 1.1 martin static int
379 1.1 martin dwc_gmac_reset(struct dwc_gmac_softc *sc)
380 1.1 martin {
381 1.1 martin size_t cnt;
382 1.1 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE,
383 1.61 msaitoh bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE)
384 1.61 msaitoh | GMAC_BUSMODE_RESET);
385 1.72 ryo for (cnt = 0; cnt < 30000; cnt++) {
386 1.1 martin if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE)
387 1.1 martin & GMAC_BUSMODE_RESET) == 0)
388 1.1 martin return 0;
389 1.1 martin delay(10);
390 1.1 martin }
391 1.1 martin
392 1.1 martin aprint_error_dev(sc->sc_dev, "reset timed out\n");
393 1.1 martin return EIO;
394 1.1 martin }
395 1.1 martin
396 1.1 martin static void
397 1.1 martin dwc_gmac_write_hwaddr(struct dwc_gmac_softc *sc,
398 1.1 martin uint8_t enaddr[ETHER_ADDR_LEN])
399 1.1 martin {
400 1.49 jmcneill uint32_t hi, lo;
401 1.1 martin
402 1.49 jmcneill hi = enaddr[4] | (enaddr[5] << 8);
403 1.1 martin lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16)
404 1.73 msaitoh | ((uint32_t)enaddr[3] << 24);
405 1.49 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_ADDR0HI, hi);
406 1.1 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_ADDR0LO, lo);
407 1.1 martin }
408 1.1 martin
409 1.1 martin static int
410 1.56 msaitoh dwc_gmac_miibus_read_reg(device_t self, int phy, int reg, uint16_t *val)
411 1.1 martin {
412 1.1 martin struct dwc_gmac_softc * const sc = device_private(self);
413 1.6 martin uint16_t mii;
414 1.1 martin size_t cnt;
415 1.1 martin
416 1.61 msaitoh mii = __SHIFTIN(phy, GMAC_MII_PHY_MASK)
417 1.61 msaitoh | __SHIFTIN(reg, GMAC_MII_REG_MASK)
418 1.61 msaitoh | __SHIFTIN(sc->sc_mii_clk, GMAC_MII_CLKMASK)
419 1.6 martin | GMAC_MII_BUSY;
420 1.1 martin
421 1.1 martin mutex_enter(&sc->sc_mdio_lock);
422 1.6 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIADDR, mii);
423 1.1 martin
424 1.1 martin for (cnt = 0; cnt < 1000; cnt++) {
425 1.3 martin if (!(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
426 1.3 martin AWIN_GMAC_MAC_MIIADDR) & GMAC_MII_BUSY)) {
427 1.56 msaitoh *val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
428 1.3 martin AWIN_GMAC_MAC_MIIDATA);
429 1.1 martin break;
430 1.1 martin }
431 1.1 martin delay(10);
432 1.1 martin }
433 1.1 martin
434 1.1 martin mutex_exit(&sc->sc_mdio_lock);
435 1.1 martin
436 1.56 msaitoh if (cnt >= 1000)
437 1.56 msaitoh return ETIMEDOUT;
438 1.61 msaitoh
439 1.56 msaitoh return 0;
440 1.1 martin }
441 1.1 martin
442 1.56 msaitoh static int
443 1.56 msaitoh dwc_gmac_miibus_write_reg(device_t self, int phy, int reg, uint16_t val)
444 1.1 martin {
445 1.1 martin struct dwc_gmac_softc * const sc = device_private(self);
446 1.6 martin uint16_t mii;
447 1.1 martin size_t cnt;
448 1.1 martin
449 1.61 msaitoh mii = __SHIFTIN(phy, GMAC_MII_PHY_MASK)
450 1.61 msaitoh | __SHIFTIN(reg, GMAC_MII_REG_MASK)
451 1.61 msaitoh | __SHIFTIN(sc->sc_mii_clk, GMAC_MII_CLKMASK)
452 1.6 martin | GMAC_MII_BUSY | GMAC_MII_WRITE;
453 1.1 martin
454 1.1 martin mutex_enter(&sc->sc_mdio_lock);
455 1.1 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIDATA, val);
456 1.6 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIADDR, mii);
457 1.1 martin
458 1.1 martin for (cnt = 0; cnt < 1000; cnt++) {
459 1.3 martin if (!(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
460 1.3 martin AWIN_GMAC_MAC_MIIADDR) & GMAC_MII_BUSY))
461 1.1 martin break;
462 1.1 martin delay(10);
463 1.1 martin }
464 1.38 skrll
465 1.1 martin mutex_exit(&sc->sc_mdio_lock);
466 1.56 msaitoh
467 1.56 msaitoh if (cnt >= 1000)
468 1.56 msaitoh return ETIMEDOUT;
469 1.56 msaitoh
470 1.56 msaitoh return 0;
471 1.1 martin }
472 1.1 martin
473 1.1 martin static int
474 1.1 martin dwc_gmac_alloc_rx_ring(struct dwc_gmac_softc *sc,
475 1.1 martin struct dwc_gmac_rx_ring *ring)
476 1.1 martin {
477 1.1 martin struct dwc_gmac_rx_data *data;
478 1.1 martin bus_addr_t physaddr;
479 1.89 skrll const size_t rxringsz = AWGE_RX_RING_COUNT * sizeof(*ring->r_desc);
480 1.1 martin int error, i, next;
481 1.1 martin
482 1.1 martin ring->r_cur = ring->r_next = 0;
483 1.89 skrll memset(ring->r_desc, 0, rxringsz);
484 1.1 martin
485 1.1 martin /*
486 1.1 martin * Pre-allocate Rx buffers and populate Rx ring.
487 1.1 martin */
488 1.1 martin for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
489 1.1 martin struct dwc_gmac_dev_dmadesc *desc;
490 1.1 martin
491 1.1 martin data = &sc->sc_rxq.r_data[i];
492 1.1 martin
493 1.1 martin MGETHDR(data->rd_m, M_DONTWAIT, MT_DATA);
494 1.1 martin if (data->rd_m == NULL) {
495 1.1 martin aprint_error_dev(sc->sc_dev,
496 1.1 martin "could not allocate rx mbuf #%d\n", i);
497 1.1 martin error = ENOMEM;
498 1.1 martin goto fail;
499 1.1 martin }
500 1.1 martin error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
501 1.1 martin MCLBYTES, 0, BUS_DMA_NOWAIT, &data->rd_map);
502 1.1 martin if (error != 0) {
503 1.1 martin aprint_error_dev(sc->sc_dev,
504 1.1 martin "could not create DMA map\n");
505 1.1 martin data->rd_map = NULL;
506 1.1 martin goto fail;
507 1.1 martin }
508 1.1 martin MCLGET(data->rd_m, M_DONTWAIT);
509 1.1 martin if (!(data->rd_m->m_flags & M_EXT)) {
510 1.1 martin aprint_error_dev(sc->sc_dev,
511 1.1 martin "could not allocate mbuf cluster #%d\n", i);
512 1.1 martin error = ENOMEM;
513 1.1 martin goto fail;
514 1.1 martin }
515 1.66 tnn data->rd_m->m_len = data->rd_m->m_pkthdr.len
516 1.66 tnn = data->rd_m->m_ext.ext_size;
517 1.66 tnn if (data->rd_m->m_len > AWGE_MAX_PACKET) {
518 1.66 tnn data->rd_m->m_len = data->rd_m->m_pkthdr.len
519 1.66 tnn = AWGE_MAX_PACKET;
520 1.66 tnn }
521 1.1 martin
522 1.66 tnn error = bus_dmamap_load_mbuf(sc->sc_dmat, data->rd_map,
523 1.66 tnn data->rd_m, BUS_DMA_READ | BUS_DMA_NOWAIT);
524 1.1 martin if (error != 0) {
525 1.1 martin aprint_error_dev(sc->sc_dev,
526 1.1 martin "could not load rx buf DMA map #%d", i);
527 1.1 martin goto fail;
528 1.1 martin }
529 1.66 tnn bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
530 1.66 tnn data->rd_map->dm_mapsize, BUS_DMASYNC_PREREAD);
531 1.1 martin physaddr = data->rd_map->dm_segs[0].ds_addr;
532 1.1 martin
533 1.1 martin desc = &sc->sc_rxq.r_desc[i];
534 1.1 martin desc->ddesc_data = htole32(physaddr);
535 1.8 martin next = RX_NEXT(i);
536 1.38 skrll desc->ddesc_next = htole32(ring->r_physaddr
537 1.1 martin + next * sizeof(*desc));
538 1.55 martin sc->sc_descm->rx_init_flags(desc);
539 1.66 tnn sc->sc_descm->rx_set_len(desc, data->rd_m->m_len);
540 1.55 martin sc->sc_descm->rx_set_owned_by_dev(desc);
541 1.1 martin }
542 1.1 martin
543 1.89 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
544 1.89 skrll RX_DESC_OFFSET(0),
545 1.82 skrll AWGE_RX_RING_COUNT * sizeof(struct dwc_gmac_dev_dmadesc),
546 1.85 skrll BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
547 1.1 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
548 1.6 martin ring->r_physaddr);
549 1.1 martin
550 1.1 martin return 0;
551 1.1 martin
552 1.1 martin fail:
553 1.1 martin dwc_gmac_free_rx_ring(sc, ring);
554 1.1 martin return error;
555 1.1 martin }
556 1.1 martin
557 1.1 martin static void
558 1.1 martin dwc_gmac_reset_rx_ring(struct dwc_gmac_softc *sc,
559 1.1 martin struct dwc_gmac_rx_ring *ring)
560 1.1 martin {
561 1.1 martin struct dwc_gmac_dev_dmadesc *desc;
562 1.66 tnn struct dwc_gmac_rx_data *data;
563 1.1 martin int i;
564 1.1 martin
565 1.38 skrll mutex_enter(&ring->r_mtx);
566 1.1 martin for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
567 1.1 martin desc = &sc->sc_rxq.r_desc[i];
568 1.66 tnn data = &sc->sc_rxq.r_data[i];
569 1.55 martin sc->sc_descm->rx_init_flags(desc);
570 1.66 tnn sc->sc_descm->rx_set_len(desc, data->rd_m->m_len);
571 1.55 martin sc->sc_descm->rx_set_owned_by_dev(desc);
572 1.1 martin }
573 1.1 martin
574 1.1 martin bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map, 0,
575 1.82 skrll AWGE_RX_RING_COUNT * sizeof(struct dwc_gmac_dev_dmadesc),
576 1.61 msaitoh BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
577 1.1 martin
578 1.1 martin ring->r_cur = ring->r_next = 0;
579 1.11 martin /* reset DMA address to start of ring */
580 1.11 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
581 1.11 martin sc->sc_rxq.r_physaddr);
582 1.38 skrll mutex_exit(&ring->r_mtx);
583 1.1 martin }
584 1.1 martin
585 1.1 martin static int
586 1.1 martin dwc_gmac_alloc_dma_rings(struct dwc_gmac_softc *sc)
587 1.1 martin {
588 1.89 skrll const size_t ringsize = AWGE_TOTAL_RING_COUNT *
589 1.1 martin sizeof(struct dwc_gmac_dev_dmadesc);
590 1.1 martin int error, nsegs;
591 1.1 martin void *rings;
592 1.1 martin
593 1.89 skrll error = bus_dmamap_create(sc->sc_dmat, ringsize, 1, ringsize, 0,
594 1.1 martin BUS_DMA_NOWAIT, &sc->sc_dma_ring_map);
595 1.1 martin if (error != 0) {
596 1.1 martin aprint_error_dev(sc->sc_dev,
597 1.1 martin "could not create desc DMA map\n");
598 1.1 martin sc->sc_dma_ring_map = NULL;
599 1.1 martin goto fail;
600 1.1 martin }
601 1.1 martin
602 1.89 skrll error = bus_dmamem_alloc(sc->sc_dmat, ringsize, PAGE_SIZE, 0,
603 1.61 msaitoh &sc->sc_dma_ring_seg, 1, &nsegs, BUS_DMA_NOWAIT |BUS_DMA_COHERENT);
604 1.1 martin if (error != 0) {
605 1.1 martin aprint_error_dev(sc->sc_dev,
606 1.1 martin "could not map DMA memory\n");
607 1.1 martin goto fail;
608 1.1 martin }
609 1.1 martin
610 1.1 martin error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dma_ring_seg, nsegs,
611 1.89 skrll ringsize, &rings, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
612 1.1 martin if (error != 0) {
613 1.1 martin aprint_error_dev(sc->sc_dev,
614 1.1 martin "could not allocate DMA memory\n");
615 1.1 martin goto fail;
616 1.1 martin }
617 1.1 martin
618 1.1 martin error = bus_dmamap_load(sc->sc_dmat, sc->sc_dma_ring_map, rings,
619 1.89 skrll ringsize, NULL, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
620 1.1 martin if (error != 0) {
621 1.1 martin aprint_error_dev(sc->sc_dev,
622 1.1 martin "could not load desc DMA map\n");
623 1.1 martin goto fail;
624 1.1 martin }
625 1.1 martin
626 1.1 martin /* give first AWGE_RX_RING_COUNT to the RX side */
627 1.1 martin sc->sc_rxq.r_desc = rings;
628 1.1 martin sc->sc_rxq.r_physaddr = sc->sc_dma_ring_map->dm_segs[0].ds_addr;
629 1.1 martin
630 1.1 martin /* and next rings to the TX side */
631 1.1 martin sc->sc_txq.t_desc = sc->sc_rxq.r_desc + AWGE_RX_RING_COUNT;
632 1.38 skrll sc->sc_txq.t_physaddr = sc->sc_rxq.r_physaddr +
633 1.82 skrll AWGE_RX_RING_COUNT * sizeof(struct dwc_gmac_dev_dmadesc);
634 1.1 martin
635 1.1 martin return 0;
636 1.1 martin
637 1.1 martin fail:
638 1.1 martin dwc_gmac_free_dma_rings(sc);
639 1.1 martin return error;
640 1.1 martin }
641 1.1 martin
642 1.1 martin static void
643 1.1 martin dwc_gmac_free_dma_rings(struct dwc_gmac_softc *sc)
644 1.1 martin {
645 1.1 martin bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map, 0,
646 1.1 martin sc->sc_dma_ring_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
647 1.1 martin bus_dmamap_unload(sc->sc_dmat, sc->sc_dma_ring_map);
648 1.1 martin bus_dmamem_unmap(sc->sc_dmat, sc->sc_rxq.r_desc,
649 1.1 martin AWGE_TOTAL_RING_COUNT * sizeof(struct dwc_gmac_dev_dmadesc));
650 1.1 martin bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_ring_seg, 1);
651 1.1 martin }
652 1.1 martin
653 1.1 martin static void
654 1.1 martin dwc_gmac_free_rx_ring(struct dwc_gmac_softc *sc, struct dwc_gmac_rx_ring *ring)
655 1.1 martin {
656 1.1 martin struct dwc_gmac_rx_data *data;
657 1.1 martin int i;
658 1.1 martin
659 1.1 martin if (ring->r_desc == NULL)
660 1.1 martin return;
661 1.1 martin
662 1.1 martin for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
663 1.1 martin data = &ring->r_data[i];
664 1.1 martin
665 1.1 martin if (data->rd_map != NULL) {
666 1.1 martin bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
667 1.1 martin AWGE_RX_RING_COUNT
668 1.82 skrll * sizeof(struct dwc_gmac_dev_dmadesc),
669 1.1 martin BUS_DMASYNC_POSTREAD);
670 1.1 martin bus_dmamap_unload(sc->sc_dmat, data->rd_map);
671 1.1 martin bus_dmamap_destroy(sc->sc_dmat, data->rd_map);
672 1.1 martin }
673 1.88 rin m_freem(data->rd_m);
674 1.1 martin }
675 1.1 martin }
676 1.1 martin
677 1.1 martin static int
678 1.1 martin dwc_gmac_alloc_tx_ring(struct dwc_gmac_softc *sc,
679 1.1 martin struct dwc_gmac_tx_ring *ring)
680 1.1 martin {
681 1.1 martin int i, error = 0;
682 1.1 martin
683 1.1 martin ring->t_queued = 0;
684 1.1 martin ring->t_cur = ring->t_next = 0;
685 1.1 martin
686 1.82 skrll memset(ring->t_desc, 0, AWGE_TX_RING_COUNT * sizeof(*ring->t_desc));
687 1.1 martin bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
688 1.1 martin TX_DESC_OFFSET(0),
689 1.82 skrll AWGE_TX_RING_COUNT * sizeof(struct dwc_gmac_dev_dmadesc),
690 1.89 skrll BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
691 1.1 martin
692 1.1 martin for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
693 1.1 martin error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
694 1.1 martin AWGE_TX_RING_COUNT, MCLBYTES, 0,
695 1.61 msaitoh BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
696 1.1 martin &ring->t_data[i].td_map);
697 1.1 martin if (error != 0) {
698 1.1 martin aprint_error_dev(sc->sc_dev,
699 1.1 martin "could not create TX DMA map #%d\n", i);
700 1.1 martin ring->t_data[i].td_map = NULL;
701 1.1 martin goto fail;
702 1.1 martin }
703 1.1 martin ring->t_desc[i].ddesc_next = htole32(
704 1.1 martin ring->t_physaddr + sizeof(struct dwc_gmac_dev_dmadesc)
705 1.87 skrll * TX_NEXT(i));
706 1.1 martin }
707 1.89 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
708 1.89 skrll TX_DESC_OFFSET(0),
709 1.89 skrll AWGE_TX_RING_COUNT * sizeof(struct dwc_gmac_dev_dmadesc),
710 1.89 skrll BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
711 1.1 martin
712 1.1 martin return 0;
713 1.1 martin
714 1.1 martin fail:
715 1.1 martin dwc_gmac_free_tx_ring(sc, ring);
716 1.1 martin return error;
717 1.1 martin }
718 1.1 martin
719 1.1 martin static void
720 1.1 martin dwc_gmac_txdesc_sync(struct dwc_gmac_softc *sc, int start, int end, int ops)
721 1.1 martin {
722 1.64 mrg /* 'end' is pointing one descriptor beyond the last we want to sync */
723 1.1 martin if (end > start) {
724 1.1 martin bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
725 1.1 martin TX_DESC_OFFSET(start),
726 1.84 skrll TX_DESC_OFFSET(end) - TX_DESC_OFFSET(start),
727 1.1 martin ops);
728 1.1 martin return;
729 1.1 martin }
730 1.1 martin /* sync from 'start' to end of ring */
731 1.1 martin bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
732 1.1 martin TX_DESC_OFFSET(start),
733 1.84 skrll TX_DESC_OFFSET(AWGE_TX_RING_COUNT) - TX_DESC_OFFSET(start),
734 1.1 martin ops);
735 1.47 jmcneill if (TX_DESC_OFFSET(end) - TX_DESC_OFFSET(0) > 0) {
736 1.47 jmcneill /* sync from start of ring to 'end' */
737 1.47 jmcneill bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
738 1.47 jmcneill TX_DESC_OFFSET(0),
739 1.84 skrll TX_DESC_OFFSET(end) - TX_DESC_OFFSET(0),
740 1.47 jmcneill ops);
741 1.47 jmcneill }
742 1.1 martin }
743 1.1 martin
744 1.1 martin static void
745 1.1 martin dwc_gmac_reset_tx_ring(struct dwc_gmac_softc *sc,
746 1.1 martin struct dwc_gmac_tx_ring *ring)
747 1.1 martin {
748 1.1 martin int i;
749 1.1 martin
750 1.38 skrll mutex_enter(&ring->t_mtx);
751 1.1 martin for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
752 1.1 martin struct dwc_gmac_tx_data *data = &ring->t_data[i];
753 1.1 martin
754 1.1 martin if (data->td_m != NULL) {
755 1.1 martin bus_dmamap_sync(sc->sc_dmat, data->td_active,
756 1.1 martin 0, data->td_active->dm_mapsize,
757 1.1 martin BUS_DMASYNC_POSTWRITE);
758 1.1 martin bus_dmamap_unload(sc->sc_dmat, data->td_active);
759 1.1 martin m_freem(data->td_m);
760 1.1 martin data->td_m = NULL;
761 1.1 martin }
762 1.1 martin }
763 1.1 martin
764 1.1 martin bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
765 1.1 martin TX_DESC_OFFSET(0),
766 1.82 skrll AWGE_TX_RING_COUNT * sizeof(struct dwc_gmac_dev_dmadesc),
767 1.61 msaitoh BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
768 1.6 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
769 1.6 martin sc->sc_txq.t_physaddr);
770 1.1 martin
771 1.1 martin ring->t_queued = 0;
772 1.1 martin ring->t_cur = ring->t_next = 0;
773 1.38 skrll mutex_exit(&ring->t_mtx);
774 1.1 martin }
775 1.1 martin
776 1.1 martin static void
777 1.1 martin dwc_gmac_free_tx_ring(struct dwc_gmac_softc *sc,
778 1.1 martin struct dwc_gmac_tx_ring *ring)
779 1.1 martin {
780 1.1 martin int i;
781 1.1 martin
782 1.1 martin /* unload the maps */
783 1.1 martin for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
784 1.1 martin struct dwc_gmac_tx_data *data = &ring->t_data[i];
785 1.1 martin
786 1.1 martin if (data->td_m != NULL) {
787 1.1 martin bus_dmamap_sync(sc->sc_dmat, data->td_active,
788 1.1 martin 0, data->td_map->dm_mapsize,
789 1.1 martin BUS_DMASYNC_POSTWRITE);
790 1.1 martin bus_dmamap_unload(sc->sc_dmat, data->td_active);
791 1.1 martin m_freem(data->td_m);
792 1.1 martin data->td_m = NULL;
793 1.1 martin }
794 1.1 martin }
795 1.1 martin
796 1.1 martin /* and actually free them */
797 1.1 martin for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
798 1.1 martin struct dwc_gmac_tx_data *data = &ring->t_data[i];
799 1.1 martin
800 1.1 martin bus_dmamap_destroy(sc->sc_dmat, data->td_map);
801 1.1 martin }
802 1.1 martin }
803 1.1 martin
804 1.1 martin static void
805 1.1 martin dwc_gmac_miibus_statchg(struct ifnet *ifp)
806 1.1 martin {
807 1.1 martin struct dwc_gmac_softc * const sc = ifp->if_softc;
808 1.1 martin struct mii_data * const mii = &sc->sc_mii;
809 1.25 jmcneill uint32_t conf, flow;
810 1.1 martin
811 1.1 martin /*
812 1.1 martin * Set MII or GMII interface based on the speed
813 1.38 skrll * negotiated by the PHY.
814 1.9 martin */
815 1.9 martin conf = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_CONF);
816 1.61 msaitoh conf &= ~(AWIN_GMAC_MAC_CONF_FES100 | AWIN_GMAC_MAC_CONF_MIISEL
817 1.61 msaitoh | AWIN_GMAC_MAC_CONF_FULLDPLX);
818 1.11 martin conf |= AWIN_GMAC_MAC_CONF_FRAMEBURST
819 1.11 martin | AWIN_GMAC_MAC_CONF_DISABLERXOWN
820 1.25 jmcneill | AWIN_GMAC_MAC_CONF_DISABLEJABBER
821 1.11 martin | AWIN_GMAC_MAC_CONF_RXENABLE
822 1.11 martin | AWIN_GMAC_MAC_CONF_TXENABLE;
823 1.1 martin switch (IFM_SUBTYPE(mii->mii_media_active)) {
824 1.1 martin case IFM_10_T:
825 1.12 jmcneill conf |= AWIN_GMAC_MAC_CONF_MIISEL;
826 1.9 martin break;
827 1.1 martin case IFM_100_TX:
828 1.12 jmcneill conf |= AWIN_GMAC_MAC_CONF_FES100 |
829 1.12 jmcneill AWIN_GMAC_MAC_CONF_MIISEL;
830 1.1 martin break;
831 1.1 martin case IFM_1000_T:
832 1.1 martin break;
833 1.1 martin }
834 1.46 jmcneill if (sc->sc_set_speed)
835 1.46 jmcneill sc->sc_set_speed(sc, IFM_SUBTYPE(mii->mii_media_active));
836 1.25 jmcneill
837 1.25 jmcneill flow = 0;
838 1.25 jmcneill if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
839 1.9 martin conf |= AWIN_GMAC_MAC_CONF_FULLDPLX;
840 1.25 jmcneill flow |= __SHIFTIN(0x200, AWIN_GMAC_MAC_FLOWCTRL_PAUSE);
841 1.25 jmcneill }
842 1.25 jmcneill if (mii->mii_media_active & IFM_ETH_TXPAUSE) {
843 1.25 jmcneill flow |= AWIN_GMAC_MAC_FLOWCTRL_TFE;
844 1.25 jmcneill }
845 1.25 jmcneill if (mii->mii_media_active & IFM_ETH_RXPAUSE) {
846 1.25 jmcneill flow |= AWIN_GMAC_MAC_FLOWCTRL_RFE;
847 1.25 jmcneill }
848 1.25 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh,
849 1.25 jmcneill AWIN_GMAC_MAC_FLOWCTRL, flow);
850 1.9 martin
851 1.9 martin #ifdef DWC_GMAC_DEBUG
852 1.9 martin aprint_normal_dev(sc->sc_dev,
853 1.9 martin "setting MAC conf register: %08x\n", conf);
854 1.9 martin #endif
855 1.9 martin
856 1.9 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh,
857 1.9 martin AWIN_GMAC_MAC_CONF, conf);
858 1.1 martin }
859 1.1 martin
860 1.1 martin static int
861 1.1 martin dwc_gmac_init(struct ifnet *ifp)
862 1.1 martin {
863 1.92 skrll struct dwc_gmac_softc * const sc = ifp->if_softc;
864 1.38 skrll
865 1.38 skrll mutex_enter(sc->sc_lock);
866 1.38 skrll int ret = dwc_gmac_init_locked(ifp);
867 1.38 skrll mutex_exit(sc->sc_lock);
868 1.38 skrll
869 1.38 skrll return ret;
870 1.38 skrll }
871 1.38 skrll
872 1.38 skrll static int
873 1.38 skrll dwc_gmac_init_locked(struct ifnet *ifp)
874 1.38 skrll {
875 1.92 skrll struct dwc_gmac_softc * const sc = ifp->if_softc;
876 1.13 jmcneill uint32_t ffilt;
877 1.1 martin
878 1.1 martin if (ifp->if_flags & IFF_RUNNING)
879 1.1 martin return 0;
880 1.1 martin
881 1.38 skrll dwc_gmac_stop_locked(ifp, 0);
882 1.1 martin
883 1.1 martin /*
884 1.11 martin * Configure DMA burst/transfer mode and RX/TX priorities.
885 1.11 martin * XXX - the GMAC_BUSMODE_PRIORXTX bits are undocumented.
886 1.11 martin */
887 1.11 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE,
888 1.25 jmcneill GMAC_BUSMODE_FIXEDBURST | GMAC_BUSMODE_4PBL |
889 1.25 jmcneill __SHIFTIN(2, GMAC_BUSMODE_RPBL) |
890 1.25 jmcneill __SHIFTIN(2, GMAC_BUSMODE_PBL));
891 1.11 martin
892 1.11 martin /*
893 1.13 jmcneill * Set up address filter
894 1.11 martin */
895 1.20 jmcneill ffilt = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT);
896 1.20 jmcneill if (ifp->if_flags & IFF_PROMISC) {
897 1.13 jmcneill ffilt |= AWIN_GMAC_MAC_FFILT_PR;
898 1.20 jmcneill } else {
899 1.20 jmcneill ffilt &= ~AWIN_GMAC_MAC_FFILT_PR;
900 1.20 jmcneill }
901 1.20 jmcneill if (ifp->if_flags & IFF_BROADCAST) {
902 1.20 jmcneill ffilt &= ~AWIN_GMAC_MAC_FFILT_DBF;
903 1.20 jmcneill } else {
904 1.20 jmcneill ffilt |= AWIN_GMAC_MAC_FFILT_DBF;
905 1.20 jmcneill }
906 1.13 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT, ffilt);
907 1.11 martin
908 1.11 martin /*
909 1.20 jmcneill * Set up multicast filter
910 1.20 jmcneill */
911 1.20 jmcneill dwc_gmac_setmulti(sc);
912 1.20 jmcneill
913 1.20 jmcneill /*
914 1.6 martin * Set up dma pointer for RX and TX ring
915 1.1 martin */
916 1.6 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
917 1.6 martin sc->sc_rxq.r_physaddr);
918 1.6 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
919 1.6 martin sc->sc_txq.t_physaddr);
920 1.6 martin
921 1.6 martin /*
922 1.10 martin * Start RX/TX part
923 1.6 martin */
924 1.46 jmcneill uint32_t opmode = GMAC_DMA_OP_RXSTART | GMAC_DMA_OP_TXSTART;
925 1.46 jmcneill if ((sc->sc_flags & DWC_GMAC_FORCE_THRESH_DMA_MODE) == 0) {
926 1.46 jmcneill opmode |= GMAC_DMA_OP_RXSTOREFORWARD | GMAC_DMA_OP_TXSTOREFORWARD;
927 1.46 jmcneill }
928 1.46 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_OPMODE, opmode);
929 1.90 skrll #ifdef DWC_GMAC_DEBUG
930 1.90 skrll aprint_normal_dev(sc->sc_dev,
931 1.90 skrll "setting DMA opmode register: %08x\n", opmode);
932 1.90 skrll #endif
933 1.1 martin
934 1.38 skrll sc->sc_stopping = false;
935 1.38 skrll
936 1.1 martin ifp->if_flags |= IFF_RUNNING;
937 1.78 thorpej sc->sc_txbusy = false;
938 1.1 martin
939 1.1 martin return 0;
940 1.1 martin }
941 1.1 martin
942 1.1 martin static void
943 1.1 martin dwc_gmac_start(struct ifnet *ifp)
944 1.1 martin {
945 1.92 skrll struct dwc_gmac_softc * const sc = ifp->if_softc;
946 1.45 martin #ifdef DWCGMAC_MPSAFE
947 1.43 ozaki KASSERT(if_is_mpsafe(ifp));
948 1.45 martin #endif
949 1.38 skrll
950 1.38 skrll mutex_enter(sc->sc_lock);
951 1.38 skrll if (!sc->sc_stopping) {
952 1.38 skrll mutex_enter(&sc->sc_txq.t_mtx);
953 1.38 skrll dwc_gmac_start_locked(ifp);
954 1.38 skrll mutex_exit(&sc->sc_txq.t_mtx);
955 1.38 skrll }
956 1.38 skrll mutex_exit(sc->sc_lock);
957 1.38 skrll }
958 1.38 skrll
959 1.38 skrll static void
960 1.38 skrll dwc_gmac_start_locked(struct ifnet *ifp)
961 1.38 skrll {
962 1.92 skrll struct dwc_gmac_softc * const sc = ifp->if_softc;
963 1.1 martin int old = sc->sc_txq.t_queued;
964 1.30 martin int start = sc->sc_txq.t_cur;
965 1.1 martin struct mbuf *m0;
966 1.1 martin
967 1.78 thorpej if ((ifp->if_flags & IFF_RUNNING) == 0)
968 1.78 thorpej return;
969 1.78 thorpej if (sc->sc_txbusy)
970 1.1 martin return;
971 1.1 martin
972 1.1 martin for (;;) {
973 1.1 martin IFQ_POLL(&ifp->if_snd, m0);
974 1.1 martin if (m0 == NULL)
975 1.1 martin break;
976 1.1 martin if (dwc_gmac_queue(sc, m0) != 0) {
977 1.78 thorpej sc->sc_txbusy = true;
978 1.1 martin break;
979 1.1 martin }
980 1.1 martin IFQ_DEQUEUE(&ifp->if_snd, m0);
981 1.50 msaitoh bpf_mtap(ifp, m0, BPF_D_OUT);
982 1.32 martin if (sc->sc_txq.t_queued == AWGE_TX_RING_COUNT) {
983 1.78 thorpej sc->sc_txbusy = true;
984 1.32 martin break;
985 1.32 martin }
986 1.1 martin }
987 1.1 martin
988 1.1 martin if (sc->sc_txq.t_queued != old) {
989 1.1 martin /* packets have been queued, kick it off */
990 1.30 martin dwc_gmac_txdesc_sync(sc, start, sc->sc_txq.t_cur,
991 1.61 msaitoh BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
992 1.10 martin
993 1.10 martin #ifdef DWC_GMAC_DEBUG
994 1.10 martin dwc_dump_status(sc);
995 1.10 martin #endif
996 1.55 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh,
997 1.55 martin AWIN_GMAC_DMA_TXPOLL, ~0U);
998 1.1 martin }
999 1.1 martin }
1000 1.1 martin
1001 1.1 martin static void
1002 1.1 martin dwc_gmac_stop(struct ifnet *ifp, int disable)
1003 1.1 martin {
1004 1.92 skrll struct dwc_gmac_softc * const sc = ifp->if_softc;
1005 1.1 martin
1006 1.38 skrll mutex_enter(sc->sc_lock);
1007 1.38 skrll dwc_gmac_stop_locked(ifp, disable);
1008 1.38 skrll mutex_exit(sc->sc_lock);
1009 1.38 skrll }
1010 1.38 skrll
1011 1.38 skrll static void
1012 1.38 skrll dwc_gmac_stop_locked(struct ifnet *ifp, int disable)
1013 1.38 skrll {
1014 1.92 skrll struct dwc_gmac_softc * const sc = ifp->if_softc;
1015 1.38 skrll
1016 1.38 skrll sc->sc_stopping = true;
1017 1.38 skrll
1018 1.6 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh,
1019 1.6 martin AWIN_GMAC_DMA_OPMODE,
1020 1.6 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1021 1.62 msaitoh AWIN_GMAC_DMA_OPMODE)
1022 1.61 msaitoh & ~(GMAC_DMA_OP_TXSTART | GMAC_DMA_OP_RXSTART));
1023 1.6 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh,
1024 1.6 martin AWIN_GMAC_DMA_OPMODE,
1025 1.6 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1026 1.62 msaitoh AWIN_GMAC_DMA_OPMODE) | GMAC_DMA_OP_FLUSHTX);
1027 1.6 martin
1028 1.1 martin mii_down(&sc->sc_mii);
1029 1.1 martin dwc_gmac_reset_tx_ring(sc, &sc->sc_txq);
1030 1.1 martin dwc_gmac_reset_rx_ring(sc, &sc->sc_rxq);
1031 1.48 jmcneill
1032 1.78 thorpej ifp->if_flags &= ~IFF_RUNNING;
1033 1.78 thorpej sc->sc_txbusy = false;
1034 1.1 martin }
1035 1.1 martin
1036 1.1 martin /*
1037 1.1 martin * Add m0 to the TX ring
1038 1.1 martin */
1039 1.1 martin static int
1040 1.1 martin dwc_gmac_queue(struct dwc_gmac_softc *sc, struct mbuf *m0)
1041 1.1 martin {
1042 1.1 martin struct dwc_gmac_dev_dmadesc *desc = NULL;
1043 1.1 martin struct dwc_gmac_tx_data *data = NULL;
1044 1.1 martin bus_dmamap_t map;
1045 1.1 martin int error, i, first;
1046 1.1 martin
1047 1.8 martin #ifdef DWC_GMAC_DEBUG
1048 1.8 martin aprint_normal_dev(sc->sc_dev,
1049 1.8 martin "dwc_gmac_queue: adding mbuf chain %p\n", m0);
1050 1.8 martin #endif
1051 1.8 martin
1052 1.1 martin first = sc->sc_txq.t_cur;
1053 1.1 martin map = sc->sc_txq.t_data[first].td_map;
1054 1.1 martin
1055 1.1 martin error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0,
1056 1.61 msaitoh BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1057 1.1 martin if (error != 0) {
1058 1.1 martin aprint_error_dev(sc->sc_dev, "could not map mbuf "
1059 1.1 martin "(len: %d, error %d)\n", m0->m_pkthdr.len, error);
1060 1.1 martin return error;
1061 1.1 martin }
1062 1.1 martin
1063 1.32 martin if (sc->sc_txq.t_queued + map->dm_nsegs > AWGE_TX_RING_COUNT) {
1064 1.1 martin bus_dmamap_unload(sc->sc_dmat, map);
1065 1.1 martin return ENOBUFS;
1066 1.1 martin }
1067 1.1 martin
1068 1.1 martin for (i = 0; i < map->dm_nsegs; i++) {
1069 1.1 martin data = &sc->sc_txq.t_data[sc->sc_txq.t_cur];
1070 1.8 martin desc = &sc->sc_txq.t_desc[sc->sc_txq.t_cur];
1071 1.8 martin
1072 1.8 martin desc->ddesc_data = htole32(map->dm_segs[i].ds_addr);
1073 1.7 martin
1074 1.7 martin #ifdef DWC_GMAC_DEBUG
1075 1.81 skrll aprint_normal_dev(sc->sc_dev, "enqueuing desc #%d data %08lx "
1076 1.55 martin "len %lu\n", sc->sc_txq.t_cur,
1077 1.7 martin (unsigned long)map->dm_segs[i].ds_addr,
1078 1.55 martin (unsigned long)map->dm_segs[i].ds_len);
1079 1.7 martin #endif
1080 1.7 martin
1081 1.55 martin sc->sc_descm->tx_init_flags(desc);
1082 1.55 martin sc->sc_descm->tx_set_len(desc, map->dm_segs[i].ds_len);
1083 1.55 martin
1084 1.55 martin if (i == 0)
1085 1.55 martin sc->sc_descm->tx_set_first_frag(desc);
1086 1.1 martin
1087 1.1 martin /*
1088 1.1 martin * Defer passing ownership of the first descriptor
1089 1.23 joerg * until we are done.
1090 1.1 martin */
1091 1.55 martin if (i != 0)
1092 1.55 martin sc->sc_descm->tx_set_owned_by_dev(desc);
1093 1.8 martin
1094 1.6 martin sc->sc_txq.t_queued++;
1095 1.8 martin sc->sc_txq.t_cur = TX_NEXT(sc->sc_txq.t_cur);
1096 1.1 martin }
1097 1.1 martin
1098 1.55 martin sc->sc_descm->tx_set_last_frag(desc);
1099 1.1 martin
1100 1.1 martin data->td_m = m0;
1101 1.1 martin data->td_active = map;
1102 1.1 martin
1103 1.89 skrll /* sync the packet buffer */
1104 1.1 martin bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1105 1.34 jmcneill BUS_DMASYNC_PREWRITE);
1106 1.1 martin
1107 1.89 skrll /* sync the new descriptors - ownership not transferred yet */
1108 1.89 skrll dwc_gmac_txdesc_sync(sc, first, sc->sc_txq.t_cur,
1109 1.89 skrll BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1110 1.89 skrll
1111 1.32 martin /* Pass first to device */
1112 1.55 martin sc->sc_descm->tx_set_owned_by_dev(&sc->sc_txq.t_desc[first]);
1113 1.55 martin
1114 1.1 martin return 0;
1115 1.1 martin }
1116 1.1 martin
1117 1.22 martin /*
1118 1.22 martin * If the interface is up and running, only modify the receive
1119 1.22 martin * filter when setting promiscuous or debug mode. Otherwise fall
1120 1.22 martin * through to ether_ioctl, which will reset the chip.
1121 1.22 martin */
1122 1.22 martin static int
1123 1.22 martin dwc_gmac_ifflags_cb(struct ethercom *ec)
1124 1.22 martin {
1125 1.92 skrll struct ifnet * const ifp = &ec->ec_if;
1126 1.92 skrll struct dwc_gmac_softc * const sc = ifp->if_softc;
1127 1.38 skrll int ret = 0;
1128 1.38 skrll
1129 1.38 skrll mutex_enter(sc->sc_lock);
1130 1.65 msaitoh u_short change = ifp->if_flags ^ sc->sc_if_flags;
1131 1.38 skrll sc->sc_if_flags = ifp->if_flags;
1132 1.22 martin
1133 1.61 msaitoh if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
1134 1.38 skrll ret = ENETRESET;
1135 1.38 skrll goto out;
1136 1.38 skrll }
1137 1.38 skrll if ((change & IFF_PROMISC) != 0) {
1138 1.22 martin dwc_gmac_setmulti(sc);
1139 1.38 skrll }
1140 1.38 skrll out:
1141 1.38 skrll mutex_exit(sc->sc_lock);
1142 1.38 skrll
1143 1.38 skrll return ret;
1144 1.22 martin }
1145 1.22 martin
1146 1.1 martin static int
1147 1.1 martin dwc_gmac_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1148 1.1 martin {
1149 1.92 skrll struct dwc_gmac_softc * const sc = ifp->if_softc;
1150 1.38 skrll int error = 0;
1151 1.38 skrll
1152 1.38 skrll int s = splnet();
1153 1.38 skrll error = ether_ioctl(ifp, cmd, data);
1154 1.1 martin
1155 1.38 skrll #ifdef DWCGMAC_MPSAFE
1156 1.38 skrll splx(s);
1157 1.38 skrll #endif
1158 1.1 martin
1159 1.38 skrll if (error == ENETRESET) {
1160 1.1 martin error = 0;
1161 1.1 martin if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
1162 1.1 martin ;
1163 1.22 martin else if (ifp->if_flags & IFF_RUNNING) {
1164 1.22 martin /*
1165 1.22 martin * Multicast list has changed; set the hardware filter
1166 1.22 martin * accordingly.
1167 1.22 martin */
1168 1.38 skrll mutex_enter(sc->sc_lock);
1169 1.20 jmcneill dwc_gmac_setmulti(sc);
1170 1.38 skrll mutex_exit(sc->sc_lock);
1171 1.22 martin }
1172 1.1 martin }
1173 1.1 martin
1174 1.22 martin /* Try to get things going again */
1175 1.22 martin if (ifp->if_flags & IFF_UP)
1176 1.22 martin dwc_gmac_start(ifp);
1177 1.22 martin sc->sc_if_flags = sc->sc_ec.ec_if.if_flags;
1178 1.38 skrll
1179 1.38 skrll #ifndef DWCGMAC_MPSAFE
1180 1.1 martin splx(s);
1181 1.38 skrll #endif
1182 1.38 skrll
1183 1.1 martin return error;
1184 1.1 martin }
1185 1.1 martin
1186 1.8 martin static void
1187 1.8 martin dwc_gmac_tx_intr(struct dwc_gmac_softc *sc)
1188 1.8 martin {
1189 1.92 skrll struct ifnet * const ifp = &sc->sc_ec.ec_if;
1190 1.8 martin struct dwc_gmac_tx_data *data;
1191 1.8 martin struct dwc_gmac_dev_dmadesc *desc;
1192 1.32 martin int i, nsegs;
1193 1.8 martin
1194 1.38 skrll mutex_enter(&sc->sc_txq.t_mtx);
1195 1.38 skrll
1196 1.32 martin for (i = sc->sc_txq.t_next; sc->sc_txq.t_queued > 0; i = TX_NEXT(i)) {
1197 1.8 martin #ifdef DWC_GMAC_DEBUG
1198 1.8 martin aprint_normal_dev(sc->sc_dev,
1199 1.90 skrll "%s: checking desc #%d (t_queued: %d)\n", __func__,
1200 1.8 martin i, sc->sc_txq.t_queued);
1201 1.8 martin #endif
1202 1.8 martin
1203 1.26 martin /*
1204 1.82 skrll * i + 1 does not need to be a valid descriptor,
1205 1.26 martin * this is just a special notion to just sync
1206 1.26 martin * a single tx descriptor (i)
1207 1.26 martin */
1208 1.82 skrll dwc_gmac_txdesc_sync(sc, i, i + 1,
1209 1.61 msaitoh BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1210 1.11 martin
1211 1.32 martin desc = &sc->sc_txq.t_desc[i];
1212 1.55 martin if (sc->sc_descm->tx_is_owned_by_dev(desc))
1213 1.8 martin break;
1214 1.11 martin
1215 1.8 martin data = &sc->sc_txq.t_data[i];
1216 1.8 martin if (data->td_m == NULL)
1217 1.8 martin continue;
1218 1.32 martin
1219 1.69 thorpej if_statinc(ifp, if_opackets);
1220 1.32 martin nsegs = data->td_active->dm_nsegs;
1221 1.8 martin bus_dmamap_sync(sc->sc_dmat, data->td_active, 0,
1222 1.8 martin data->td_active->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1223 1.8 martin bus_dmamap_unload(sc->sc_dmat, data->td_active);
1224 1.8 martin
1225 1.8 martin #ifdef DWC_GMAC_DEBUG
1226 1.8 martin aprint_normal_dev(sc->sc_dev,
1227 1.90 skrll "%s: done with packet at desc #%d, freeing mbuf %p\n",
1228 1.90 skrll __func__, i, data->td_m);
1229 1.8 martin #endif
1230 1.8 martin
1231 1.8 martin m_freem(data->td_m);
1232 1.8 martin data->td_m = NULL;
1233 1.32 martin
1234 1.32 martin sc->sc_txq.t_queued -= nsegs;
1235 1.8 martin }
1236 1.8 martin
1237 1.8 martin sc->sc_txq.t_next = i;
1238 1.8 martin
1239 1.8 martin if (sc->sc_txq.t_queued < AWGE_TX_RING_COUNT) {
1240 1.78 thorpej sc->sc_txbusy = false;
1241 1.8 martin }
1242 1.38 skrll mutex_exit(&sc->sc_txq.t_mtx);
1243 1.8 martin }
1244 1.8 martin
1245 1.8 martin static void
1246 1.8 martin dwc_gmac_rx_intr(struct dwc_gmac_softc *sc)
1247 1.8 martin {
1248 1.92 skrll struct ifnet * const ifp = &sc->sc_ec.ec_if;
1249 1.11 martin struct dwc_gmac_dev_dmadesc *desc;
1250 1.11 martin struct dwc_gmac_rx_data *data;
1251 1.11 martin bus_addr_t physaddr;
1252 1.11 martin struct mbuf *m, *mnew;
1253 1.11 martin int i, len, error;
1254 1.11 martin
1255 1.38 skrll mutex_enter(&sc->sc_rxq.r_mtx);
1256 1.11 martin for (i = sc->sc_rxq.r_cur; ; i = RX_NEXT(i)) {
1257 1.90 skrll #ifdef DWC_GMAC_DEBUG
1258 1.90 skrll aprint_normal_dev(sc->sc_dev, "%s: checking desc #%d\n",
1259 1.90 skrll __func__, i);
1260 1.90 skrll #endif
1261 1.11 martin bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
1262 1.11 martin RX_DESC_OFFSET(i), sizeof(*desc),
1263 1.61 msaitoh BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1264 1.11 martin desc = &sc->sc_rxq.r_desc[i];
1265 1.11 martin data = &sc->sc_rxq.r_data[i];
1266 1.11 martin
1267 1.55 martin if (sc->sc_descm->rx_is_owned_by_dev(desc))
1268 1.11 martin break;
1269 1.11 martin
1270 1.55 martin if (sc->sc_descm->rx_has_error(desc)) {
1271 1.11 martin #ifdef DWC_GMAC_DEBUG
1272 1.15 martin aprint_normal_dev(sc->sc_dev,
1273 1.90 skrll "%s: RX error: status %08x, skipping\n",
1274 1.90 skrll __func__, le32toh(desc->ddesc_status0));
1275 1.11 martin #endif
1276 1.69 thorpej if_statinc(ifp, if_ierrors);
1277 1.11 martin goto skip;
1278 1.11 martin }
1279 1.11 martin
1280 1.55 martin len = sc->sc_descm->rx_get_len(desc);
1281 1.11 martin
1282 1.11 martin #ifdef DWC_GMAC_DEBUG
1283 1.15 martin aprint_normal_dev(sc->sc_dev,
1284 1.90 skrll "%s: device is done with descriptor #%d, len: %d\n",
1285 1.90 skrll __func__, i, len);
1286 1.11 martin #endif
1287 1.11 martin
1288 1.11 martin /*
1289 1.11 martin * Try to get a new mbuf before passing this one
1290 1.11 martin * up, if that fails, drop the packet and reuse
1291 1.11 martin * the existing one.
1292 1.11 martin */
1293 1.11 martin MGETHDR(mnew, M_DONTWAIT, MT_DATA);
1294 1.11 martin if (mnew == NULL) {
1295 1.69 thorpej if_statinc(ifp, if_ierrors);
1296 1.11 martin goto skip;
1297 1.11 martin }
1298 1.11 martin MCLGET(mnew, M_DONTWAIT);
1299 1.11 martin if ((mnew->m_flags & M_EXT) == 0) {
1300 1.11 martin m_freem(mnew);
1301 1.69 thorpej if_statinc(ifp, if_ierrors);
1302 1.11 martin goto skip;
1303 1.11 martin }
1304 1.66 tnn mnew->m_len = mnew->m_pkthdr.len = mnew->m_ext.ext_size;
1305 1.66 tnn if (mnew->m_len > AWGE_MAX_PACKET) {
1306 1.66 tnn mnew->m_len = mnew->m_pkthdr.len = AWGE_MAX_PACKET;
1307 1.66 tnn }
1308 1.11 martin
1309 1.11 martin /* unload old DMA map */
1310 1.11 martin bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
1311 1.11 martin data->rd_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1312 1.11 martin bus_dmamap_unload(sc->sc_dmat, data->rd_map);
1313 1.11 martin
1314 1.11 martin /* and reload with new mbuf */
1315 1.66 tnn error = bus_dmamap_load_mbuf(sc->sc_dmat, data->rd_map,
1316 1.66 tnn mnew, BUS_DMA_READ | BUS_DMA_NOWAIT);
1317 1.11 martin if (error != 0) {
1318 1.11 martin m_freem(mnew);
1319 1.11 martin /* try to reload old mbuf */
1320 1.66 tnn error = bus_dmamap_load_mbuf(sc->sc_dmat, data->rd_map,
1321 1.66 tnn data->rd_m, BUS_DMA_READ | BUS_DMA_NOWAIT);
1322 1.11 martin if (error != 0) {
1323 1.11 martin panic("%s: could not load old rx mbuf",
1324 1.11 martin device_xname(sc->sc_dev));
1325 1.11 martin }
1326 1.69 thorpej if_statinc(ifp, if_ierrors);
1327 1.11 martin goto skip;
1328 1.11 martin }
1329 1.11 martin physaddr = data->rd_map->dm_segs[0].ds_addr;
1330 1.11 martin
1331 1.90 skrll #ifdef DWC_GMAC_DEBUG
1332 1.90 skrll aprint_normal_dev(sc->sc_dev,
1333 1.90 skrll "%s: receiving packet at desc #%d, using mbuf %p\n",
1334 1.90 skrll __func__, i, data->rd_m);
1335 1.90 skrll #endif
1336 1.11 martin /*
1337 1.11 martin * New mbuf loaded, update RX ring and continue
1338 1.11 martin */
1339 1.11 martin m = data->rd_m;
1340 1.11 martin data->rd_m = mnew;
1341 1.11 martin desc->ddesc_data = htole32(physaddr);
1342 1.11 martin
1343 1.11 martin /* finalize mbuf */
1344 1.11 martin m->m_pkthdr.len = m->m_len = len;
1345 1.36 ozaki m_set_rcvif(m, ifp);
1346 1.77 sekiya m->m_flags |= M_HASFCS;
1347 1.11 martin
1348 1.39 skrll if_percpuq_enqueue(sc->sc_ipq, m);
1349 1.11 martin
1350 1.11 martin skip:
1351 1.27 matt bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
1352 1.27 matt data->rd_map->dm_mapsize, BUS_DMASYNC_PREREAD);
1353 1.55 martin
1354 1.55 martin sc->sc_descm->rx_init_flags(desc);
1355 1.66 tnn sc->sc_descm->rx_set_len(desc, data->rd_m->m_len);
1356 1.89 skrll
1357 1.89 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
1358 1.89 skrll RX_DESC_OFFSET(i), sizeof(*desc),
1359 1.89 skrll BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1360 1.89 skrll
1361 1.55 martin sc->sc_descm->rx_set_owned_by_dev(desc);
1362 1.55 martin
1363 1.11 martin bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
1364 1.11 martin RX_DESC_OFFSET(i), sizeof(*desc),
1365 1.61 msaitoh BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1366 1.11 martin }
1367 1.11 martin
1368 1.11 martin /* update RX pointer */
1369 1.11 martin sc->sc_rxq.r_cur = i;
1370 1.11 martin
1371 1.38 skrll mutex_exit(&sc->sc_rxq.r_mtx);
1372 1.8 martin }
1373 1.8 martin
1374 1.20 jmcneill static void
1375 1.20 jmcneill dwc_gmac_setmulti(struct dwc_gmac_softc *sc)
1376 1.20 jmcneill {
1377 1.20 jmcneill struct ifnet * const ifp = &sc->sc_ec.ec_if;
1378 1.20 jmcneill struct ether_multi *enm;
1379 1.20 jmcneill struct ether_multistep step;
1380 1.59 ozaki struct ethercom *ec = &sc->sc_ec;
1381 1.20 jmcneill uint32_t hashes[2] = { 0, 0 };
1382 1.22 martin uint32_t ffilt, h;
1383 1.38 skrll int mcnt;
1384 1.22 martin
1385 1.38 skrll KASSERT(mutex_owned(sc->sc_lock));
1386 1.20 jmcneill
1387 1.20 jmcneill ffilt = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT);
1388 1.38 skrll
1389 1.20 jmcneill if (ifp->if_flags & IFF_PROMISC) {
1390 1.22 martin ffilt |= AWIN_GMAC_MAC_FFILT_PR;
1391 1.22 martin goto special_filter;
1392 1.20 jmcneill }
1393 1.20 jmcneill
1394 1.61 msaitoh ffilt &= ~(AWIN_GMAC_MAC_FFILT_PM | AWIN_GMAC_MAC_FFILT_PR);
1395 1.20 jmcneill
1396 1.20 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW, 0);
1397 1.20 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH, 0);
1398 1.20 jmcneill
1399 1.59 ozaki ETHER_LOCK(ec);
1400 1.60 ozaki ec->ec_flags &= ~ETHER_F_ALLMULTI;
1401 1.59 ozaki ETHER_FIRST_MULTI(step, ec, enm);
1402 1.20 jmcneill mcnt = 0;
1403 1.20 jmcneill while (enm != NULL) {
1404 1.20 jmcneill if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1405 1.22 martin ETHER_ADDR_LEN) != 0) {
1406 1.60 ozaki ffilt |= AWIN_GMAC_MAC_FFILT_PM;
1407 1.60 ozaki ec->ec_flags |= ETHER_F_ALLMULTI;
1408 1.59 ozaki ETHER_UNLOCK(ec);
1409 1.22 martin goto special_filter;
1410 1.22 martin }
1411 1.20 jmcneill
1412 1.86 jakllsch h = ~ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
1413 1.20 jmcneill hashes[h >> 5] |= (1 << (h & 0x1f));
1414 1.20 jmcneill
1415 1.20 jmcneill mcnt++;
1416 1.20 jmcneill ETHER_NEXT_MULTI(step, enm);
1417 1.20 jmcneill }
1418 1.59 ozaki ETHER_UNLOCK(ec);
1419 1.20 jmcneill
1420 1.20 jmcneill if (mcnt)
1421 1.20 jmcneill ffilt |= AWIN_GMAC_MAC_FFILT_HMC;
1422 1.20 jmcneill else
1423 1.20 jmcneill ffilt &= ~AWIN_GMAC_MAC_FFILT_HMC;
1424 1.20 jmcneill
1425 1.20 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT, ffilt);
1426 1.20 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW,
1427 1.20 jmcneill hashes[0]);
1428 1.20 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH,
1429 1.20 jmcneill hashes[1]);
1430 1.60 ozaki sc->sc_if_flags = ifp->if_flags;
1431 1.22 martin
1432 1.22 martin #ifdef DWC_GMAC_DEBUG
1433 1.22 martin dwc_gmac_dump_ffilt(sc, ffilt);
1434 1.22 martin #endif
1435 1.22 martin return;
1436 1.22 martin
1437 1.22 martin special_filter:
1438 1.22 martin #ifdef DWC_GMAC_DEBUG
1439 1.22 martin dwc_gmac_dump_ffilt(sc, ffilt);
1440 1.22 martin #endif
1441 1.22 martin /* no MAC hashes, ALLMULTI or PROMISC */
1442 1.22 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT,
1443 1.22 martin ffilt);
1444 1.22 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW,
1445 1.22 martin 0xffffffff);
1446 1.22 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH,
1447 1.22 martin 0xffffffff);
1448 1.22 martin sc->sc_if_flags = sc->sc_ec.ec_if.if_flags;
1449 1.20 jmcneill }
1450 1.20 jmcneill
1451 1.1 martin int
1452 1.1 martin dwc_gmac_intr(struct dwc_gmac_softc *sc)
1453 1.1 martin {
1454 1.1 martin uint32_t status, dma_status;
1455 1.8 martin int rv = 0;
1456 1.1 martin
1457 1.38 skrll if (sc->sc_stopping)
1458 1.38 skrll return 0;
1459 1.38 skrll
1460 1.1 martin status = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTR);
1461 1.2 martin if (status & AWIN_GMAC_MII_IRQ) {
1462 1.1 martin (void)bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1463 1.1 martin AWIN_GMAC_MII_STATUS);
1464 1.8 martin rv = 1;
1465 1.2 martin mii_pollstat(&sc->sc_mii);
1466 1.2 martin }
1467 1.1 martin
1468 1.1 martin dma_status = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1469 1.1 martin AWIN_GMAC_DMA_STATUS);
1470 1.1 martin
1471 1.61 msaitoh if (dma_status & (GMAC_DMA_INT_NIE | GMAC_DMA_INT_AIE))
1472 1.8 martin rv = 1;
1473 1.1 martin
1474 1.8 martin if (dma_status & GMAC_DMA_INT_TIE)
1475 1.8 martin dwc_gmac_tx_intr(sc);
1476 1.1 martin
1477 1.8 martin if (dma_status & GMAC_DMA_INT_RIE)
1478 1.8 martin dwc_gmac_rx_intr(sc);
1479 1.8 martin
1480 1.8 martin /*
1481 1.8 martin * Check error conditions
1482 1.8 martin */
1483 1.8 martin if (dma_status & GMAC_DMA_INT_ERRORS) {
1484 1.69 thorpej if_statinc(&sc->sc_ec.ec_if, if_oerrors);
1485 1.8 martin #ifdef DWC_GMAC_DEBUG
1486 1.8 martin dwc_dump_and_abort(sc, "interrupt error condition");
1487 1.8 martin #endif
1488 1.8 martin }
1489 1.8 martin
1490 1.63 msaitoh rnd_add_uint32(&sc->rnd_source, dma_status);
1491 1.63 msaitoh
1492 1.8 martin /* ack interrupt */
1493 1.8 martin if (dma_status)
1494 1.8 martin bus_space_write_4(sc->sc_bst, sc->sc_bsh,
1495 1.8 martin AWIN_GMAC_DMA_STATUS, dma_status & GMAC_DMA_INT_MASK);
1496 1.8 martin
1497 1.28 martin /*
1498 1.28 martin * Get more packets
1499 1.28 martin */
1500 1.28 martin if (rv)
1501 1.40 ozaki if_schedule_deferred_start(&sc->sc_ec.ec_if);
1502 1.28 martin
1503 1.8 martin return rv;
1504 1.1 martin }
1505 1.7 martin
1506 1.55 martin static void
1507 1.55 martin dwc_gmac_desc_set_owned_by_dev(struct dwc_gmac_dev_dmadesc *desc)
1508 1.55 martin {
1509 1.55 martin
1510 1.55 martin desc->ddesc_status0 |= htole32(DDESC_STATUS_OWNEDBYDEV);
1511 1.55 martin }
1512 1.55 martin
1513 1.55 martin static int
1514 1.55 martin dwc_gmac_desc_is_owned_by_dev(struct dwc_gmac_dev_dmadesc *desc)
1515 1.55 martin {
1516 1.55 martin
1517 1.55 martin return !!(le32toh(desc->ddesc_status0) & DDESC_STATUS_OWNEDBYDEV);
1518 1.55 martin }
1519 1.55 martin
1520 1.55 martin static void
1521 1.55 martin dwc_gmac_desc_std_set_len(struct dwc_gmac_dev_dmadesc *desc, int len)
1522 1.55 martin {
1523 1.55 martin uint32_t cntl = le32toh(desc->ddesc_cntl1);
1524 1.55 martin
1525 1.55 martin desc->ddesc_cntl1 = htole32((cntl & ~DDESC_CNTL_SIZE1MASK) |
1526 1.55 martin __SHIFTIN(len, DDESC_CNTL_SIZE1MASK));
1527 1.55 martin }
1528 1.55 martin
1529 1.55 martin static uint32_t
1530 1.55 martin dwc_gmac_desc_std_get_len(struct dwc_gmac_dev_dmadesc *desc)
1531 1.55 martin {
1532 1.55 martin
1533 1.55 martin return __SHIFTOUT(le32toh(desc->ddesc_status0), DDESC_STATUS_FRMLENMSK);
1534 1.55 martin }
1535 1.55 martin
1536 1.55 martin static void
1537 1.55 martin dwc_gmac_desc_std_tx_init_flags(struct dwc_gmac_dev_dmadesc *desc)
1538 1.55 martin {
1539 1.55 martin
1540 1.55 martin desc->ddesc_status0 = 0;
1541 1.55 martin desc->ddesc_cntl1 = htole32(DDESC_CNTL_TXCHAIN);
1542 1.55 martin }
1543 1.55 martin
1544 1.55 martin static void
1545 1.55 martin dwc_gmac_desc_std_tx_set_first_frag(struct dwc_gmac_dev_dmadesc *desc)
1546 1.55 martin {
1547 1.55 martin uint32_t cntl = le32toh(desc->ddesc_cntl1);
1548 1.55 martin
1549 1.55 martin desc->ddesc_cntl1 = htole32(cntl | DDESC_CNTL_TXFIRST);
1550 1.55 martin }
1551 1.55 martin
1552 1.55 martin static void
1553 1.55 martin dwc_gmac_desc_std_tx_set_last_frag(struct dwc_gmac_dev_dmadesc *desc)
1554 1.55 martin {
1555 1.55 martin uint32_t cntl = le32toh(desc->ddesc_cntl1);
1556 1.55 martin
1557 1.55 martin desc->ddesc_cntl1 = htole32(cntl |
1558 1.55 martin DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT);
1559 1.55 martin }
1560 1.55 martin
1561 1.55 martin static void
1562 1.55 martin dwc_gmac_desc_std_rx_init_flags(struct dwc_gmac_dev_dmadesc *desc)
1563 1.55 martin {
1564 1.55 martin
1565 1.55 martin desc->ddesc_status0 = 0;
1566 1.55 martin desc->ddesc_cntl1 = htole32(DDESC_CNTL_TXCHAIN);
1567 1.55 martin }
1568 1.55 martin
1569 1.55 martin static int
1570 1.55 martin dwc_gmac_desc_std_rx_has_error(struct dwc_gmac_dev_dmadesc *desc) {
1571 1.55 martin return !!(le32toh(desc->ddesc_status0) &
1572 1.55 martin (DDESC_STATUS_RXERROR | DDESC_STATUS_RXTRUNCATED));
1573 1.55 martin }
1574 1.55 martin
1575 1.55 martin static void
1576 1.55 martin dwc_gmac_desc_enh_set_len(struct dwc_gmac_dev_dmadesc *desc, int len)
1577 1.55 martin {
1578 1.55 martin uint32_t tdes1 = le32toh(desc->ddesc_cntl1);
1579 1.55 martin
1580 1.55 martin desc->ddesc_cntl1 = htole32((tdes1 & ~DDESC_DES1_SIZE1MASK) |
1581 1.55 martin __SHIFTIN(len, DDESC_DES1_SIZE1MASK));
1582 1.55 martin }
1583 1.55 martin
1584 1.55 martin static uint32_t
1585 1.55 martin dwc_gmac_desc_enh_get_len(struct dwc_gmac_dev_dmadesc *desc)
1586 1.55 martin {
1587 1.55 martin
1588 1.55 martin return __SHIFTOUT(le32toh(desc->ddesc_status0), DDESC_RDES0_FL);
1589 1.55 martin }
1590 1.55 martin
1591 1.55 martin static void
1592 1.55 martin dwc_gmac_desc_enh_tx_init_flags(struct dwc_gmac_dev_dmadesc *desc)
1593 1.55 martin {
1594 1.55 martin
1595 1.55 martin desc->ddesc_status0 = htole32(DDESC_TDES0_TCH);
1596 1.55 martin desc->ddesc_cntl1 = 0;
1597 1.55 martin }
1598 1.55 martin
1599 1.55 martin static void
1600 1.55 martin dwc_gmac_desc_enh_tx_set_first_frag(struct dwc_gmac_dev_dmadesc *desc)
1601 1.55 martin {
1602 1.55 martin uint32_t tdes0 = le32toh(desc->ddesc_status0);
1603 1.55 martin
1604 1.55 martin desc->ddesc_status0 = htole32(tdes0 | DDESC_TDES0_FS);
1605 1.55 martin }
1606 1.55 martin
1607 1.55 martin static void
1608 1.55 martin dwc_gmac_desc_enh_tx_set_last_frag(struct dwc_gmac_dev_dmadesc *desc)
1609 1.55 martin {
1610 1.55 martin uint32_t tdes0 = le32toh(desc->ddesc_status0);
1611 1.55 martin
1612 1.55 martin desc->ddesc_status0 = htole32(tdes0 | DDESC_TDES0_LS | DDESC_TDES0_IC);
1613 1.55 martin }
1614 1.55 martin
1615 1.55 martin static void
1616 1.55 martin dwc_gmac_desc_enh_rx_init_flags(struct dwc_gmac_dev_dmadesc *desc)
1617 1.55 martin {
1618 1.55 martin
1619 1.55 martin desc->ddesc_status0 = 0;
1620 1.55 martin desc->ddesc_cntl1 = htole32(DDESC_RDES1_RCH);
1621 1.55 martin }
1622 1.55 martin
1623 1.55 martin static int
1624 1.55 martin dwc_gmac_desc_enh_rx_has_error(struct dwc_gmac_dev_dmadesc *desc)
1625 1.55 martin {
1626 1.55 martin
1627 1.55 martin return !!(le32toh(desc->ddesc_status0) &
1628 1.55 martin (DDESC_RDES0_ES | DDESC_RDES0_LE));
1629 1.55 martin }
1630 1.55 martin
1631 1.7 martin #ifdef DWC_GMAC_DEBUG
1632 1.7 martin static void
1633 1.7 martin dwc_gmac_dump_dma(struct dwc_gmac_softc *sc)
1634 1.7 martin {
1635 1.7 martin aprint_normal_dev(sc->sc_dev, "busmode: %08x\n",
1636 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE));
1637 1.7 martin aprint_normal_dev(sc->sc_dev, "tx poll: %08x\n",
1638 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TXPOLL));
1639 1.7 martin aprint_normal_dev(sc->sc_dev, "rx poll: %08x\n",
1640 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RXPOLL));
1641 1.7 martin aprint_normal_dev(sc->sc_dev, "rx descriptors: %08x\n",
1642 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR));
1643 1.7 martin aprint_normal_dev(sc->sc_dev, "tx descriptors: %08x\n",
1644 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR));
1645 1.90 skrll aprint_normal_dev(sc->sc_dev, " status: %08x\n",
1646 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_STATUS));
1647 1.7 martin aprint_normal_dev(sc->sc_dev, "op mode: %08x\n",
1648 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_OPMODE));
1649 1.90 skrll aprint_normal_dev(sc->sc_dev, "int en.: %08x\n",
1650 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_INTENABLE));
1651 1.90 skrll aprint_normal_dev(sc->sc_dev, " cur tx: %08x\n",
1652 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_CUR_TX_DESC));
1653 1.90 skrll aprint_normal_dev(sc->sc_dev, " cur rx: %08x\n",
1654 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_CUR_RX_DESC));
1655 1.90 skrll aprint_normal_dev(sc->sc_dev, "cur txb: %08x\n",
1656 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_CUR_TX_BUFADDR));
1657 1.90 skrll aprint_normal_dev(sc->sc_dev, "cur rxb: %08x\n",
1658 1.7 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_CUR_RX_BUFADDR));
1659 1.7 martin }
1660 1.7 martin
1661 1.7 martin static void
1662 1.7 martin dwc_gmac_dump_tx_desc(struct dwc_gmac_softc *sc)
1663 1.7 martin {
1664 1.89 skrll const size_t descsz = sizeof(struct dwc_gmac_dev_dmadesc);
1665 1.7 martin
1666 1.8 martin aprint_normal_dev(sc->sc_dev, "TX queue: cur=%d, next=%d, queued=%d\n",
1667 1.8 martin sc->sc_txq.t_cur, sc->sc_txq.t_next, sc->sc_txq.t_queued);
1668 1.8 martin aprint_normal_dev(sc->sc_dev, "TX DMA descriptors:\n");
1669 1.89 skrll
1670 1.89 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
1671 1.89 skrll TX_DESC_OFFSET(0), AWGE_TX_RING_COUNT * descsz,
1672 1.89 skrll BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1673 1.89 skrll
1674 1.90 skrll for (size_t i = 0; i < AWGE_TX_RING_COUNT; i++) {
1675 1.7 martin struct dwc_gmac_dev_dmadesc *desc = &sc->sc_txq.t_desc[i];
1676 1.90 skrll aprint_normal("#%3zu (%08lx): status: %08x cntl: %08x "
1677 1.15 martin "data: %08x next: %08x\n",
1678 1.90 skrll i, sc->sc_txq.t_physaddr + i * descsz,
1679 1.55 martin le32toh(desc->ddesc_status0), le32toh(desc->ddesc_cntl1),
1680 1.7 martin le32toh(desc->ddesc_data), le32toh(desc->ddesc_next));
1681 1.7 martin }
1682 1.7 martin }
1683 1.8 martin
1684 1.8 martin static void
1685 1.11 martin dwc_gmac_dump_rx_desc(struct dwc_gmac_softc *sc)
1686 1.11 martin {
1687 1.89 skrll const size_t descsz = sizeof(struct dwc_gmac_dev_dmadesc);
1688 1.11 martin
1689 1.11 martin aprint_normal_dev(sc->sc_dev, "RX queue: cur=%d, next=%d\n",
1690 1.11 martin sc->sc_rxq.r_cur, sc->sc_rxq.r_next);
1691 1.11 martin aprint_normal_dev(sc->sc_dev, "RX DMA descriptors:\n");
1692 1.89 skrll
1693 1.89 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
1694 1.89 skrll RX_DESC_OFFSET(0), AWGE_RX_RING_COUNT * descsz,
1695 1.89 skrll BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1696 1.89 skrll
1697 1.90 skrll for (size_t i = 0; i < AWGE_RX_RING_COUNT; i++) {
1698 1.11 martin struct dwc_gmac_dev_dmadesc *desc = &sc->sc_rxq.r_desc[i];
1699 1.90 skrll char buf[200];
1700 1.90 skrll
1701 1.90 skrll if (!sc->sc_descm->rx_is_owned_by_dev(desc)) {
1702 1.90 skrll /* print interrupt state */
1703 1.90 skrll snprintb(buf, sizeof(buf),
1704 1.90 skrll "\177\20"
1705 1.90 skrll "b\x1e" "daff\0"
1706 1.90 skrll "f\x10\xe" "frlen\0"
1707 1.90 skrll "b\x0f" "error\0"
1708 1.90 skrll "b\x0e" "rxtrunc\0" /* descriptor error? */
1709 1.90 skrll "b\x0d" "saff\0"
1710 1.90 skrll "b\x0c" "giantframe\0" /* length error? */
1711 1.90 skrll "b\x0b" "damaged\0"
1712 1.90 skrll "b\x0a" "vlan\0"
1713 1.90 skrll "b\x09" "first\0"
1714 1.90 skrll "b\x08" "last\0"
1715 1.90 skrll "b\x07" "giant\0"
1716 1.90 skrll "b\x06" "collison\0"
1717 1.90 skrll "b\x05" "ether\0"
1718 1.90 skrll "b\x04" "watchdog\0"
1719 1.90 skrll "b\x03" "miierror\0"
1720 1.90 skrll "b\x02" "dribbling\0"
1721 1.90 skrll "b\x01" "crc\0"
1722 1.90 skrll "\0", le32toh(desc->ddesc_status0));
1723 1.90 skrll }
1724 1.90 skrll
1725 1.90 skrll aprint_normal("#%3zu (%08lx): status: %08x cntl: %08x "
1726 1.90 skrll "data: %08x next: %08x %s\n",
1727 1.90 skrll i, sc->sc_rxq.r_physaddr + i * descsz,
1728 1.55 martin le32toh(desc->ddesc_status0), le32toh(desc->ddesc_cntl1),
1729 1.90 skrll le32toh(desc->ddesc_data), le32toh(desc->ddesc_next),
1730 1.90 skrll sc->sc_descm->rx_is_owned_by_dev(desc) ? "" : buf);
1731 1.11 martin }
1732 1.11 martin }
1733 1.11 martin
1734 1.11 martin static void
1735 1.10 martin dwc_dump_status(struct dwc_gmac_softc *sc)
1736 1.8 martin {
1737 1.8 martin uint32_t status = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1738 1.87 skrll AWIN_GMAC_MAC_INTR);
1739 1.8 martin uint32_t dma_status = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1740 1.87 skrll AWIN_GMAC_DMA_STATUS);
1741 1.8 martin char buf[200];
1742 1.8 martin
1743 1.8 martin /* print interrupt state */
1744 1.90 skrll snprintb(buf, sizeof(buf),
1745 1.90 skrll "\177\20"
1746 1.90 skrll "b\x1c" "GPI\0"
1747 1.90 skrll "b\x1b" "GMC\0"
1748 1.90 skrll "b\x1a" "GLI\0"
1749 1.90 skrll "f\x17\x3" "EB\0"
1750 1.90 skrll "f\x14\x3" "TPS\0"
1751 1.90 skrll "f\x11\x3" "RPS\0"
1752 1.90 skrll "b\x10" "NI\0"
1753 1.90 skrll "b\x0f" "AI\0"
1754 1.90 skrll "b\x0e" "ER\0"
1755 1.90 skrll "b\x0d" "FB\0"
1756 1.90 skrll "b\x0a" "ET\0"
1757 1.90 skrll "b\x09" "RW\0"
1758 1.90 skrll "b\x08" "RS\0"
1759 1.90 skrll "b\x07" "RU\0"
1760 1.90 skrll "b\x06" "RI\0"
1761 1.90 skrll "b\x05" "UN\0"
1762 1.90 skrll "b\x04" "OV\0"
1763 1.90 skrll "b\x03" "TJ\0"
1764 1.90 skrll "b\x02" "TU\0"
1765 1.90 skrll "b\x01" "TS\0"
1766 1.90 skrll "b\x00" "TI\0"
1767 1.8 martin "\0", dma_status);
1768 1.10 martin aprint_normal_dev(sc->sc_dev, "INTR status: %08x, DMA status: %s\n",
1769 1.8 martin status, buf);
1770 1.10 martin }
1771 1.8 martin
1772 1.10 martin static void
1773 1.10 martin dwc_dump_and_abort(struct dwc_gmac_softc *sc, const char *msg)
1774 1.10 martin {
1775 1.10 martin dwc_dump_status(sc);
1776 1.22 martin dwc_gmac_dump_ffilt(sc,
1777 1.22 martin bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT));
1778 1.8 martin dwc_gmac_dump_dma(sc);
1779 1.8 martin dwc_gmac_dump_tx_desc(sc);
1780 1.11 martin dwc_gmac_dump_rx_desc(sc);
1781 1.8 martin
1782 1.21 joerg panic("%s", msg);
1783 1.8 martin }
1784 1.22 martin
1785 1.22 martin static void dwc_gmac_dump_ffilt(struct dwc_gmac_softc *sc, uint32_t ffilt)
1786 1.22 martin {
1787 1.22 martin char buf[200];
1788 1.22 martin
1789 1.22 martin /* print filter setup */
1790 1.22 martin snprintb(buf, sizeof(buf), "\177\20"
1791 1.22 martin "b\x1f""RA\0"
1792 1.22 martin "b\x0a""HPF\0"
1793 1.22 martin "b\x09""SAF\0"
1794 1.22 martin "b\x08""SAIF\0"
1795 1.22 martin "b\x05""DBF\0"
1796 1.22 martin "b\x04""PM\0"
1797 1.22 martin "b\x03""DAIF\0"
1798 1.22 martin "b\x02""HMC\0"
1799 1.22 martin "b\x01""HUC\0"
1800 1.22 martin "b\x00""PR\0"
1801 1.22 martin "\0", ffilt);
1802 1.22 martin aprint_normal_dev(sc->sc_dev, "FFILT: %s\n", buf);
1803 1.22 martin }
1804 1.7 martin #endif
1805