dwc_mmc.c revision 1.1
1 /* $NetBSD: dwc_mmc.c,v 1.1 2014/12/27 01:18:48 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_dwc_mmc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.1 2014/12/27 01:18:48 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/sdmmc/sdmmcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmc_ioreg.h> 44 45 #include <dev/ic/dwc_mmc_reg.h> 46 #include <dev/ic/dwc_mmc_var.h> 47 48 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 49 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 50 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 51 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 52 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 53 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 54 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 55 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 56 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 57 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 58 struct sdmmc_command *); 59 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 60 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 61 62 static int dwc_mmc_set_clock(struct dwc_mmc_softc *, u_int); 63 static int dwc_mmc_update_clock(struct dwc_mmc_softc *); 64 static int dwc_mmc_wait_rint(struct dwc_mmc_softc *, uint32_t, int); 65 static int dwc_mmc_pio_wait(struct dwc_mmc_softc *, 66 struct sdmmc_command *); 67 static int dwc_mmc_pio_transfer(struct dwc_mmc_softc *, 68 struct sdmmc_command *); 69 70 void dwc_mmc_dump_regs(void); 71 72 static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 73 .host_reset = dwc_mmc_host_reset, 74 .host_ocr = dwc_mmc_host_ocr, 75 .host_maxblklen = dwc_mmc_host_maxblklen, 76 .card_detect = dwc_mmc_card_detect, 77 .write_protect = dwc_mmc_write_protect, 78 .bus_power = dwc_mmc_bus_power, 79 .bus_clock = dwc_mmc_bus_clock, 80 .bus_width = dwc_mmc_bus_width, 81 .bus_rod = dwc_mmc_bus_rod, 82 .exec_command = dwc_mmc_exec_command, 83 .card_enable_intr = dwc_mmc_card_enable_intr, 84 .card_intr_ack = dwc_mmc_card_intr_ack, 85 }; 86 87 #define MMC_WRITE(sc, reg, val) \ 88 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 89 #define MMC_READ(sc, reg) \ 90 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 91 92 void 93 dwc_mmc_init(struct dwc_mmc_softc *sc) 94 { 95 struct sdmmcbus_attach_args saa; 96 97 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 98 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 99 100 dwc_mmc_host_reset(sc); 101 dwc_mmc_bus_width(sc, 1); 102 dwc_mmc_bus_clock(sc, 400); 103 104 memset(&saa, 0, sizeof(saa)); 105 saa.saa_busname = "sdmmc"; 106 saa.saa_sct = &dwc_mmc_chip_functions; 107 saa.saa_sch = sc; 108 saa.saa_clkmin = 400; 109 saa.saa_clkmax = 25000; 110 saa.saa_caps = SMC_CAPS_4BIT_MODE| 111 SMC_CAPS_8BIT_MODE| 112 SMC_CAPS_SD_HIGHSPEED| 113 SMC_CAPS_MMC_HIGHSPEED| 114 SMC_CAPS_AUTO_STOP; 115 #if notyet 116 saa.saa_dmat = sc->sc_dmat; 117 saa.saa_caps |= SMC_CAPS_DMA| 118 SMC_CAPS_MULTI_SEG_DMA; 119 #endif 120 121 sc->sc_sdmmc_dev = config_found(sc->sc_dev, &saa, NULL); 122 } 123 124 int 125 dwc_mmc_intr(void *priv) 126 { 127 struct dwc_mmc_softc *sc = priv; 128 uint32_t mint, rint; 129 130 mutex_enter(&sc->sc_intr_lock); 131 rint = MMC_READ(sc, DWC_MMC_RINTSTS_REG); 132 mint = MMC_READ(sc, DWC_MMC_MINTSTS_REG); 133 if (!rint && !mint) { 134 mutex_exit(&sc->sc_intr_lock); 135 return 0; 136 } 137 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, rint); 138 MMC_WRITE(sc, DWC_MMC_MINTSTS_REG, mint); 139 140 #ifdef DWC_MMC_DEBUG 141 device_printf(sc->sc_dev, "mint %#x rint %#x\n", mint, rint); 142 #endif 143 144 if (rint & DWC_MMC_INT_CARDDET) { 145 rint &= ~DWC_MMC_INT_CARDDET; 146 if (sc->sc_sdmmc_dev) { 147 sdmmc_needs_discover(sc->sc_sdmmc_dev); 148 } 149 } 150 151 if (rint) { 152 sc->sc_intr_rint |= rint; 153 cv_broadcast(&sc->sc_intr_cv); 154 } 155 156 mutex_exit(&sc->sc_intr_lock); 157 158 return 1; 159 } 160 161 static int 162 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 163 { 164 u_int pll_freq = sc->sc_clock_freq / 1000; 165 u_int n = howmany(pll_freq, freq) >> 1; 166 167 #ifdef DWC_MMC_DEBUG 168 device_printf(sc->sc_dev, "%s: n=%u freq=%u\n", 169 __func__, n, n ? pll_freq / (2 * n) : pll_freq); 170 #endif 171 172 MMC_WRITE(sc, DWC_MMC_CLKDIV_REG, 173 __SHIFTIN(n, DWC_MMC_CLKDIV_CLK_DIVIDER0)); 174 175 return dwc_mmc_update_clock(sc); 176 } 177 178 static int 179 dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 180 { 181 uint32_t cmd; 182 int retry; 183 184 cmd = DWC_MMC_CMD_START_CMD | 185 DWC_MMC_CMD_UPDATE_CLOCK_REGS_ONLY | 186 DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE; 187 188 if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG) 189 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 190 191 MMC_WRITE(sc, DWC_MMC_CMD_REG, cmd); 192 retry = 0xfffff; 193 while (--retry > 0) { 194 cmd = MMC_READ(sc, DWC_MMC_CMD_REG); 195 if ((cmd & DWC_MMC_CMD_START_CMD) == 0) 196 break; 197 delay(10); 198 } 199 200 if (retry == 0) { 201 device_printf(sc->sc_dev, "timeout updating clock\n"); 202 return ETIMEDOUT; 203 } 204 205 return 0; 206 } 207 208 static int 209 dwc_mmc_wait_rint(struct dwc_mmc_softc *sc, uint32_t mask, int timeout) 210 { 211 int retry, error; 212 213 KASSERT(mutex_owned(&sc->sc_intr_lock)); 214 215 if (sc->sc_intr_rint & mask) 216 return 0; 217 218 retry = timeout / hz; 219 220 while (retry > 0) { 221 error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, hz); 222 if (error && error != EWOULDBLOCK) 223 return error; 224 if (sc->sc_intr_rint & mask) 225 return 0; 226 --retry; 227 } 228 229 return ETIMEDOUT; 230 } 231 232 static int 233 dwc_mmc_pio_wait(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 234 { 235 int retry = 0xfffff; 236 uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ? 237 DWC_MMC_STATUS_FIFO_EMPTY : DWC_MMC_STATUS_FIFO_FULL; 238 239 while (--retry > 0) { 240 uint32_t status = MMC_READ(sc, DWC_MMC_STATUS_REG); 241 if (!(status & bit)) 242 return 0; 243 delay(10); 244 } 245 246 #ifdef DWC_MMC_DEBUG 247 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 248 #endif 249 250 return ETIMEDOUT; 251 } 252 253 static int 254 dwc_mmc_pio_transfer(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 255 { 256 uint32_t *datap = (uint32_t *)cmd->c_data; 257 int i; 258 259 for (i = 0; i < (cmd->c_resid >> 2); i++) { 260 if (dwc_mmc_pio_wait(sc, cmd)) 261 return ETIMEDOUT; 262 if (cmd->c_flags & SCF_CMD_READ) { 263 datap[i] = MMC_READ(sc, DWC_MMC_FIFO_BASE_REG); 264 } else { 265 MMC_WRITE(sc, DWC_MMC_FIFO_BASE_REG, datap[i]); 266 } 267 } 268 269 return 0; 270 } 271 272 static int 273 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 274 { 275 struct dwc_mmc_softc *sc = sch; 276 int retry = 1000; 277 uint32_t ctrl, fifoth; 278 uint32_t rx_wmark, tx_wmark; 279 280 MMC_WRITE(sc, DWC_MMC_PWREN_REG, DWC_MMC_PWREN_POWER_ENABLE); 281 282 MMC_WRITE(sc, DWC_MMC_CTRL_REG, 283 MMC_READ(sc, DWC_MMC_CTRL_REG) | DWC_MMC_CTRL_CONTROLLER_RESET); 284 while (--retry > 0) { 285 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 286 if (ctrl & DWC_MMC_CTRL_CONTROLLER_RESET) 287 break; 288 delay(100); 289 } 290 291 MMC_WRITE(sc, DWC_MMC_TMOUT_REG, 0xffffffff); 292 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, 0xffffffff); 293 294 MMC_WRITE(sc, DWC_MMC_INTMASK_REG, 295 DWC_MMC_INT_CD | DWC_MMC_INT_ACD | DWC_MMC_INT_DTO | 296 DWC_MMC_INT_ERROR | DWC_MMC_INT_CARDDET); 297 298 rx_wmark = (sc->sc_fifo_depth / 2) - 1; 299 tx_wmark = sc->sc_fifo_depth / 2; 300 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 301 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 302 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 303 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 304 MMC_WRITE(sc, DWC_MMC_FIFOTH_REG, fifoth); 305 306 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 307 ctrl |= DWC_MMC_CTRL_INT_ENABLE; 308 MMC_WRITE(sc, DWC_MMC_CTRL_REG, ctrl); 309 310 return 0; 311 } 312 313 static uint32_t 314 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 315 { 316 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 317 } 318 319 static int 320 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 321 { 322 return 32768; 323 } 324 325 static int 326 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 327 { 328 struct dwc_mmc_softc *sc = sch; 329 uint32_t cdetect; 330 331 cdetect = MMC_READ(sc, DWC_MMC_CDETECT_REG); 332 return !!(cdetect & DWC_MMC_CDETECT_CARD_DETECT_N); 333 } 334 335 static int 336 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 337 { 338 struct dwc_mmc_softc *sc = sch; 339 uint32_t wrtprt; 340 341 wrtprt = MMC_READ(sc, DWC_MMC_WRTPRT_REG); 342 return !!(wrtprt & DWC_MMC_WRTPRT_WRITE_PROTECT); 343 } 344 345 static int 346 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 347 { 348 return 0; 349 } 350 351 static int 352 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 353 { 354 struct dwc_mmc_softc *sc = sch; 355 uint32_t clkdiv, clkena; 356 357 #ifdef DWC_MMC_DEBUG 358 device_printf(sc->sc_dev, "%s: freq %d\n", __func__, freq); 359 #endif 360 361 clkena = MMC_READ(sc, DWC_MMC_CLKENA_REG); 362 if (clkena & DWC_MMC_CLKENA_CCLK_ENABLE) { 363 clkena &= ~DWC_MMC_CLKENA_CCLK_ENABLE; 364 MMC_WRITE(sc, DWC_MMC_CLKENA_REG, clkena); 365 if (dwc_mmc_update_clock(sc) != 0) 366 return ETIMEDOUT; 367 } 368 369 if (freq) { 370 clkdiv = MMC_READ(sc, DWC_MMC_CLKDIV_REG); 371 clkdiv &= ~DWC_MMC_CLKDIV_CLK_DIVIDER0; 372 if (dwc_mmc_update_clock(sc) != 0) 373 return ETIMEDOUT; 374 375 if (dwc_mmc_set_clock(sc, freq) != 0) 376 return EIO; 377 378 clkena |= DWC_MMC_CLKENA_CCLK_ENABLE; 379 clkena |= DWC_MMC_CLKENA_CCLK_LOW_POWER; /* XXX SD/MMC only */ 380 MMC_WRITE(sc, DWC_MMC_CLKENA_REG, clkena); 381 if (dwc_mmc_update_clock(sc) != 0) 382 return ETIMEDOUT; 383 } 384 385 return 0; 386 } 387 388 static int 389 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 390 { 391 struct dwc_mmc_softc *sc = sch; 392 uint32_t ctype; 393 394 switch (width) { 395 case 1: 396 ctype = DWC_MMC_CTYPE_CARD_WIDTH_1; 397 break; 398 case 4: 399 ctype = DWC_MMC_CTYPE_CARD_WIDTH_4; 400 break; 401 case 8: 402 ctype = DWC_MMC_CTYPE_CARD_WIDTH_8; 403 break; 404 default: 405 return EINVAL; 406 } 407 408 MMC_WRITE(sc, DWC_MMC_CTYPE_REG, ctype); 409 410 return 0; 411 } 412 413 static int 414 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 415 { 416 return ENOTSUP; 417 } 418 419 static void 420 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 421 { 422 struct dwc_mmc_softc *sc = sch; 423 uint32_t cmdval = DWC_MMC_CMD_START_CMD; 424 uint32_t ctrl; 425 426 if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG) 427 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 428 429 mutex_enter(&sc->sc_intr_lock); 430 if (cmd->c_opcode == 0) 431 cmdval |= DWC_MMC_CMD_SEND_INIT; 432 if (cmd->c_flags & SCF_RSP_PRESENT) 433 cmdval |= DWC_MMC_CMD_RESP_EXPECTED; 434 if (cmd->c_flags & SCF_RSP_136) 435 cmdval |= DWC_MMC_CMD_RESP_LEN; 436 if (cmd->c_flags & SCF_RSP_CRC) 437 cmdval |= DWC_MMC_CMD_CHECK_RESP_CRC; 438 439 if (cmd->c_datalen > 0) { 440 unsigned int nblks; 441 442 cmdval |= DWC_MMC_CMD_DATA_EXPECTED; 443 cmdval |= DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE; 444 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 445 cmdval |= DWC_MMC_CMD_WR; 446 } 447 448 nblks = cmd->c_datalen / cmd->c_blklen; 449 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 450 ++nblks; 451 452 if (nblks > 1) { 453 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 454 } 455 456 MMC_WRITE(sc, DWC_MMC_BLKSIZ_REG, cmd->c_blklen); 457 MMC_WRITE(sc, DWC_MMC_BYTCNT_REG, nblks * cmd->c_blklen); 458 } 459 460 sc->sc_intr_rint = 0; 461 462 MMC_WRITE(sc, DWC_MMC_CMDARG_REG, cmd->c_arg); 463 464 cmd->c_resid = cmd->c_datalen; 465 MMC_WRITE(sc, DWC_MMC_CMD_REG, cmdval | cmd->c_opcode); 466 if (cmd->c_datalen > 0) { 467 cmd->c_error = dwc_mmc_pio_transfer(sc, cmd); 468 if (cmd->c_error) { 469 goto done; 470 } 471 } 472 473 cmd->c_error = dwc_mmc_wait_rint(sc, 474 DWC_MMC_INT_ERROR|DWC_MMC_INT_CD, hz * 10); 475 if (cmd->c_error == 0 && (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 476 #ifdef DWC_MMC_DEBUG 477 device_printf(sc->sc_dev, "%s: rint %#x\n", __func__, 478 sc->sc_intr_rint); 479 #endif 480 if (sc->sc_intr_rint & DWC_MMC_INT_RTO) { 481 cmd->c_error = ETIMEDOUT; 482 } else { 483 cmd->c_error = EIO; 484 } 485 } 486 if (cmd->c_error) { 487 goto done; 488 } 489 490 if (cmd->c_datalen > 0) { 491 cmd->c_error = dwc_mmc_wait_rint(sc, 492 DWC_MMC_INT_ERROR|DWC_MMC_INT_ACD|DWC_MMC_INT_DTO, 493 hz * 10); 494 if (cmd->c_error == 0 && 495 (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 496 #ifdef DWC_MMC_DEBUG 497 device_printf(sc->sc_dev, "%s: rint2 %#x\n", __func__, 498 sc->sc_intr_rint); 499 #endif 500 cmd->c_error = ETIMEDOUT; 501 } 502 if (cmd->c_error) { 503 goto done; 504 } 505 } 506 507 if (cmd->c_flags & SCF_RSP_PRESENT) { 508 if (cmd->c_flags & SCF_RSP_136) { 509 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0_REG); 510 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1_REG); 511 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2_REG); 512 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3_REG); 513 if (cmd->c_flags & SCF_RSP_CRC) { 514 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 515 (cmd->c_resp[1] << 24); 516 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 517 (cmd->c_resp[2] << 24); 518 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 519 (cmd->c_resp[3] << 24); 520 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 521 } 522 } else { 523 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0_REG); 524 } 525 } 526 527 done: 528 cmd->c_flags |= SCF_ITSDONE; 529 mutex_exit(&sc->sc_intr_lock); 530 531 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 532 ctrl |= DWC_MMC_CTRL_FIFO_RESET; 533 MMC_WRITE(sc, DWC_MMC_CTRL_REG, ctrl); 534 } 535 536 static void 537 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 538 { 539 } 540 541 static void 542 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 543 { 544 } 545 546 void 547 dwc_mmc_dump_regs(void) 548 { 549 static const struct { 550 const char *name; 551 unsigned int reg; 552 } regs[] = { 553 { "CTRL", DWC_MMC_CTRL_REG }, 554 { "PWREN", DWC_MMC_PWREN_REG }, 555 { "CLKDIV", DWC_MMC_CLKDIV_REG }, 556 { "CLKENA", DWC_MMC_CLKENA_REG }, 557 { "TMOUT", DWC_MMC_TMOUT_REG }, 558 { "CTYPE", DWC_MMC_CTYPE_REG }, 559 { "BLKSIZ", DWC_MMC_BLKSIZ_REG }, 560 { "BYTCNT", DWC_MMC_BYTCNT_REG }, 561 { "INTMASK", DWC_MMC_INTMASK_REG }, 562 { "MINTSTS", DWC_MMC_MINTSTS_REG }, 563 { "RINTSTS", DWC_MMC_RINTSTS_REG }, 564 { "STATUS", DWC_MMC_STATUS_REG }, 565 { "CDETECT", DWC_MMC_CDETECT_REG }, 566 { "WRTPRT", DWC_MMC_WRTPRT_REG }, 567 { "USRID", DWC_MMC_USRID_REG }, 568 { "VERID", DWC_MMC_VERID_REG }, 569 { "RST", DWC_MMC_RST_REG }, 570 { "BACK_END_POWER", DWC_MMC_BACK_END_POWER_REG }, 571 }; 572 device_t self = device_find_by_driver_unit("dwcmmc", 0); 573 if (self == NULL) 574 return; 575 struct dwc_mmc_softc *sc = device_private(self); 576 int i; 577 578 for (i = 0; i < __arraycount(regs); i++) { 579 device_printf(sc->sc_dev, "%s: %#x\n", regs[i].name, 580 MMC_READ(sc, regs[i].reg)); 581 } 582 } 583
Indexes created Sun Sep 21 16:09:51 GMT 2025