dwc_mmc.c revision 1.11
1 /* $NetBSD: dwc_mmc.c,v 1.11 2017/06/19 22:03:02 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.11 2017/06/19 22:03:02 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/sdmmc/sdmmcvar.h> 40 #include <dev/sdmmc/sdmmcchip.h> 41 #include <dev/sdmmc/sdmmc_ioreg.h> 42 43 #include <dev/ic/dwc_mmc_reg.h> 44 #include <dev/ic/dwc_mmc_var.h> 45 46 #define DWC_MMC_NDESC 64 47 48 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 49 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 50 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 51 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 52 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 53 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 54 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 55 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 56 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 57 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 58 struct sdmmc_command *); 59 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 60 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 61 62 static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 63 .host_reset = dwc_mmc_host_reset, 64 .host_ocr = dwc_mmc_host_ocr, 65 .host_maxblklen = dwc_mmc_host_maxblklen, 66 .card_detect = dwc_mmc_card_detect, 67 .write_protect = dwc_mmc_write_protect, 68 .bus_power = dwc_mmc_bus_power, 69 .bus_clock = dwc_mmc_bus_clock, 70 .bus_width = dwc_mmc_bus_width, 71 .bus_rod = dwc_mmc_bus_rod, 72 .exec_command = dwc_mmc_exec_command, 73 .card_enable_intr = dwc_mmc_card_enable_intr, 74 .card_intr_ack = dwc_mmc_card_intr_ack, 75 }; 76 77 #define MMC_WRITE(sc, reg, val) \ 78 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 79 #define MMC_READ(sc, reg) \ 80 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 81 82 static void 83 dwc_mmc_dump_regs(struct dwc_mmc_softc *sc) 84 { 85 device_printf(sc->sc_dev, "device registers:\n"); 86 for (u_int off = 0x00; off < 0x100; off += 16) { 87 device_printf(sc->sc_dev, "xxxxxx%02x: %08x %08x %08x %08x\n", 88 off, 89 MMC_READ(sc, off + 0), MMC_READ(sc, off + 4), 90 MMC_READ(sc, off + 8), MMC_READ(sc, off + 12)); 91 } 92 } 93 94 static int 95 dwc_mmc_idma_setup(struct dwc_mmc_softc *sc) 96 { 97 int error; 98 99 sc->sc_idma_xferlen = 0x1000; 100 101 sc->sc_idma_ndesc = DWC_MMC_NDESC; 102 sc->sc_idma_size = sizeof(struct dwc_mmc_idma_desc) * 103 sc->sc_idma_ndesc; 104 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 8, 105 sc->sc_idma_size, sc->sc_idma_segs, 1, 106 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 107 if (error) 108 return error; 109 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 110 sc->sc_idma_nsegs, sc->sc_idma_size, 111 &sc->sc_idma_desc, BUS_DMA_WAITOK); 112 if (error) 113 goto free; 114 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 115 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 116 if (error) 117 goto unmap; 118 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 119 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 120 if (error) 121 goto destroy; 122 return 0; 123 124 destroy: 125 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 126 unmap: 127 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 128 free: 129 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 130 return error; 131 } 132 133 static void 134 dwc_mmc_attach_i(device_t self) 135 { 136 struct dwc_mmc_softc *sc = device_private(self); 137 struct sdmmcbus_attach_args saa; 138 139 dwc_mmc_host_reset(sc); 140 dwc_mmc_bus_width(sc, 1); 141 142 memset(&saa, 0, sizeof(saa)); 143 saa.saa_busname = "sdmmc"; 144 saa.saa_sct = &dwc_mmc_chip_functions; 145 saa.saa_sch = sc; 146 saa.saa_clkmin = 400; 147 saa.saa_clkmax = sc->sc_clock_freq / 1000; 148 saa.saa_caps = SMC_CAPS_4BIT_MODE| 149 SMC_CAPS_8BIT_MODE| 150 SMC_CAPS_SD_HIGHSPEED| 151 SMC_CAPS_MMC_HIGHSPEED| 152 SMC_CAPS_AUTO_STOP; 153 if (ISSET(sc->sc_flags, DWC_MMC_F_DMA)) { 154 saa.saa_dmat = sc->sc_dmat; 155 saa.saa_caps |= SMC_CAPS_DMA | 156 SMC_CAPS_MULTI_SEG_DMA; 157 } 158 if (sc->sc_card_detect) 159 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 160 161 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 162 } 163 164 static int 165 dwc_mmc_wait_rint(struct dwc_mmc_softc *sc, uint32_t mask, int timeout) 166 { 167 const bool use_dma = ISSET(sc->sc_flags, DWC_MMC_F_DMA); 168 int retry, error; 169 170 KASSERT(mutex_owned(&sc->sc_intr_lock)); 171 172 if (sc->sc_intr_rint & mask) 173 return 0; 174 175 retry = timeout / hz; 176 177 while (retry > 0) { 178 if (use_dma) { 179 error = cv_timedwait(&sc->sc_intr_cv, 180 &sc->sc_intr_lock, hz); 181 if (error && error != EWOULDBLOCK) 182 return error; 183 if (sc->sc_intr_rint & mask) 184 return 0; 185 } else { 186 sc->sc_intr_rint |= MMC_READ(sc, DWC_MMC_RINT); 187 if (sc->sc_intr_rint & mask) 188 return 0; 189 delay(1000); 190 } 191 --retry; 192 } 193 194 return ETIMEDOUT; 195 } 196 197 static void 198 dwc_mmc_led(struct dwc_mmc_softc *sc, int on) 199 { 200 if (sc->sc_set_led) 201 sc->sc_set_led(sc, on); 202 } 203 204 static int 205 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 206 { 207 struct dwc_mmc_softc *sc = sch; 208 uint32_t fifoth, ctrl; 209 int retry = 1000; 210 211 #ifdef DWC_MMC_DEBUG 212 aprint_normal_dev(sc->sc_dev, "host reset\n"); 213 #endif 214 215 MMC_WRITE(sc, DWC_MMC_PWREN, 1); 216 217 MMC_WRITE(sc, DWC_MMC_GCTRL, 218 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_RESET); 219 while (--retry > 0) { 220 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET)) 221 break; 222 delay(100); 223 } 224 225 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 226 227 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff); 228 229 MMC_WRITE(sc, DWC_MMC_IMASK, 230 DWC_MMC_INT_CMD_DONE | DWC_MMC_INT_ERROR | 231 DWC_MMC_INT_DATA_OVER | DWC_MMC_INT_AUTO_CMD_DONE); 232 233 const uint32_t rx_wmark = (sc->sc_fifo_depth / 2) - 1; 234 const uint32_t tx_wmark = sc->sc_fifo_depth / 2; 235 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 236 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 237 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 238 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 239 MMC_WRITE(sc, DWC_MMC_FIFOTH, fifoth); 240 241 MMC_WRITE(sc, DWC_MMC_UHS, 0); 242 243 ctrl = MMC_READ(sc, DWC_MMC_GCTRL); 244 ctrl |= DWC_MMC_GCTRL_INTEN; 245 ctrl |= DWC_MMC_GCTRL_DMAEN; 246 ctrl |= DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD; 247 ctrl |= DWC_MMC_GCTRL_USE_INTERNAL_DMAC; 248 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl); 249 250 return 0; 251 } 252 253 static uint32_t 254 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 255 { 256 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 257 } 258 259 static int 260 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 261 { 262 return 32768; 263 } 264 265 static int 266 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 267 { 268 struct dwc_mmc_softc *sc = sch; 269 int v = 0, i; 270 271 if (!sc->sc_card_detect) 272 return 1; /* no card detect pin, assume present */ 273 274 for (i = 0; i < 5; i++) { 275 v += sc->sc_card_detect(sc); 276 delay(1000); 277 } 278 if (v == 5) 279 sc->sc_mmc_present = 0; 280 else if (v == 0) 281 sc->sc_mmc_present = 1; 282 return sc->sc_mmc_present; 283 } 284 285 static int 286 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 287 { 288 struct dwc_mmc_softc *sc = sch; 289 290 if (!sc->sc_write_protect) 291 return 0; /* no write protect pin, assume rw */ 292 293 return sc->sc_write_protect(sc); 294 } 295 296 static int 297 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 298 { 299 return 0; 300 } 301 302 static int 303 dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 304 { 305 uint32_t cmd; 306 int retry; 307 308 #ifdef DWC_MMC_DEBUG 309 aprint_normal_dev(sc->sc_dev, "update clock\n"); 310 #endif 311 312 cmd = DWC_MMC_CMD_START | 313 DWC_MMC_CMD_UPCLK_ONLY | 314 DWC_MMC_CMD_WAIT_PRE_OVER; 315 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 316 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 317 MMC_WRITE(sc, DWC_MMC_ARG, 0); 318 MMC_WRITE(sc, DWC_MMC_CMD, cmd); 319 retry = 0xfffff; 320 while (--retry > 0) { 321 if (!(MMC_READ(sc, DWC_MMC_CMD) & DWC_MMC_CMD_START)) 322 break; 323 delay(10); 324 } 325 326 if (retry == 0) { 327 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 328 #ifdef DWC_MMC_DEBUG 329 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 330 MMC_READ(sc, DWC_MMC_GCTRL)); 331 device_printf(sc->sc_dev, "CLKENA: 0x%08x\n", 332 MMC_READ(sc, DWC_MMC_CLKENA)); 333 device_printf(sc->sc_dev, "CLKDIV: 0x%08x\n", 334 MMC_READ(sc, DWC_MMC_CLKDIV)); 335 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 336 MMC_READ(sc, DWC_MMC_TIMEOUT)); 337 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 338 MMC_READ(sc, DWC_MMC_WIDTH)); 339 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 340 MMC_READ(sc, DWC_MMC_CMD)); 341 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 342 MMC_READ(sc, DWC_MMC_MINT)); 343 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 344 MMC_READ(sc, DWC_MMC_RINT)); 345 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 346 MMC_READ(sc, DWC_MMC_STATUS)); 347 #endif 348 return ETIMEDOUT; 349 } 350 351 return 0; 352 } 353 354 static int 355 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 356 { 357 const u_int pll_freq = sc->sc_clock_freq / 1000; 358 const u_int clk_div = howmany(pll_freq, freq * 2); 359 360 MMC_WRITE(sc, DWC_MMC_CLKDIV, clk_div); 361 362 return dwc_mmc_update_clock(sc); 363 } 364 365 static int 366 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 367 { 368 struct dwc_mmc_softc *sc = sch; 369 uint32_t clkena; 370 371 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 372 MMC_WRITE(sc, DWC_MMC_CLKENA, 0); 373 if (dwc_mmc_update_clock(sc) != 0) 374 return 1; 375 376 if (freq) { 377 if (dwc_mmc_set_clock(sc, freq) != 0) 378 return 1; 379 380 clkena = DWC_MMC_CLKENA_CARDCLKON; 381 MMC_WRITE(sc, DWC_MMC_CLKENA, clkena); 382 if (dwc_mmc_update_clock(sc) != 0) 383 return 1; 384 } 385 386 delay(1000); 387 388 return 0; 389 } 390 391 static int 392 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 393 { 394 struct dwc_mmc_softc *sc = sch; 395 396 #ifdef DWC_MMC_DEBUG 397 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 398 #endif 399 400 switch (width) { 401 case 1: 402 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_1); 403 break; 404 case 4: 405 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_4); 406 break; 407 case 8: 408 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_8); 409 break; 410 default: 411 return 1; 412 } 413 414 sc->sc_mmc_width = width; 415 416 return 0; 417 } 418 419 static int 420 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 421 { 422 return -1; 423 } 424 425 426 static int 427 dwc_mmc_pio_wait(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 428 { 429 int retry = 0xfffff; 430 uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ? 431 DWC_MMC_STATUS_FIFO_EMPTY : DWC_MMC_STATUS_FIFO_FULL; 432 433 while (--retry > 0) { 434 uint32_t status = MMC_READ(sc, DWC_MMC_STATUS); 435 if (!(status & bit)) 436 return 0; 437 delay(10); 438 } 439 440 return ETIMEDOUT; 441 } 442 443 static int 444 dwc_mmc_pio_transfer(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 445 { 446 uint32_t *datap = (uint32_t *)cmd->c_data; 447 int i; 448 449 for (i = 0; i < (cmd->c_resid >> 2); i++) { 450 if (dwc_mmc_pio_wait(sc, cmd)) 451 return ETIMEDOUT; 452 if (cmd->c_flags & SCF_CMD_READ) { 453 datap[i] = MMC_READ(sc, sc->sc_fifo_reg); 454 } else { 455 MMC_WRITE(sc, sc->sc_fifo_reg, datap[i]); 456 } 457 } 458 459 return 0; 460 } 461 462 static int 463 dwc_mmc_dma_prepare(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 464 { 465 struct dwc_mmc_idma_desc *dma = sc->sc_idma_desc; 466 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 467 bus_size_t off; 468 int desc, resid, seg; 469 uint32_t val; 470 471 desc = 0; 472 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 473 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 474 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 475 resid = min(len, cmd->c_resid); 476 off = 0; 477 while (resid > 0) { 478 if (desc == sc->sc_idma_ndesc) 479 break; 480 len = min(sc->sc_idma_xferlen, resid); 481 dma[desc].dma_buf_size = htole32(len); 482 dma[desc].dma_buf_addr = htole32(paddr + off); 483 dma[desc].dma_config = htole32( 484 DWC_MMC_IDMA_CONFIG_OWN); 485 cmd->c_resid -= len; 486 resid -= len; 487 off += len; 488 dma[desc].dma_next = htole32( 489 desc_paddr + ((desc+1) * 490 sizeof(struct dwc_mmc_idma_desc))); 491 if (desc == 0) { 492 dma[desc].dma_config |= htole32( 493 DWC_MMC_IDMA_CONFIG_FD); 494 } 495 if (cmd->c_resid == 0) { 496 dma[desc].dma_config |= htole32( 497 DWC_MMC_IDMA_CONFIG_LD); 498 } else { 499 dma[desc].dma_config |= 500 htole32(DWC_MMC_IDMA_CONFIG_CH| 501 DWC_MMC_IDMA_CONFIG_DIC); 502 } 503 ++desc; 504 } 505 } 506 if (desc == sc->sc_idma_ndesc) { 507 aprint_error_dev(sc->sc_dev, 508 "not enough descriptors for %d byte transfer!\n", 509 cmd->c_datalen); 510 return EIO; 511 } 512 513 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 514 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 515 516 sc->sc_idma_idst = 0; 517 518 val = MMC_READ(sc, DWC_MMC_GCTRL); 519 val |= DWC_MMC_GCTRL_DMAEN; 520 val |= DWC_MMC_GCTRL_INTEN; 521 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 522 val |= DWC_MMC_GCTRL_DMARESET; 523 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 524 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET); 525 MMC_WRITE(sc, DWC_MMC_DMAC, 526 DWC_MMC_DMAC_IDMA_ON|DWC_MMC_DMAC_FIX_BURST); 527 val = MMC_READ(sc, DWC_MMC_IDIE); 528 val &= ~(DWC_MMC_IDST_RECEIVE_INT|DWC_MMC_IDST_TRANSMIT_INT); 529 if (cmd->c_flags & SCF_CMD_READ) 530 val |= DWC_MMC_IDST_RECEIVE_INT; 531 else 532 val |= DWC_MMC_IDST_TRANSMIT_INT; 533 MMC_WRITE(sc, DWC_MMC_IDIE, val); 534 MMC_WRITE(sc, DWC_MMC_DLBA, desc_paddr); 535 536 return 0; 537 } 538 539 static void 540 dwc_mmc_dma_complete(struct dwc_mmc_softc *sc) 541 { 542 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 543 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 544 } 545 546 static void 547 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 548 { 549 struct dwc_mmc_softc *sc = sch; 550 uint32_t cmdval = DWC_MMC_CMD_START; 551 int retry = 0xfffff; 552 553 #ifdef DWC_MMC_DEBUG 554 aprint_normal_dev(sc->sc_dev, 555 "opcode %d flags 0x%x data %p datalen %d blklen %d\n", 556 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 557 cmd->c_blklen); 558 #endif 559 560 mutex_enter(&sc->sc_intr_lock); 561 562 do { 563 const uint32_t status = MMC_READ(sc, DWC_MMC_STATUS); 564 if ((status & DWC_MMC_STATUS_CARD_DATA_BUSY) == 0) 565 break; 566 delay(10); 567 } while (--retry > 0); 568 if (retry == 0) { 569 aprint_error_dev(sc->sc_dev, "timeout waiting for data busy\n"); 570 cmd->c_error = ETIMEDOUT; 571 goto done; 572 } 573 574 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff); 575 MMC_WRITE(sc, DWC_MMC_RINT, 0xffffffff); 576 577 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 578 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 579 580 if (cmd->c_opcode == 0) 581 cmdval |= DWC_MMC_CMD_SEND_INIT_SEQ; 582 if (cmd->c_flags & SCF_RSP_PRESENT) 583 cmdval |= DWC_MMC_CMD_RSP_EXP; 584 if (cmd->c_flags & SCF_RSP_136) 585 cmdval |= DWC_MMC_CMD_LONG_RSP; 586 if (cmd->c_flags & SCF_RSP_CRC) 587 cmdval |= DWC_MMC_CMD_CHECK_RSP_CRC; 588 589 if (cmd->c_datalen > 0) { 590 unsigned int nblks; 591 592 cmdval |= DWC_MMC_CMD_DATA_EXP | DWC_MMC_CMD_WAIT_PRE_OVER; 593 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 594 cmdval |= DWC_MMC_CMD_WRITE; 595 } 596 597 nblks = cmd->c_datalen / cmd->c_blklen; 598 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 599 ++nblks; 600 601 if (nblks > 1) { 602 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 603 } 604 605 MMC_WRITE(sc, DWC_MMC_BLKSZ, cmd->c_blklen); 606 MMC_WRITE(sc, DWC_MMC_BYTECNT, nblks * cmd->c_blklen); 607 } 608 609 sc->sc_intr_rint = 0; 610 611 MMC_WRITE(sc, DWC_MMC_ARG, cmd->c_arg); 612 613 #ifdef DWC_MMC_DEBUG 614 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 615 #endif 616 617 if (cmd->c_datalen > 0) { 618 cmd->c_resid = cmd->c_datalen; 619 dwc_mmc_led(sc, 0); 620 if (ISSET(sc->sc_flags, DWC_MMC_F_DMA)) { 621 cmd->c_error = dwc_mmc_dma_prepare(sc, cmd); 622 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 623 MMC_WRITE(sc, DWC_MMC_PLDMND, 1); 624 if (cmd->c_error == 0) { 625 const uint32_t idst_mask = 626 DWC_MMC_IDST_ERROR | DWC_MMC_IDST_COMPLETE; 627 retry = 10; 628 while ((sc->sc_idma_idst & idst_mask) == 0) { 629 if (retry == 0) { 630 cmd->c_error = ETIMEDOUT; 631 break; 632 } 633 cv_timedwait(&sc->sc_idst_cv, 634 &sc->sc_intr_lock, hz); 635 } 636 } 637 dwc_mmc_dma_complete(sc); 638 if (sc->sc_idma_idst & DWC_MMC_IDST_ERROR) { 639 cmd->c_error = EIO; 640 } else if (!(sc->sc_idma_idst & DWC_MMC_IDST_COMPLETE)) { 641 cmd->c_error = ETIMEDOUT; 642 } 643 } else { 644 mutex_exit(&sc->sc_intr_lock); 645 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 646 cmd->c_error = dwc_mmc_pio_transfer(sc, cmd); 647 mutex_enter(&sc->sc_intr_lock); 648 } 649 dwc_mmc_led(sc, 1); 650 if (cmd->c_error) { 651 #ifdef DWC_MMC_DEBUG 652 aprint_error_dev(sc->sc_dev, 653 "xfer failed, error %d\n", cmd->c_error); 654 #endif 655 goto done; 656 } 657 } else { 658 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 659 } 660 661 cmd->c_error = dwc_mmc_wait_rint(sc, 662 DWC_MMC_INT_ERROR|DWC_MMC_INT_CMD_DONE, hz * 10); 663 if (cmd->c_error == 0 && (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 664 if (sc->sc_intr_rint & DWC_MMC_INT_RESP_TIMEOUT) { 665 cmd->c_error = ETIMEDOUT; 666 } else { 667 cmd->c_error = EIO; 668 } 669 } 670 if (cmd->c_error) { 671 #ifdef DWC_MMC_DEBUG 672 aprint_error_dev(sc->sc_dev, 673 "cmd failed, error %d\n", cmd->c_error); 674 #endif 675 goto done; 676 } 677 678 if (cmd->c_datalen > 0) { 679 cmd->c_error = dwc_mmc_wait_rint(sc, 680 DWC_MMC_INT_ERROR| 681 DWC_MMC_INT_AUTO_CMD_DONE| 682 DWC_MMC_INT_DATA_OVER, 683 hz*10); 684 if (cmd->c_error == 0 && 685 (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 686 cmd->c_error = ETIMEDOUT; 687 } 688 if (cmd->c_error) { 689 #ifdef DWC_MMC_DEBUG 690 aprint_error_dev(sc->sc_dev, 691 "data timeout, rint = %08x\n", 692 sc->sc_intr_rint); 693 #endif 694 dwc_mmc_dump_regs(sc); 695 cmd->c_error = ETIMEDOUT; 696 goto done; 697 } 698 } 699 700 if (cmd->c_flags & SCF_RSP_PRESENT) { 701 if (cmd->c_flags & SCF_RSP_136) { 702 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 703 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1); 704 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2); 705 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3); 706 if (cmd->c_flags & SCF_RSP_CRC) { 707 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 708 (cmd->c_resp[1] << 24); 709 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 710 (cmd->c_resp[2] << 24); 711 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 712 (cmd->c_resp[3] << 24); 713 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 714 } 715 } else { 716 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 717 } 718 } 719 720 done: 721 cmd->c_flags |= SCF_ITSDONE; 722 mutex_exit(&sc->sc_intr_lock); 723 724 if (cmd->c_error) { 725 #ifdef DWC_MMC_DEBUG 726 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 727 #endif 728 MMC_WRITE(sc, DWC_MMC_GCTRL, 729 MMC_READ(sc, DWC_MMC_GCTRL) | 730 DWC_MMC_GCTRL_DMARESET | DWC_MMC_GCTRL_FIFORESET); 731 for (retry = 0; retry < 1000; retry++) { 732 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET)) 733 break; 734 delay(10); 735 } 736 dwc_mmc_update_clock(sc); 737 } 738 739 if (!ISSET(sc->sc_flags, DWC_MMC_F_DMA)) { 740 MMC_WRITE(sc, DWC_MMC_GCTRL, 741 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_FIFORESET); 742 } 743 } 744 745 static void 746 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 747 { 748 } 749 750 static void 751 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 752 { 753 } 754 755 int 756 dwc_mmc_init(struct dwc_mmc_softc *sc) 757 { 758 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 759 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 760 cv_init(&sc->sc_idst_cv, "dwcmmcdma"); 761 762 const bool use_dma = ISSET(sc->sc_flags, DWC_MMC_F_DMA); 763 764 aprint_debug_dev(sc->sc_dev, "using %s for transfers\n", 765 use_dma ? "DMA" : "PIO"); 766 767 if (use_dma && dwc_mmc_idma_setup(sc) != 0) { 768 aprint_error_dev(sc->sc_dev, "failed to setup DMA\n"); 769 return ENOMEM; 770 } 771 772 config_interrupts(sc->sc_dev, dwc_mmc_attach_i); 773 774 return 0; 775 } 776 777 int 778 dwc_mmc_intr(void *priv) 779 { 780 struct dwc_mmc_softc *sc = priv; 781 uint32_t idst, rint, mint; 782 783 mutex_enter(&sc->sc_intr_lock); 784 idst = MMC_READ(sc, DWC_MMC_IDST); 785 rint = MMC_READ(sc, DWC_MMC_RINT); 786 mint = MMC_READ(sc, DWC_MMC_MINT); 787 if (!idst && !rint && !mint) { 788 mutex_exit(&sc->sc_intr_lock); 789 return 0; 790 } 791 MMC_WRITE(sc, DWC_MMC_IDST, idst); 792 MMC_WRITE(sc, DWC_MMC_RINT, rint); 793 MMC_WRITE(sc, DWC_MMC_MINT, mint); 794 795 #ifdef DWC_MMC_DEBUG 796 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 797 idst, rint, mint); 798 #endif 799 800 if (idst) { 801 sc->sc_idma_idst |= idst; 802 cv_broadcast(&sc->sc_idst_cv); 803 } 804 805 if (rint) { 806 sc->sc_intr_rint |= rint; 807 cv_broadcast(&sc->sc_intr_cv); 808 } 809 810 mutex_exit(&sc->sc_intr_lock); 811 812 return 1; 813 } 814
Indexes created Mon Sep 22 10:09:38 GMT 2025