dwc_mmc.c revision 1.14
1 /* $NetBSD: dwc_mmc.c,v 1.14 2018/07/02 12:47:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.14 2018/07/02 12:47:19 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/sdmmc/sdmmcvar.h> 40 #include <dev/sdmmc/sdmmcchip.h> 41 #include <dev/sdmmc/sdmmc_ioreg.h> 42 43 #include <dev/ic/dwc_mmc_reg.h> 44 #include <dev/ic/dwc_mmc_var.h> 45 46 #define DWC_MMC_NDESC 64 47 48 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 49 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 50 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 51 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 52 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 53 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 54 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 55 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 56 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 57 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 58 struct sdmmc_command *); 59 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 60 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 61 62 static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 63 .host_reset = dwc_mmc_host_reset, 64 .host_ocr = dwc_mmc_host_ocr, 65 .host_maxblklen = dwc_mmc_host_maxblklen, 66 .card_detect = dwc_mmc_card_detect, 67 .write_protect = dwc_mmc_write_protect, 68 .bus_power = dwc_mmc_bus_power, 69 .bus_clock = dwc_mmc_bus_clock, 70 .bus_width = dwc_mmc_bus_width, 71 .bus_rod = dwc_mmc_bus_rod, 72 .exec_command = dwc_mmc_exec_command, 73 .card_enable_intr = dwc_mmc_card_enable_intr, 74 .card_intr_ack = dwc_mmc_card_intr_ack, 75 }; 76 77 #define MMC_WRITE(sc, reg, val) \ 78 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 79 #define MMC_READ(sc, reg) \ 80 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 81 82 static void 83 dwc_mmc_dump_regs(struct dwc_mmc_softc *sc) 84 { 85 device_printf(sc->sc_dev, "device registers:\n"); 86 for (u_int off = 0x00; off < 0x100; off += 16) { 87 device_printf(sc->sc_dev, "xxxxxx%02x: %08x %08x %08x %08x\n", 88 off, 89 MMC_READ(sc, off + 0), MMC_READ(sc, off + 4), 90 MMC_READ(sc, off + 8), MMC_READ(sc, off + 12)); 91 } 92 } 93 94 static int 95 dwc_mmc_idma_setup(struct dwc_mmc_softc *sc) 96 { 97 int error; 98 99 sc->sc_idma_xferlen = 0x1000; 100 101 sc->sc_idma_ndesc = DWC_MMC_NDESC; 102 sc->sc_idma_size = sizeof(struct dwc_mmc_idma_desc) * 103 sc->sc_idma_ndesc; 104 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 8, 105 sc->sc_idma_size, sc->sc_idma_segs, 1, 106 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 107 if (error) 108 return error; 109 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 110 sc->sc_idma_nsegs, sc->sc_idma_size, 111 &sc->sc_idma_desc, BUS_DMA_WAITOK); 112 if (error) 113 goto free; 114 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 115 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 116 if (error) 117 goto unmap; 118 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 119 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 120 if (error) 121 goto destroy; 122 return 0; 123 124 destroy: 125 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 126 unmap: 127 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 128 free: 129 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 130 return error; 131 } 132 133 static void 134 dwc_mmc_attach_i(device_t self) 135 { 136 struct dwc_mmc_softc *sc = device_private(self); 137 struct sdmmcbus_attach_args saa; 138 139 dwc_mmc_host_reset(sc); 140 dwc_mmc_bus_width(sc, 1); 141 142 memset(&saa, 0, sizeof(saa)); 143 saa.saa_busname = "sdmmc"; 144 saa.saa_sct = &dwc_mmc_chip_functions; 145 saa.saa_sch = sc; 146 saa.saa_clkmin = 400; 147 saa.saa_clkmax = sc->sc_clock_freq / 1000; 148 saa.saa_caps = SMC_CAPS_4BIT_MODE| 149 SMC_CAPS_8BIT_MODE| 150 SMC_CAPS_SD_HIGHSPEED| 151 SMC_CAPS_MMC_HIGHSPEED| 152 SMC_CAPS_AUTO_STOP; 153 if (ISSET(sc->sc_flags, DWC_MMC_F_DMA)) { 154 saa.saa_dmat = sc->sc_dmat; 155 saa.saa_caps |= SMC_CAPS_DMA | 156 SMC_CAPS_MULTI_SEG_DMA; 157 } 158 if (sc->sc_card_detect) 159 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 160 161 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 162 } 163 164 static int 165 dwc_mmc_wait_rint(struct dwc_mmc_softc *sc, uint32_t mask, int timeout) 166 { 167 const bool use_dma = ISSET(sc->sc_flags, DWC_MMC_F_DMA); 168 int retry, error; 169 170 KASSERT(mutex_owned(&sc->sc_intr_lock)); 171 172 if (sc->sc_intr_rint & mask) 173 return 0; 174 175 retry = timeout / hz; 176 177 while (retry > 0) { 178 if (use_dma) { 179 error = cv_timedwait(&sc->sc_intr_cv, 180 &sc->sc_intr_lock, hz); 181 if (error && error != EWOULDBLOCK) 182 return error; 183 if (sc->sc_intr_rint & mask) 184 return 0; 185 } else { 186 sc->sc_intr_rint |= MMC_READ(sc, DWC_MMC_RINT); 187 if (sc->sc_intr_rint & mask) 188 return 0; 189 delay(1000); 190 } 191 --retry; 192 } 193 194 return ETIMEDOUT; 195 } 196 197 static void 198 dwc_mmc_led(struct dwc_mmc_softc *sc, int on) 199 { 200 if (sc->sc_set_led) 201 sc->sc_set_led(sc, on); 202 } 203 204 static int 205 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 206 { 207 struct dwc_mmc_softc *sc = sch; 208 uint32_t fifoth, ctrl; 209 int retry = 1000; 210 211 #ifdef DWC_MMC_DEBUG 212 aprint_normal_dev(sc->sc_dev, "host reset\n"); 213 #endif 214 215 MMC_WRITE(sc, DWC_MMC_PWREN, 1); 216 217 MMC_WRITE(sc, DWC_MMC_GCTRL, 218 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_RESET); 219 while (--retry > 0) { 220 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET)) 221 break; 222 delay(100); 223 } 224 225 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 226 227 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff); 228 229 MMC_WRITE(sc, DWC_MMC_IMASK, 230 DWC_MMC_INT_CMD_DONE | DWC_MMC_INT_ERROR | 231 DWC_MMC_INT_DATA_OVER | DWC_MMC_INT_AUTO_CMD_DONE); 232 233 const uint32_t rx_wmark = (sc->sc_fifo_depth / 2) - 1; 234 const uint32_t tx_wmark = sc->sc_fifo_depth / 2; 235 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 236 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 237 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 238 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 239 MMC_WRITE(sc, DWC_MMC_FIFOTH, fifoth); 240 241 MMC_WRITE(sc, DWC_MMC_UHS, 0); 242 243 ctrl = MMC_READ(sc, DWC_MMC_GCTRL); 244 ctrl |= DWC_MMC_GCTRL_INTEN; 245 ctrl |= DWC_MMC_GCTRL_DMAEN; 246 ctrl |= DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD; 247 ctrl |= DWC_MMC_GCTRL_USE_INTERNAL_DMAC; 248 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl); 249 250 return 0; 251 } 252 253 static uint32_t 254 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 255 { 256 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 257 } 258 259 static int 260 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 261 { 262 return 32768; 263 } 264 265 static int 266 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 267 { 268 struct dwc_mmc_softc *sc = sch; 269 int v = 0, i; 270 271 if (!sc->sc_card_detect) 272 return 1; /* no card detect pin, assume present */ 273 274 for (i = 0; i < 5; i++) { 275 v += sc->sc_card_detect(sc); 276 delay(1000); 277 } 278 if (v == 5) 279 sc->sc_mmc_present = 0; 280 else if (v == 0) 281 sc->sc_mmc_present = 1; 282 return sc->sc_mmc_present; 283 } 284 285 static int 286 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 287 { 288 struct dwc_mmc_softc *sc = sch; 289 290 if (!sc->sc_write_protect) 291 return 0; /* no write protect pin, assume rw */ 292 293 return sc->sc_write_protect(sc); 294 } 295 296 static int 297 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 298 { 299 return 0; 300 } 301 302 static int 303 dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 304 { 305 uint32_t cmd; 306 int retry; 307 308 #ifdef DWC_MMC_DEBUG 309 aprint_normal_dev(sc->sc_dev, "update clock\n"); 310 #endif 311 312 cmd = DWC_MMC_CMD_START | 313 DWC_MMC_CMD_UPCLK_ONLY | 314 DWC_MMC_CMD_WAIT_PRE_OVER; 315 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 316 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 317 MMC_WRITE(sc, DWC_MMC_ARG, 0); 318 MMC_WRITE(sc, DWC_MMC_CMD, cmd); 319 retry = 200000; 320 while (--retry > 0) { 321 if (!(MMC_READ(sc, DWC_MMC_CMD) & DWC_MMC_CMD_START)) 322 break; 323 delay(10); 324 } 325 326 if (retry == 0) { 327 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 328 #ifdef DWC_MMC_DEBUG 329 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 330 MMC_READ(sc, DWC_MMC_GCTRL)); 331 device_printf(sc->sc_dev, "CLKENA: 0x%08x\n", 332 MMC_READ(sc, DWC_MMC_CLKENA)); 333 device_printf(sc->sc_dev, "CLKDIV: 0x%08x\n", 334 MMC_READ(sc, DWC_MMC_CLKDIV)); 335 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 336 MMC_READ(sc, DWC_MMC_TIMEOUT)); 337 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 338 MMC_READ(sc, DWC_MMC_WIDTH)); 339 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 340 MMC_READ(sc, DWC_MMC_CMD)); 341 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 342 MMC_READ(sc, DWC_MMC_MINT)); 343 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 344 MMC_READ(sc, DWC_MMC_RINT)); 345 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 346 MMC_READ(sc, DWC_MMC_STATUS)); 347 #endif 348 return ETIMEDOUT; 349 } 350 351 return 0; 352 } 353 354 static int 355 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 356 { 357 const u_int pll_freq = sc->sc_clock_freq / 1000; 358 u_int clk_div; 359 360 if (freq != pll_freq) 361 clk_div = howmany(pll_freq, freq); 362 else 363 clk_div = 0; 364 365 MMC_WRITE(sc, DWC_MMC_CLKDIV, clk_div); 366 367 return dwc_mmc_update_clock(sc); 368 } 369 370 static int 371 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 372 { 373 struct dwc_mmc_softc *sc = sch; 374 uint32_t clkena; 375 376 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 377 MMC_WRITE(sc, DWC_MMC_CLKENA, 0); 378 if (dwc_mmc_update_clock(sc) != 0) 379 return 1; 380 381 if (freq) { 382 if (sc->sc_bus_clock && sc->sc_bus_clock(sc, freq) != 0) 383 return 1; 384 385 if (dwc_mmc_set_clock(sc, freq) != 0) 386 return 1; 387 388 clkena = DWC_MMC_CLKENA_CARDCLKON; 389 MMC_WRITE(sc, DWC_MMC_CLKENA, clkena); 390 if (dwc_mmc_update_clock(sc) != 0) 391 return 1; 392 } 393 394 delay(1000); 395 396 return 0; 397 } 398 399 static int 400 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 401 { 402 struct dwc_mmc_softc *sc = sch; 403 404 #ifdef DWC_MMC_DEBUG 405 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 406 #endif 407 408 switch (width) { 409 case 1: 410 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_1); 411 break; 412 case 4: 413 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_4); 414 break; 415 case 8: 416 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_8); 417 break; 418 default: 419 return 1; 420 } 421 422 sc->sc_mmc_width = width; 423 424 return 0; 425 } 426 427 static int 428 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 429 { 430 return -1; 431 } 432 433 434 static int 435 dwc_mmc_pio_wait(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 436 { 437 int retry = 0xfffff; 438 uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ? 439 DWC_MMC_STATUS_FIFO_EMPTY : DWC_MMC_STATUS_FIFO_FULL; 440 441 while (--retry > 0) { 442 uint32_t status = MMC_READ(sc, DWC_MMC_STATUS); 443 if (!(status & bit)) 444 return 0; 445 delay(10); 446 } 447 448 return ETIMEDOUT; 449 } 450 451 static int 452 dwc_mmc_pio_transfer(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 453 { 454 uint32_t *datap = (uint32_t *)cmd->c_data; 455 int i; 456 457 for (i = 0; i < (cmd->c_resid >> 2); i++) { 458 if (dwc_mmc_pio_wait(sc, cmd)) 459 return ETIMEDOUT; 460 if (cmd->c_flags & SCF_CMD_READ) { 461 datap[i] = MMC_READ(sc, sc->sc_fifo_reg); 462 } else { 463 MMC_WRITE(sc, sc->sc_fifo_reg, datap[i]); 464 } 465 } 466 467 return 0; 468 } 469 470 static int 471 dwc_mmc_dma_prepare(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 472 { 473 struct dwc_mmc_idma_desc *dma = sc->sc_idma_desc; 474 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 475 bus_size_t off; 476 int desc, resid, seg; 477 uint32_t val; 478 479 desc = 0; 480 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 481 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 482 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 483 resid = min(len, cmd->c_resid); 484 off = 0; 485 while (resid > 0) { 486 if (desc == sc->sc_idma_ndesc) 487 break; 488 len = min(sc->sc_idma_xferlen, resid); 489 dma[desc].dma_buf_size = htole32(len); 490 dma[desc].dma_buf_addr = htole32(paddr + off); 491 dma[desc].dma_config = htole32( 492 DWC_MMC_IDMA_CONFIG_OWN); 493 cmd->c_resid -= len; 494 resid -= len; 495 off += len; 496 dma[desc].dma_next = htole32( 497 desc_paddr + ((desc+1) * 498 sizeof(struct dwc_mmc_idma_desc))); 499 if (desc == 0) { 500 dma[desc].dma_config |= htole32( 501 DWC_MMC_IDMA_CONFIG_FD); 502 } 503 if (cmd->c_resid == 0) { 504 dma[desc].dma_config |= htole32( 505 DWC_MMC_IDMA_CONFIG_LD); 506 } else { 507 dma[desc].dma_config |= 508 htole32(DWC_MMC_IDMA_CONFIG_CH| 509 DWC_MMC_IDMA_CONFIG_DIC); 510 } 511 ++desc; 512 } 513 } 514 if (desc == sc->sc_idma_ndesc) { 515 aprint_error_dev(sc->sc_dev, 516 "not enough descriptors for %d byte transfer!\n", 517 cmd->c_datalen); 518 return EIO; 519 } 520 521 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 522 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 523 524 sc->sc_idma_idst = 0; 525 526 val = MMC_READ(sc, DWC_MMC_GCTRL); 527 val |= DWC_MMC_GCTRL_DMAEN; 528 val |= DWC_MMC_GCTRL_INTEN; 529 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 530 val |= DWC_MMC_GCTRL_DMARESET; 531 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 532 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET); 533 MMC_WRITE(sc, DWC_MMC_DMAC, 534 DWC_MMC_DMAC_IDMA_ON|DWC_MMC_DMAC_FIX_BURST); 535 val = MMC_READ(sc, DWC_MMC_IDIE); 536 val &= ~(DWC_MMC_IDST_RECEIVE_INT|DWC_MMC_IDST_TRANSMIT_INT); 537 if (cmd->c_flags & SCF_CMD_READ) 538 val |= DWC_MMC_IDST_RECEIVE_INT; 539 else 540 val |= DWC_MMC_IDST_TRANSMIT_INT; 541 MMC_WRITE(sc, DWC_MMC_IDIE, val); 542 MMC_WRITE(sc, DWC_MMC_DLBA, desc_paddr); 543 544 return 0; 545 } 546 547 static void 548 dwc_mmc_dma_complete(struct dwc_mmc_softc *sc) 549 { 550 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 551 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 552 } 553 554 static void 555 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 556 { 557 struct dwc_mmc_softc *sc = sch; 558 uint32_t cmdval = DWC_MMC_CMD_START; 559 int retry = 200000; 560 561 #ifdef DWC_MMC_DEBUG 562 aprint_normal_dev(sc->sc_dev, 563 "opcode %d flags 0x%x data %p datalen %d blklen %d\n", 564 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 565 cmd->c_blklen); 566 #endif 567 568 mutex_enter(&sc->sc_intr_lock); 569 570 do { 571 const uint32_t status = MMC_READ(sc, DWC_MMC_STATUS); 572 if ((status & DWC_MMC_STATUS_CARD_DATA_BUSY) == 0) 573 break; 574 delay(10); 575 } while (--retry > 0); 576 if (retry == 0) { 577 aprint_error_dev(sc->sc_dev, "timeout waiting for data busy\n"); 578 cmd->c_error = ETIMEDOUT; 579 goto done; 580 } 581 582 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff); 583 MMC_WRITE(sc, DWC_MMC_RINT, 0xffffffff); 584 585 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 586 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 587 588 if (cmd->c_opcode == 0) 589 cmdval |= DWC_MMC_CMD_SEND_INIT_SEQ; 590 if (cmd->c_flags & SCF_RSP_PRESENT) 591 cmdval |= DWC_MMC_CMD_RSP_EXP; 592 if (cmd->c_flags & SCF_RSP_136) 593 cmdval |= DWC_MMC_CMD_LONG_RSP; 594 if (cmd->c_flags & SCF_RSP_CRC) 595 cmdval |= DWC_MMC_CMD_CHECK_RSP_CRC; 596 597 if (cmd->c_datalen > 0) { 598 unsigned int nblks; 599 600 cmdval |= DWC_MMC_CMD_DATA_EXP | DWC_MMC_CMD_WAIT_PRE_OVER; 601 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 602 cmdval |= DWC_MMC_CMD_WRITE; 603 } 604 605 nblks = cmd->c_datalen / cmd->c_blklen; 606 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 607 ++nblks; 608 609 if (nblks > 1) { 610 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 611 } 612 613 MMC_WRITE(sc, DWC_MMC_BLKSZ, cmd->c_blklen); 614 MMC_WRITE(sc, DWC_MMC_BYTECNT, nblks * cmd->c_blklen); 615 } 616 617 sc->sc_intr_rint = 0; 618 619 MMC_WRITE(sc, DWC_MMC_ARG, cmd->c_arg); 620 621 #ifdef DWC_MMC_DEBUG 622 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 623 #endif 624 625 if (cmd->c_datalen > 0) { 626 cmd->c_resid = cmd->c_datalen; 627 dwc_mmc_led(sc, 0); 628 if (ISSET(sc->sc_flags, DWC_MMC_F_DMA)) { 629 cmd->c_error = dwc_mmc_dma_prepare(sc, cmd); 630 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 631 MMC_WRITE(sc, DWC_MMC_PLDMND, 1); 632 if (cmd->c_error == 0) { 633 const uint32_t idst_mask = 634 DWC_MMC_IDST_ERROR | DWC_MMC_IDST_COMPLETE; 635 retry = 10; 636 while ((sc->sc_idma_idst & idst_mask) == 0) { 637 if (retry == 0) { 638 cmd->c_error = ETIMEDOUT; 639 break; 640 } 641 cv_timedwait(&sc->sc_idst_cv, 642 &sc->sc_intr_lock, hz); 643 } 644 } 645 dwc_mmc_dma_complete(sc); 646 if (sc->sc_idma_idst & DWC_MMC_IDST_ERROR) { 647 cmd->c_error = EIO; 648 } else if (!(sc->sc_idma_idst & DWC_MMC_IDST_COMPLETE)) { 649 cmd->c_error = ETIMEDOUT; 650 } 651 } else { 652 mutex_exit(&sc->sc_intr_lock); 653 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 654 cmd->c_error = dwc_mmc_pio_transfer(sc, cmd); 655 mutex_enter(&sc->sc_intr_lock); 656 } 657 dwc_mmc_led(sc, 1); 658 if (cmd->c_error) { 659 #ifdef DWC_MMC_DEBUG 660 aprint_error_dev(sc->sc_dev, 661 "xfer failed, error %d\n", cmd->c_error); 662 #endif 663 goto done; 664 } 665 } else { 666 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 667 } 668 669 cmd->c_error = dwc_mmc_wait_rint(sc, 670 DWC_MMC_INT_ERROR|DWC_MMC_INT_CMD_DONE, hz * 10); 671 if (cmd->c_error == 0 && (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 672 if (sc->sc_intr_rint & DWC_MMC_INT_RESP_TIMEOUT) { 673 cmd->c_error = ETIMEDOUT; 674 } else { 675 cmd->c_error = EIO; 676 } 677 } 678 if (cmd->c_error) { 679 #ifdef DWC_MMC_DEBUG 680 aprint_error_dev(sc->sc_dev, 681 "cmd failed, error %d\n", cmd->c_error); 682 #endif 683 goto done; 684 } 685 686 if (cmd->c_datalen > 0) { 687 cmd->c_error = dwc_mmc_wait_rint(sc, 688 DWC_MMC_INT_ERROR| 689 DWC_MMC_INT_AUTO_CMD_DONE| 690 DWC_MMC_INT_DATA_OVER, 691 hz*10); 692 if (cmd->c_error == 0 && 693 (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 694 cmd->c_error = ETIMEDOUT; 695 } 696 if (cmd->c_error) { 697 #ifdef DWC_MMC_DEBUG 698 aprint_error_dev(sc->sc_dev, 699 "data timeout, rint = %08x\n", 700 sc->sc_intr_rint); 701 #endif 702 dwc_mmc_dump_regs(sc); 703 cmd->c_error = ETIMEDOUT; 704 goto done; 705 } 706 } 707 708 if (cmd->c_flags & SCF_RSP_PRESENT) { 709 if (cmd->c_flags & SCF_RSP_136) { 710 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 711 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1); 712 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2); 713 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3); 714 if (cmd->c_flags & SCF_RSP_CRC) { 715 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 716 (cmd->c_resp[1] << 24); 717 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 718 (cmd->c_resp[2] << 24); 719 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 720 (cmd->c_resp[3] << 24); 721 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 722 } 723 } else { 724 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 725 } 726 } 727 728 done: 729 cmd->c_flags |= SCF_ITSDONE; 730 mutex_exit(&sc->sc_intr_lock); 731 732 if (cmd->c_error) { 733 #ifdef DWC_MMC_DEBUG 734 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 735 #endif 736 MMC_WRITE(sc, DWC_MMC_GCTRL, 737 MMC_READ(sc, DWC_MMC_GCTRL) | 738 DWC_MMC_GCTRL_DMARESET | DWC_MMC_GCTRL_FIFORESET); 739 for (retry = 0; retry < 1000; retry++) { 740 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET)) 741 break; 742 delay(10); 743 } 744 dwc_mmc_update_clock(sc); 745 } 746 747 if (!ISSET(sc->sc_flags, DWC_MMC_F_DMA)) { 748 MMC_WRITE(sc, DWC_MMC_GCTRL, 749 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_FIFORESET); 750 } 751 } 752 753 static void 754 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 755 { 756 } 757 758 static void 759 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 760 { 761 } 762 763 int 764 dwc_mmc_init(struct dwc_mmc_softc *sc) 765 { 766 uint32_t val; 767 768 if (sc->sc_fifo_reg == 0) { 769 val = MMC_READ(sc, DWC_MMC_VERID); 770 const u_int id = __SHIFTOUT(val, DWC_MMC_VERID_ID); 771 772 if (id < DWC_MMC_VERID_240A) 773 sc->sc_fifo_reg = 0x100; 774 else 775 sc->sc_fifo_reg = 0x200; 776 } 777 778 if (sc->sc_fifo_depth == 0) { 779 val = MMC_READ(sc, DWC_MMC_FIFOTH); 780 sc->sc_fifo_depth = __SHIFTOUT(val, DWC_MMC_FIFOTH_RX_WMARK) + 1; 781 } 782 783 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 784 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 785 cv_init(&sc->sc_idst_cv, "dwcmmcdma"); 786 787 const bool use_dma = ISSET(sc->sc_flags, DWC_MMC_F_DMA); 788 789 aprint_debug_dev(sc->sc_dev, "using %s for transfers\n", 790 use_dma ? "DMA" : "PIO"); 791 792 if (use_dma && dwc_mmc_idma_setup(sc) != 0) { 793 aprint_error_dev(sc->sc_dev, "failed to setup DMA\n"); 794 return ENOMEM; 795 } 796 797 config_interrupts(sc->sc_dev, dwc_mmc_attach_i); 798 799 return 0; 800 } 801 802 int 803 dwc_mmc_intr(void *priv) 804 { 805 struct dwc_mmc_softc *sc = priv; 806 uint32_t idst, rint, mint; 807 808 mutex_enter(&sc->sc_intr_lock); 809 idst = MMC_READ(sc, DWC_MMC_IDST); 810 rint = MMC_READ(sc, DWC_MMC_RINT); 811 mint = MMC_READ(sc, DWC_MMC_MINT); 812 if (!idst && !rint && !mint) { 813 mutex_exit(&sc->sc_intr_lock); 814 return 0; 815 } 816 MMC_WRITE(sc, DWC_MMC_IDST, idst); 817 MMC_WRITE(sc, DWC_MMC_RINT, rint); 818 MMC_WRITE(sc, DWC_MMC_MINT, mint); 819 820 #ifdef DWC_MMC_DEBUG 821 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 822 idst, rint, mint); 823 #endif 824 825 if (idst) { 826 sc->sc_idma_idst |= idst; 827 cv_broadcast(&sc->sc_idst_cv); 828 } 829 830 if (rint) { 831 sc->sc_intr_rint |= rint; 832 cv_broadcast(&sc->sc_intr_cv); 833 } 834 835 mutex_exit(&sc->sc_intr_lock); 836 837 return 1; 838 } 839
Indexes created Sun Sep 21 16:09:51 GMT 2025