Home | History | Annotate | Line # | Download | only in ic
dwc_mmc.c revision 1.16
      1 /* $NetBSD: dwc_mmc.c,v 1.16 2019/04/30 23:19:55 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.16 2019/04/30 23:19:55 jmcneill Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/bus.h>
     34 #include <sys/device.h>
     35 #include <sys/intr.h>
     36 #include <sys/systm.h>
     37 #include <sys/kernel.h>
     38 
     39 #include <dev/sdmmc/sdmmcvar.h>
     40 #include <dev/sdmmc/sdmmcchip.h>
     41 #include <dev/sdmmc/sdmmc_ioreg.h>
     42 
     43 #include <dev/ic/dwc_mmc_reg.h>
     44 #include <dev/ic/dwc_mmc_var.h>
     45 
     46 #define DWC_MMC_NDESC		64
     47 
     48 static int	dwc_mmc_host_reset(sdmmc_chipset_handle_t);
     49 static uint32_t	dwc_mmc_host_ocr(sdmmc_chipset_handle_t);
     50 static int	dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t);
     51 static int	dwc_mmc_card_detect(sdmmc_chipset_handle_t);
     52 static int	dwc_mmc_write_protect(sdmmc_chipset_handle_t);
     53 static int	dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
     54 static int	dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int);
     55 static int	dwc_mmc_bus_width(sdmmc_chipset_handle_t, int);
     56 static int	dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int);
     57 static void	dwc_mmc_exec_command(sdmmc_chipset_handle_t,
     58 				      struct sdmmc_command *);
     59 static void	dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int);
     60 static void	dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t);
     61 
     62 static struct sdmmc_chip_functions dwc_mmc_chip_functions = {
     63 	.host_reset = dwc_mmc_host_reset,
     64 	.host_ocr = dwc_mmc_host_ocr,
     65 	.host_maxblklen = dwc_mmc_host_maxblklen,
     66 	.card_detect = dwc_mmc_card_detect,
     67 	.write_protect = dwc_mmc_write_protect,
     68 	.bus_power = dwc_mmc_bus_power,
     69 	.bus_clock = dwc_mmc_bus_clock,
     70 	.bus_width = dwc_mmc_bus_width,
     71 	.bus_rod = dwc_mmc_bus_rod,
     72 	.exec_command = dwc_mmc_exec_command,
     73 	.card_enable_intr = dwc_mmc_card_enable_intr,
     74 	.card_intr_ack = dwc_mmc_card_intr_ack,
     75 };
     76 
     77 #define MMC_WRITE(sc, reg, val)	\
     78 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
     79 #define MMC_READ(sc, reg) \
     80 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
     81 
     82 static void
     83 dwc_mmc_dump_regs(struct dwc_mmc_softc *sc)
     84 {
     85 	device_printf(sc->sc_dev, "device registers:\n");
     86 	for (u_int off = 0x00; off < 0x100; off += 16) {
     87 		device_printf(sc->sc_dev, "xxxxxx%02x: %08x %08x %08x %08x\n",
     88 		    off,
     89 		    MMC_READ(sc, off + 0), MMC_READ(sc, off + 4),
     90 		    MMC_READ(sc, off + 8), MMC_READ(sc, off + 12));
     91 	}
     92 }
     93 
     94 static int
     95 dwc_mmc_idma_setup(struct dwc_mmc_softc *sc)
     96 {
     97 	int error;
     98 
     99 	sc->sc_idma_xferlen = 0x1000;
    100 
    101 	sc->sc_idma_ndesc = DWC_MMC_NDESC;
    102 	sc->sc_idma_size = sizeof(struct dwc_mmc_idma_desc) *
    103 	    sc->sc_idma_ndesc;
    104 	error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 8,
    105 	    sc->sc_idma_size, sc->sc_idma_segs, 1,
    106 	    &sc->sc_idma_nsegs, BUS_DMA_WAITOK);
    107 	if (error)
    108 		return error;
    109 	error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs,
    110 	    sc->sc_idma_nsegs, sc->sc_idma_size,
    111 	    &sc->sc_idma_desc, BUS_DMA_WAITOK);
    112 	if (error)
    113 		goto free;
    114 	error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1,
    115 	    sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map);
    116 	if (error)
    117 		goto unmap;
    118 	error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map,
    119 	    sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK);
    120 	if (error)
    121 		goto destroy;
    122 	return 0;
    123 
    124 destroy:
    125 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map);
    126 unmap:
    127 	bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size);
    128 free:
    129 	bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs);
    130 	return error;
    131 }
    132 
    133 static void
    134 dwc_mmc_attach_i(device_t self)
    135 {
    136 	struct dwc_mmc_softc *sc = device_private(self);
    137 	struct sdmmcbus_attach_args saa;
    138 
    139 	dwc_mmc_host_reset(sc);
    140 	dwc_mmc_bus_width(sc, 1);
    141 
    142 	memset(&saa, 0, sizeof(saa));
    143 	saa.saa_busname = "sdmmc";
    144 	saa.saa_sct = &dwc_mmc_chip_functions;
    145 	saa.saa_sch = sc;
    146 	saa.saa_clkmin = 400;
    147 	saa.saa_clkmax = sc->sc_clock_freq / 1000;
    148 	saa.saa_caps = SMC_CAPS_4BIT_MODE|
    149 		       SMC_CAPS_8BIT_MODE|
    150 		       SMC_CAPS_SD_HIGHSPEED|
    151 		       SMC_CAPS_MMC_HIGHSPEED|
    152 		       SMC_CAPS_AUTO_STOP;
    153 	if (ISSET(sc->sc_flags, DWC_MMC_F_DMA)) {
    154 		saa.saa_dmat = sc->sc_dmat;
    155 		saa.saa_caps |= SMC_CAPS_DMA |
    156 				SMC_CAPS_MULTI_SEG_DMA;
    157 	}
    158 	if (sc->sc_card_detect)
    159 		saa.saa_caps |= SMC_CAPS_POLL_CARD_DET;
    160 
    161 	sc->sc_sdmmc_dev = config_found(self, &saa, NULL);
    162 }
    163 
    164 static int
    165 dwc_mmc_wait_rint(struct dwc_mmc_softc *sc, uint32_t mask, int timeout)
    166 {
    167 	const bool use_dma = ISSET(sc->sc_flags, DWC_MMC_F_DMA);
    168 	int retry, error;
    169 
    170 	KASSERT(mutex_owned(&sc->sc_intr_lock));
    171 
    172 	if (sc->sc_intr_rint & mask)
    173 		return 0;
    174 
    175 	retry = timeout / hz;
    176 
    177 	while (retry > 0) {
    178 		if (use_dma) {
    179 			error = cv_timedwait(&sc->sc_intr_cv,
    180 			    &sc->sc_intr_lock, hz);
    181 			if (error && error != EWOULDBLOCK)
    182 				return error;
    183 			if (sc->sc_intr_rint & mask)
    184 				return 0;
    185 		} else {
    186 			sc->sc_intr_rint |= MMC_READ(sc, DWC_MMC_RINT);
    187 			if (sc->sc_intr_rint & mask)
    188 				return 0;
    189 			delay(1000);
    190 		}
    191 		--retry;
    192 	}
    193 
    194 	return ETIMEDOUT;
    195 }
    196 
    197 static void
    198 dwc_mmc_led(struct dwc_mmc_softc *sc, int on)
    199 {
    200 	if (sc->sc_set_led)
    201 		sc->sc_set_led(sc, on);
    202 }
    203 
    204 static int
    205 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch)
    206 {
    207 	struct dwc_mmc_softc *sc = sch;
    208 	uint32_t fifoth, ctrl;
    209 	int retry = 1000;
    210 
    211 #ifdef DWC_MMC_DEBUG
    212 	aprint_normal_dev(sc->sc_dev, "host reset\n");
    213 #endif
    214 
    215 	MMC_WRITE(sc, DWC_MMC_PWREN, 1);
    216 
    217 	MMC_WRITE(sc, DWC_MMC_GCTRL,
    218 	    MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_RESET);
    219 	while (--retry > 0) {
    220 		if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET))
    221 			break;
    222 		delay(100);
    223 	}
    224 
    225 	MMC_WRITE(sc, DWC_MMC_CLKSRC, 0);
    226 
    227 	MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff);
    228 
    229 	MMC_WRITE(sc, DWC_MMC_IMASK,
    230 	    DWC_MMC_INT_CMD_DONE | DWC_MMC_INT_ERROR |
    231 	    DWC_MMC_INT_DATA_OVER | DWC_MMC_INT_AUTO_CMD_DONE);
    232 
    233 	const uint32_t rx_wmark = (sc->sc_fifo_depth / 2) - 1;
    234 	const uint32_t tx_wmark = sc->sc_fifo_depth / 2;
    235 	fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16,
    236 			   DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE);
    237 	fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK);
    238 	fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK);
    239 	MMC_WRITE(sc, DWC_MMC_FIFOTH, fifoth);
    240 
    241 	MMC_WRITE(sc, DWC_MMC_UHS, 0);
    242 
    243 	ctrl = MMC_READ(sc, DWC_MMC_GCTRL);
    244 	ctrl |= DWC_MMC_GCTRL_INTEN;
    245 	ctrl |= DWC_MMC_GCTRL_DMAEN;
    246 	ctrl |= DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD;
    247 	ctrl |= DWC_MMC_GCTRL_USE_INTERNAL_DMAC;
    248 	MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl);
    249 
    250 	return 0;
    251 }
    252 
    253 static uint32_t
    254 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch)
    255 {
    256 	return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS;
    257 }
    258 
    259 static int
    260 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch)
    261 {
    262 	return 32768;
    263 }
    264 
    265 static int
    266 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch)
    267 {
    268 	struct dwc_mmc_softc *sc = sch;
    269 
    270 	if (!sc->sc_card_detect)
    271 		return 1;	/* no card detect pin, assume present */
    272 
    273 	return sc->sc_card_detect(sc);
    274 }
    275 
    276 static int
    277 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch)
    278 {
    279 	struct dwc_mmc_softc *sc = sch;
    280 
    281 	if (!sc->sc_write_protect)
    282 		return 0;	/* no write protect pin, assume rw */
    283 
    284 	return sc->sc_write_protect(sc);
    285 }
    286 
    287 static int
    288 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
    289 {
    290 	return 0;
    291 }
    292 
    293 static int
    294 dwc_mmc_update_clock(struct dwc_mmc_softc *sc)
    295 {
    296 	uint32_t cmd;
    297 	int retry;
    298 
    299 #ifdef DWC_MMC_DEBUG
    300 	aprint_normal_dev(sc->sc_dev, "update clock\n");
    301 #endif
    302 
    303 	cmd = DWC_MMC_CMD_START |
    304 	      DWC_MMC_CMD_UPCLK_ONLY |
    305 	      DWC_MMC_CMD_WAIT_PRE_OVER;
    306 	if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG))
    307 		cmd |= DWC_MMC_CMD_USE_HOLD_REG;
    308 	MMC_WRITE(sc, DWC_MMC_ARG, 0);
    309 	MMC_WRITE(sc, DWC_MMC_CMD, cmd);
    310 	retry = 200000;
    311 	while (--retry > 0) {
    312 		if (!(MMC_READ(sc, DWC_MMC_CMD) & DWC_MMC_CMD_START))
    313 			break;
    314 		delay(10);
    315 	}
    316 
    317 	if (retry == 0) {
    318 		aprint_error_dev(sc->sc_dev, "timeout updating clock\n");
    319 #ifdef DWC_MMC_DEBUG
    320 		device_printf(sc->sc_dev, "GCTRL: 0x%08x\n",
    321 		    MMC_READ(sc, DWC_MMC_GCTRL));
    322 		device_printf(sc->sc_dev, "CLKENA: 0x%08x\n",
    323 		    MMC_READ(sc, DWC_MMC_CLKENA));
    324 		device_printf(sc->sc_dev, "CLKDIV: 0x%08x\n",
    325 		    MMC_READ(sc, DWC_MMC_CLKDIV));
    326 		device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n",
    327 		    MMC_READ(sc, DWC_MMC_TIMEOUT));
    328 		device_printf(sc->sc_dev, "WIDTH: 0x%08x\n",
    329 		    MMC_READ(sc, DWC_MMC_WIDTH));
    330 		device_printf(sc->sc_dev, "CMD: 0x%08x\n",
    331 		    MMC_READ(sc, DWC_MMC_CMD));
    332 		device_printf(sc->sc_dev, "MINT: 0x%08x\n",
    333 		    MMC_READ(sc, DWC_MMC_MINT));
    334 		device_printf(sc->sc_dev, "RINT: 0x%08x\n",
    335 		    MMC_READ(sc, DWC_MMC_RINT));
    336 		device_printf(sc->sc_dev, "STATUS: 0x%08x\n",
    337 		    MMC_READ(sc, DWC_MMC_STATUS));
    338 #endif
    339 		return ETIMEDOUT;
    340 	}
    341 
    342 	return 0;
    343 }
    344 
    345 static int
    346 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq)
    347 {
    348 	const u_int pll_freq = sc->sc_clock_freq / 1000;
    349 	u_int clk_div;
    350 
    351 	if (freq != pll_freq)
    352 		clk_div = howmany(pll_freq, freq);
    353 	else
    354 		clk_div = 0;
    355 
    356 	MMC_WRITE(sc, DWC_MMC_CLKDIV, clk_div);
    357 
    358 	return dwc_mmc_update_clock(sc);
    359 }
    360 
    361 static int
    362 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
    363 {
    364 	struct dwc_mmc_softc *sc = sch;
    365 	uint32_t clkena;
    366 
    367 	MMC_WRITE(sc, DWC_MMC_CLKSRC, 0);
    368 	MMC_WRITE(sc, DWC_MMC_CLKENA, 0);
    369 	if (dwc_mmc_update_clock(sc) != 0)
    370 		return 1;
    371 
    372 	if (freq) {
    373 		if (sc->sc_bus_clock && sc->sc_bus_clock(sc, freq) != 0)
    374 			return 1;
    375 
    376 		if (dwc_mmc_set_clock(sc, freq) != 0)
    377 			return 1;
    378 
    379 		clkena = DWC_MMC_CLKENA_CARDCLKON;
    380 		MMC_WRITE(sc, DWC_MMC_CLKENA, clkena);
    381 		if (dwc_mmc_update_clock(sc) != 0)
    382 			return 1;
    383 	}
    384 
    385 	delay(1000);
    386 
    387 	return 0;
    388 }
    389 
    390 static int
    391 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width)
    392 {
    393 	struct dwc_mmc_softc *sc = sch;
    394 
    395 #ifdef DWC_MMC_DEBUG
    396 	aprint_normal_dev(sc->sc_dev, "width = %d\n", width);
    397 #endif
    398 
    399 	switch (width) {
    400 	case 1:
    401 		MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_1);
    402 		break;
    403 	case 4:
    404 		MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_4);
    405 		break;
    406 	case 8:
    407 		MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_8);
    408 		break;
    409 	default:
    410 		return 1;
    411 	}
    412 
    413 	sc->sc_mmc_width = width;
    414 
    415 	return 0;
    416 }
    417 
    418 static int
    419 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on)
    420 {
    421 	return -1;
    422 }
    423 
    424 
    425 static int
    426 dwc_mmc_pio_wait(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd)
    427 {
    428 	int retry = 0xfffff;
    429 	uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ?
    430 	    DWC_MMC_STATUS_FIFO_EMPTY : DWC_MMC_STATUS_FIFO_FULL;
    431 
    432 	while (--retry > 0) {
    433 		uint32_t status = MMC_READ(sc, DWC_MMC_STATUS);
    434 		if (!(status & bit))
    435 			return 0;
    436 		delay(10);
    437 	}
    438 
    439 	return ETIMEDOUT;
    440 }
    441 
    442 static int
    443 dwc_mmc_pio_transfer(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd)
    444 {
    445 	uint32_t *datap = (uint32_t *)cmd->c_data;
    446 	int i;
    447 
    448 	for (i = 0; i < (cmd->c_resid >> 2); i++) {
    449 		if (dwc_mmc_pio_wait(sc, cmd))
    450 			return ETIMEDOUT;
    451 		if (cmd->c_flags & SCF_CMD_READ) {
    452 			datap[i] = MMC_READ(sc, sc->sc_fifo_reg);
    453 		} else {
    454 			MMC_WRITE(sc, sc->sc_fifo_reg, datap[i]);
    455 		}
    456 	}
    457 
    458 	return 0;
    459 }
    460 
    461 static int
    462 dwc_mmc_dma_prepare(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd)
    463 {
    464 	struct dwc_mmc_idma_desc *dma = sc->sc_idma_desc;
    465 	bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr;
    466 	bus_size_t off;
    467 	int desc, resid, seg;
    468 	uint32_t val;
    469 
    470 	desc = 0;
    471 	for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) {
    472 		bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr;
    473 		bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len;
    474 		resid = uimin(len, cmd->c_resid);
    475 		off = 0;
    476 		while (resid > 0) {
    477 			if (desc == sc->sc_idma_ndesc)
    478 				break;
    479 			len = uimin(sc->sc_idma_xferlen, resid);
    480 			dma[desc].dma_buf_size = htole32(len);
    481 			dma[desc].dma_buf_addr = htole32(paddr + off);
    482 			dma[desc].dma_config = htole32(
    483 			    DWC_MMC_IDMA_CONFIG_OWN);
    484 			cmd->c_resid -= len;
    485 			resid -= len;
    486 			off += len;
    487 			dma[desc].dma_next = htole32(
    488 			    desc_paddr + ((desc+1) *
    489 			    sizeof(struct dwc_mmc_idma_desc)));
    490 			if (desc == 0) {
    491 				dma[desc].dma_config |= htole32(
    492 				    DWC_MMC_IDMA_CONFIG_FD);
    493 			}
    494 			if (cmd->c_resid == 0) {
    495 				dma[desc].dma_config |= htole32(
    496 				    DWC_MMC_IDMA_CONFIG_LD);
    497 			} else {
    498 				dma[desc].dma_config |=
    499 				    htole32(DWC_MMC_IDMA_CONFIG_CH|
    500 					    DWC_MMC_IDMA_CONFIG_DIC);
    501 			}
    502 			++desc;
    503 		}
    504 	}
    505 	if (desc == sc->sc_idma_ndesc) {
    506 		aprint_error_dev(sc->sc_dev,
    507 		    "not enough descriptors for %d byte transfer!\n",
    508 		    cmd->c_datalen);
    509 		return EIO;
    510 	}
    511 
    512 	bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0,
    513 	    sc->sc_idma_size, BUS_DMASYNC_PREWRITE);
    514 
    515 	sc->sc_idma_idst = 0;
    516 
    517 	val = MMC_READ(sc, DWC_MMC_GCTRL);
    518 	val |= DWC_MMC_GCTRL_DMAEN;
    519 	val |= DWC_MMC_GCTRL_INTEN;
    520 	MMC_WRITE(sc, DWC_MMC_GCTRL, val);
    521 	val |= DWC_MMC_GCTRL_DMARESET;
    522 	MMC_WRITE(sc, DWC_MMC_GCTRL, val);
    523 	MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET);
    524 	MMC_WRITE(sc, DWC_MMC_DMAC,
    525 	    DWC_MMC_DMAC_IDMA_ON|DWC_MMC_DMAC_FIX_BURST);
    526 	val = MMC_READ(sc, DWC_MMC_IDIE);
    527 	val &= ~(DWC_MMC_IDST_RECEIVE_INT|DWC_MMC_IDST_TRANSMIT_INT);
    528 	if (cmd->c_flags & SCF_CMD_READ)
    529 		val |= DWC_MMC_IDST_RECEIVE_INT;
    530 	else
    531 		val |= DWC_MMC_IDST_TRANSMIT_INT;
    532 	MMC_WRITE(sc, DWC_MMC_IDIE, val);
    533 	MMC_WRITE(sc, DWC_MMC_DLBA, desc_paddr);
    534 
    535 	return 0;
    536 }
    537 
    538 static void
    539 dwc_mmc_dma_complete(struct dwc_mmc_softc *sc)
    540 {
    541 	bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0,
    542 	    sc->sc_idma_size, BUS_DMASYNC_POSTWRITE);
    543 }
    544 
    545 static void
    546 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
    547 {
    548 	struct dwc_mmc_softc *sc = sch;
    549 	uint32_t cmdval = DWC_MMC_CMD_START;
    550 	int retry = 200000;
    551 
    552 #ifdef DWC_MMC_DEBUG
    553 	aprint_normal_dev(sc->sc_dev,
    554 	    "opcode %d flags 0x%x data %p datalen %d blklen %d\n",
    555 	    cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen,
    556 	    cmd->c_blklen);
    557 #endif
    558 
    559 	mutex_enter(&sc->sc_intr_lock);
    560 
    561 	do {
    562 		const uint32_t status = MMC_READ(sc, DWC_MMC_STATUS);
    563 		if ((status & DWC_MMC_STATUS_CARD_DATA_BUSY) == 0)
    564 			break;
    565 		delay(10);
    566 	} while (--retry > 0);
    567 	if (retry == 0) {
    568 		aprint_error_dev(sc->sc_dev, "timeout waiting for data busy\n");
    569 		cmd->c_error = ETIMEDOUT;
    570 		goto done;
    571 	}
    572 
    573 	MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff);
    574 	MMC_WRITE(sc, DWC_MMC_RINT, 0xffffffff);
    575 
    576 	if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG))
    577 		cmdval |= DWC_MMC_CMD_USE_HOLD_REG;
    578 
    579 	if (cmd->c_opcode == 0)
    580 		cmdval |= DWC_MMC_CMD_SEND_INIT_SEQ;
    581 	if (cmd->c_flags & SCF_RSP_PRESENT)
    582 		cmdval |= DWC_MMC_CMD_RSP_EXP;
    583 	if (cmd->c_flags & SCF_RSP_136)
    584 		cmdval |= DWC_MMC_CMD_LONG_RSP;
    585 	if (cmd->c_flags & SCF_RSP_CRC)
    586 		cmdval |= DWC_MMC_CMD_CHECK_RSP_CRC;
    587 
    588 	if (cmd->c_datalen > 0) {
    589 		unsigned int nblks;
    590 
    591 		cmdval |= DWC_MMC_CMD_DATA_EXP | DWC_MMC_CMD_WAIT_PRE_OVER;
    592 		if (!ISSET(cmd->c_flags, SCF_CMD_READ)) {
    593 			cmdval |= DWC_MMC_CMD_WRITE;
    594 		}
    595 
    596 		nblks = cmd->c_datalen / cmd->c_blklen;
    597 		if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0)
    598 			++nblks;
    599 
    600 		if (nblks > 1) {
    601 			cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP;
    602 		}
    603 
    604 		MMC_WRITE(sc, DWC_MMC_BLKSZ, cmd->c_blklen);
    605 		MMC_WRITE(sc, DWC_MMC_BYTECNT, nblks * cmd->c_blklen);
    606 	}
    607 
    608 	sc->sc_intr_rint = 0;
    609 
    610 	MMC_WRITE(sc, DWC_MMC_ARG, cmd->c_arg);
    611 
    612 #ifdef DWC_MMC_DEBUG
    613 	aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval);
    614 #endif
    615 
    616 	if (cmd->c_datalen > 0) {
    617 		cmd->c_resid = cmd->c_datalen;
    618 		dwc_mmc_led(sc, 0);
    619 		if (ISSET(sc->sc_flags, DWC_MMC_F_DMA)) {
    620 			cmd->c_error = dwc_mmc_dma_prepare(sc, cmd);
    621 			MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode);
    622 			MMC_WRITE(sc, DWC_MMC_PLDMND, 1);
    623 			if (cmd->c_error == 0) {
    624 				const uint32_t idst_mask =
    625 				    DWC_MMC_IDST_ERROR | DWC_MMC_IDST_COMPLETE;
    626 				retry = 10;
    627 				while ((sc->sc_idma_idst & idst_mask) == 0) {
    628 					if (retry == 0) {
    629 						cmd->c_error = ETIMEDOUT;
    630 						break;
    631 					}
    632 					cv_timedwait(&sc->sc_idst_cv,
    633 					    &sc->sc_intr_lock, hz);
    634 				}
    635 			}
    636 			dwc_mmc_dma_complete(sc);
    637 			if (sc->sc_idma_idst & DWC_MMC_IDST_ERROR) {
    638 				cmd->c_error = EIO;
    639 			} else if (!(sc->sc_idma_idst & DWC_MMC_IDST_COMPLETE)) {
    640 				cmd->c_error = ETIMEDOUT;
    641 			}
    642 		} else {
    643 			mutex_exit(&sc->sc_intr_lock);
    644 			MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode);
    645 			cmd->c_error = dwc_mmc_pio_transfer(sc, cmd);
    646 			mutex_enter(&sc->sc_intr_lock);
    647 		}
    648 		dwc_mmc_led(sc, 1);
    649 		if (cmd->c_error) {
    650 #ifdef DWC_MMC_DEBUG
    651 			aprint_error_dev(sc->sc_dev,
    652 			    "xfer failed, error %d\n", cmd->c_error);
    653 #endif
    654 			goto done;
    655 		}
    656 	} else {
    657 		MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode);
    658 	}
    659 
    660 	cmd->c_error = dwc_mmc_wait_rint(sc,
    661 	    DWC_MMC_INT_ERROR|DWC_MMC_INT_CMD_DONE, hz * 10);
    662 	if (cmd->c_error == 0 && (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) {
    663 		if (sc->sc_intr_rint & DWC_MMC_INT_RESP_TIMEOUT) {
    664 			cmd->c_error = ETIMEDOUT;
    665 		} else {
    666 			cmd->c_error = EIO;
    667 		}
    668 	}
    669 	if (cmd->c_error) {
    670 #ifdef DWC_MMC_DEBUG
    671 		aprint_error_dev(sc->sc_dev,
    672 		    "cmd failed, error %d\n", cmd->c_error);
    673 #endif
    674 		goto done;
    675 	}
    676 
    677 	if (cmd->c_datalen > 0) {
    678 		cmd->c_error = dwc_mmc_wait_rint(sc,
    679 		    DWC_MMC_INT_ERROR|
    680 		    DWC_MMC_INT_AUTO_CMD_DONE|
    681 		    DWC_MMC_INT_DATA_OVER,
    682 		    hz*10);
    683 		if (cmd->c_error == 0 &&
    684 		    (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) {
    685 			cmd->c_error = ETIMEDOUT;
    686 		}
    687 		if (cmd->c_error) {
    688 #ifdef DWC_MMC_DEBUG
    689 			aprint_error_dev(sc->sc_dev,
    690 			    "data timeout, rint = %08x\n",
    691 			    sc->sc_intr_rint);
    692 #endif
    693 			dwc_mmc_dump_regs(sc);
    694 			cmd->c_error = ETIMEDOUT;
    695 			goto done;
    696 		}
    697 	}
    698 
    699 	if (cmd->c_flags & SCF_RSP_PRESENT) {
    700 		if (cmd->c_flags & SCF_RSP_136) {
    701 			cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0);
    702 			cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1);
    703 			cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2);
    704 			cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3);
    705 			if (cmd->c_flags & SCF_RSP_CRC) {
    706 				cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
    707 				    (cmd->c_resp[1] << 24);
    708 				cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
    709 				    (cmd->c_resp[2] << 24);
    710 				cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
    711 				    (cmd->c_resp[3] << 24);
    712 				cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
    713 			}
    714 		} else {
    715 			cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0);
    716 		}
    717 	}
    718 
    719 done:
    720 	cmd->c_flags |= SCF_ITSDONE;
    721 	mutex_exit(&sc->sc_intr_lock);
    722 
    723 	if (cmd->c_error) {
    724 #ifdef DWC_MMC_DEBUG
    725 		aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error);
    726 #endif
    727 		MMC_WRITE(sc, DWC_MMC_GCTRL,
    728 		    MMC_READ(sc, DWC_MMC_GCTRL) |
    729 		      DWC_MMC_GCTRL_DMARESET | DWC_MMC_GCTRL_FIFORESET);
    730 		for (retry = 0; retry < 1000; retry++) {
    731 			if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET))
    732 				break;
    733 			delay(10);
    734 		}
    735 		dwc_mmc_update_clock(sc);
    736 	}
    737 
    738 	if (!ISSET(sc->sc_flags, DWC_MMC_F_DMA)) {
    739 		MMC_WRITE(sc, DWC_MMC_GCTRL,
    740 		    MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_FIFORESET);
    741 	}
    742 }
    743 
    744 static void
    745 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
    746 {
    747 }
    748 
    749 static void
    750 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch)
    751 {
    752 }
    753 
    754 int
    755 dwc_mmc_init(struct dwc_mmc_softc *sc)
    756 {
    757 	uint32_t val;
    758 
    759 	if (sc->sc_fifo_reg == 0) {
    760 		val = MMC_READ(sc, DWC_MMC_VERID);
    761 		const u_int id = __SHIFTOUT(val, DWC_MMC_VERID_ID);
    762 
    763 		if (id < DWC_MMC_VERID_240A)
    764 			sc->sc_fifo_reg = 0x100;
    765 		else
    766 			sc->sc_fifo_reg = 0x200;
    767 	}
    768 
    769 	if (sc->sc_fifo_depth == 0) {
    770 		val = MMC_READ(sc, DWC_MMC_FIFOTH);
    771 		sc->sc_fifo_depth = __SHIFTOUT(val, DWC_MMC_FIFOTH_RX_WMARK) + 1;
    772 	}
    773 
    774 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
    775 	cv_init(&sc->sc_intr_cv, "dwcmmcirq");
    776 	cv_init(&sc->sc_idst_cv, "dwcmmcdma");
    777 
    778 	const bool use_dma = ISSET(sc->sc_flags, DWC_MMC_F_DMA);
    779 
    780 	aprint_debug_dev(sc->sc_dev, "using %s for transfers\n",
    781 	    use_dma ? "DMA" : "PIO");
    782 
    783 	if (use_dma && dwc_mmc_idma_setup(sc) != 0) {
    784 		aprint_error_dev(sc->sc_dev, "failed to setup DMA\n");
    785 		return ENOMEM;
    786 	}
    787 
    788 	config_interrupts(sc->sc_dev, dwc_mmc_attach_i);
    789 
    790 	return 0;
    791 }
    792 
    793 int
    794 dwc_mmc_intr(void *priv)
    795 {
    796 	struct dwc_mmc_softc *sc = priv;
    797 	uint32_t idst, rint, mint;
    798 
    799 	mutex_enter(&sc->sc_intr_lock);
    800 	idst = MMC_READ(sc, DWC_MMC_IDST);
    801 	rint = MMC_READ(sc, DWC_MMC_RINT);
    802 	mint = MMC_READ(sc, DWC_MMC_MINT);
    803 	if (!idst && !rint && !mint) {
    804 		mutex_exit(&sc->sc_intr_lock);
    805 		return 0;
    806 	}
    807 	MMC_WRITE(sc, DWC_MMC_IDST, idst);
    808 	MMC_WRITE(sc, DWC_MMC_RINT, rint);
    809 	MMC_WRITE(sc, DWC_MMC_MINT, mint);
    810 
    811 #ifdef DWC_MMC_DEBUG
    812 	device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n",
    813 	    idst, rint, mint);
    814 #endif
    815 
    816 	if (idst) {
    817 		sc->sc_idma_idst |= idst;
    818 		cv_broadcast(&sc->sc_idst_cv);
    819 	}
    820 
    821 	if (rint) {
    822 		sc->sc_intr_rint |= rint;
    823 		cv_broadcast(&sc->sc_intr_cv);
    824 	}
    825 
    826 	mutex_exit(&sc->sc_intr_lock);
    827 
    828 	return 1;
    829 }
    830