dwc_mmc.c revision 1.18
1 /* $NetBSD: dwc_mmc.c,v 1.18 2019/10/05 12:27:14 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.18 2019/10/05 12:27:14 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/sdmmc/sdmmcvar.h> 40 #include <dev/sdmmc/sdmmcchip.h> 41 #include <dev/sdmmc/sdmmc_ioreg.h> 42 43 #include <dev/ic/dwc_mmc_reg.h> 44 #include <dev/ic/dwc_mmc_var.h> 45 46 #define DWC_MMC_NDESC 64 47 48 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 49 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 50 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 51 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 52 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 53 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 54 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 55 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 56 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 57 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 58 struct sdmmc_command *); 59 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 60 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 61 62 static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 63 .host_reset = dwc_mmc_host_reset, 64 .host_ocr = dwc_mmc_host_ocr, 65 .host_maxblklen = dwc_mmc_host_maxblklen, 66 .card_detect = dwc_mmc_card_detect, 67 .write_protect = dwc_mmc_write_protect, 68 .bus_power = dwc_mmc_bus_power, 69 .bus_clock = dwc_mmc_bus_clock, 70 .bus_width = dwc_mmc_bus_width, 71 .bus_rod = dwc_mmc_bus_rod, 72 .exec_command = dwc_mmc_exec_command, 73 .card_enable_intr = dwc_mmc_card_enable_intr, 74 .card_intr_ack = dwc_mmc_card_intr_ack, 75 }; 76 77 #define MMC_WRITE(sc, reg, val) \ 78 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 79 #define MMC_READ(sc, reg) \ 80 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 81 82 static int 83 dwc_mmc_dmabounce_setup(struct dwc_mmc_softc *sc) 84 { 85 bus_dma_segment_t ds[1]; 86 int error, rseg; 87 88 sc->sc_dmabounce_buflen = dwc_mmc_host_maxblklen(sc); 89 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0, 90 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK); 91 if (error) 92 return error; 93 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen, 94 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK); 95 if (error) 96 goto free; 97 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1, 98 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map); 99 if (error) 100 goto unmap; 101 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map, 102 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL, 103 BUS_DMA_WAITOK); 104 if (error) 105 goto destroy; 106 return 0; 107 108 destroy: 109 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map); 110 unmap: 111 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf, 112 sc->sc_dmabounce_buflen); 113 free: 114 bus_dmamem_free(sc->sc_dmat, ds, rseg); 115 return error; 116 } 117 118 static int 119 dwc_mmc_idma_setup(struct dwc_mmc_softc *sc) 120 { 121 int error; 122 123 sc->sc_idma_xferlen = 0x1000; 124 125 sc->sc_idma_ndesc = DWC_MMC_NDESC; 126 sc->sc_idma_size = sizeof(struct dwc_mmc_idma_desc) * 127 sc->sc_idma_ndesc; 128 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 8, 129 sc->sc_idma_size, sc->sc_idma_segs, 1, 130 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 131 if (error) 132 return error; 133 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 134 sc->sc_idma_nsegs, sc->sc_idma_size, 135 &sc->sc_idma_desc, BUS_DMA_WAITOK); 136 if (error) 137 goto free; 138 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 139 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 140 if (error) 141 goto unmap; 142 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 143 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 144 if (error) 145 goto destroy; 146 return 0; 147 148 destroy: 149 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 150 unmap: 151 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 152 free: 153 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 154 return error; 155 } 156 157 static void 158 dwc_mmc_attach_i(device_t self) 159 { 160 struct dwc_mmc_softc *sc = device_private(self); 161 struct sdmmcbus_attach_args saa; 162 163 dwc_mmc_host_reset(sc); 164 dwc_mmc_bus_width(sc, 1); 165 166 memset(&saa, 0, sizeof(saa)); 167 saa.saa_busname = "sdmmc"; 168 saa.saa_sct = &dwc_mmc_chip_functions; 169 saa.saa_sch = sc; 170 saa.saa_clkmin = 400; 171 saa.saa_clkmax = sc->sc_clock_freq / 1000; 172 saa.saa_dmat = sc->sc_dmat; 173 saa.saa_caps = SMC_CAPS_4BIT_MODE| 174 SMC_CAPS_8BIT_MODE| 175 SMC_CAPS_SD_HIGHSPEED| 176 SMC_CAPS_MMC_HIGHSPEED| 177 SMC_CAPS_AUTO_STOP | 178 SMC_CAPS_DMA | 179 SMC_CAPS_MULTI_SEG_DMA; 180 if (sc->sc_card_detect) 181 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 182 183 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 184 } 185 186 static void 187 dwc_mmc_led(struct dwc_mmc_softc *sc, int on) 188 { 189 if (sc->sc_set_led) 190 sc->sc_set_led(sc, on); 191 } 192 193 static int 194 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 195 { 196 struct dwc_mmc_softc *sc = sch; 197 uint32_t fifoth, ctrl; 198 int retry = 1000; 199 200 #ifdef DWC_MMC_DEBUG 201 aprint_normal_dev(sc->sc_dev, "host reset\n"); 202 #endif 203 204 MMC_WRITE(sc, DWC_MMC_PWREN, 1); 205 206 MMC_WRITE(sc, DWC_MMC_GCTRL, 207 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_RESET); 208 while (--retry > 0) { 209 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET)) 210 break; 211 delay(100); 212 } 213 214 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 215 216 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff); 217 218 MMC_WRITE(sc, DWC_MMC_IMASK, 0); 219 220 MMC_WRITE(sc, DWC_MMC_RINT, 0xffffffff); 221 222 const uint32_t rx_wmark = (sc->sc_fifo_depth / 2) - 1; 223 const uint32_t tx_wmark = sc->sc_fifo_depth / 2; 224 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 225 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 226 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 227 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 228 MMC_WRITE(sc, DWC_MMC_FIFOTH, fifoth); 229 230 MMC_WRITE(sc, DWC_MMC_UHS, 0); 231 232 ctrl = MMC_READ(sc, DWC_MMC_GCTRL); 233 ctrl |= DWC_MMC_GCTRL_INTEN; 234 ctrl |= DWC_MMC_GCTRL_DMAEN; 235 ctrl |= DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD; 236 ctrl |= DWC_MMC_GCTRL_USE_INTERNAL_DMAC; 237 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl); 238 239 return 0; 240 } 241 242 static uint32_t 243 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 244 { 245 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 246 } 247 248 static int 249 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 250 { 251 return 32768; 252 } 253 254 static int 255 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 256 { 257 struct dwc_mmc_softc *sc = sch; 258 259 if (!sc->sc_card_detect) 260 return 1; /* no card detect pin, assume present */ 261 262 return sc->sc_card_detect(sc); 263 } 264 265 static int 266 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 267 { 268 struct dwc_mmc_softc *sc = sch; 269 270 if (!sc->sc_write_protect) 271 return 0; /* no write protect pin, assume rw */ 272 273 return sc->sc_write_protect(sc); 274 } 275 276 static int 277 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 278 { 279 return 0; 280 } 281 282 static int 283 dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 284 { 285 uint32_t cmd; 286 int retry; 287 288 #ifdef DWC_MMC_DEBUG 289 aprint_normal_dev(sc->sc_dev, "update clock\n"); 290 #endif 291 292 cmd = DWC_MMC_CMD_START | 293 DWC_MMC_CMD_UPCLK_ONLY | 294 DWC_MMC_CMD_WAIT_PRE_OVER; 295 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 296 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 297 MMC_WRITE(sc, DWC_MMC_ARG, 0); 298 MMC_WRITE(sc, DWC_MMC_CMD, cmd); 299 retry = 200000; 300 while (--retry > 0) { 301 if (!(MMC_READ(sc, DWC_MMC_CMD) & DWC_MMC_CMD_START)) 302 break; 303 delay(10); 304 } 305 306 if (retry == 0) { 307 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 308 #ifdef DWC_MMC_DEBUG 309 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 310 MMC_READ(sc, DWC_MMC_GCTRL)); 311 device_printf(sc->sc_dev, "CLKENA: 0x%08x\n", 312 MMC_READ(sc, DWC_MMC_CLKENA)); 313 device_printf(sc->sc_dev, "CLKDIV: 0x%08x\n", 314 MMC_READ(sc, DWC_MMC_CLKDIV)); 315 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 316 MMC_READ(sc, DWC_MMC_TIMEOUT)); 317 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 318 MMC_READ(sc, DWC_MMC_WIDTH)); 319 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 320 MMC_READ(sc, DWC_MMC_CMD)); 321 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 322 MMC_READ(sc, DWC_MMC_MINT)); 323 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 324 MMC_READ(sc, DWC_MMC_RINT)); 325 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 326 MMC_READ(sc, DWC_MMC_STATUS)); 327 #endif 328 return ETIMEDOUT; 329 } 330 331 return 0; 332 } 333 334 static int 335 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 336 { 337 const u_int pll_freq = sc->sc_clock_freq / 1000; 338 u_int clk_div; 339 340 if (freq != pll_freq) 341 clk_div = howmany(pll_freq, freq); 342 else 343 clk_div = 0; 344 345 MMC_WRITE(sc, DWC_MMC_CLKDIV, clk_div); 346 347 return dwc_mmc_update_clock(sc); 348 } 349 350 static int 351 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 352 { 353 struct dwc_mmc_softc *sc = sch; 354 uint32_t clkena; 355 356 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 357 MMC_WRITE(sc, DWC_MMC_CLKENA, 0); 358 if (dwc_mmc_update_clock(sc) != 0) 359 return 1; 360 361 if (freq) { 362 if (sc->sc_bus_clock && sc->sc_bus_clock(sc, freq) != 0) 363 return 1; 364 365 if (dwc_mmc_set_clock(sc, freq) != 0) 366 return 1; 367 368 clkena = DWC_MMC_CLKENA_CARDCLKON; 369 MMC_WRITE(sc, DWC_MMC_CLKENA, clkena); 370 if (dwc_mmc_update_clock(sc) != 0) 371 return 1; 372 } 373 374 delay(1000); 375 376 return 0; 377 } 378 379 static int 380 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 381 { 382 struct dwc_mmc_softc *sc = sch; 383 384 #ifdef DWC_MMC_DEBUG 385 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 386 #endif 387 388 switch (width) { 389 case 1: 390 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_1); 391 break; 392 case 4: 393 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_4); 394 break; 395 case 8: 396 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_8); 397 break; 398 default: 399 return 1; 400 } 401 402 sc->sc_mmc_width = width; 403 404 return 0; 405 } 406 407 static int 408 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 409 { 410 return -1; 411 } 412 413 static int 414 dwc_mmc_dma_prepare(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 415 { 416 struct dwc_mmc_idma_desc *dma = sc->sc_idma_desc; 417 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 418 bus_dmamap_t map; 419 bus_size_t off; 420 int desc, resid, seg; 421 uint32_t val; 422 423 /* 424 * If the command includs a dma map use it, otherwise we need to 425 * bounce. This can happen for SDIO IO_RW_EXTENDED (CMD53) commands. 426 */ 427 if (cmd->c_dmamap) { 428 map = cmd->c_dmamap; 429 } else { 430 if (cmd->c_datalen > sc->sc_dmabounce_buflen) 431 return E2BIG; 432 map = sc->sc_dmabounce_map; 433 434 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 435 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen); 436 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 437 0, cmd->c_datalen, BUS_DMASYNC_PREREAD); 438 } else { 439 memcpy(sc->sc_dmabounce_buf, cmd->c_data, 440 cmd->c_datalen); 441 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 442 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE); 443 } 444 } 445 446 desc = 0; 447 for (seg = 0; seg < map->dm_nsegs; seg++) { 448 bus_addr_t paddr = map->dm_segs[seg].ds_addr; 449 bus_size_t len = map->dm_segs[seg].ds_len; 450 resid = uimin(len, cmd->c_resid); 451 off = 0; 452 while (resid > 0) { 453 if (desc == sc->sc_idma_ndesc) 454 break; 455 len = uimin(sc->sc_idma_xferlen, resid); 456 dma[desc].dma_buf_size = htole32(len); 457 dma[desc].dma_buf_addr = htole32(paddr + off); 458 dma[desc].dma_config = htole32( 459 DWC_MMC_IDMA_CONFIG_CH | 460 DWC_MMC_IDMA_CONFIG_OWN); 461 cmd->c_resid -= len; 462 resid -= len; 463 off += len; 464 if (desc == 0) { 465 dma[desc].dma_config |= htole32( 466 DWC_MMC_IDMA_CONFIG_FD); 467 } 468 if (cmd->c_resid == 0) { 469 dma[desc].dma_config |= htole32( 470 DWC_MMC_IDMA_CONFIG_LD); 471 dma[desc].dma_config |= htole32( 472 DWC_MMC_IDMA_CONFIG_ER); 473 dma[desc].dma_next = 0; 474 } else { 475 dma[desc].dma_config |= 476 htole32(DWC_MMC_IDMA_CONFIG_DIC); 477 dma[desc].dma_next = htole32( 478 desc_paddr + ((desc+1) * 479 sizeof(struct dwc_mmc_idma_desc))); 480 } 481 ++desc; 482 } 483 } 484 if (desc == sc->sc_idma_ndesc) { 485 aprint_error_dev(sc->sc_dev, 486 "not enough descriptors for %d byte transfer!\n", 487 cmd->c_datalen); 488 return EIO; 489 } 490 491 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 492 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 493 494 MMC_WRITE(sc, DWC_MMC_DLBA, desc_paddr); 495 496 val = MMC_READ(sc, DWC_MMC_GCTRL); 497 val |= DWC_MMC_GCTRL_DMAEN; 498 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 499 val |= DWC_MMC_GCTRL_DMARESET; 500 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 501 502 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET); 503 if (cmd->c_flags & SCF_CMD_READ) 504 val = DWC_MMC_IDST_RECEIVE_INT; 505 else 506 val = 0; 507 MMC_WRITE(sc, DWC_MMC_IDIE, val); 508 MMC_WRITE(sc, DWC_MMC_DMAC, 509 DWC_MMC_DMAC_IDMA_ON|DWC_MMC_DMAC_FIX_BURST); 510 511 return 0; 512 } 513 514 static void 515 dwc_mmc_dma_complete(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 516 { 517 MMC_WRITE(sc, DWC_MMC_DMAC, 0); 518 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 519 520 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 521 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 522 523 if (cmd->c_dmamap == NULL) { 524 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 525 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 526 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD); 527 memcpy(cmd->c_data, sc->sc_dmabounce_buf, 528 cmd->c_datalen); 529 } else { 530 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 531 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 532 } 533 } 534 } 535 536 static void 537 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 538 { 539 struct dwc_mmc_softc *sc = sch; 540 uint32_t cmdval = DWC_MMC_CMD_START; 541 int retry, error; 542 uint32_t imask; 543 544 #ifdef DWC_MMC_DEBUG 545 aprint_normal_dev(sc->sc_dev, 546 "opcode %d flags 0x%x data %p datalen %d blklen %d\n", 547 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 548 cmd->c_blklen); 549 #endif 550 551 mutex_enter(&sc->sc_intr_lock); 552 if (sc->sc_curcmd != NULL) { 553 device_printf(sc->sc_dev, 554 "WARNING: driver submitted a command while the controller was busy\n"); 555 cmd->c_error = EBUSY; 556 SET(cmd->c_flags, SCF_ITSDONE); 557 mutex_exit(&sc->sc_intr_lock); 558 return; 559 } 560 sc->sc_curcmd = cmd; 561 562 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff); 563 564 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 565 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 566 567 if (cmd->c_opcode == 0) 568 cmdval |= DWC_MMC_CMD_SEND_INIT_SEQ; 569 if (cmd->c_flags & SCF_RSP_PRESENT) 570 cmdval |= DWC_MMC_CMD_RSP_EXP; 571 if (cmd->c_flags & SCF_RSP_136) 572 cmdval |= DWC_MMC_CMD_LONG_RSP; 573 if (cmd->c_flags & SCF_RSP_CRC) 574 cmdval |= DWC_MMC_CMD_CHECK_RSP_CRC; 575 576 imask = DWC_MMC_INT_ERROR | DWC_MMC_INT_CMD_DONE; 577 578 if (cmd->c_datalen > 0) { 579 unsigned int nblks; 580 581 cmdval |= DWC_MMC_CMD_DATA_EXP | DWC_MMC_CMD_WAIT_PRE_OVER; 582 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 583 cmdval |= DWC_MMC_CMD_WRITE; 584 } 585 586 nblks = cmd->c_datalen / cmd->c_blklen; 587 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 588 ++nblks; 589 590 if (nblks > 1) { 591 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 592 imask |= DWC_MMC_INT_AUTO_CMD_DONE; 593 } else { 594 imask |= DWC_MMC_INT_DATA_OVER; 595 } 596 597 MMC_WRITE(sc, DWC_MMC_BLKSZ, cmd->c_blklen); 598 MMC_WRITE(sc, DWC_MMC_BYTECNT, nblks * cmd->c_blklen); 599 } 600 601 MMC_WRITE(sc, DWC_MMC_IMASK, imask | sc->sc_intr_card); 602 MMC_WRITE(sc, DWC_MMC_RINT, 0x7fff); 603 604 MMC_WRITE(sc, DWC_MMC_ARG, cmd->c_arg); 605 606 #ifdef DWC_MMC_DEBUG 607 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 608 #endif 609 610 cmd->c_resid = cmd->c_datalen; 611 if (cmd->c_datalen > 0) { 612 dwc_mmc_led(sc, 0); 613 cmd->c_error = dwc_mmc_dma_prepare(sc, cmd); 614 if (cmd->c_error != 0) { 615 SET(cmd->c_flags, SCF_ITSDONE); 616 goto done; 617 } 618 sc->sc_wait_dma = ISSET(cmd->c_flags, SCF_CMD_READ); 619 sc->sc_wait_data = true; 620 } else { 621 sc->sc_wait_dma = false; 622 sc->sc_wait_data = false; 623 } 624 sc->sc_wait_cmd = true; 625 626 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 627 628 if (sc->sc_wait_dma) 629 MMC_WRITE(sc, DWC_MMC_PLDMND, 1); 630 631 struct bintime timeout = { .sec = 15, .frac = 0 }; 632 const struct bintime epsilon = { .sec = 1, .frac = 0 }; 633 while (!ISSET(cmd->c_flags, SCF_ITSDONE)) { 634 error = cv_timedwaitbt(&sc->sc_intr_cv, 635 &sc->sc_intr_lock, &timeout, &epsilon); 636 if (error != 0) { 637 cmd->c_error = error; 638 SET(cmd->c_flags, SCF_ITSDONE); 639 goto done; 640 } 641 } 642 643 if (cmd->c_error == 0 && cmd->c_datalen > 0) 644 dwc_mmc_dma_complete(sc, cmd); 645 646 if (cmd->c_datalen > 0) 647 dwc_mmc_led(sc, 1); 648 649 if (cmd->c_flags & SCF_RSP_PRESENT) { 650 if (cmd->c_flags & SCF_RSP_136) { 651 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 652 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1); 653 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2); 654 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3); 655 if (cmd->c_flags & SCF_RSP_CRC) { 656 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 657 (cmd->c_resp[1] << 24); 658 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 659 (cmd->c_resp[2] << 24); 660 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 661 (cmd->c_resp[3] << 24); 662 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 663 } 664 } else { 665 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 666 } 667 } 668 669 done: 670 KASSERT(ISSET(cmd->c_flags, SCF_ITSDONE)); 671 MMC_WRITE(sc, DWC_MMC_IMASK, sc->sc_intr_card); 672 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 673 MMC_WRITE(sc, DWC_MMC_RINT, 0x7fff); 674 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff); 675 sc->sc_curcmd = NULL; 676 mutex_exit(&sc->sc_intr_lock); 677 678 if (cmd->c_error) { 679 #ifdef DWC_MMC_DEBUG 680 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 681 #endif 682 MMC_WRITE(sc, DWC_MMC_GCTRL, 683 MMC_READ(sc, DWC_MMC_GCTRL) | 684 DWC_MMC_GCTRL_DMARESET | DWC_MMC_GCTRL_FIFORESET); 685 for (retry = 0; retry < 1000; retry++) { 686 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET)) 687 break; 688 delay(10); 689 } 690 dwc_mmc_update_clock(sc); 691 } 692 693 MMC_WRITE(sc, DWC_MMC_GCTRL, 694 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_FIFORESET); 695 } 696 697 static void 698 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 699 { 700 struct dwc_mmc_softc *sc = sch; 701 uint32_t imask; 702 703 mutex_enter(&sc->sc_intr_lock); 704 imask = MMC_READ(sc, DWC_MMC_IMASK); 705 if (enable) 706 imask |= DWC_MMC_INT_SDIO_INT; 707 else 708 imask &= ~DWC_MMC_INT_SDIO_INT; 709 sc->sc_intr_card = imask & DWC_MMC_INT_SDIO_INT; 710 MMC_WRITE(sc, DWC_MMC_IMASK, imask); 711 mutex_exit(&sc->sc_intr_lock); 712 } 713 714 static void 715 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 716 { 717 struct dwc_mmc_softc *sc = sch; 718 uint32_t imask; 719 720 mutex_enter(&sc->sc_intr_lock); 721 imask = MMC_READ(sc, DWC_MMC_IMASK); 722 MMC_WRITE(sc, DWC_MMC_IMASK, imask | sc->sc_intr_card); 723 mutex_exit(&sc->sc_intr_lock); 724 } 725 726 int 727 dwc_mmc_init(struct dwc_mmc_softc *sc) 728 { 729 uint32_t val; 730 731 if (sc->sc_fifo_reg == 0) { 732 val = MMC_READ(sc, DWC_MMC_VERID); 733 const u_int id = __SHIFTOUT(val, DWC_MMC_VERID_ID); 734 735 if (id < DWC_MMC_VERID_240A) 736 sc->sc_fifo_reg = 0x100; 737 else 738 sc->sc_fifo_reg = 0x200; 739 } 740 741 if (sc->sc_fifo_depth == 0) { 742 val = MMC_READ(sc, DWC_MMC_FIFOTH); 743 sc->sc_fifo_depth = __SHIFTOUT(val, DWC_MMC_FIFOTH_RX_WMARK) + 1; 744 } 745 746 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 747 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 748 749 if (dwc_mmc_dmabounce_setup(sc) != 0 || 750 dwc_mmc_idma_setup(sc) != 0) { 751 aprint_error_dev(sc->sc_dev, "failed to setup DMA\n"); 752 return ENOMEM; 753 } 754 755 config_interrupts(sc->sc_dev, dwc_mmc_attach_i); 756 757 return 0; 758 } 759 760 int 761 dwc_mmc_intr(void *priv) 762 { 763 struct dwc_mmc_softc *sc = priv; 764 struct sdmmc_command *cmd; 765 uint32_t idst, mint, imask; 766 767 mutex_enter(&sc->sc_intr_lock); 768 idst = MMC_READ(sc, DWC_MMC_IDST); 769 mint = MMC_READ(sc, DWC_MMC_MINT); 770 if (!idst && !mint) { 771 mutex_exit(&sc->sc_intr_lock); 772 return 0; 773 } 774 MMC_WRITE(sc, DWC_MMC_IDST, idst); 775 MMC_WRITE(sc, DWC_MMC_RINT, mint); 776 777 cmd = sc->sc_curcmd; 778 779 #ifdef DWC_MMC_DEBUG 780 device_printf(sc->sc_dev, "mmc intr idst=%08X mint=%08X\n", 781 idst, mint); 782 #endif 783 784 /* Handle SDIO card interrupt */ 785 if ((mint & DWC_MMC_INT_SDIO_INT) != 0) { 786 imask = MMC_READ(sc, DWC_MMC_IMASK); 787 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_SDIO_INT); 788 sdmmc_card_intr(sc->sc_sdmmc_dev); 789 } 790 791 /* Error interrupts take priority over command and transfer interrupts */ 792 if (cmd != NULL && (mint & DWC_MMC_INT_ERROR) != 0) { 793 imask = MMC_READ(sc, DWC_MMC_IMASK); 794 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_ERROR); 795 if ((mint & DWC_MMC_INT_RESP_TIMEOUT) != 0) { 796 cmd->c_error = ETIMEDOUT; 797 /* Wait for command to complete */ 798 sc->sc_wait_data = sc->sc_wait_dma = false; 799 if (cmd->c_opcode != SD_IO_SEND_OP_COND && 800 cmd->c_opcode != SD_IO_RW_DIRECT && 801 !ISSET(cmd->c_flags, SCF_TOUT_OK)) 802 device_printf(sc->sc_dev, "host controller timeout, mint=0x%08x\n", mint); 803 } else { 804 device_printf(sc->sc_dev, "host controller error, mint=0x%08x\n", mint); 805 cmd->c_error = EIO; 806 SET(cmd->c_flags, SCF_ITSDONE); 807 goto done; 808 } 809 } 810 811 if (cmd != NULL && (idst & DWC_MMC_IDST_RECEIVE_INT) != 0) { 812 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 813 if (sc->sc_wait_dma == false) 814 device_printf(sc->sc_dev, "unexpected DMA receive interrupt\n"); 815 sc->sc_wait_dma = false; 816 } 817 818 if (cmd != NULL && (mint & DWC_MMC_INT_CMD_DONE) != 0) { 819 imask = MMC_READ(sc, DWC_MMC_IMASK); 820 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_CMD_DONE); 821 if (sc->sc_wait_cmd == false) 822 device_printf(sc->sc_dev, "unexpected command complete interrupt\n"); 823 sc->sc_wait_cmd = false; 824 } 825 826 const uint32_t dmadone_mask = DWC_MMC_INT_AUTO_CMD_DONE|DWC_MMC_INT_DATA_OVER; 827 if (cmd != NULL && (mint & dmadone_mask) != 0) { 828 imask = MMC_READ(sc, DWC_MMC_IMASK); 829 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~dmadone_mask); 830 if (sc->sc_wait_data == false) 831 device_printf(sc->sc_dev, "unexpected data complete interrupt\n"); 832 sc->sc_wait_data = false; 833 } 834 835 if (cmd != NULL && 836 sc->sc_wait_dma == false && 837 sc->sc_wait_cmd == false && 838 sc->sc_wait_data == false) { 839 SET(cmd->c_flags, SCF_ITSDONE); 840 } 841 842 done: 843 if (cmd != NULL && ISSET(cmd->c_flags, SCF_ITSDONE)) { 844 cv_broadcast(&sc->sc_intr_cv); 845 } 846 847 mutex_exit(&sc->sc_intr_lock); 848 849 return 1; 850 } 851
Indexes created Wed Sep 24 22:09:59 GMT 2025