dwc_mmc.c revision 1.2
1 /* $NetBSD: dwc_mmc.c,v 1.2 2014/12/27 19:18:04 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_dwc_mmc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.2 2014/12/27 19:18:04 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/sdmmc/sdmmcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmc_ioreg.h> 44 45 #include <dev/ic/dwc_mmc_reg.h> 46 #include <dev/ic/dwc_mmc_var.h> 47 48 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 49 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 50 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 51 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 52 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 53 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 54 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 55 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 56 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 57 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 58 struct sdmmc_command *); 59 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 60 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 61 62 static int dwc_mmc_set_clock(struct dwc_mmc_softc *, u_int); 63 static int dwc_mmc_update_clock(struct dwc_mmc_softc *); 64 static int dwc_mmc_wait_rint(struct dwc_mmc_softc *, uint32_t, int); 65 static int dwc_mmc_pio_wait(struct dwc_mmc_softc *, 66 struct sdmmc_command *); 67 static int dwc_mmc_pio_transfer(struct dwc_mmc_softc *, 68 struct sdmmc_command *); 69 70 void dwc_mmc_dump_regs(void); 71 72 static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 73 .host_reset = dwc_mmc_host_reset, 74 .host_ocr = dwc_mmc_host_ocr, 75 .host_maxblklen = dwc_mmc_host_maxblklen, 76 .card_detect = dwc_mmc_card_detect, 77 .write_protect = dwc_mmc_write_protect, 78 .bus_power = dwc_mmc_bus_power, 79 .bus_clock = dwc_mmc_bus_clock, 80 .bus_width = dwc_mmc_bus_width, 81 .bus_rod = dwc_mmc_bus_rod, 82 .exec_command = dwc_mmc_exec_command, 83 .card_enable_intr = dwc_mmc_card_enable_intr, 84 .card_intr_ack = dwc_mmc_card_intr_ack, 85 }; 86 87 #define MMC_WRITE(sc, reg, val) \ 88 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 89 #define MMC_READ(sc, reg) \ 90 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 91 92 void 93 dwc_mmc_init(struct dwc_mmc_softc *sc) 94 { 95 struct sdmmcbus_attach_args saa; 96 97 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 98 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 99 100 dwc_mmc_host_reset(sc); 101 dwc_mmc_bus_width(sc, 1); 102 103 memset(&saa, 0, sizeof(saa)); 104 saa.saa_busname = "sdmmc"; 105 saa.saa_sct = &dwc_mmc_chip_functions; 106 saa.saa_sch = sc; 107 saa.saa_clkmin = 400; 108 saa.saa_clkmax = sc->sc_clock_freq / 1000; 109 saa.saa_caps = SMC_CAPS_4BIT_MODE| 110 SMC_CAPS_8BIT_MODE| 111 SMC_CAPS_SD_HIGHSPEED| 112 SMC_CAPS_MMC_HIGHSPEED| 113 SMC_CAPS_AUTO_STOP; 114 saa.saa_dmat = sc->sc_dmat; 115 116 #if notyet 117 saa.saa_caps |= SMC_CAPS_DMA| 118 SMC_CAPS_MULTI_SEG_DMA; 119 #endif 120 121 sc->sc_sdmmc_dev = config_found(sc->sc_dev, &saa, NULL); 122 } 123 124 int 125 dwc_mmc_intr(void *priv) 126 { 127 struct dwc_mmc_softc *sc = priv; 128 uint32_t mint, rint; 129 130 mutex_enter(&sc->sc_intr_lock); 131 rint = MMC_READ(sc, DWC_MMC_RINTSTS_REG); 132 mint = MMC_READ(sc, DWC_MMC_MINTSTS_REG); 133 if (!rint && !mint) { 134 mutex_exit(&sc->sc_intr_lock); 135 return 0; 136 } 137 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, rint); 138 MMC_WRITE(sc, DWC_MMC_MINTSTS_REG, mint); 139 140 #ifdef DWC_MMC_DEBUG 141 device_printf(sc->sc_dev, "mint %#x rint %#x\n", mint, rint); 142 #endif 143 144 if (rint & DWC_MMC_INT_CARDDET) { 145 rint &= ~DWC_MMC_INT_CARDDET; 146 if (sc->sc_sdmmc_dev) { 147 sdmmc_needs_discover(sc->sc_sdmmc_dev); 148 } 149 } 150 151 if (rint) { 152 sc->sc_intr_rint |= rint; 153 cv_broadcast(&sc->sc_intr_cv); 154 } 155 156 mutex_exit(&sc->sc_intr_lock); 157 158 return 1; 159 } 160 161 static int 162 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 163 { 164 u_int pll_freq = sc->sc_clock_freq / 1000; 165 u_int clk_div, mmc_div; 166 167 mmc_div = min(howmany(pll_freq, freq), 0x3c); 168 clk_div = howmany(pll_freq / mmc_div, freq); 169 if (clk_div > 1 && (clk_div & 1) != 0) 170 clk_div++; 171 172 #ifdef DWC_MMC_DEBUG 173 device_printf(sc->sc_dev, "%s: mmc_div=%u clk_div=%u freq=%u\n", 174 __func__, mmc_div, clk_div, pll_freq / mmc_div / clk_div); 175 #endif 176 177 MMC_WRITE(sc, DWC_MMC_CLKDIV_REG, 178 __SHIFTIN(clk_div >> 1, DWC_MMC_CLKDIV_CLK_DIVIDER0)); 179 if (dwc_mmc_update_clock(sc)) 180 return ETIMEDOUT; 181 182 return sc->sc_set_clkdiv(sc, mmc_div); 183 } 184 185 static int 186 dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 187 { 188 uint32_t cmd; 189 int retry; 190 191 cmd = DWC_MMC_CMD_START_CMD | 192 DWC_MMC_CMD_UPDATE_CLOCK_REGS_ONLY | 193 DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE; 194 195 if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG) 196 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 197 198 MMC_WRITE(sc, DWC_MMC_CMD_REG, cmd); 199 retry = 0xfffff; 200 while (--retry > 0) { 201 cmd = MMC_READ(sc, DWC_MMC_CMD_REG); 202 if ((cmd & DWC_MMC_CMD_START_CMD) == 0) 203 break; 204 delay(10); 205 } 206 207 if (retry == 0) { 208 device_printf(sc->sc_dev, "timeout updating clock\n"); 209 return ETIMEDOUT; 210 } 211 212 return 0; 213 } 214 215 static int 216 dwc_mmc_wait_rint(struct dwc_mmc_softc *sc, uint32_t mask, int timeout) 217 { 218 int retry, error; 219 220 KASSERT(mutex_owned(&sc->sc_intr_lock)); 221 222 if (sc->sc_intr_rint & mask) 223 return 0; 224 225 retry = timeout / hz; 226 227 while (retry > 0) { 228 error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, hz); 229 if (error && error != EWOULDBLOCK) 230 return error; 231 if (sc->sc_intr_rint & mask) 232 return 0; 233 --retry; 234 } 235 236 return ETIMEDOUT; 237 } 238 239 static int 240 dwc_mmc_pio_wait(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 241 { 242 int retry = 0xfffff; 243 uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ? 244 DWC_MMC_STATUS_FIFO_EMPTY : DWC_MMC_STATUS_FIFO_FULL; 245 246 while (--retry > 0) { 247 uint32_t status = MMC_READ(sc, DWC_MMC_STATUS_REG); 248 if (!(status & bit)) 249 return 0; 250 delay(10); 251 } 252 253 #ifdef DWC_MMC_DEBUG 254 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 255 #endif 256 257 return ETIMEDOUT; 258 } 259 260 static int 261 dwc_mmc_pio_transfer(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 262 { 263 uint32_t *datap = (uint32_t *)cmd->c_data; 264 int i; 265 266 for (i = 0; i < (cmd->c_resid >> 2); i++) { 267 if (dwc_mmc_pio_wait(sc, cmd)) 268 return ETIMEDOUT; 269 if (cmd->c_flags & SCF_CMD_READ) { 270 datap[i] = MMC_READ(sc, DWC_MMC_FIFO_BASE_REG); 271 } else { 272 MMC_WRITE(sc, DWC_MMC_FIFO_BASE_REG, datap[i]); 273 } 274 } 275 276 return 0; 277 } 278 279 static int 280 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 281 { 282 struct dwc_mmc_softc *sc = sch; 283 int retry = 1000; 284 uint32_t ctrl, fifoth; 285 uint32_t rx_wmark, tx_wmark; 286 287 if (sc->sc_flags & DWC_MMC_F_PWREN_CLEAR) { 288 MMC_WRITE(sc, DWC_MMC_PWREN_REG, 0); 289 } else { 290 MMC_WRITE(sc, DWC_MMC_PWREN_REG, DWC_MMC_PWREN_POWER_ENABLE); 291 } 292 293 MMC_WRITE(sc, DWC_MMC_CTRL_REG, 294 MMC_READ(sc, DWC_MMC_CTRL_REG) | DWC_MMC_CTRL_RESET_ALL); 295 while (--retry > 0) { 296 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 297 if ((ctrl & DWC_MMC_CTRL_RESET_ALL) == 0) 298 break; 299 delay(100); 300 } 301 302 MMC_WRITE(sc, DWC_MMC_CLKSRC_REG, 0); 303 304 MMC_WRITE(sc, DWC_MMC_TMOUT_REG, 0xffffff40); 305 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, 0xffffffff); 306 307 MMC_WRITE(sc, DWC_MMC_INTMASK_REG, 308 DWC_MMC_INT_CD | DWC_MMC_INT_ACD | DWC_MMC_INT_DTO | 309 DWC_MMC_INT_ERROR | DWC_MMC_INT_CARDDET | 310 DWC_MMC_INT_RXDR | DWC_MMC_INT_TXDR); 311 312 rx_wmark = (sc->sc_fifo_depth / 2) - 1; 313 tx_wmark = sc->sc_fifo_depth / 2; 314 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 315 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 316 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 317 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 318 MMC_WRITE(sc, DWC_MMC_FIFOTH_REG, fifoth); 319 320 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 321 ctrl |= DWC_MMC_CTRL_INT_ENABLE; 322 MMC_WRITE(sc, DWC_MMC_CTRL_REG, ctrl); 323 324 return 0; 325 } 326 327 static uint32_t 328 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 329 { 330 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 331 } 332 333 static int 334 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 335 { 336 return 32768; 337 } 338 339 static int 340 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 341 { 342 struct dwc_mmc_softc *sc = sch; 343 uint32_t cdetect; 344 345 cdetect = MMC_READ(sc, DWC_MMC_CDETECT_REG); 346 return !!(cdetect & DWC_MMC_CDETECT_CARD_DETECT_N); 347 } 348 349 static int 350 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 351 { 352 struct dwc_mmc_softc *sc = sch; 353 uint32_t wrtprt; 354 355 wrtprt = MMC_READ(sc, DWC_MMC_WRTPRT_REG); 356 return !!(wrtprt & DWC_MMC_WRTPRT_WRITE_PROTECT); 357 } 358 359 static int 360 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 361 { 362 return 0; 363 } 364 365 static int 366 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 367 { 368 struct dwc_mmc_softc *sc = sch; 369 uint32_t clkena; 370 371 #ifdef DWC_MMC_DEBUG 372 device_printf(sc->sc_dev, "%s: freq %d\n", __func__, freq); 373 #endif 374 375 MMC_WRITE(sc, DWC_MMC_CLKENA_REG, 0); 376 if (dwc_mmc_update_clock(sc) != 0) 377 return ETIMEDOUT; 378 379 if (freq) { 380 if (dwc_mmc_set_clock(sc, freq) != 0) 381 return EIO; 382 383 clkena = DWC_MMC_CLKENA_CCLK_ENABLE; 384 clkena |= DWC_MMC_CLKENA_CCLK_LOW_POWER; /* XXX SD/MMC only */ 385 MMC_WRITE(sc, DWC_MMC_CLKENA_REG, clkena); 386 if (dwc_mmc_update_clock(sc) != 0) 387 return ETIMEDOUT; 388 } 389 390 delay(1000); 391 392 return 0; 393 } 394 395 static int 396 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 397 { 398 struct dwc_mmc_softc *sc = sch; 399 uint32_t ctype; 400 401 switch (width) { 402 case 1: 403 ctype = DWC_MMC_CTYPE_CARD_WIDTH_1; 404 break; 405 case 4: 406 ctype = DWC_MMC_CTYPE_CARD_WIDTH_4; 407 break; 408 case 8: 409 ctype = DWC_MMC_CTYPE_CARD_WIDTH_8; 410 break; 411 default: 412 return EINVAL; 413 } 414 415 MMC_WRITE(sc, DWC_MMC_CTYPE_REG, ctype); 416 417 return 0; 418 } 419 420 static int 421 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 422 { 423 return ENOTSUP; 424 } 425 426 static void 427 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 428 { 429 struct dwc_mmc_softc *sc = sch; 430 uint32_t cmdval = DWC_MMC_CMD_START_CMD; 431 uint32_t ctrl; 432 433 #ifdef DWC_MMC_DEBUG 434 device_printf(sc->sc_dev, "exec opcode=%d flags=%#x\n", 435 cmd->c_opcode, cmd->c_flags); 436 #endif 437 438 if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG) 439 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 440 441 mutex_enter(&sc->sc_intr_lock); 442 if (cmd->c_opcode == 0) 443 cmdval |= DWC_MMC_CMD_SEND_INIT; 444 if (cmd->c_flags & SCF_RSP_PRESENT) 445 cmdval |= DWC_MMC_CMD_RESP_EXPECTED; 446 if (cmd->c_flags & SCF_RSP_136) 447 cmdval |= DWC_MMC_CMD_RESP_LEN; 448 if (cmd->c_flags & SCF_RSP_CRC) 449 cmdval |= DWC_MMC_CMD_CHECK_RESP_CRC; 450 451 if (cmd->c_datalen > 0) { 452 unsigned int nblks; 453 454 cmdval |= DWC_MMC_CMD_DATA_EXPECTED; 455 cmdval |= DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE; 456 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 457 cmdval |= DWC_MMC_CMD_WR; 458 } 459 460 nblks = cmd->c_datalen / cmd->c_blklen; 461 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 462 ++nblks; 463 464 if (nblks > 1) { 465 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 466 } 467 468 MMC_WRITE(sc, DWC_MMC_BLKSIZ_REG, cmd->c_blklen); 469 MMC_WRITE(sc, DWC_MMC_BYTCNT_REG, nblks * cmd->c_blklen); 470 } 471 472 sc->sc_intr_rint = 0; 473 474 MMC_WRITE(sc, DWC_MMC_CMDARG_REG, cmd->c_arg); 475 476 cmd->c_resid = cmd->c_datalen; 477 MMC_WRITE(sc, DWC_MMC_CMD_REG, cmdval | cmd->c_opcode); 478 if (cmd->c_datalen > 0) { 479 cmd->c_error = dwc_mmc_pio_transfer(sc, cmd); 480 if (cmd->c_error) { 481 goto done; 482 } 483 } 484 485 cmd->c_error = dwc_mmc_wait_rint(sc, 486 DWC_MMC_INT_ERROR|DWC_MMC_INT_CD, hz * 10); 487 if (cmd->c_error == 0 && (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 488 #ifdef DWC_MMC_DEBUG 489 device_printf(sc->sc_dev, "%s: rint %#x\n", __func__, 490 sc->sc_intr_rint); 491 #endif 492 if (sc->sc_intr_rint & DWC_MMC_INT_RTO) { 493 cmd->c_error = ETIMEDOUT; 494 } else { 495 cmd->c_error = EIO; 496 } 497 } 498 if (cmd->c_error) { 499 goto done; 500 } 501 502 if (cmd->c_datalen > 0) { 503 cmd->c_error = dwc_mmc_wait_rint(sc, 504 DWC_MMC_INT_ERROR|DWC_MMC_INT_ACD|DWC_MMC_INT_DTO, 505 hz * 10); 506 if (cmd->c_error == 0 && 507 (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 508 #ifdef DWC_MMC_DEBUG 509 device_printf(sc->sc_dev, "%s: rint2 %#x\n", __func__, 510 sc->sc_intr_rint); 511 #endif 512 cmd->c_error = ETIMEDOUT; 513 } 514 if (cmd->c_error) { 515 goto done; 516 } 517 } 518 519 if (cmd->c_flags & SCF_RSP_PRESENT) { 520 if (cmd->c_flags & SCF_RSP_136) { 521 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0_REG); 522 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1_REG); 523 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2_REG); 524 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3_REG); 525 if (cmd->c_flags & SCF_RSP_CRC) { 526 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 527 (cmd->c_resp[1] << 24); 528 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 529 (cmd->c_resp[2] << 24); 530 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 531 (cmd->c_resp[3] << 24); 532 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 533 } 534 } else { 535 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0_REG); 536 } 537 } 538 539 done: 540 cmd->c_flags |= SCF_ITSDONE; 541 mutex_exit(&sc->sc_intr_lock); 542 543 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 544 ctrl |= DWC_MMC_CTRL_FIFO_RESET; 545 MMC_WRITE(sc, DWC_MMC_CTRL_REG, ctrl); 546 } 547 548 static void 549 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 550 { 551 } 552 553 static void 554 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 555 { 556 } 557 558 void 559 dwc_mmc_dump_regs(void) 560 { 561 static const struct { 562 const char *name; 563 unsigned int reg; 564 } regs[] = { 565 { "CTRL", DWC_MMC_CTRL_REG }, 566 { "PWREN", DWC_MMC_PWREN_REG }, 567 { "CLKDIV", DWC_MMC_CLKDIV_REG }, 568 { "CLKENA", DWC_MMC_CLKENA_REG }, 569 { "TMOUT", DWC_MMC_TMOUT_REG }, 570 { "CTYPE", DWC_MMC_CTYPE_REG }, 571 { "BLKSIZ", DWC_MMC_BLKSIZ_REG }, 572 { "BYTCNT", DWC_MMC_BYTCNT_REG }, 573 { "INTMASK", DWC_MMC_INTMASK_REG }, 574 { "MINTSTS", DWC_MMC_MINTSTS_REG }, 575 { "RINTSTS", DWC_MMC_RINTSTS_REG }, 576 { "STATUS", DWC_MMC_STATUS_REG }, 577 { "CDETECT", DWC_MMC_CDETECT_REG }, 578 { "WRTPRT", DWC_MMC_WRTPRT_REG }, 579 { "USRID", DWC_MMC_USRID_REG }, 580 { "VERID", DWC_MMC_VERID_REG }, 581 { "RST", DWC_MMC_RST_REG }, 582 { "BACK_END_POWER", DWC_MMC_BACK_END_POWER_REG }, 583 }; 584 device_t self = device_find_by_driver_unit("dwcmmc", 0); 585 if (self == NULL) 586 return; 587 struct dwc_mmc_softc *sc = device_private(self); 588 int i; 589 590 for (i = 0; i < __arraycount(regs); i++) { 591 device_printf(sc->sc_dev, "%s: %#x\n", regs[i].name, 592 MMC_READ(sc, regs[i].reg)); 593 } 594 } 595
Indexes created Mon Sep 22 05:09:51 GMT 2025