dwc_mmc.c revision 1.21
1 /* $NetBSD: dwc_mmc.c,v 1.21 2020/01/22 23:19:12 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.21 2020/01/22 23:19:12 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/proc.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/ic/dwc_mmc_reg.h> 45 #include <dev/ic/dwc_mmc_var.h> 46 47 #define DWC_MMC_NDESC 64 48 49 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 50 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 51 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 52 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 53 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 54 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 55 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 56 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 57 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 58 static int dwc_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 59 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 60 struct sdmmc_command *); 61 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 62 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 63 64 static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 65 .host_reset = dwc_mmc_host_reset, 66 .host_ocr = dwc_mmc_host_ocr, 67 .host_maxblklen = dwc_mmc_host_maxblklen, 68 .card_detect = dwc_mmc_card_detect, 69 .write_protect = dwc_mmc_write_protect, 70 .bus_power = dwc_mmc_bus_power, 71 .bus_clock = dwc_mmc_bus_clock, 72 .bus_width = dwc_mmc_bus_width, 73 .bus_rod = dwc_mmc_bus_rod, 74 .signal_voltage = dwc_mmc_signal_voltage, 75 .exec_command = dwc_mmc_exec_command, 76 .card_enable_intr = dwc_mmc_card_enable_intr, 77 .card_intr_ack = dwc_mmc_card_intr_ack, 78 }; 79 80 #define MMC_WRITE(sc, reg, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82 #define MMC_READ(sc, reg) \ 83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 85 static int 86 dwc_mmc_dmabounce_setup(struct dwc_mmc_softc *sc) 87 { 88 bus_dma_segment_t ds[1]; 89 int error, rseg; 90 91 sc->sc_dmabounce_buflen = dwc_mmc_host_maxblklen(sc); 92 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0, 93 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK); 94 if (error) 95 return error; 96 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen, 97 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK); 98 if (error) 99 goto free; 100 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1, 101 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map); 102 if (error) 103 goto unmap; 104 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map, 105 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL, 106 BUS_DMA_WAITOK); 107 if (error) 108 goto destroy; 109 return 0; 110 111 destroy: 112 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map); 113 unmap: 114 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf, 115 sc->sc_dmabounce_buflen); 116 free: 117 bus_dmamem_free(sc->sc_dmat, ds, rseg); 118 return error; 119 } 120 121 static int 122 dwc_mmc_idma_setup(struct dwc_mmc_softc *sc) 123 { 124 int error; 125 126 sc->sc_idma_xferlen = 0x1000; 127 128 sc->sc_idma_ndesc = DWC_MMC_NDESC; 129 sc->sc_idma_size = sizeof(struct dwc_mmc_idma_desc) * 130 sc->sc_idma_ndesc; 131 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 8, 132 sc->sc_idma_size, sc->sc_idma_segs, 1, 133 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 134 if (error) 135 return error; 136 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 137 sc->sc_idma_nsegs, sc->sc_idma_size, 138 &sc->sc_idma_desc, BUS_DMA_WAITOK); 139 if (error) 140 goto free; 141 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 142 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 143 if (error) 144 goto unmap; 145 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 146 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 147 if (error) 148 goto destroy; 149 return 0; 150 151 destroy: 152 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 153 unmap: 154 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 155 free: 156 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 157 return error; 158 } 159 160 static void 161 dwc_mmc_attach_i(device_t self) 162 { 163 struct dwc_mmc_softc *sc = device_private(self); 164 struct sdmmcbus_attach_args saa; 165 166 if (sc->sc_pre_power_on) 167 sc->sc_pre_power_on(sc); 168 169 dwc_mmc_signal_voltage(sc, SDMMC_SIGNAL_VOLTAGE_330); 170 dwc_mmc_host_reset(sc); 171 dwc_mmc_bus_width(sc, 1); 172 173 if (sc->sc_post_power_on) 174 sc->sc_post_power_on(sc); 175 176 memset(&saa, 0, sizeof(saa)); 177 saa.saa_busname = "sdmmc"; 178 saa.saa_sct = &dwc_mmc_chip_functions; 179 saa.saa_sch = sc; 180 saa.saa_clkmin = 400; 181 saa.saa_clkmax = sc->sc_clock_freq / 1000; 182 saa.saa_dmat = sc->sc_dmat; 183 saa.saa_caps = SMC_CAPS_SD_HIGHSPEED | 184 SMC_CAPS_MMC_HIGHSPEED | 185 SMC_CAPS_AUTO_STOP | 186 SMC_CAPS_DMA | 187 SMC_CAPS_MULTI_SEG_DMA; 188 if (sc->sc_bus_width == 8) 189 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 190 else 191 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 192 if (sc->sc_card_detect) 193 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 194 195 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 196 } 197 198 static void 199 dwc_mmc_led(struct dwc_mmc_softc *sc, int on) 200 { 201 if (sc->sc_set_led) 202 sc->sc_set_led(sc, on); 203 } 204 205 static int 206 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 207 { 208 struct dwc_mmc_softc *sc = sch; 209 uint32_t fifoth, ctrl; 210 int retry = 1000; 211 212 #ifdef DWC_MMC_DEBUG 213 aprint_normal_dev(sc->sc_dev, "host reset\n"); 214 #endif 215 216 if (ISSET(sc->sc_flags, DWC_MMC_F_PWREN_INV)) 217 MMC_WRITE(sc, DWC_MMC_PWREN, 0); 218 else 219 MMC_WRITE(sc, DWC_MMC_PWREN, 1); 220 221 ctrl = MMC_READ(sc, DWC_MMC_GCTRL); 222 ctrl &= ~DWC_MMC_GCTRL_USE_INTERNAL_DMAC; 223 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl); 224 225 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET); 226 227 MMC_WRITE(sc, DWC_MMC_GCTRL, 228 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_RESET); 229 while (--retry > 0) { 230 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET)) 231 break; 232 delay(100); 233 } 234 235 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 236 237 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff); 238 239 MMC_WRITE(sc, DWC_MMC_IMASK, 0); 240 241 MMC_WRITE(sc, DWC_MMC_RINT, 0xffffffff); 242 243 const uint32_t rx_wmark = (sc->sc_fifo_depth / 2) - 1; 244 const uint32_t tx_wmark = sc->sc_fifo_depth / 2; 245 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 246 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 247 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 248 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 249 MMC_WRITE(sc, DWC_MMC_FIFOTH, fifoth); 250 251 MMC_WRITE(sc, DWC_MMC_UHS, 0); 252 253 ctrl = MMC_READ(sc, DWC_MMC_GCTRL); 254 ctrl |= DWC_MMC_GCTRL_INTEN; 255 ctrl |= DWC_MMC_GCTRL_DMAEN; 256 ctrl |= DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD; 257 ctrl |= DWC_MMC_GCTRL_USE_INTERNAL_DMAC; 258 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl); 259 260 return 0; 261 } 262 263 static uint32_t 264 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 265 { 266 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 267 } 268 269 static int 270 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 271 { 272 return 32768; 273 } 274 275 static int 276 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 277 { 278 struct dwc_mmc_softc *sc = sch; 279 280 if (!sc->sc_card_detect) 281 return 1; /* no card detect pin, assume present */ 282 283 return sc->sc_card_detect(sc); 284 } 285 286 static int 287 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 288 { 289 struct dwc_mmc_softc *sc = sch; 290 291 if (!sc->sc_write_protect) 292 return 0; /* no write protect pin, assume rw */ 293 294 return sc->sc_write_protect(sc); 295 } 296 297 static int 298 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 299 { 300 return 0; 301 } 302 303 static int 304 dwc_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 305 { 306 struct dwc_mmc_softc *sc = sch; 307 308 if (sc->sc_signal_voltage == NULL) 309 return 0; 310 311 return sc->sc_signal_voltage(sc, signal_voltage); 312 } 313 314 static int 315 dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 316 { 317 uint32_t cmd; 318 int retry; 319 320 #ifdef DWC_MMC_DEBUG 321 aprint_normal_dev(sc->sc_dev, "update clock\n"); 322 #endif 323 324 cmd = DWC_MMC_CMD_START | 325 DWC_MMC_CMD_UPCLK_ONLY | 326 DWC_MMC_CMD_WAIT_PRE_OVER; 327 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 328 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 329 MMC_WRITE(sc, DWC_MMC_ARG, 0); 330 MMC_WRITE(sc, DWC_MMC_CMD, cmd); 331 retry = 200000; 332 while (--retry > 0) { 333 if (!(MMC_READ(sc, DWC_MMC_CMD) & DWC_MMC_CMD_START)) 334 break; 335 delay(10); 336 } 337 338 if (retry == 0) { 339 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 340 #ifdef DWC_MMC_DEBUG 341 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 342 MMC_READ(sc, DWC_MMC_GCTRL)); 343 device_printf(sc->sc_dev, "CLKENA: 0x%08x\n", 344 MMC_READ(sc, DWC_MMC_CLKENA)); 345 device_printf(sc->sc_dev, "CLKDIV: 0x%08x\n", 346 MMC_READ(sc, DWC_MMC_CLKDIV)); 347 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 348 MMC_READ(sc, DWC_MMC_TIMEOUT)); 349 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 350 MMC_READ(sc, DWC_MMC_WIDTH)); 351 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 352 MMC_READ(sc, DWC_MMC_CMD)); 353 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 354 MMC_READ(sc, DWC_MMC_MINT)); 355 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 356 MMC_READ(sc, DWC_MMC_RINT)); 357 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 358 MMC_READ(sc, DWC_MMC_STATUS)); 359 #endif 360 return ETIMEDOUT; 361 } 362 363 return 0; 364 } 365 366 static int 367 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 368 { 369 const u_int pll_freq = sc->sc_clock_freq / 1000; 370 u_int clk_div, ciu_div; 371 372 ciu_div = sc->sc_ciu_div > 0 ? sc->sc_ciu_div : 1; 373 374 if (freq != pll_freq) 375 clk_div = howmany(pll_freq, freq * ciu_div); 376 else 377 clk_div = 0; 378 379 MMC_WRITE(sc, DWC_MMC_CLKDIV, clk_div); 380 381 return dwc_mmc_update_clock(sc); 382 } 383 384 static int 385 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 386 { 387 struct dwc_mmc_softc *sc = sch; 388 uint32_t clkena; 389 390 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 391 MMC_WRITE(sc, DWC_MMC_CLKENA, 0); 392 if (dwc_mmc_update_clock(sc) != 0) 393 return 1; 394 395 if (freq) { 396 if (sc->sc_bus_clock && sc->sc_bus_clock(sc, freq) != 0) 397 return 1; 398 399 if (dwc_mmc_set_clock(sc, freq) != 0) 400 return 1; 401 402 clkena = DWC_MMC_CLKENA_CARDCLKON; 403 MMC_WRITE(sc, DWC_MMC_CLKENA, clkena); 404 if (dwc_mmc_update_clock(sc) != 0) 405 return 1; 406 } 407 408 delay(1000); 409 410 return 0; 411 } 412 413 static int 414 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 415 { 416 struct dwc_mmc_softc *sc = sch; 417 418 #ifdef DWC_MMC_DEBUG 419 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 420 #endif 421 422 switch (width) { 423 case 1: 424 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_1); 425 break; 426 case 4: 427 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_4); 428 break; 429 case 8: 430 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_8); 431 break; 432 default: 433 return 1; 434 } 435 436 sc->sc_mmc_width = width; 437 438 return 0; 439 } 440 441 static int 442 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 443 { 444 return -1; 445 } 446 447 static int 448 dwc_mmc_dma_prepare(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 449 { 450 struct dwc_mmc_idma_desc *dma = sc->sc_idma_desc; 451 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 452 bus_dmamap_t map; 453 bus_size_t off; 454 int desc, resid, seg; 455 uint32_t val; 456 457 /* 458 * If the command includs a dma map use it, otherwise we need to 459 * bounce. This can happen for SDIO IO_RW_EXTENDED (CMD53) commands. 460 */ 461 if (cmd->c_dmamap) { 462 map = cmd->c_dmamap; 463 } else { 464 if (cmd->c_datalen > sc->sc_dmabounce_buflen) 465 return E2BIG; 466 map = sc->sc_dmabounce_map; 467 468 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 469 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen); 470 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 471 0, cmd->c_datalen, BUS_DMASYNC_PREREAD); 472 } else { 473 memcpy(sc->sc_dmabounce_buf, cmd->c_data, 474 cmd->c_datalen); 475 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 476 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE); 477 } 478 } 479 480 desc = 0; 481 for (seg = 0; seg < map->dm_nsegs; seg++) { 482 bus_addr_t paddr = map->dm_segs[seg].ds_addr; 483 bus_size_t len = map->dm_segs[seg].ds_len; 484 resid = uimin(len, cmd->c_resid); 485 off = 0; 486 while (resid > 0) { 487 if (desc == sc->sc_idma_ndesc) 488 break; 489 len = uimin(sc->sc_idma_xferlen, resid); 490 dma[desc].dma_buf_size = htole32(len); 491 dma[desc].dma_buf_addr = htole32(paddr + off); 492 dma[desc].dma_config = htole32( 493 DWC_MMC_IDMA_CONFIG_CH | 494 DWC_MMC_IDMA_CONFIG_OWN); 495 cmd->c_resid -= len; 496 resid -= len; 497 off += len; 498 if (desc == 0) { 499 dma[desc].dma_config |= htole32( 500 DWC_MMC_IDMA_CONFIG_FD); 501 } 502 if (cmd->c_resid == 0) { 503 dma[desc].dma_config |= htole32( 504 DWC_MMC_IDMA_CONFIG_LD); 505 dma[desc].dma_config |= htole32( 506 DWC_MMC_IDMA_CONFIG_ER); 507 dma[desc].dma_next = 0; 508 } else { 509 dma[desc].dma_config |= 510 htole32(DWC_MMC_IDMA_CONFIG_DIC); 511 dma[desc].dma_next = htole32( 512 desc_paddr + ((desc+1) * 513 sizeof(struct dwc_mmc_idma_desc))); 514 } 515 ++desc; 516 } 517 } 518 if (desc == sc->sc_idma_ndesc) { 519 aprint_error_dev(sc->sc_dev, 520 "not enough descriptors for %d byte transfer!\n", 521 cmd->c_datalen); 522 return EIO; 523 } 524 525 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 526 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 527 528 MMC_WRITE(sc, DWC_MMC_DLBA, desc_paddr); 529 530 val = MMC_READ(sc, DWC_MMC_GCTRL); 531 val |= DWC_MMC_GCTRL_DMAEN; 532 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 533 val |= DWC_MMC_GCTRL_DMARESET; 534 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 535 536 if (cmd->c_flags & SCF_CMD_READ) 537 val = DWC_MMC_IDST_RECEIVE_INT; 538 else 539 val = 0; 540 MMC_WRITE(sc, DWC_MMC_IDIE, val); 541 MMC_WRITE(sc, DWC_MMC_DMAC, 542 DWC_MMC_DMAC_IDMA_ON|DWC_MMC_DMAC_FIX_BURST); 543 544 return 0; 545 } 546 547 static void 548 dwc_mmc_dma_complete(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 549 { 550 MMC_WRITE(sc, DWC_MMC_DMAC, 0); 551 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 552 553 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 554 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 555 556 if (cmd->c_dmamap == NULL) { 557 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 558 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 559 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD); 560 memcpy(cmd->c_data, sc->sc_dmabounce_buf, 561 cmd->c_datalen); 562 } else { 563 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 564 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 565 } 566 } 567 } 568 569 static void 570 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 571 { 572 struct dwc_mmc_softc *sc = sch; 573 uint32_t cmdval = DWC_MMC_CMD_START; 574 int retry, error; 575 uint32_t imask; 576 577 #ifdef DWC_MMC_DEBUG 578 aprint_normal_dev(sc->sc_dev, 579 "opcode %d flags 0x%x data %p datalen %d blklen %d\n", 580 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 581 cmd->c_blklen); 582 #endif 583 584 mutex_enter(&sc->sc_intr_lock); 585 if (sc->sc_curcmd != NULL) { 586 device_printf(sc->sc_dev, 587 "WARNING: driver submitted a command while the controller was busy\n"); 588 cmd->c_error = EBUSY; 589 SET(cmd->c_flags, SCF_ITSDONE); 590 mutex_exit(&sc->sc_intr_lock); 591 return; 592 } 593 sc->sc_curcmd = cmd; 594 595 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff); 596 597 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 598 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 599 600 if (cmd->c_opcode == MMC_GO_IDLE_STATE) 601 cmdval |= DWC_MMC_CMD_SEND_INIT_SEQ; 602 if (cmd->c_flags & SCF_RSP_PRESENT) 603 cmdval |= DWC_MMC_CMD_RSP_EXP; 604 if (cmd->c_flags & SCF_RSP_136) 605 cmdval |= DWC_MMC_CMD_LONG_RSP; 606 if (cmd->c_flags & SCF_RSP_CRC) 607 cmdval |= DWC_MMC_CMD_CHECK_RSP_CRC; 608 609 imask = DWC_MMC_INT_ERROR | DWC_MMC_INT_CMD_DONE; 610 611 if (cmd->c_datalen > 0) { 612 unsigned int nblks; 613 614 MMC_WRITE(sc, DWC_MMC_GCTRL, 615 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_FIFORESET); 616 for (retry = 0; retry < 100; retry++) { 617 if (!(MMC_READ(sc, DWC_MMC_DMAC) & DWC_MMC_DMAC_SOFTRESET)) 618 break; 619 kpause("dwcmmcfifo", false, uimax(mstohz(1), 1), &sc->sc_intr_lock); 620 } 621 622 cmdval |= DWC_MMC_CMD_DATA_EXP | DWC_MMC_CMD_WAIT_PRE_OVER; 623 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 624 cmdval |= DWC_MMC_CMD_WRITE; 625 } 626 627 nblks = cmd->c_datalen / cmd->c_blklen; 628 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 629 ++nblks; 630 631 if (nblks > 1 && cmd->c_opcode != SD_IO_RW_EXTENDED) { 632 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 633 imask |= DWC_MMC_INT_AUTO_CMD_DONE; 634 } else { 635 imask |= DWC_MMC_INT_DATA_OVER; 636 } 637 638 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff); 639 MMC_WRITE(sc, DWC_MMC_BLKSZ, cmd->c_blklen); 640 MMC_WRITE(sc, DWC_MMC_BYTECNT, 641 nblks > 1 ? nblks * cmd->c_blklen : cmd->c_datalen); 642 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 643 MMC_WRITE(sc, DWC_MMC_CARDTHRCTL, 644 __SHIFTIN(cmd->c_blklen, DWC_MMC_CARDTHRCTL_RDTHR) | 645 DWC_MMC_CARDTHRCTL_RDTHREN); 646 } 647 } 648 649 MMC_WRITE(sc, DWC_MMC_IMASK, imask | sc->sc_intr_card); 650 MMC_WRITE(sc, DWC_MMC_RINT, 0x7fff); 651 652 MMC_WRITE(sc, DWC_MMC_ARG, cmd->c_arg); 653 654 #ifdef DWC_MMC_DEBUG 655 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 656 #endif 657 658 cmd->c_resid = cmd->c_datalen; 659 if (cmd->c_datalen > 0) { 660 dwc_mmc_led(sc, 0); 661 cmd->c_error = dwc_mmc_dma_prepare(sc, cmd); 662 if (cmd->c_error != 0) { 663 SET(cmd->c_flags, SCF_ITSDONE); 664 goto done; 665 } 666 sc->sc_wait_dma = ISSET(cmd->c_flags, SCF_CMD_READ); 667 sc->sc_wait_data = true; 668 } else { 669 sc->sc_wait_dma = false; 670 sc->sc_wait_data = false; 671 } 672 sc->sc_wait_cmd = true; 673 674 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 675 676 if (sc->sc_wait_dma) 677 MMC_WRITE(sc, DWC_MMC_PLDMND, 1); 678 679 struct bintime timeout = { .sec = 15, .frac = 0 }; 680 const struct bintime epsilon = { .sec = 1, .frac = 0 }; 681 while (!ISSET(cmd->c_flags, SCF_ITSDONE)) { 682 error = cv_timedwaitbt(&sc->sc_intr_cv, 683 &sc->sc_intr_lock, &timeout, &epsilon); 684 if (error != 0) { 685 cmd->c_error = error; 686 SET(cmd->c_flags, SCF_ITSDONE); 687 goto done; 688 } 689 } 690 691 if (cmd->c_error == 0 && cmd->c_datalen > 0) 692 dwc_mmc_dma_complete(sc, cmd); 693 694 if (cmd->c_datalen > 0) 695 dwc_mmc_led(sc, 1); 696 697 if (cmd->c_flags & SCF_RSP_PRESENT) { 698 if (cmd->c_flags & SCF_RSP_136) { 699 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 700 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1); 701 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2); 702 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3); 703 if (cmd->c_flags & SCF_RSP_CRC) { 704 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 705 (cmd->c_resp[1] << 24); 706 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 707 (cmd->c_resp[2] << 24); 708 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 709 (cmd->c_resp[3] << 24); 710 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 711 } 712 } else { 713 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 714 } 715 } 716 717 done: 718 KASSERT(ISSET(cmd->c_flags, SCF_ITSDONE)); 719 MMC_WRITE(sc, DWC_MMC_IMASK, sc->sc_intr_card); 720 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 721 MMC_WRITE(sc, DWC_MMC_RINT, 0x7fff); 722 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff); 723 sc->sc_curcmd = NULL; 724 mutex_exit(&sc->sc_intr_lock); 725 726 if (cmd->c_error) { 727 #ifdef DWC_MMC_DEBUG 728 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 729 #endif 730 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET); 731 for (retry = 0; retry < 100; retry++) { 732 if (!(MMC_READ(sc, DWC_MMC_DMAC) & DWC_MMC_DMAC_SOFTRESET)) 733 break; 734 kpause("dwcmmcrst", false, uimax(mstohz(1), 1), NULL); 735 } 736 } 737 } 738 739 static void 740 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 741 { 742 struct dwc_mmc_softc *sc = sch; 743 uint32_t imask; 744 745 mutex_enter(&sc->sc_intr_lock); 746 imask = MMC_READ(sc, DWC_MMC_IMASK); 747 if (enable) 748 imask |= sc->sc_intr_cardmask; 749 else 750 imask &= ~sc->sc_intr_cardmask; 751 sc->sc_intr_card = imask & sc->sc_intr_cardmask; 752 MMC_WRITE(sc, DWC_MMC_IMASK, imask); 753 mutex_exit(&sc->sc_intr_lock); 754 } 755 756 static void 757 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 758 { 759 struct dwc_mmc_softc *sc = sch; 760 uint32_t imask; 761 762 mutex_enter(&sc->sc_intr_lock); 763 imask = MMC_READ(sc, DWC_MMC_IMASK); 764 MMC_WRITE(sc, DWC_MMC_IMASK, imask | sc->sc_intr_card); 765 mutex_exit(&sc->sc_intr_lock); 766 } 767 768 int 769 dwc_mmc_init(struct dwc_mmc_softc *sc) 770 { 771 uint32_t val; 772 773 if (sc->sc_fifo_reg == 0) { 774 val = MMC_READ(sc, DWC_MMC_VERID); 775 const u_int id = __SHIFTOUT(val, DWC_MMC_VERID_ID); 776 777 if (id < DWC_MMC_VERID_240A) 778 sc->sc_fifo_reg = 0x100; 779 else 780 sc->sc_fifo_reg = 0x200; 781 } 782 783 if (sc->sc_fifo_depth == 0) { 784 val = MMC_READ(sc, DWC_MMC_FIFOTH); 785 sc->sc_fifo_depth = __SHIFTOUT(val, DWC_MMC_FIFOTH_RX_WMARK) + 1; 786 } 787 788 if (sc->sc_intr_cardmask == 0) 789 sc->sc_intr_cardmask = DWC_MMC_INT_SDIO_INT(0); 790 791 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 792 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 793 794 if (dwc_mmc_dmabounce_setup(sc) != 0 || 795 dwc_mmc_idma_setup(sc) != 0) { 796 aprint_error_dev(sc->sc_dev, "failed to setup DMA\n"); 797 return ENOMEM; 798 } 799 800 config_interrupts(sc->sc_dev, dwc_mmc_attach_i); 801 802 return 0; 803 } 804 805 int 806 dwc_mmc_intr(void *priv) 807 { 808 struct dwc_mmc_softc *sc = priv; 809 struct sdmmc_command *cmd; 810 uint32_t idst, mint, imask; 811 812 mutex_enter(&sc->sc_intr_lock); 813 idst = MMC_READ(sc, DWC_MMC_IDST); 814 mint = MMC_READ(sc, DWC_MMC_MINT); 815 if (!idst && !mint) { 816 mutex_exit(&sc->sc_intr_lock); 817 return 0; 818 } 819 MMC_WRITE(sc, DWC_MMC_IDST, idst); 820 MMC_WRITE(sc, DWC_MMC_RINT, mint); 821 822 cmd = sc->sc_curcmd; 823 824 #ifdef DWC_MMC_DEBUG 825 device_printf(sc->sc_dev, "mmc intr idst=%08X mint=%08X\n", 826 idst, mint); 827 #endif 828 829 /* Handle SDIO card interrupt */ 830 if ((mint & sc->sc_intr_cardmask) != 0) { 831 imask = MMC_READ(sc, DWC_MMC_IMASK); 832 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~sc->sc_intr_cardmask); 833 sdmmc_card_intr(sc->sc_sdmmc_dev); 834 } 835 836 /* Error interrupts take priority over command and transfer interrupts */ 837 if (cmd != NULL && (mint & DWC_MMC_INT_ERROR) != 0) { 838 imask = MMC_READ(sc, DWC_MMC_IMASK); 839 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_ERROR); 840 if ((mint & DWC_MMC_INT_RESP_TIMEOUT) != 0) { 841 cmd->c_error = ETIMEDOUT; 842 /* Wait for command to complete */ 843 sc->sc_wait_data = sc->sc_wait_dma = false; 844 if (cmd->c_opcode != SD_IO_SEND_OP_COND && 845 cmd->c_opcode != SD_IO_RW_DIRECT && 846 !ISSET(cmd->c_flags, SCF_TOUT_OK)) 847 device_printf(sc->sc_dev, "host controller timeout, mint=0x%08x\n", mint); 848 } else { 849 device_printf(sc->sc_dev, "host controller error, mint=0x%08x\n", mint); 850 cmd->c_error = EIO; 851 SET(cmd->c_flags, SCF_ITSDONE); 852 goto done; 853 } 854 } 855 856 if (cmd != NULL && (idst & DWC_MMC_IDST_RECEIVE_INT) != 0) { 857 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 858 if (sc->sc_wait_dma == false) 859 device_printf(sc->sc_dev, "unexpected DMA receive interrupt\n"); 860 sc->sc_wait_dma = false; 861 } 862 863 if (cmd != NULL && (mint & DWC_MMC_INT_CMD_DONE) != 0) { 864 imask = MMC_READ(sc, DWC_MMC_IMASK); 865 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_CMD_DONE); 866 if (sc->sc_wait_cmd == false) 867 device_printf(sc->sc_dev, "unexpected command complete interrupt\n"); 868 sc->sc_wait_cmd = false; 869 } 870 871 const uint32_t dmadone_mask = DWC_MMC_INT_AUTO_CMD_DONE|DWC_MMC_INT_DATA_OVER; 872 if (cmd != NULL && (mint & dmadone_mask) != 0) { 873 imask = MMC_READ(sc, DWC_MMC_IMASK); 874 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~dmadone_mask); 875 if (sc->sc_wait_data == false) 876 device_printf(sc->sc_dev, "unexpected data complete interrupt\n"); 877 sc->sc_wait_data = false; 878 } 879 880 if (cmd != NULL && 881 sc->sc_wait_dma == false && 882 sc->sc_wait_cmd == false && 883 sc->sc_wait_data == false) { 884 SET(cmd->c_flags, SCF_ITSDONE); 885 } 886 887 done: 888 if (cmd != NULL && ISSET(cmd->c_flags, SCF_ITSDONE)) { 889 cv_broadcast(&sc->sc_intr_cv); 890 } 891 892 mutex_exit(&sc->sc_intr_lock); 893 894 return 1; 895 } 896
Indexes created Tue Sep 23 14:10:03 GMT 2025