dwc_mmc.c revision 1.28
1 /* $NetBSD: dwc_mmc.c,v 1.28 2021/08/07 16:19:12 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.28 2021/08/07 16:19:12 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/proc.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/ic/dwc_mmc_reg.h> 45 #include <dev/ic/dwc_mmc_var.h> 46 47 #define DWC_MMC_NDESC 64 48 49 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 50 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 51 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 52 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 53 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 54 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 55 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 56 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 57 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 58 static int dwc_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 59 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 60 struct sdmmc_command *); 61 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 62 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 63 64 static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 65 .host_reset = dwc_mmc_host_reset, 66 .host_ocr = dwc_mmc_host_ocr, 67 .host_maxblklen = dwc_mmc_host_maxblklen, 68 .card_detect = dwc_mmc_card_detect, 69 .write_protect = dwc_mmc_write_protect, 70 .bus_power = dwc_mmc_bus_power, 71 .bus_clock = dwc_mmc_bus_clock, 72 .bus_width = dwc_mmc_bus_width, 73 .bus_rod = dwc_mmc_bus_rod, 74 .signal_voltage = dwc_mmc_signal_voltage, 75 .exec_command = dwc_mmc_exec_command, 76 .card_enable_intr = dwc_mmc_card_enable_intr, 77 .card_intr_ack = dwc_mmc_card_intr_ack, 78 }; 79 80 #define MMC_WRITE(sc, reg, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82 #define MMC_READ(sc, reg) \ 83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 85 static int 86 dwc_mmc_dmabounce_setup(struct dwc_mmc_softc *sc) 87 { 88 bus_dma_segment_t ds[1]; 89 int error, rseg; 90 91 sc->sc_dmabounce_buflen = dwc_mmc_host_maxblklen(sc); 92 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0, 93 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK); 94 if (error) 95 return error; 96 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen, 97 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK); 98 if (error) 99 goto free; 100 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1, 101 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map); 102 if (error) 103 goto unmap; 104 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map, 105 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL, 106 BUS_DMA_WAITOK); 107 if (error) 108 goto destroy; 109 return 0; 110 111 destroy: 112 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map); 113 unmap: 114 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf, 115 sc->sc_dmabounce_buflen); 116 free: 117 bus_dmamem_free(sc->sc_dmat, ds, rseg); 118 return error; 119 } 120 121 static int 122 dwc_mmc_idma_setup(struct dwc_mmc_softc *sc) 123 { 124 int error; 125 126 sc->sc_idma_xferlen = 0x1000; 127 128 sc->sc_idma_ndesc = DWC_MMC_NDESC; 129 sc->sc_idma_size = sizeof(struct dwc_mmc_idma_desc) * 130 sc->sc_idma_ndesc; 131 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 8, 132 sc->sc_idma_size, sc->sc_idma_segs, 1, 133 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 134 if (error) 135 return error; 136 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 137 sc->sc_idma_nsegs, sc->sc_idma_size, 138 &sc->sc_idma_desc, BUS_DMA_WAITOK); 139 if (error) 140 goto free; 141 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 142 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 143 if (error) 144 goto unmap; 145 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 146 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 147 if (error) 148 goto destroy; 149 return 0; 150 151 destroy: 152 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 153 unmap: 154 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 155 free: 156 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 157 return error; 158 } 159 160 static void 161 dwc_mmc_attach_i(device_t self) 162 { 163 struct dwc_mmc_softc *sc = device_private(self); 164 struct sdmmcbus_attach_args saa; 165 166 if (sc->sc_pre_power_on) 167 sc->sc_pre_power_on(sc); 168 169 dwc_mmc_signal_voltage(sc, SDMMC_SIGNAL_VOLTAGE_330); 170 dwc_mmc_host_reset(sc); 171 dwc_mmc_bus_width(sc, 1); 172 173 if (sc->sc_post_power_on) 174 sc->sc_post_power_on(sc); 175 176 memset(&saa, 0, sizeof(saa)); 177 saa.saa_busname = "sdmmc"; 178 saa.saa_sct = &dwc_mmc_chip_functions; 179 saa.saa_sch = sc; 180 saa.saa_clkmin = 400; 181 saa.saa_clkmax = sc->sc_clock_freq / 1000; 182 saa.saa_dmat = sc->sc_dmat; 183 saa.saa_caps = SMC_CAPS_SD_HIGHSPEED | 184 SMC_CAPS_MMC_HIGHSPEED | 185 SMC_CAPS_AUTO_STOP | 186 SMC_CAPS_DMA | 187 SMC_CAPS_MULTI_SEG_DMA; 188 if (sc->sc_bus_width == 8) 189 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 190 else 191 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 192 if (sc->sc_card_detect) 193 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 194 195 sc->sc_sdmmc_dev = config_found(self, &saa, NULL, CFARGS_NONE); 196 } 197 198 static void 199 dwc_mmc_led(struct dwc_mmc_softc *sc, int on) 200 { 201 if (sc->sc_set_led) 202 sc->sc_set_led(sc, on); 203 } 204 205 static int 206 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 207 { 208 struct dwc_mmc_softc *sc = sch; 209 uint32_t fifoth, ctrl; 210 int retry = 1000; 211 212 #ifdef DWC_MMC_DEBUG 213 aprint_normal_dev(sc->sc_dev, "host reset\n"); 214 #endif 215 216 if (ISSET(sc->sc_flags, DWC_MMC_F_PWREN_INV)) 217 MMC_WRITE(sc, DWC_MMC_PWREN, 0); 218 else 219 MMC_WRITE(sc, DWC_MMC_PWREN, 1); 220 221 ctrl = MMC_READ(sc, DWC_MMC_GCTRL); 222 ctrl &= ~DWC_MMC_GCTRL_USE_INTERNAL_DMAC; 223 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl); 224 225 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET); 226 227 MMC_WRITE(sc, DWC_MMC_GCTRL, 228 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_RESET); 229 while (--retry > 0) { 230 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET)) 231 break; 232 delay(100); 233 } 234 235 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 236 237 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff); 238 239 MMC_WRITE(sc, DWC_MMC_IMASK, 0); 240 241 MMC_WRITE(sc, DWC_MMC_RINT, 0xffffffff); 242 243 const uint32_t rx_wmark = (sc->sc_fifo_depth / 2) - 1; 244 const uint32_t tx_wmark = sc->sc_fifo_depth / 2; 245 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 246 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 247 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 248 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 249 MMC_WRITE(sc, DWC_MMC_FIFOTH, fifoth); 250 251 MMC_WRITE(sc, DWC_MMC_UHS, 0); 252 253 ctrl = MMC_READ(sc, DWC_MMC_GCTRL); 254 ctrl |= DWC_MMC_GCTRL_INTEN; 255 ctrl |= DWC_MMC_GCTRL_DMAEN; 256 ctrl |= DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD; 257 ctrl |= DWC_MMC_GCTRL_USE_INTERNAL_DMAC; 258 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl); 259 260 return 0; 261 } 262 263 static uint32_t 264 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 265 { 266 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 267 } 268 269 static int 270 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 271 { 272 return 32768; 273 } 274 275 static int 276 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 277 { 278 struct dwc_mmc_softc *sc = sch; 279 280 if (!sc->sc_card_detect) 281 return 1; /* no card detect pin, assume present */ 282 283 return sc->sc_card_detect(sc); 284 } 285 286 static int 287 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 288 { 289 struct dwc_mmc_softc *sc = sch; 290 291 if (!sc->sc_write_protect) 292 return 0; /* no write protect pin, assume rw */ 293 294 return sc->sc_write_protect(sc); 295 } 296 297 static int 298 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 299 { 300 struct dwc_mmc_softc *sc = sch; 301 302 if (ocr == 0) 303 sc->sc_card_inited = false; 304 305 return 0; 306 } 307 308 static int 309 dwc_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 310 { 311 struct dwc_mmc_softc *sc = sch; 312 313 if (sc->sc_signal_voltage == NULL) 314 return 0; 315 316 return sc->sc_signal_voltage(sc, signal_voltage); 317 } 318 319 static int 320 dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 321 { 322 uint32_t cmd; 323 int retry; 324 325 #ifdef DWC_MMC_DEBUG 326 aprint_normal_dev(sc->sc_dev, "update clock\n"); 327 #endif 328 329 cmd = DWC_MMC_CMD_START | 330 DWC_MMC_CMD_UPCLK_ONLY | 331 DWC_MMC_CMD_WAIT_PRE_OVER; 332 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 333 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 334 MMC_WRITE(sc, DWC_MMC_ARG, 0); 335 MMC_WRITE(sc, DWC_MMC_CMD, cmd); 336 retry = 200000; 337 while (--retry > 0) { 338 if (!(MMC_READ(sc, DWC_MMC_CMD) & DWC_MMC_CMD_START)) 339 break; 340 delay(10); 341 } 342 343 if (retry == 0) { 344 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 345 #ifdef DWC_MMC_DEBUG 346 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 347 MMC_READ(sc, DWC_MMC_GCTRL)); 348 device_printf(sc->sc_dev, "CLKENA: 0x%08x\n", 349 MMC_READ(sc, DWC_MMC_CLKENA)); 350 device_printf(sc->sc_dev, "CLKDIV: 0x%08x\n", 351 MMC_READ(sc, DWC_MMC_CLKDIV)); 352 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 353 MMC_READ(sc, DWC_MMC_TIMEOUT)); 354 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 355 MMC_READ(sc, DWC_MMC_WIDTH)); 356 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 357 MMC_READ(sc, DWC_MMC_CMD)); 358 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 359 MMC_READ(sc, DWC_MMC_MINT)); 360 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 361 MMC_READ(sc, DWC_MMC_RINT)); 362 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 363 MMC_READ(sc, DWC_MMC_STATUS)); 364 #endif 365 return ETIMEDOUT; 366 } 367 368 return 0; 369 } 370 371 static int 372 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 373 { 374 const u_int pll_freq = sc->sc_clock_freq / 1000; 375 u_int clk_div, ciu_div; 376 377 ciu_div = sc->sc_ciu_div > 0 ? sc->sc_ciu_div : 1; 378 379 if (freq != pll_freq) 380 clk_div = howmany(pll_freq, freq * ciu_div); 381 else 382 clk_div = 0; 383 384 MMC_WRITE(sc, DWC_MMC_CLKDIV, clk_div); 385 386 return dwc_mmc_update_clock(sc); 387 } 388 389 static int 390 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 391 { 392 struct dwc_mmc_softc *sc = sch; 393 uint32_t clkena; 394 395 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0); 396 MMC_WRITE(sc, DWC_MMC_CLKENA, 0); 397 if (dwc_mmc_update_clock(sc) != 0) 398 return 1; 399 400 if (freq) { 401 if (sc->sc_bus_clock && sc->sc_bus_clock(sc, freq) != 0) 402 return 1; 403 404 if (dwc_mmc_set_clock(sc, freq) != 0) 405 return 1; 406 407 clkena = DWC_MMC_CLKENA_CARDCLKON; 408 MMC_WRITE(sc, DWC_MMC_CLKENA, clkena); 409 if (dwc_mmc_update_clock(sc) != 0) 410 return 1; 411 } 412 413 delay(1000); 414 415 return 0; 416 } 417 418 static int 419 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 420 { 421 struct dwc_mmc_softc *sc = sch; 422 423 #ifdef DWC_MMC_DEBUG 424 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 425 #endif 426 427 switch (width) { 428 case 1: 429 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_1); 430 break; 431 case 4: 432 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_4); 433 break; 434 case 8: 435 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_8); 436 break; 437 default: 438 return 1; 439 } 440 441 sc->sc_mmc_width = width; 442 443 return 0; 444 } 445 446 static int 447 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 448 { 449 return -1; 450 } 451 452 static int 453 dwc_mmc_dma_prepare(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 454 { 455 struct dwc_mmc_idma_desc *dma = sc->sc_idma_desc; 456 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 457 bus_dmamap_t map; 458 bus_size_t off; 459 int desc, resid, seg; 460 uint32_t val; 461 462 /* 463 * If the command includs a dma map use it, otherwise we need to 464 * bounce. This can happen for SDIO IO_RW_EXTENDED (CMD53) commands. 465 */ 466 if (cmd->c_dmamap) { 467 map = cmd->c_dmamap; 468 } else { 469 if (cmd->c_datalen > sc->sc_dmabounce_buflen) 470 return E2BIG; 471 map = sc->sc_dmabounce_map; 472 473 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 474 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen); 475 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 476 0, cmd->c_datalen, BUS_DMASYNC_PREREAD); 477 } else { 478 memcpy(sc->sc_dmabounce_buf, cmd->c_data, 479 cmd->c_datalen); 480 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 481 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE); 482 } 483 } 484 485 desc = 0; 486 for (seg = 0; seg < map->dm_nsegs; seg++) { 487 bus_addr_t paddr = map->dm_segs[seg].ds_addr; 488 bus_size_t len = map->dm_segs[seg].ds_len; 489 resid = uimin(len, cmd->c_resid); 490 off = 0; 491 while (resid > 0) { 492 if (desc == sc->sc_idma_ndesc) 493 break; 494 len = uimin(sc->sc_idma_xferlen, resid); 495 dma[desc].dma_buf_size = htole32(len); 496 dma[desc].dma_buf_addr = htole32(paddr + off); 497 dma[desc].dma_config = htole32( 498 DWC_MMC_IDMA_CONFIG_CH | 499 DWC_MMC_IDMA_CONFIG_OWN); 500 cmd->c_resid -= len; 501 resid -= len; 502 off += len; 503 if (desc == 0) { 504 dma[desc].dma_config |= htole32( 505 DWC_MMC_IDMA_CONFIG_FD); 506 } 507 if (cmd->c_resid == 0) { 508 dma[desc].dma_config |= htole32( 509 DWC_MMC_IDMA_CONFIG_LD); 510 dma[desc].dma_config |= htole32( 511 DWC_MMC_IDMA_CONFIG_ER); 512 dma[desc].dma_next = 0; 513 } else { 514 dma[desc].dma_config |= 515 htole32(DWC_MMC_IDMA_CONFIG_DIC); 516 dma[desc].dma_next = htole32( 517 desc_paddr + ((desc+1) * 518 sizeof(struct dwc_mmc_idma_desc))); 519 } 520 ++desc; 521 } 522 } 523 if (desc == sc->sc_idma_ndesc) { 524 aprint_error_dev(sc->sc_dev, 525 "not enough descriptors for %d byte transfer!\n", 526 cmd->c_datalen); 527 return EIO; 528 } 529 530 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 531 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 532 533 MMC_WRITE(sc, DWC_MMC_DLBA, desc_paddr); 534 535 val = MMC_READ(sc, DWC_MMC_GCTRL); 536 val |= DWC_MMC_GCTRL_DMAEN; 537 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 538 val |= DWC_MMC_GCTRL_DMARESET; 539 MMC_WRITE(sc, DWC_MMC_GCTRL, val); 540 541 if (cmd->c_flags & SCF_CMD_READ) 542 val = DWC_MMC_IDST_RECEIVE_INT; 543 else 544 val = 0; 545 MMC_WRITE(sc, DWC_MMC_IDIE, val); 546 MMC_WRITE(sc, DWC_MMC_DMAC, 547 DWC_MMC_DMAC_IDMA_ON|DWC_MMC_DMAC_FIX_BURST); 548 549 return 0; 550 } 551 552 static void 553 dwc_mmc_dma_complete(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 554 { 555 MMC_WRITE(sc, DWC_MMC_DMAC, 0); 556 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 557 558 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 559 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 560 561 if (cmd->c_dmamap == NULL) { 562 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 563 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 564 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD); 565 memcpy(cmd->c_data, sc->sc_dmabounce_buf, 566 cmd->c_datalen); 567 } else { 568 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 569 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 570 } 571 } 572 } 573 574 static void 575 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 576 { 577 struct dwc_mmc_softc *sc = sch; 578 uint32_t cmdval = DWC_MMC_CMD_START; 579 int retry, error; 580 uint32_t imask; 581 u_int reg; 582 583 #ifdef DWC_MMC_DEBUG 584 aprint_normal_dev(sc->sc_dev, 585 "opcode %d flags 0x%x data %p datalen %d blklen %d\n", 586 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 587 cmd->c_blklen); 588 #endif 589 590 mutex_enter(&sc->sc_lock); 591 if (sc->sc_curcmd != NULL) { 592 device_printf(sc->sc_dev, 593 "WARNING: driver submitted a command while the controller was busy\n"); 594 cmd->c_error = EBUSY; 595 SET(cmd->c_flags, SCF_ITSDONE); 596 mutex_exit(&sc->sc_lock); 597 return; 598 } 599 sc->sc_curcmd = cmd; 600 601 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff); 602 603 if (!sc->sc_card_inited) { 604 cmdval |= DWC_MMC_CMD_SEND_INIT_SEQ; 605 sc->sc_card_inited = true; 606 } 607 608 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG)) 609 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 610 611 switch (cmd->c_opcode) { 612 case SD_IO_RW_DIRECT: 613 reg = (cmd->c_arg >> SD_ARG_CMD52_REG_SHIFT) & 614 SD_ARG_CMD52_REG_MASK; 615 if (reg != 0x6) /* func abort / card reset */ 616 break; 617 /* FALLTHROUGH */ 618 case MMC_GO_IDLE_STATE: 619 case MMC_STOP_TRANSMISSION: 620 case MMC_INACTIVE_STATE: 621 cmdval |= DWC_MMC_CMD_STOP_ABORT_CMD; 622 break; 623 } 624 625 if (cmd->c_flags & SCF_RSP_PRESENT) 626 cmdval |= DWC_MMC_CMD_RSP_EXP; 627 if (cmd->c_flags & SCF_RSP_136) 628 cmdval |= DWC_MMC_CMD_LONG_RSP; 629 if (cmd->c_flags & SCF_RSP_CRC) 630 cmdval |= DWC_MMC_CMD_CHECK_RSP_CRC; 631 632 imask = DWC_MMC_INT_ERROR | DWC_MMC_INT_CMD_DONE; 633 634 if (cmd->c_datalen > 0) { 635 unsigned int nblks; 636 637 MMC_WRITE(sc, DWC_MMC_GCTRL, 638 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_FIFORESET); 639 for (retry = 0; retry < 100000; retry++) { 640 if (!(MMC_READ(sc, DWC_MMC_DMAC) & DWC_MMC_DMAC_SOFTRESET)) 641 break; 642 delay(1); 643 } 644 645 cmdval |= DWC_MMC_CMD_DATA_EXP | DWC_MMC_CMD_WAIT_PRE_OVER; 646 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 647 cmdval |= DWC_MMC_CMD_WRITE; 648 } 649 650 nblks = cmd->c_datalen / cmd->c_blklen; 651 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 652 ++nblks; 653 654 if (nblks > 1 && cmd->c_opcode != SD_IO_RW_EXTENDED) { 655 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 656 imask |= DWC_MMC_INT_AUTO_CMD_DONE; 657 } else { 658 imask |= DWC_MMC_INT_DATA_OVER; 659 } 660 661 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff); 662 MMC_WRITE(sc, DWC_MMC_BLKSZ, cmd->c_blklen); 663 MMC_WRITE(sc, DWC_MMC_BYTECNT, 664 nblks > 1 ? nblks * cmd->c_blklen : cmd->c_datalen); 665 666 #if 0 667 /* 668 * The following doesn't work on the 250a verid IP in Odroid-XU4. 669 * 670 * thrctl should only be used for UHS/HS200 and faster timings on 671 * >=240a 672 */ 673 674 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 675 MMC_WRITE(sc, DWC_MMC_CARDTHRCTL, 676 __SHIFTIN(cmd->c_blklen, DWC_MMC_CARDTHRCTL_RDTHR) | 677 DWC_MMC_CARDTHRCTL_RDTHREN); 678 } 679 #endif 680 } 681 682 MMC_WRITE(sc, DWC_MMC_IMASK, imask | sc->sc_intr_card); 683 MMC_WRITE(sc, DWC_MMC_RINT, 0x7fff); 684 685 MMC_WRITE(sc, DWC_MMC_ARG, cmd->c_arg); 686 687 #ifdef DWC_MMC_DEBUG 688 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 689 #endif 690 691 cmd->c_resid = cmd->c_datalen; 692 if (cmd->c_datalen > 0) { 693 dwc_mmc_led(sc, 0); 694 cmd->c_error = dwc_mmc_dma_prepare(sc, cmd); 695 if (cmd->c_error != 0) { 696 SET(cmd->c_flags, SCF_ITSDONE); 697 goto done; 698 } 699 sc->sc_wait_dma = ISSET(cmd->c_flags, SCF_CMD_READ); 700 sc->sc_wait_data = true; 701 } else { 702 sc->sc_wait_dma = false; 703 sc->sc_wait_data = false; 704 } 705 sc->sc_wait_cmd = true; 706 707 if ((cmdval & DWC_MMC_CMD_WAIT_PRE_OVER) != 0) { 708 for (retry = 0; retry < 10000; retry++) { 709 if (!(MMC_READ(sc, DWC_MMC_STATUS) & DWC_MMC_STATUS_CARD_DATA_BUSY)) 710 break; 711 delay(1); 712 } 713 } 714 715 mutex_enter(&sc->sc_intr_lock); 716 717 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode); 718 719 if (sc->sc_wait_dma) 720 MMC_WRITE(sc, DWC_MMC_PLDMND, 1); 721 722 struct bintime timeout = { .sec = 15, .frac = 0 }; 723 const struct bintime epsilon = { .sec = 1, .frac = 0 }; 724 while (!ISSET(cmd->c_flags, SCF_ITSDONE)) { 725 error = cv_timedwaitbt(&sc->sc_intr_cv, 726 &sc->sc_intr_lock, &timeout, &epsilon); 727 if (error != 0) { 728 cmd->c_error = error; 729 SET(cmd->c_flags, SCF_ITSDONE); 730 mutex_exit(&sc->sc_intr_lock); 731 goto done; 732 } 733 } 734 735 mutex_exit(&sc->sc_intr_lock); 736 737 if (cmd->c_error == 0 && cmd->c_datalen > 0) 738 dwc_mmc_dma_complete(sc, cmd); 739 740 if (cmd->c_datalen > 0) 741 dwc_mmc_led(sc, 1); 742 743 if (cmd->c_flags & SCF_RSP_PRESENT) { 744 if (cmd->c_flags & SCF_RSP_136) { 745 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 746 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1); 747 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2); 748 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3); 749 if (cmd->c_flags & SCF_RSP_CRC) { 750 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 751 (cmd->c_resp[1] << 24); 752 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 753 (cmd->c_resp[2] << 24); 754 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 755 (cmd->c_resp[3] << 24); 756 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 757 } 758 } else { 759 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0); 760 } 761 } 762 763 done: 764 KASSERT(ISSET(cmd->c_flags, SCF_ITSDONE)); 765 MMC_WRITE(sc, DWC_MMC_IMASK, sc->sc_intr_card); 766 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 767 MMC_WRITE(sc, DWC_MMC_RINT, 0x7fff); 768 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff); 769 770 if (cmd->c_error) { 771 #ifdef DWC_MMC_DEBUG 772 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 773 #endif 774 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET); 775 for (retry = 0; retry < 100; retry++) { 776 if (!(MMC_READ(sc, DWC_MMC_DMAC) & DWC_MMC_DMAC_SOFTRESET)) 777 break; 778 kpause("dwcmmcrst", false, uimax(mstohz(1), 1), &sc->sc_lock); 779 } 780 } 781 782 sc->sc_curcmd = NULL; 783 mutex_exit(&sc->sc_lock); 784 } 785 786 static void 787 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 788 { 789 struct dwc_mmc_softc *sc = sch; 790 uint32_t imask; 791 792 mutex_enter(&sc->sc_intr_lock); 793 imask = MMC_READ(sc, DWC_MMC_IMASK); 794 if (enable) 795 imask |= sc->sc_intr_cardmask; 796 else 797 imask &= ~sc->sc_intr_cardmask; 798 sc->sc_intr_card = imask & sc->sc_intr_cardmask; 799 MMC_WRITE(sc, DWC_MMC_IMASK, imask); 800 mutex_exit(&sc->sc_intr_lock); 801 } 802 803 static void 804 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 805 { 806 struct dwc_mmc_softc *sc = sch; 807 uint32_t imask; 808 809 mutex_enter(&sc->sc_intr_lock); 810 imask = MMC_READ(sc, DWC_MMC_IMASK); 811 MMC_WRITE(sc, DWC_MMC_IMASK, imask | sc->sc_intr_card); 812 mutex_exit(&sc->sc_intr_lock); 813 } 814 815 int 816 dwc_mmc_init(struct dwc_mmc_softc *sc) 817 { 818 uint32_t val; 819 820 val = MMC_READ(sc, DWC_MMC_VERID); 821 sc->sc_verid = __SHIFTOUT(val, DWC_MMC_VERID_ID); 822 823 if (sc->sc_fifo_reg == 0) { 824 if (sc->sc_verid < DWC_MMC_VERID_240A) 825 sc->sc_fifo_reg = 0x100; 826 else 827 sc->sc_fifo_reg = 0x200; 828 } 829 830 if (sc->sc_fifo_depth == 0) { 831 val = MMC_READ(sc, DWC_MMC_FIFOTH); 832 sc->sc_fifo_depth = __SHIFTOUT(val, DWC_MMC_FIFOTH_RX_WMARK) + 1; 833 } 834 835 if (sc->sc_intr_cardmask == 0) 836 sc->sc_intr_cardmask = DWC_MMC_INT_SDIO_INT(0); 837 838 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 839 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 840 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 841 842 if (dwc_mmc_dmabounce_setup(sc) != 0 || 843 dwc_mmc_idma_setup(sc) != 0) { 844 aprint_error_dev(sc->sc_dev, "failed to setup DMA\n"); 845 return ENOMEM; 846 } 847 848 config_interrupts(sc->sc_dev, dwc_mmc_attach_i); 849 850 return 0; 851 } 852 853 int 854 dwc_mmc_intr(void *priv) 855 { 856 struct dwc_mmc_softc *sc = priv; 857 struct sdmmc_command *cmd; 858 uint32_t idst, mint, imask; 859 860 mutex_enter(&sc->sc_intr_lock); 861 idst = MMC_READ(sc, DWC_MMC_IDST); 862 mint = MMC_READ(sc, DWC_MMC_MINT); 863 if (!idst && !mint) { 864 mutex_exit(&sc->sc_intr_lock); 865 return 0; 866 } 867 MMC_WRITE(sc, DWC_MMC_IDST, idst); 868 MMC_WRITE(sc, DWC_MMC_RINT, mint); 869 870 cmd = sc->sc_curcmd; 871 872 #ifdef DWC_MMC_DEBUG 873 device_printf(sc->sc_dev, "mmc intr idst=%08X mint=%08X\n", 874 idst, mint); 875 #endif 876 877 /* Handle SDIO card interrupt */ 878 if ((mint & sc->sc_intr_cardmask) != 0) { 879 imask = MMC_READ(sc, DWC_MMC_IMASK); 880 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~sc->sc_intr_cardmask); 881 sdmmc_card_intr(sc->sc_sdmmc_dev); 882 } 883 884 /* Error interrupts take priority over command and transfer interrupts */ 885 if (cmd != NULL && (mint & DWC_MMC_INT_ERROR) != 0) { 886 imask = MMC_READ(sc, DWC_MMC_IMASK); 887 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_ERROR); 888 if ((mint & DWC_MMC_INT_RESP_TIMEOUT) != 0) { 889 cmd->c_error = ETIMEDOUT; 890 /* Wait for command to complete */ 891 sc->sc_wait_data = sc->sc_wait_dma = false; 892 if (cmd->c_opcode != SD_IO_SEND_OP_COND && 893 cmd->c_opcode != SD_IO_RW_DIRECT && 894 !ISSET(cmd->c_flags, SCF_TOUT_OK)) 895 device_printf(sc->sc_dev, "host controller timeout, mint=0x%08x\n", mint); 896 } else { 897 device_printf(sc->sc_dev, "host controller error, mint=0x%08x\n", mint); 898 cmd->c_error = EIO; 899 SET(cmd->c_flags, SCF_ITSDONE); 900 goto done; 901 } 902 } 903 904 if (cmd != NULL && (idst & DWC_MMC_IDST_RECEIVE_INT) != 0) { 905 MMC_WRITE(sc, DWC_MMC_IDIE, 0); 906 if (sc->sc_wait_dma == false) 907 device_printf(sc->sc_dev, "unexpected DMA receive interrupt\n"); 908 sc->sc_wait_dma = false; 909 } 910 911 if (cmd != NULL && (mint & DWC_MMC_INT_CMD_DONE) != 0) { 912 imask = MMC_READ(sc, DWC_MMC_IMASK); 913 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_CMD_DONE); 914 if (sc->sc_wait_cmd == false) 915 device_printf(sc->sc_dev, "unexpected command complete interrupt\n"); 916 sc->sc_wait_cmd = false; 917 } 918 919 const uint32_t dmadone_mask = DWC_MMC_INT_AUTO_CMD_DONE|DWC_MMC_INT_DATA_OVER; 920 if (cmd != NULL && (mint & dmadone_mask) != 0) { 921 imask = MMC_READ(sc, DWC_MMC_IMASK); 922 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~dmadone_mask); 923 if (sc->sc_wait_data == false) 924 device_printf(sc->sc_dev, "unexpected data complete interrupt\n"); 925 sc->sc_wait_data = false; 926 } 927 928 if (cmd != NULL && 929 sc->sc_wait_dma == false && 930 sc->sc_wait_cmd == false && 931 sc->sc_wait_data == false) { 932 SET(cmd->c_flags, SCF_ITSDONE); 933 } 934 935 done: 936 if (cmd != NULL && ISSET(cmd->c_flags, SCF_ITSDONE)) { 937 cv_broadcast(&sc->sc_intr_cv); 938 } 939 940 mutex_exit(&sc->sc_intr_lock); 941 942 return 1; 943 } 944
Indexes created Thu Sep 25 16:09:42 GMT 2025