dwc_mmc.c revision 1.6.2.4
1 /* $NetBSD: dwc_mmc.c,v 1.6.2.4 2016/03/19 11:30:09 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_dwc_mmc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.6.2.4 2016/03/19 11:30:09 skrll Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/sdmmc/sdmmcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmc_ioreg.h> 44 45 #include <dev/ic/dwc_mmc_reg.h> 46 #include <dev/ic/dwc_mmc_var.h> 47 48 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 49 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 50 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 51 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 52 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 53 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 54 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 55 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 56 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 57 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 58 struct sdmmc_command *); 59 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 60 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 61 62 static int dwc_mmc_set_clock(struct dwc_mmc_softc *, u_int); 63 static int dwc_mmc_update_clock(struct dwc_mmc_softc *); 64 static int dwc_mmc_wait_rint(struct dwc_mmc_softc *, uint32_t, int); 65 static int dwc_mmc_pio_wait(struct dwc_mmc_softc *, 66 struct sdmmc_command *); 67 static int dwc_mmc_pio_transfer(struct dwc_mmc_softc *, 68 struct sdmmc_command *); 69 70 #ifdef DWC_MMC_DEBUG 71 static void dwc_mmc_print_rint(struct dwc_mmc_softc *, const char *, 72 uint32_t); 73 #endif 74 75 void dwc_mmc_dump_regs(int); 76 77 static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 78 .host_reset = dwc_mmc_host_reset, 79 .host_ocr = dwc_mmc_host_ocr, 80 .host_maxblklen = dwc_mmc_host_maxblklen, 81 .card_detect = dwc_mmc_card_detect, 82 .write_protect = dwc_mmc_write_protect, 83 .bus_power = dwc_mmc_bus_power, 84 .bus_clock = dwc_mmc_bus_clock, 85 .bus_width = dwc_mmc_bus_width, 86 .bus_rod = dwc_mmc_bus_rod, 87 .exec_command = dwc_mmc_exec_command, 88 .card_enable_intr = dwc_mmc_card_enable_intr, 89 .card_intr_ack = dwc_mmc_card_intr_ack, 90 }; 91 92 #define MMC_WRITE(sc, reg, val) \ 93 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 94 #define MMC_READ(sc, reg) \ 95 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 96 97 void 98 dwc_mmc_init(struct dwc_mmc_softc *sc) 99 { 100 struct sdmmcbus_attach_args saa; 101 102 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 103 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 104 105 #ifdef DWC_MMC_DEBUG 106 const uint32_t verid = MMC_READ(sc, DWC_MMC_VERID_REG); 107 aprint_normal_dev(sc->sc_dev, "version 0x%04x\n", verid & 0xffff); 108 #endif 109 110 dwc_mmc_host_reset(sc); 111 dwc_mmc_bus_width(sc, 1); 112 113 memset(&saa, 0, sizeof(saa)); 114 saa.saa_busname = "sdmmc"; 115 saa.saa_sct = &dwc_mmc_chip_functions; 116 saa.saa_sch = sc; 117 saa.saa_clkmin = 400; 118 if (sc->sc_clock_max) { 119 saa.saa_clkmax = sc->sc_clock_max; 120 } else { 121 saa.saa_clkmax = sc->sc_clock_freq / 1000; 122 } 123 saa.saa_caps = SMC_CAPS_4BIT_MODE| 124 SMC_CAPS_8BIT_MODE| 125 SMC_CAPS_SD_HIGHSPEED| 126 SMC_CAPS_MMC_HIGHSPEED| 127 SMC_CAPS_AUTO_STOP; 128 129 #if notyet 130 saa.saa_dmat = sc->sc_dmat; 131 saa.saa_caps |= SMC_CAPS_DMA| 132 SMC_CAPS_MULTI_SEG_DMA; 133 #endif 134 135 sc->sc_sdmmc_dev = config_found(sc->sc_dev, &saa, NULL); 136 } 137 138 int 139 dwc_mmc_intr(void *priv) 140 { 141 struct dwc_mmc_softc *sc = priv; 142 uint32_t mint, rint; 143 144 mutex_enter(&sc->sc_intr_lock); 145 rint = MMC_READ(sc, DWC_MMC_RINTSTS_REG); 146 mint = MMC_READ(sc, DWC_MMC_MINTSTS_REG); 147 if (!rint && !mint) { 148 mutex_exit(&sc->sc_intr_lock); 149 return 0; 150 } 151 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, rint); 152 MMC_WRITE(sc, DWC_MMC_MINTSTS_REG, mint); 153 154 #ifdef DWC_MMC_DEBUG 155 dwc_mmc_print_rint(sc, "irq", rint); 156 #endif 157 158 if (rint & DWC_MMC_INT_CARDDET) { 159 rint &= ~DWC_MMC_INT_CARDDET; 160 if (sc->sc_sdmmc_dev) { 161 sdmmc_needs_discover(sc->sc_sdmmc_dev); 162 } 163 } 164 165 if (rint) { 166 sc->sc_intr_rint |= rint; 167 cv_broadcast(&sc->sc_intr_cv); 168 } 169 170 mutex_exit(&sc->sc_intr_lock); 171 172 return 1; 173 } 174 175 static int 176 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 177 { 178 const u_int pll_freq = sc->sc_clock_freq / 1000; 179 const u_int clk_div = howmany(pll_freq, freq * 2); 180 181 #ifdef DWC_MMC_DEBUG 182 printf("%s: using clk_div %d for freq %d (act %u)\n", 183 __func__, clk_div, freq, pll_freq / (clk_div * 2)); 184 #endif 185 186 MMC_WRITE(sc, DWC_MMC_CLKDIV_REG, 187 __SHIFTIN(clk_div, DWC_MMC_CLKDIV_CLK_DIVIDER0)); 188 MMC_WRITE(sc, DWC_MMC_CLKSRC_REG, 0); /* clock divider 0 */ 189 190 return dwc_mmc_update_clock(sc); 191 } 192 193 static int 194 dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 195 { 196 uint32_t cmd; 197 int retry; 198 199 cmd = DWC_MMC_CMD_START_CMD | 200 DWC_MMC_CMD_UPDATE_CLOCK_REGS_ONLY | 201 DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE; 202 203 if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG) 204 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 205 206 MMC_WRITE(sc, DWC_MMC_CMD_REG, cmd); 207 retry = 0xfffff; 208 while (--retry > 0) { 209 cmd = MMC_READ(sc, DWC_MMC_CMD_REG); 210 if ((cmd & DWC_MMC_CMD_START_CMD) == 0) 211 break; 212 delay(10); 213 } 214 215 if (retry == 0) { 216 device_printf(sc->sc_dev, "timeout updating clock\n"); 217 return ETIMEDOUT; 218 } 219 220 return 0; 221 } 222 223 static int 224 dwc_mmc_wait_rint(struct dwc_mmc_softc *sc, uint32_t mask, int timeout) 225 { 226 int retry, error; 227 228 KASSERT(mutex_owned(&sc->sc_intr_lock)); 229 230 if (sc->sc_intr_rint & mask) 231 return 0; 232 233 retry = timeout / hz; 234 235 while (retry > 0) { 236 error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, hz); 237 if (error && error != EWOULDBLOCK) 238 return error; 239 if (sc->sc_intr_rint & mask) 240 return 0; 241 --retry; 242 } 243 244 return ETIMEDOUT; 245 } 246 247 static int 248 dwc_mmc_pio_wait(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 249 { 250 int retry = 0xfffff; 251 uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ? 252 DWC_MMC_STATUS_FIFO_EMPTY : DWC_MMC_STATUS_FIFO_FULL; 253 254 while (--retry > 0) { 255 uint32_t status = MMC_READ(sc, DWC_MMC_STATUS_REG); 256 if (!(status & bit)) 257 return 0; 258 delay(10); 259 } 260 261 #ifdef DWC_MMC_DEBUG 262 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 263 #endif 264 265 return ETIMEDOUT; 266 } 267 268 static int 269 dwc_mmc_pio_transfer(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 270 { 271 uint32_t *datap = (uint32_t *)cmd->c_data; 272 int i; 273 274 for (i = 0; i < (cmd->c_resid >> 2); i++) { 275 if (dwc_mmc_pio_wait(sc, cmd)) 276 return ETIMEDOUT; 277 if (cmd->c_flags & SCF_CMD_READ) { 278 datap[i] = MMC_READ(sc, DWC_MMC_FIFO_BASE_REG); 279 } else { 280 MMC_WRITE(sc, DWC_MMC_FIFO_BASE_REG, datap[i]); 281 } 282 } 283 284 return 0; 285 } 286 287 static int 288 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 289 { 290 struct dwc_mmc_softc *sc = sch; 291 int retry = 1000; 292 uint32_t ctrl, fifoth; 293 uint32_t rx_wmark, tx_wmark; 294 295 if (sc->sc_flags & DWC_MMC_F_PWREN_CLEAR) { 296 MMC_WRITE(sc, DWC_MMC_PWREN_REG, 0); 297 } else { 298 MMC_WRITE(sc, DWC_MMC_PWREN_REG, DWC_MMC_PWREN_POWER_ENABLE); 299 } 300 301 MMC_WRITE(sc, DWC_MMC_CTRL_REG, DWC_MMC_CTRL_RESET_ALL); 302 while (--retry > 0) { 303 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 304 if ((ctrl & DWC_MMC_CTRL_RESET_ALL) == 0) 305 break; 306 delay(100); 307 } 308 309 MMC_WRITE(sc, DWC_MMC_CLKSRC_REG, 0); 310 311 MMC_WRITE(sc, DWC_MMC_TMOUT_REG, 0xffffff40); 312 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, 0xffffffff); 313 314 MMC_WRITE(sc, DWC_MMC_INTMASK_REG, 315 DWC_MMC_INT_CD | DWC_MMC_INT_ACD | DWC_MMC_INT_DTO | 316 DWC_MMC_INT_ERROR | DWC_MMC_INT_CARDDET | 317 DWC_MMC_INT_RXDR | DWC_MMC_INT_TXDR); 318 319 rx_wmark = (sc->sc_fifo_depth / 2) - 1; 320 tx_wmark = sc->sc_fifo_depth / 2; 321 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 322 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 323 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 324 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 325 MMC_WRITE(sc, DWC_MMC_FIFOTH_REG, fifoth); 326 327 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 328 ctrl |= DWC_MMC_CTRL_INT_ENABLE; 329 MMC_WRITE(sc, DWC_MMC_CTRL_REG, ctrl); 330 331 return 0; 332 } 333 334 static uint32_t 335 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 336 { 337 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 338 } 339 340 static int 341 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 342 { 343 return 32768; 344 } 345 346 static int 347 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 348 { 349 struct dwc_mmc_softc *sc = sch; 350 uint32_t cdetect; 351 352 if (sc->sc_flags & DWC_MMC_F_BROKEN_CD) { 353 return 1; 354 } else if (sc->sc_card_detect) { 355 return sc->sc_card_detect(sc); 356 } else { 357 cdetect = MMC_READ(sc, DWC_MMC_CDETECT_REG); 358 return !(cdetect & DWC_MMC_CDETECT_CARD_DETECT_N); 359 } 360 } 361 362 static int 363 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 364 { 365 struct dwc_mmc_softc *sc = sch; 366 uint32_t wrtprt; 367 368 wrtprt = MMC_READ(sc, DWC_MMC_WRTPRT_REG); 369 return !!(wrtprt & DWC_MMC_WRTPRT_WRITE_PROTECT); 370 } 371 372 static int 373 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 374 { 375 return 0; 376 } 377 378 static int 379 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 380 { 381 struct dwc_mmc_softc *sc = sch; 382 uint32_t clkena; 383 384 #ifdef DWC_MMC_DEBUG 385 device_printf(sc->sc_dev, "%s: freq %d\n", __func__, freq); 386 #endif 387 388 MMC_WRITE(sc, DWC_MMC_CLKENA_REG, 0); 389 if (dwc_mmc_update_clock(sc) != 0) 390 return ETIMEDOUT; 391 392 if (freq) { 393 if (dwc_mmc_set_clock(sc, freq) != 0) 394 return EIO; 395 396 clkena = DWC_MMC_CLKENA_CCLK_ENABLE; 397 clkena |= DWC_MMC_CLKENA_CCLK_LOW_POWER; /* XXX SD/MMC only */ 398 MMC_WRITE(sc, DWC_MMC_CLKENA_REG, clkena); 399 if (dwc_mmc_update_clock(sc) != 0) 400 return ETIMEDOUT; 401 } 402 403 delay(1000); 404 405 sc->sc_cur_freq = freq; 406 407 return 0; 408 } 409 410 static int 411 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 412 { 413 struct dwc_mmc_softc *sc = sch; 414 uint32_t ctype; 415 416 switch (width) { 417 case 1: 418 ctype = DWC_MMC_CTYPE_CARD_WIDTH_1; 419 break; 420 case 4: 421 ctype = DWC_MMC_CTYPE_CARD_WIDTH_4; 422 break; 423 case 8: 424 ctype = DWC_MMC_CTYPE_CARD_WIDTH_8; 425 break; 426 default: 427 return EINVAL; 428 } 429 430 MMC_WRITE(sc, DWC_MMC_CTYPE_REG, ctype); 431 432 return 0; 433 } 434 435 static int 436 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 437 { 438 return ENOTSUP; 439 } 440 441 static void 442 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 443 { 444 struct dwc_mmc_softc *sc = sch; 445 uint32_t cmdval = DWC_MMC_CMD_START_CMD; 446 uint32_t ctrl; 447 448 #ifdef DWC_MMC_DEBUG 449 device_printf(sc->sc_dev, "exec opcode=%d flags=%#x\n", 450 cmd->c_opcode, cmd->c_flags); 451 #endif 452 453 if (sc->sc_flags & DWC_MMC_F_FORCE_CLK) { 454 cmd->c_error = dwc_mmc_bus_clock(sc, sc->sc_cur_freq); 455 if (cmd->c_error) 456 return; 457 } 458 459 if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG) 460 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 461 462 mutex_enter(&sc->sc_intr_lock); 463 464 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, 0xffffffff); 465 466 if (cmd->c_opcode == 0) 467 cmdval |= DWC_MMC_CMD_SEND_INIT; 468 if (cmd->c_flags & SCF_RSP_PRESENT) 469 cmdval |= DWC_MMC_CMD_RESP_EXPECTED; 470 if (cmd->c_flags & SCF_RSP_136) 471 cmdval |= DWC_MMC_CMD_RESP_LEN; 472 if (cmd->c_flags & SCF_RSP_CRC) 473 cmdval |= DWC_MMC_CMD_CHECK_RESP_CRC; 474 475 if (cmd->c_datalen > 0) { 476 unsigned int nblks; 477 478 cmdval |= DWC_MMC_CMD_DATA_EXPECTED; 479 cmdval |= DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE; 480 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 481 cmdval |= DWC_MMC_CMD_WR; 482 } 483 484 nblks = cmd->c_datalen / cmd->c_blklen; 485 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 486 ++nblks; 487 488 if (nblks > 1) { 489 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 490 } 491 492 MMC_WRITE(sc, DWC_MMC_BLKSIZ_REG, cmd->c_blklen); 493 MMC_WRITE(sc, DWC_MMC_BYTCNT_REG, nblks * cmd->c_blklen); 494 } 495 496 sc->sc_intr_rint = 0; 497 498 MMC_WRITE(sc, DWC_MMC_CMDARG_REG, cmd->c_arg); 499 500 cmd->c_resid = cmd->c_datalen; 501 MMC_WRITE(sc, DWC_MMC_CMD_REG, cmdval | cmd->c_opcode); 502 503 cmd->c_error = dwc_mmc_wait_rint(sc, 504 DWC_MMC_INT_ERROR|DWC_MMC_INT_CD, hz * 5); 505 if (cmd->c_error == 0 && (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 506 #ifdef DWC_MMC_DEBUG 507 dwc_mmc_print_rint(sc, "exec1", sc->sc_intr_rint); 508 #endif 509 if (sc->sc_intr_rint & DWC_MMC_INT_RTO) { 510 cmd->c_error = ETIMEDOUT; 511 } else { 512 cmd->c_error = EIO; 513 } 514 } 515 if (cmd->c_error) { 516 goto done; 517 } 518 519 if (cmd->c_datalen > 0) { 520 cmd->c_error = dwc_mmc_pio_transfer(sc, cmd); 521 if (cmd->c_error) { 522 goto done; 523 } 524 525 cmd->c_error = dwc_mmc_wait_rint(sc, 526 DWC_MMC_INT_ERROR|DWC_MMC_INT_ACD|DWC_MMC_INT_DTO, 527 hz * 5); 528 if (cmd->c_error == 0 && 529 (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 530 #ifdef DWC_MMC_DEBUG 531 dwc_mmc_print_rint(sc, "exec2", sc->sc_intr_rint); 532 #endif 533 cmd->c_error = ETIMEDOUT; 534 } 535 if (cmd->c_error) { 536 goto done; 537 } 538 } 539 540 if (cmd->c_flags & SCF_RSP_PRESENT) { 541 if (cmd->c_flags & SCF_RSP_136) { 542 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0_REG); 543 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1_REG); 544 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2_REG); 545 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3_REG); 546 if (cmd->c_flags & SCF_RSP_CRC) { 547 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 548 (cmd->c_resp[1] << 24); 549 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 550 (cmd->c_resp[2] << 24); 551 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 552 (cmd->c_resp[3] << 24); 553 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 554 } 555 } else { 556 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0_REG); 557 } 558 } 559 560 done: 561 cmd->c_flags |= SCF_ITSDONE; 562 mutex_exit(&sc->sc_intr_lock); 563 564 if (cmd->c_error == ETIMEDOUT && !ISSET(cmd->c_flags, SCF_TOUT_OK)) { 565 device_printf(sc->sc_dev, "Device timeout!\n"); 566 dwc_mmc_dump_regs(device_unit(sc->sc_dev)); 567 } 568 569 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 570 ctrl |= DWC_MMC_CTRL_FIFO_RESET; 571 MMC_WRITE(sc, DWC_MMC_CTRL_REG, ctrl); 572 } 573 574 static void 575 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 576 { 577 } 578 579 static void 580 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 581 { 582 } 583 584 #ifdef DWC_MMC_DEBUG 585 static void 586 dwc_mmc_print_rint(struct dwc_mmc_softc *sc, const char *tag, uint32_t rint) 587 { 588 char buf[128]; 589 snprintb(buf, sizeof(buf), DWC_MMC_INT_BITS, rint); 590 device_printf(sc->sc_dev, "[%s] rint %s\n", tag, buf); 591 } 592 #endif 593 594 void 595 dwc_mmc_dump_regs(int unit) 596 { 597 static const struct { 598 const char *name; 599 unsigned int reg; 600 } regs[] = { 601 { "CTRL", DWC_MMC_CTRL_REG }, 602 { "PWREN", DWC_MMC_PWREN_REG }, 603 { "CLKDIV", DWC_MMC_CLKDIV_REG }, 604 { "CLKENA", DWC_MMC_CLKENA_REG }, 605 { "TMOUT", DWC_MMC_TMOUT_REG }, 606 { "CTYPE", DWC_MMC_CTYPE_REG }, 607 { "BLKSIZ", DWC_MMC_BLKSIZ_REG }, 608 { "BYTCNT", DWC_MMC_BYTCNT_REG }, 609 { "INTMASK", DWC_MMC_INTMASK_REG }, 610 { "MINTSTS", DWC_MMC_MINTSTS_REG }, 611 { "RINTSTS", DWC_MMC_RINTSTS_REG }, 612 { "STATUS", DWC_MMC_STATUS_REG }, 613 { "CDETECT", DWC_MMC_CDETECT_REG }, 614 { "WRTPRT", DWC_MMC_WRTPRT_REG }, 615 { "USRID", DWC_MMC_USRID_REG }, 616 { "VERID", DWC_MMC_VERID_REG }, 617 { "RST", DWC_MMC_RST_REG }, 618 { "BACK_END_POWER", DWC_MMC_BACK_END_POWER_REG }, 619 }; 620 device_t self = device_find_by_driver_unit("dwcmmc", unit); 621 if (self == NULL) 622 return; 623 struct dwc_mmc_softc *sc = device_private(self); 624 int i; 625 626 for (i = 0; i < __arraycount(regs); i += 2) { 627 device_printf(sc->sc_dev, " %s: 0x%08x\t%s: 0x%08x\n", 628 regs[i+0].name, MMC_READ(sc, regs[i+0].reg), 629 regs[i+1].name, MMC_READ(sc, regs[i+1].reg)); 630 } 631 } 632
Indexes created Wed Oct 15 03:09:54 GMT 2025