dwc_mmc_var.h revision 1.5.10.1
1 1.5.10.1 snj /* $NetBSD: dwc_mmc_var.h,v 1.5.10.1 2017/07/18 19:13:10 snj Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /*- 4 1.5.10.1 snj * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 1.1 jmcneill * All rights reserved. 6 1.1 jmcneill * 7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without 8 1.1 jmcneill * modification, are permitted provided that the following conditions 9 1.1 jmcneill * are met: 10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright 11 1.1 jmcneill * notice, this list of conditions and the following disclaimer. 12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the 14 1.1 jmcneill * documentation and/or other materials provided with the distribution. 15 1.1 jmcneill * 16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 jmcneill * SUCH DAMAGE. 27 1.1 jmcneill */ 28 1.1 jmcneill 29 1.1 jmcneill #ifndef _DWC_MMC_VAR_H 30 1.1 jmcneill #define _DWC_MMC_VAR_H 31 1.1 jmcneill 32 1.1 jmcneill struct dwc_mmc_softc { 33 1.5.10.1 snj device_t sc_dev; 34 1.5.10.1 snj bus_space_tag_t sc_bst; 35 1.5.10.1 snj bus_space_handle_t sc_bsh; 36 1.5.10.1 snj bus_space_handle_t sc_clk_bsh; 37 1.5.10.1 snj bus_dma_tag_t sc_dmat; 38 1.5.10.1 snj 39 1.5.10.1 snj u_int sc_flags; 40 1.5.10.1 snj #define DWC_MMC_F_DMA __BIT(0) 41 1.5.10.1 snj #define DWC_MMC_F_USE_HOLD_REG __BIT(1) 42 1.5.10.1 snj uint32_t sc_fifo_reg; 43 1.5.10.1 snj uint32_t sc_fifo_depth; 44 1.5.10.1 snj u_int sc_clock_freq; 45 1.5.10.1 snj 46 1.5.10.1 snj void *sc_ih; 47 1.5.10.1 snj kmutex_t sc_intr_lock; 48 1.5.10.1 snj kcondvar_t sc_intr_cv; 49 1.5.10.1 snj kcondvar_t sc_idst_cv; 50 1.5.10.1 snj 51 1.5.10.1 snj int sc_mmc_width; 52 1.5.10.1 snj int sc_mmc_present; 53 1.5.10.1 snj int sc_mmc_port; 54 1.5.10.1 snj 55 1.5.10.1 snj device_t sc_sdmmc_dev; 56 1.5.10.1 snj 57 1.5.10.1 snj uint32_t sc_idma_xferlen; 58 1.5.10.1 snj bus_dma_segment_t sc_idma_segs[1]; 59 1.5.10.1 snj int sc_idma_nsegs; 60 1.5.10.1 snj bus_size_t sc_idma_size; 61 1.5.10.1 snj bus_dmamap_t sc_idma_map; 62 1.5.10.1 snj int sc_idma_ndesc; 63 1.5.10.1 snj void *sc_idma_desc; 64 1.5.10.1 snj 65 1.5.10.1 snj uint32_t sc_intr_rint; 66 1.5.10.1 snj uint32_t sc_intr_mint; 67 1.5.10.1 snj uint32_t sc_idma_idst; 68 1.5.10.1 snj 69 1.5.10.1 snj int (*sc_card_detect)(struct dwc_mmc_softc *); 70 1.5.10.1 snj int (*sc_write_protect)(struct dwc_mmc_softc *); 71 1.5.10.1 snj void (*sc_set_led)(struct dwc_mmc_softc *, int); 72 1.1 jmcneill }; 73 1.1 jmcneill 74 1.5.10.1 snj int dwc_mmc_init(struct dwc_mmc_softc *); 75 1.1 jmcneill int dwc_mmc_intr(void *); 76 1.1 jmcneill 77 1.1 jmcneill #endif /* !_DWC_MMC_VAR_H */ 78
Indexes created Mon Oct 13 05:10:05 GMT 2025