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dwc_mmc_var.h revision 1.2 
      1 /* $NetBSD: dwc_mmc_var.h,v 1.2 2014/12/27 19:18:04 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _DWC_MMC_VAR_H
     30 #define _DWC_MMC_VAR_H
     31 
     32 struct dwc_mmc_softc {
     33 	device_t		sc_dev;
     34 	bus_space_tag_t		sc_bst;
     35 	bus_space_handle_t	sc_bsh;
     36 	bus_dma_tag_t		sc_dmat;
     37 	void			*sc_ih;
     38 	unsigned int		sc_clock_freq;
     39 	unsigned int		sc_fifo_depth;
     40 	uint32_t		sc_flags;
     41 #define DWC_MMC_F_USE_HOLD_REG	0x0001	/* set USE_HOLD_REG with every cmd */
     42 #define DWC_MMC_F_PWREN_CLEAR	0x0002	/* clear POWER_ENABLE bit to enable */
     43 	int			(*sc_set_clkdiv)(struct dwc_mmc_softc *, int);
     44 
     45 	device_t		sc_sdmmc_dev;
     46 	kmutex_t		sc_intr_lock;
     47 	kcondvar_t		sc_intr_cv;
     48 
     49 	uint32_t		sc_intr_rint;
     50 };
     51 
     52 void	dwc_mmc_init(struct dwc_mmc_softc *);
     53 int	dwc_mmc_intr(void *);
     54 
     55 #endif /* !_DWC_MMC_VAR_H */
     56