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dwc_mmc_var.h revision 1.9 
      1 /* $NetBSD: dwc_mmc_var.h,v 1.9 2019/10/05 12:27:14 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _DWC_MMC_VAR_H
     30 #define _DWC_MMC_VAR_H
     31 
     32 struct dwc_mmc_softc {
     33 	device_t sc_dev;
     34 	bus_space_tag_t sc_bst;
     35 	bus_space_handle_t sc_bsh;
     36 	bus_space_handle_t sc_clk_bsh;
     37 	bus_dma_tag_t sc_dmat;
     38 
     39 	u_int sc_flags;
     40 #define	DWC_MMC_F_DMA		__BIT(0)
     41 #define	DWC_MMC_F_USE_HOLD_REG	__BIT(1)
     42 	uint32_t sc_fifo_reg;
     43 	uint32_t sc_fifo_depth;
     44 	u_int sc_clock_freq;
     45 
     46 	void *sc_ih;
     47 	kmutex_t sc_intr_lock;
     48 	kcondvar_t sc_intr_cv;
     49 
     50 	int sc_mmc_width;
     51 	int sc_mmc_port;
     52 
     53 	device_t sc_sdmmc_dev;
     54 
     55 	uint32_t sc_idma_xferlen;
     56 	bus_dma_segment_t sc_idma_segs[1];
     57 	int sc_idma_nsegs;
     58 	bus_size_t sc_idma_size;
     59 	bus_dmamap_t sc_idma_map;
     60 	int sc_idma_ndesc;
     61 	void *sc_idma_desc;
     62 
     63 	bus_dmamap_t sc_dmabounce_map;
     64 	void *sc_dmabounce_buf;
     65 	size_t sc_dmabounce_buflen;
     66 
     67 	uint32_t sc_intr_card;
     68 	struct sdmmc_command *sc_curcmd;
     69 	bool sc_wait_dma;
     70 	bool sc_wait_cmd;
     71 	bool sc_wait_data;
     72 
     73 	int (*sc_card_detect)(struct dwc_mmc_softc *);
     74 	int (*sc_write_protect)(struct dwc_mmc_softc *);
     75 	void (*sc_set_led)(struct dwc_mmc_softc *, int);
     76 	int (*sc_bus_clock)(struct dwc_mmc_softc *, int);
     77 };
     78 
     79 int	dwc_mmc_init(struct dwc_mmc_softc *);
     80 int	dwc_mmc_intr(void *);
     81 
     82 #endif /* !_DWC_MMC_VAR_H */
     83