elink3.c revision 1.41
1 /* $NetBSD: elink3.c,v 1.41 1998/08/12 18:51:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #define ETHER_MIN_LEN 64 124 #define ETHER_MAX_LEN 1518 125 #define ETHER_ADDR_LEN 6 126 127 #ifdef DEBUG 128 int epdebug = 0; 129 #endif 130 131 /* 132 * Structure to map media-present bits in boards to ifmedia codes and 133 * printable media names. Used for table-driven ifmedia initialization. 134 */ 135 struct ep_media { 136 int epm_mpbit; /* media present bit */ 137 const char *epm_name; /* name of medium */ 138 int epm_ifmedia; /* ifmedia word for medium */ 139 int epm_epmedia; /* EPMEDIA_* constant */ 140 }; 141 142 /* 143 * Media table for the Demon/Vortex/Boomerang chipsets. 144 * 145 * Note that MII on the Demon and Vortex (3c59x) indicates an external 146 * MII connector (for connecting an external PHY) ... I think. Treat 147 * it as `manual' on these chips. 148 * 149 * Any Boomerang (3c90x) chips with MII really do have an internal 150 * MII and real PHYs attached; no `native' media. 151 */ 152 struct ep_media ep_vortex_media[] = { 153 { EP_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 154 EPMEDIA_10BASE_T }, 155 { EP_PCI_AUI, "10base5/AUI", IFM_ETHER|IFM_10_5, 156 EPMEDIA_AUI }, 157 { EP_PCI_BNC, "10base2/BNC", IFM_ETHER|IFM_10_2, 158 EPMEDIA_10BASE_2 }, 159 { EP_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 160 EPMEDIA_100BASE_TX }, 161 { EP_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 162 EPMEDIA_100BASE_FX }, 163 { EP_PCI_100BASE_MII, "manual", IFM_ETHER|IFM_MANUAL, 164 EPMEDIA_MII }, 165 { EP_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 166 EPMEDIA_100BASE_T4 }, 167 { 0, NULL, 0, 168 0 }, 169 }; 170 171 /* 172 * Media table for the older 3Com Etherlink III chipset, used 173 * in the 3c509, 3c579, and 3c589. 174 */ 175 struct ep_media ep_509_media[] = { 176 { EP_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 177 EPMEDIA_10BASE_T }, 178 { EP_W0_CC_AUI, "10base5/AUI", IFM_ETHER|IFM_10_5, 179 EPMEDIA_AUI }, 180 { EP_W0_CC_BNC, "10base2/BNC", IFM_ETHER|IFM_10_2, 181 EPMEDIA_10BASE_2 }, 182 { 0, NULL, 0, 183 0 }, 184 }; 185 186 void ep_internalconfig __P((struct ep_softc *sc)); 187 void ep_vortex_probemedia __P((struct ep_softc *sc)); 188 void ep_509_probemedia __P((struct ep_softc *sc)); 189 190 static void eptxstat __P((struct ep_softc *)); 191 static int epstatus __P((struct ep_softc *)); 192 void epinit __P((struct ep_softc *)); 193 int epioctl __P((struct ifnet *, u_long, caddr_t)); 194 void epstart __P((struct ifnet *)); 195 void epwatchdog __P((struct ifnet *)); 196 void epreset __P((struct ep_softc *)); 197 static void epshutdown __P((void *)); 198 void epread __P((struct ep_softc *)); 199 struct mbuf *epget __P((struct ep_softc *, int)); 200 void epmbuffill __P((void *)); 201 void epmbufempty __P((struct ep_softc *)); 202 void epsetfilter __P((struct ep_softc *)); 203 void epsetmedia __P((struct ep_softc *)); 204 205 int epenable __P((struct ep_softc *)); 206 void epdisable __P((struct ep_softc *)); 207 208 /* ifmedia callbacks */ 209 int ep_media_change __P((struct ifnet *ifp)); 210 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 211 212 /* MII callbacks */ 213 int ep_mii_readreg __P((struct device *, int, int)); 214 void ep_mii_writereg __P((struct device *, int, int, int)); 215 void ep_statchg __P((struct device *)); 216 217 void ep_tick __P((void *)); 218 219 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 220 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 221 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 222 void ep_mii_sync __P((struct ep_softc *)); 223 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 224 225 static int epbusyeeprom __P((struct ep_softc *)); 226 static inline void ep_complete_cmd __P((struct ep_softc *sc, 227 u_int cmd, u_int arg)); 228 229 230 /* 231 * Issue a (reset) command, and be sure it has completed. 232 * Used for commands that reset part or all of the board. 233 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 234 * but older hardware doesn't implement it and we must delay. 235 * It's easiest to just delay always. 236 */ 237 static inline void 238 ep_complete_cmd(sc, cmd, arg) 239 struct ep_softc *sc; 240 u_int cmd, arg; 241 { 242 register bus_space_tag_t iot = sc->sc_iot; 243 register bus_space_handle_t ioh = sc->sc_ioh; 244 245 bus_space_write_2(iot, ioh, cmd, arg); 246 247 #ifdef notyet 248 /* if this adapter family has S_COMMAND_IN_PROGRESS, use it */ 249 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 250 ; 251 else 252 #else 253 DELAY(100000); /* need at least 1 ms, but be generous. */ 254 #endif 255 } 256 257 /* 258 * Back-end attach and configure. 259 */ 260 void 261 epconfig(sc, chipset, enaddr) 262 struct ep_softc *sc; 263 u_short chipset; 264 u_int8_t *enaddr; 265 { 266 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 267 bus_space_tag_t iot = sc->sc_iot; 268 bus_space_handle_t ioh = sc->sc_ioh; 269 u_int16_t i; 270 u_int8_t myla[6]; 271 272 sc->ep_chipset = chipset; 273 274 /* 275 * We could have been groveling around in other register 276 * windows in the front-end; make sure we're in window 0 277 * to read the EEPROM. 278 */ 279 GO_WINDOW(0); 280 281 if (enaddr == NULL) { 282 /* 283 * Read the station address from the eeprom 284 */ 285 for (i = 0; i < 3; i++) { 286 u_int16_t x; 287 if (epbusyeeprom(sc)) 288 return; /* XXX why is eeprom busy? */ 289 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 290 READ_EEPROM | i); 291 if (epbusyeeprom(sc)) 292 return; /* XXX why is eeprom busy? */ 293 x = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 294 myla[(i << 1)] = x >> 8; 295 myla[(i << 1) + 1] = x; 296 } 297 enaddr = myla; 298 } 299 300 /* 301 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 302 * allow FDDI-sized (4500) byte packets. Commands only take an 303 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 304 * packet length. 305 * Commands to these cards implicitly upshift a packet size 306 * or threshold by 2 bits. 307 * To detect cards with large-packet support, we probe by setting 308 * the transmit threshold register, then change windows and 309 * read back the threshold register directly, and see if the 310 * threshold value was shifted or not. 311 */ 312 bus_space_write_2(iot, ioh, EP_COMMAND, 313 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 314 GO_WINDOW(5); 315 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 316 GO_WINDOW(1); 317 switch (i) { 318 case EP_LARGEWIN_PROBE: 319 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 320 sc->ep_pktlenshift = 0; 321 break; 322 323 case (EP_LARGEWIN_PROBE << 2): 324 sc->ep_pktlenshift = 2; 325 break; 326 327 default: 328 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 329 "Interface disabled\n", 330 sc->sc_dev.dv_xname, EP_LARGEWIN_PROBE, (int) i); 331 return; 332 } 333 334 /* 335 * Ensure Tx-available interrupts are enabled for 336 * start the interface. 337 * XXX should be in epinit()? 338 */ 339 bus_space_write_2(iot, ioh, EP_COMMAND, 340 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 341 342 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 343 ifp->if_softc = sc; 344 ifp->if_start = epstart; 345 ifp->if_ioctl = epioctl; 346 ifp->if_watchdog = epwatchdog; 347 ifp->if_flags = 348 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 349 350 if_attach(ifp); 351 ether_ifattach(ifp, enaddr); 352 353 /* 354 * Finish configuration: 355 * determine chipset if the front-end couldn't do so, 356 * show board details, set media. 357 */ 358 359 /* 360 * Print RAM size. We also print the Ethernet address in here. 361 * It's extracted from the ifp, so we have to make sure it's 362 * been attached first. 363 */ 364 ep_internalconfig(sc); 365 GO_WINDOW(0); 366 367 /* 368 * Initialize our media structures and MII info. We'll 369 * probe the MII if we discover that we have one. 370 */ 371 sc->sc_mii.mii_ifp = ifp; 372 sc->sc_mii.mii_readreg = ep_mii_readreg; 373 sc->sc_mii.mii_writereg = ep_mii_writereg; 374 sc->sc_mii.mii_statchg = ep_statchg; 375 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 376 ep_media_status); 377 378 /* 379 * Now, determine which media we have. 380 */ 381 switch (sc->ep_chipset) { 382 case EP_CHIPSET_BOOMERANG: 383 /* 384 * If the device has MII, probe it. We won't be using 385 * any `native' media in this case, only PHYs. If 386 * we don't, just treat the Boomerang like the Vortex. 387 */ 388 if (sc->ep_flags & EP_FLAGS_MII) { 389 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 390 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 391 ifmedia_add(&sc->sc_mii.mii_media, 392 IFM_ETHER|IFM_NONE, 0, NULL); 393 ifmedia_set(&sc->sc_mii.mii_media, 394 IFM_ETHER|IFM_NONE); 395 } else { 396 ifmedia_set(&sc->sc_mii.mii_media, 397 IFM_ETHER|IFM_AUTO); 398 } 399 break; 400 } 401 /* FALLTHROUGH */ 402 403 case EP_CHIPSET_VORTEX: 404 ep_vortex_probemedia(sc); 405 break; 406 407 default: 408 ep_509_probemedia(sc); 409 break; 410 } 411 412 GO_WINDOW(1); /* Window 1 is operating window */ 413 414 #if NBPFILTER > 0 415 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 416 sizeof(struct ether_header)); 417 #endif 418 419 #if NRND > 0 420 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET); 421 #endif 422 423 sc->tx_start_thresh = 20; /* probably a good starting point. */ 424 425 /* Establish callback to reset card when we reboot. */ 426 shutdownhook_establish(epshutdown, sc); 427 428 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 429 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 430 } 431 432 433 /* 434 * Show interface-model-independent info from window 3 435 * internal-configuration register. 436 */ 437 void 438 ep_internalconfig(sc) 439 struct ep_softc *sc; 440 { 441 bus_space_tag_t iot = sc->sc_iot; 442 bus_space_handle_t ioh = sc->sc_ioh; 443 444 u_int config0; 445 u_int config1; 446 447 int ram_size, ram_width, ram_speed, rom_size, ram_split; 448 /* 449 * NVRAM buffer Rx:Tx config names for busmastering cards 450 * (Demon, Vortex, and later). 451 */ 452 const char *onboard_ram_config[] = { 453 "5:3", "3:1", "1:1", "3:5" }; 454 455 GO_WINDOW(3); 456 config0 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG); 457 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 458 GO_WINDOW(0); 459 460 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 461 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 462 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 463 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 464 465 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 466 467 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 468 sc->sc_dev.dv_xname, 469 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 470 8 << ram_size, 471 (ram_width) ? "word" : "byte", 472 onboard_ram_config[ram_split]); 473 } 474 475 476 /* 477 * Find supported media on 3c509-generation hardware that doesn't have 478 * a "reset_options" register in window 3. 479 * Use the config_cntrl register in window 0 instead. 480 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 481 * that implement CONFIG_CTRL. We don't have a good way to set the 482 * default active mediuim; punt to ifconfig instead. 483 */ 484 void 485 ep_509_probemedia(sc) 486 struct ep_softc *sc; 487 { 488 bus_space_tag_t iot = sc->sc_iot; 489 bus_space_handle_t ioh = sc->sc_ioh; 490 struct ifmedia *ifm = &sc->sc_mii.mii_media; 491 u_int16_t ep_w0_config, port; 492 struct ep_media *epm; 493 const char *sep = "", *defmedianame = NULL; 494 int defmedia = 0; 495 496 GO_WINDOW(0); 497 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 498 499 printf("%s: ", sc->sc_dev.dv_xname); 500 501 /* Sanity check that there are any media! */ 502 if ((ep_w0_config & EP_W0_CC_MEDIAMASK) == 0) { 503 printf("no media present!\n"); 504 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 505 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 506 return; 507 } 508 509 /* 510 * Get the default media from the EEPROM. 511 */ 512 if (epbusyeeprom(sc)) 513 return; /* XXX why is eeprom busy? */ 514 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 515 READ_EEPROM | EEPROM_ADDR_CFG); 516 if (epbusyeeprom(sc)) 517 return; /* XXX why is eeprom busy? */ 518 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA) >> 14; 519 520 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 521 522 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 523 if (ep_w0_config & epm->epm_mpbit) { 524 if (epm->epm_epmedia == port || defmedia == 0) { 525 defmedia = epm->epm_ifmedia; 526 defmedianame = epm->epm_name; 527 } 528 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 529 NULL); 530 PRINT(epm->epm_name); 531 } 532 } 533 534 #undef PRINT 535 536 #ifdef DIAGNOSTIC 537 if (defmedia == 0) 538 panic("ep_509_probemedia: impossible"); 539 #endif 540 541 printf(" (default %s)\n", defmedianame); 542 ifmedia_set(ifm, defmedia); 543 } 544 545 /* 546 * Find media present on large-packet-capable elink3 devices. 547 * Show onboard configuration of large-packet-capable elink3 devices 548 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 549 * Use media and card-version info in window 3 instead. 550 */ 551 void 552 ep_vortex_probemedia(sc) 553 struct ep_softc *sc; 554 { 555 bus_space_tag_t iot = sc->sc_iot; 556 bus_space_handle_t ioh = sc->sc_ioh; 557 struct ifmedia *ifm = &sc->sc_mii.mii_media; 558 struct ep_media *epm; 559 u_int config1; 560 int reset_options; 561 int default_media; /* 3-bit encoding of default (EEPROM) media */ 562 int defmedia = 0; 563 const char *sep = "", *defmedianame = NULL; 564 565 GO_WINDOW(3); 566 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 567 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 568 GO_WINDOW(0); 569 570 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 571 572 printf("%s: ", sc->sc_dev.dv_xname); 573 574 /* Sanity check that there are any media! */ 575 if ((reset_options & EP_PCI_MEDIAMASK) == 0) { 576 printf("no media present!\n"); 577 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 578 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 579 return; 580 } 581 582 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 583 584 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 585 if (reset_options & epm->epm_mpbit) { 586 if (epm->epm_epmedia == default_media || 587 defmedia == 0) { 588 defmedia = epm->epm_ifmedia; 589 defmedianame = epm->epm_name; 590 } 591 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 592 NULL); 593 PRINT(epm->epm_name); 594 } 595 } 596 597 #undef PRINT 598 599 #ifdef DIAGNOSTIC 600 if (defmedia == 0) 601 panic("ep_vortex_probemedia: impossible"); 602 #endif 603 604 printf(" (default %s)\n", defmedianame); 605 ifmedia_set(ifm, defmedia); 606 } 607 608 /* 609 * One second timer, used to tick the MII. 610 */ 611 void 612 ep_tick(arg) 613 void *arg; 614 { 615 struct ep_softc *sc = arg; 616 int s; 617 618 #ifdef DIAGNOSTIC 619 if ((sc->ep_flags & EP_FLAGS_MII) == 0) 620 panic("ep_tick"); 621 #endif 622 623 s = splnet(); 624 mii_tick(&sc->sc_mii); 625 splx(s); 626 627 timeout(ep_tick, sc, hz); 628 } 629 630 /* 631 * Bring device up. 632 * 633 * The order in here seems important. Otherwise we may not receive 634 * interrupts. ?! 635 */ 636 void 637 epinit(sc) 638 register struct ep_softc *sc; 639 { 640 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 641 bus_space_tag_t iot = sc->sc_iot; 642 bus_space_handle_t ioh = sc->sc_ioh; 643 int i; 644 645 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 646 ; 647 648 if (sc->bustype != EP_BUS_PCI) { 649 GO_WINDOW(0); 650 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 651 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 652 } 653 654 if (sc->bustype == EP_BUS_PCMCIA) { 655 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 656 } 657 658 GO_WINDOW(2); 659 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 660 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 661 LLADDR(ifp->if_sadl)[i]); 662 663 /* 664 * Reset the station-address receive filter. 665 * A bug workaround for busmastering (Vortex, Demon) cards. 666 */ 667 for (i = 0; i < 6; i++) 668 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 669 670 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 671 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 672 673 GO_WINDOW(1); /* Window 1 is operating window */ 674 for (i = 0; i < 31; i++) 675 bus_space_read_1(iot, ioh, EP_W1_TX_STATUS); 676 677 /* Set threshhold for for Tx-space avaiable interrupt. */ 678 bus_space_write_2(iot, ioh, EP_COMMAND, 679 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 680 681 /* Enable interrupts. */ 682 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 683 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 684 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | 685 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 686 687 /* 688 * Attempt to get rid of any stray interrupts that occured during 689 * configuration. On the i386 this isn't possible because one may 690 * already be queued. However, a single stray interrupt is 691 * unimportant. 692 */ 693 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 694 695 epsetfilter(sc); 696 epsetmedia(sc); 697 698 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 699 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 700 701 epmbuffill(sc); 702 703 /* Interface is now `running', with no output active. */ 704 ifp->if_flags |= IFF_RUNNING; 705 ifp->if_flags &= ~IFF_OACTIVE; 706 707 if (sc->ep_flags & EP_FLAGS_MII) { 708 /* Start the one second clock. */ 709 timeout(ep_tick, sc, hz); 710 } 711 712 /* Attempt to start output, if any. */ 713 epstart(ifp); 714 } 715 716 717 /* 718 * Set multicast receive filter. 719 * elink3 hardware has no selective multicast filter in hardware. 720 * Enable reception of all multicasts and filter in software. 721 */ 722 void 723 epsetfilter(sc) 724 register struct ep_softc *sc; 725 { 726 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 727 728 GO_WINDOW(1); /* Window 1 is operating window */ 729 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 730 FIL_INDIVIDUAL | FIL_BRDCST | 731 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 732 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 733 } 734 735 int 736 ep_media_change(ifp) 737 struct ifnet *ifp; 738 { 739 register struct ep_softc *sc = ifp->if_softc; 740 741 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 742 epreset(sc); 743 744 return (0); 745 } 746 747 /* 748 * Set the card to use the specified media. 749 */ 750 void 751 epsetmedia(sc) 752 struct ep_softc *sc; 753 { 754 bus_space_tag_t iot = sc->sc_iot; 755 bus_space_handle_t ioh = sc->sc_ioh; 756 757 /* Turn everything off. First turn off linkbeat and UTP. */ 758 GO_WINDOW(4); 759 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 0x0); 760 761 /* Turn off coax */ 762 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 763 delay(1000); 764 765 /* 766 * If the device has MII, select it, and then tell the 767 * PHY which media to use. 768 */ 769 if (sc->ep_flags & EP_FLAGS_MII) { 770 int config0, config1; 771 772 GO_WINDOW(3); 773 config0 = (u_int)bus_space_read_2(iot, ioh, 774 EP_W3_INTERNAL_CONFIG); 775 config1 = (u_int)bus_space_read_2(iot, ioh, 776 EP_W3_INTERNAL_CONFIG + 2); 777 778 config1 = config1 & ~CONFIG_MEDIAMASK; 779 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 780 781 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 782 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 783 GO_WINDOW(1); /* back to operating window */ 784 785 mii_mediachg(&sc->sc_mii); 786 return; 787 } 788 789 /* 790 * Now turn on the selected media/transceiver. 791 */ 792 GO_WINDOW(4); 793 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 794 case IFM_10_T: 795 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 796 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 797 break; 798 799 case IFM_10_2: 800 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 801 DELAY(1000); /* 50ms not enmough? */ 802 break; 803 804 case IFM_100_TX: 805 case IFM_100_FX: 806 case IFM_100_T4: /* XXX check documentation */ 807 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 808 LINKBEAT_ENABLE); 809 DELAY(1000); /* not strictly necessary? */ 810 break; 811 812 case IFM_10_5: 813 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 814 SQE_ENABLE); 815 DELAY(1000); /* not strictly necessary? */ 816 break; 817 818 case IFM_MANUAL: 819 /* 820 * Nothing to do here; we are actually enabling the 821 * external PHY on the MII port. 822 */ 823 break; 824 825 case IFM_NONE: 826 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 827 return; 828 829 default: 830 panic("epsetmedia: impossible"); 831 } 832 833 /* 834 * Tell the chip which port to use. 835 */ 836 switch (sc->ep_chipset) { 837 case EP_CHIPSET_VORTEX: 838 case EP_CHIPSET_BOOMERANG: 839 { 840 int config0, config1; 841 842 GO_WINDOW(3); 843 config0 = (u_int)bus_space_read_2(iot, ioh, 844 EP_W3_INTERNAL_CONFIG); 845 config1 = (u_int)bus_space_read_2(iot, ioh, 846 EP_W3_INTERNAL_CONFIG + 2); 847 848 config1 = config1 & ~CONFIG_MEDIAMASK; 849 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 850 CONFIG_MEDIAMASK_SHIFT); 851 852 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 853 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 854 break; 855 } 856 default: 857 { 858 int w0_addr_cfg; 859 860 GO_WINDOW(0); 861 w0_addr_cfg = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 862 w0_addr_cfg &= 0x3fff; 863 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, w0_addr_cfg | 864 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 865 DELAY(1000); 866 break; 867 } 868 } 869 870 GO_WINDOW(1); /* Window 1 is operating window */ 871 } 872 873 /* 874 * Get currently-selected media from card. 875 * (if_media callback, may be called before interface is brought up). 876 */ 877 void 878 ep_media_status(ifp, req) 879 struct ifnet *ifp; 880 struct ifmediareq *req; 881 { 882 register struct ep_softc *sc = ifp->if_softc; 883 bus_space_tag_t iot = sc->sc_iot; 884 bus_space_handle_t ioh = sc->sc_ioh; 885 886 if (sc->enabled == 0) { 887 req->ifm_active = IFM_ETHER|IFM_NONE; 888 req->ifm_status = 0; 889 return; 890 } 891 892 /* 893 * If we have MII, go ask the PHY what's going on. 894 */ 895 if (sc->ep_flags & EP_FLAGS_MII) { 896 mii_pollstat(&sc->sc_mii); 897 req->ifm_active = sc->sc_mii.mii_media_active; 898 req->ifm_status = sc->sc_mii.mii_media_status; 899 return; 900 } 901 902 /* 903 * Ok, at this point we claim that our active media is 904 * the currently selected media. We'll update our status 905 * if our chipset allows us to detect link. 906 */ 907 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 908 req->ifm_status = 0; 909 910 switch (sc->ep_chipset) { 911 case EP_CHIPSET_VORTEX: 912 case EP_CHIPSET_BOOMERANG: 913 GO_WINDOW(4); 914 req->ifm_status = IFM_AVALID; 915 if (bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE) & 916 LINKBEAT_DETECT) 917 req->ifm_status |= IFM_ACTIVE; 918 GO_WINDOW(1); /* back to operating window */ 919 break; 920 } 921 } 922 923 924 925 /* 926 * Start outputting on the interface. 927 * Always called as splnet(). 928 */ 929 void 930 epstart(ifp) 931 struct ifnet *ifp; 932 { 933 register struct ep_softc *sc = ifp->if_softc; 934 bus_space_tag_t iot = sc->sc_iot; 935 bus_space_handle_t ioh = sc->sc_ioh; 936 struct mbuf *m, *m0; 937 int sh, len, pad; 938 939 /* Don't transmit if interface is busy or not running */ 940 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 941 return; 942 943 startagain: 944 /* Sneak a peek at the next packet */ 945 m0 = ifp->if_snd.ifq_head; 946 if (m0 == 0) 947 return; 948 949 /* We need to use m->m_pkthdr.len, so require the header */ 950 if ((m0->m_flags & M_PKTHDR) == 0) 951 panic("epstart: no header mbuf"); 952 len = m0->m_pkthdr.len; 953 954 pad = (4 - len) & 3; 955 956 /* 957 * The 3c509 automatically pads short packets to minimum ethernet 958 * length, but we drop packets that are too large. Perhaps we should 959 * truncate them instead? 960 */ 961 if (len + pad > ETHER_MAX_LEN) { 962 /* packet is obviously too large: toss it */ 963 ++ifp->if_oerrors; 964 IF_DEQUEUE(&ifp->if_snd, m0); 965 m_freem(m0); 966 goto readcheck; 967 } 968 969 if (bus_space_read_2(iot, ioh, EP_W1_FREE_TX) < len + pad + 4) { 970 bus_space_write_2(iot, ioh, EP_COMMAND, 971 SET_TX_AVAIL_THRESH | 972 ((len + pad + 4) >> sc->ep_pktlenshift)); 973 /* not enough room in FIFO */ 974 ifp->if_flags |= IFF_OACTIVE; 975 return; 976 } else { 977 bus_space_write_2(iot, ioh, EP_COMMAND, 978 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE ); 979 } 980 981 IF_DEQUEUE(&ifp->if_snd, m0); 982 if (m0 == 0) /* not really needed */ 983 return; 984 985 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 986 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/) ); 987 988 #if NBPFILTER > 0 989 if (ifp->if_bpf) 990 bpf_mtap(ifp->if_bpf, m0); 991 #endif 992 993 /* 994 * Do the output at splhigh() so that an interrupt from another device 995 * won't cause a FIFO underrun. 996 */ 997 sh = splhigh(); 998 999 bus_space_write_2(iot, ioh, EP_W1_TX_PIO_WR_1, len); 1000 bus_space_write_2(iot, ioh, EP_W1_TX_PIO_WR_1, 1001 0xffff); /* Second dword meaningless */ 1002 if (EP_IS_BUS_32(sc->bustype)) { 1003 for (m = m0; m; ) { 1004 if (m->m_len > 3) { 1005 /* align our reads from core */ 1006 if (mtod(m, u_long) & 3) { 1007 u_long count = 1008 4 - (mtod(m, u_long) & 3); 1009 bus_space_write_multi_1(iot, ioh, 1010 EP_W1_TX_PIO_WR_1, 1011 mtod(m, u_int8_t *), count); 1012 m->m_data = 1013 (void *)(mtod(m, u_long) + count); 1014 m->m_len -= count; 1015 } 1016 bus_space_write_multi_4(iot, ioh, 1017 EP_W1_TX_PIO_WR_1, 1018 mtod(m, u_int32_t *), m->m_len >> 2); 1019 m->m_data = (void *)(mtod(m, u_long) + 1020 (u_long)(m->m_len & ~3)); 1021 m->m_len -= m->m_len & ~3; 1022 } 1023 if (m->m_len) { 1024 bus_space_write_multi_1(iot, ioh, 1025 EP_W1_TX_PIO_WR_1, 1026 mtod(m, u_int8_t *), m->m_len); 1027 } 1028 MFREE(m, m0); 1029 m = m0; 1030 } 1031 } else { 1032 for (m = m0; m; ) { 1033 if (m->m_len > 1) { 1034 if (mtod(m, u_long) & 1) { 1035 bus_space_write_1(iot, ioh, 1036 EP_W1_TX_PIO_WR_1, 1037 *(mtod(m, u_int8_t *))); 1038 m->m_data = 1039 (void *)(mtod(m, u_long) + 1); 1040 m->m_len -= 1; 1041 } 1042 bus_space_write_multi_2(iot, ioh, 1043 EP_W1_TX_PIO_WR_1, mtod(m, u_int16_t *), 1044 m->m_len >> 1); 1045 } 1046 if (m->m_len & 1) { 1047 bus_space_write_1(iot, ioh, EP_W1_TX_PIO_WR_1, 1048 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1049 } 1050 MFREE(m, m0); 1051 m = m0; 1052 } 1053 } 1054 while (pad--) 1055 bus_space_write_1(iot, ioh, EP_W1_TX_PIO_WR_1, 0); 1056 1057 splx(sh); 1058 1059 ++ifp->if_opackets; 1060 1061 readcheck: 1062 if ((bus_space_read_2(iot, ioh, EP_W1_RX_STATUS) & ERR_INCOMPLETE) == 0) { 1063 /* We received a complete packet. */ 1064 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1065 1066 if ((status & S_INTR_LATCH) == 0) { 1067 /* 1068 * No interrupt, read the packet and continue 1069 * Is this supposed to happen? Is my motherboard 1070 * completely busted? 1071 */ 1072 epread(sc); 1073 } else { 1074 /* Got an interrupt, return so that it gets serviced. */ 1075 return; 1076 } 1077 } else { 1078 /* Check if we are stuck and reset [see XXX comment] */ 1079 if (epstatus(sc)) { 1080 if (ifp->if_flags & IFF_DEBUG) 1081 printf("%s: adapter reset\n", 1082 sc->sc_dev.dv_xname); 1083 epreset(sc); 1084 } 1085 } 1086 1087 goto startagain; 1088 } 1089 1090 1091 /* 1092 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1093 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1094 * We detect this situation and we reset the adapter. 1095 * It happens at times when there is a lot of broadcast traffic 1096 * on the cable (once in a blue moon). 1097 */ 1098 static int 1099 epstatus(sc) 1100 register struct ep_softc *sc; 1101 { 1102 bus_space_tag_t iot = sc->sc_iot; 1103 bus_space_handle_t ioh = sc->sc_ioh; 1104 u_int16_t fifost; 1105 1106 /* 1107 * Check the FIFO status and act accordingly 1108 */ 1109 GO_WINDOW(4); 1110 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1111 GO_WINDOW(1); 1112 1113 if (fifost & FIFOS_RX_UNDERRUN) { 1114 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1115 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1116 epreset(sc); 1117 return 0; 1118 } 1119 1120 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1121 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1122 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1123 return 1; 1124 } 1125 1126 if (fifost & FIFOS_RX_OVERRUN) { 1127 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1128 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1129 return 1; 1130 } 1131 1132 if (fifost & FIFOS_TX_OVERRUN) { 1133 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1134 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1135 epreset(sc); 1136 return 0; 1137 } 1138 1139 return 0; 1140 } 1141 1142 1143 static void 1144 eptxstat(sc) 1145 register struct ep_softc *sc; 1146 { 1147 bus_space_tag_t iot = sc->sc_iot; 1148 bus_space_handle_t ioh = sc->sc_ioh; 1149 int i; 1150 1151 /* 1152 * We need to read+write TX_STATUS until we get a 0 status 1153 * in order to turn off the interrupt flag. 1154 */ 1155 while ((i = bus_space_read_1(iot, ioh, EP_W1_TX_STATUS)) & TXS_COMPLETE) { 1156 bus_space_write_1(iot, ioh, EP_W1_TX_STATUS, 0x0); 1157 1158 if (i & TXS_JABBER) { 1159 ++sc->sc_ethercom.ec_if.if_oerrors; 1160 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1161 printf("%s: jabber (%x)\n", 1162 sc->sc_dev.dv_xname, i); 1163 epreset(sc); 1164 } else if (i & TXS_UNDERRUN) { 1165 ++sc->sc_ethercom.ec_if.if_oerrors; 1166 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1167 printf("%s: fifo underrun (%x) @%d\n", 1168 sc->sc_dev.dv_xname, i, 1169 sc->tx_start_thresh); 1170 if (sc->tx_succ_ok < 100) 1171 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1172 sc->tx_start_thresh + 20); 1173 sc->tx_succ_ok = 0; 1174 epreset(sc); 1175 } else if (i & TXS_MAX_COLLISION) { 1176 ++sc->sc_ethercom.ec_if.if_collisions; 1177 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1178 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1179 } else 1180 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1181 } 1182 } 1183 1184 int 1185 epintr(arg) 1186 void *arg; 1187 { 1188 register struct ep_softc *sc = arg; 1189 bus_space_tag_t iot = sc->sc_iot; 1190 bus_space_handle_t ioh = sc->sc_ioh; 1191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1192 u_int16_t status; 1193 int ret = 0; 1194 int addrandom = 0; 1195 1196 if (sc->enabled == 0) 1197 return (0); 1198 1199 for (;;) { 1200 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1201 1202 status = bus_space_read_2(iot, ioh, EP_STATUS); 1203 1204 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1205 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1206 if ((status & S_INTR_LATCH) == 0) { 1207 #if 0 1208 printf("%s: intr latch cleared\n", 1209 sc->sc_dev.dv_xname); 1210 #endif 1211 break; 1212 } 1213 } 1214 1215 ret = 1; 1216 1217 /* 1218 * Acknowledge any interrupts. It's important that we do this 1219 * first, since there would otherwise be a race condition. 1220 * Due to the i386 interrupt queueing, we may get spurious 1221 * interrupts occasionally. 1222 */ 1223 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 1224 (status & (C_INTR_LATCH | 1225 C_CARD_FAILURE | 1226 C_TX_COMPLETE | 1227 C_TX_AVAIL | 1228 C_RX_COMPLETE | 1229 C_RX_EARLY | 1230 C_INT_RQD | 1231 C_UPD_STATS))); 1232 1233 #if 0 1234 status = bus_space_read_2(iot, ioh, EP_STATUS); 1235 1236 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1237 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1238 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1239 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1240 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1241 #endif 1242 1243 if (status & S_RX_COMPLETE) { 1244 epread(sc); 1245 addrandom = 1; 1246 } 1247 if (status & S_TX_AVAIL) { 1248 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1249 epstart(&sc->sc_ethercom.ec_if); 1250 addrandom = 1; 1251 } 1252 if (status & S_CARD_FAILURE) { 1253 printf("%s: adapter failure (%x)\n", 1254 sc->sc_dev.dv_xname, status); 1255 epreset(sc); 1256 return (1); 1257 } 1258 if (status & S_TX_COMPLETE) { 1259 eptxstat(sc); 1260 epstart(ifp); 1261 addrandom = 1; 1262 } 1263 1264 #if NRND > 0 1265 if (status) 1266 rnd_add_uint32(&sc->rnd_source, status); 1267 #endif 1268 } 1269 1270 /* no more interrupts */ 1271 return (ret); 1272 } 1273 1274 void 1275 epread(sc) 1276 register struct ep_softc *sc; 1277 { 1278 bus_space_tag_t iot = sc->sc_iot; 1279 bus_space_handle_t ioh = sc->sc_ioh; 1280 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1281 struct mbuf *m; 1282 struct ether_header *eh; 1283 int len; 1284 1285 len = bus_space_read_2(iot, ioh, EP_W1_RX_STATUS); 1286 1287 again: 1288 if (ifp->if_flags & IFF_DEBUG) { 1289 int err = len & ERR_MASK; 1290 char *s = NULL; 1291 1292 if (len & ERR_INCOMPLETE) 1293 s = "incomplete packet"; 1294 else if (err == ERR_OVERRUN) 1295 s = "packet overrun"; 1296 else if (err == ERR_RUNT) 1297 s = "runt packet"; 1298 else if (err == ERR_ALIGNMENT) 1299 s = "bad alignment"; 1300 else if (err == ERR_CRC) 1301 s = "bad crc"; 1302 else if (err == ERR_OVERSIZE) 1303 s = "oversized packet"; 1304 else if (err == ERR_DRIBBLE) 1305 s = "dribble bits"; 1306 1307 if (s) 1308 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1309 } 1310 1311 if (len & ERR_INCOMPLETE) 1312 return; 1313 1314 if (len & ERR_RX) { 1315 ++ifp->if_ierrors; 1316 goto abort; 1317 } 1318 1319 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1320 1321 /* Pull packet off interface. */ 1322 m = epget(sc, len); 1323 if (m == 0) { 1324 ifp->if_ierrors++; 1325 goto abort; 1326 } 1327 1328 ++ifp->if_ipackets; 1329 1330 /* We assume the header fit entirely in one mbuf. */ 1331 eh = mtod(m, struct ether_header *); 1332 1333 #if NBPFILTER > 0 1334 /* 1335 * Check if there's a BPF listener on this interface. 1336 * If so, hand off the raw packet to BPF. 1337 */ 1338 if (ifp->if_bpf) { 1339 bpf_mtap(ifp->if_bpf, m); 1340 1341 /* 1342 * Note that the interface cannot be in promiscuous mode if 1343 * there are no BPF listeners. And if we are in promiscuous 1344 * mode, we have to check if this packet is really ours. 1345 */ 1346 if ((ifp->if_flags & IFF_PROMISC) && 1347 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1348 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1349 sizeof(eh->ether_dhost)) != 0) { 1350 m_freem(m); 1351 return; 1352 } 1353 } 1354 #endif 1355 1356 /* We assume the header fit entirely in one mbuf. */ 1357 m_adj(m, sizeof(struct ether_header)); 1358 ether_input(ifp, eh, m); 1359 1360 /* 1361 * In periods of high traffic we can actually receive enough 1362 * packets so that the fifo overrun bit will be set at this point, 1363 * even though we just read a packet. In this case we 1364 * are not going to receive any more interrupts. We check for 1365 * this condition and read again until the fifo is not full. 1366 * We could simplify this test by not using epstatus(), but 1367 * rechecking the RX_STATUS register directly. This test could 1368 * result in unnecessary looping in cases where there is a new 1369 * packet but the fifo is not full, but it will not fix the 1370 * stuck behavior. 1371 * 1372 * Even with this improvement, we still get packet overrun errors 1373 * which are hurting performance. Maybe when I get some more time 1374 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1375 */ 1376 if (epstatus(sc)) { 1377 len = bus_space_read_2(iot, ioh, EP_W1_RX_STATUS); 1378 /* Check if we are stuck and reset [see XXX comment] */ 1379 if (len & ERR_INCOMPLETE) { 1380 if (ifp->if_flags & IFF_DEBUG) 1381 printf("%s: adapter reset\n", 1382 sc->sc_dev.dv_xname); 1383 epreset(sc); 1384 return; 1385 } 1386 goto again; 1387 } 1388 1389 return; 1390 1391 abort: 1392 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1393 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1394 ; 1395 } 1396 1397 struct mbuf * 1398 epget(sc, totlen) 1399 struct ep_softc *sc; 1400 int totlen; 1401 { 1402 bus_space_tag_t iot = sc->sc_iot; 1403 bus_space_handle_t ioh = sc->sc_ioh; 1404 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1405 struct mbuf *top, **mp, *m; 1406 int len, remaining; 1407 int sh; 1408 1409 m = sc->mb[sc->next_mb]; 1410 sc->mb[sc->next_mb] = 0; 1411 if (m == 0) { 1412 MGETHDR(m, M_DONTWAIT, MT_DATA); 1413 if (m == 0) 1414 return 0; 1415 } else { 1416 /* If the queue is no longer full, refill. */ 1417 if (sc->last_mb == sc->next_mb) 1418 timeout(epmbuffill, sc, 1); 1419 /* Convert one of our saved mbuf's. */ 1420 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1421 m->m_data = m->m_pktdat; 1422 m->m_flags = M_PKTHDR; 1423 } 1424 m->m_pkthdr.rcvif = ifp; 1425 m->m_pkthdr.len = totlen; 1426 len = MHLEN; 1427 top = 0; 1428 mp = ⊤ 1429 1430 /* 1431 * We read the packet at splhigh() so that an interrupt from another 1432 * device doesn't cause the card's buffer to overflow while we're 1433 * reading it. We may still lose packets at other times. 1434 */ 1435 sh = splhigh(); 1436 1437 while (totlen > 0) { 1438 if (top) { 1439 m = sc->mb[sc->next_mb]; 1440 sc->mb[sc->next_mb] = 0; 1441 if (m == 0) { 1442 MGET(m, M_DONTWAIT, MT_DATA); 1443 if (m == 0) { 1444 splx(sh); 1445 m_freem(top); 1446 return 0; 1447 } 1448 } else { 1449 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1450 } 1451 len = MLEN; 1452 } 1453 if (totlen >= MINCLSIZE) { 1454 MCLGET(m, M_DONTWAIT); 1455 if ((m->m_flags & M_EXT) == 0) { 1456 splx(sh); 1457 m_free(m); 1458 m_freem(top); 1459 return 0; 1460 } 1461 len = MCLBYTES; 1462 } 1463 if (top == 0) { 1464 /* align the struct ip header */ 1465 caddr_t newdata = (caddr_t) 1466 ALIGN(m->m_data + sizeof(struct ether_header)) 1467 - sizeof(struct ether_header); 1468 len -= newdata - m->m_data; 1469 m->m_data = newdata; 1470 } 1471 remaining = len = min(totlen, len); 1472 if (EP_IS_BUS_32(sc->bustype)) { 1473 u_long offset = mtod(m, u_long); 1474 /* 1475 * Read bytes up to the point where we are aligned. 1476 * (We can align to 4 bytes, rather than ALIGNBYTES, 1477 * here because we're later reading 4-byte chunks.) 1478 */ 1479 if ((remaining > 3) && (offset & 3)) { 1480 int count = (4 - (offset & 3)); 1481 bus_space_read_multi_1(iot, ioh, 1482 EP_W1_RX_PIO_RD_1, 1483 (u_int8_t *) offset, count); 1484 offset += count; 1485 remaining -= count; 1486 } 1487 if (remaining > 3) { 1488 bus_space_read_multi_4(iot, ioh, 1489 EP_W1_RX_PIO_RD_1, 1490 (u_int32_t *) offset, remaining >> 2); 1491 offset += remaining & ~3; 1492 remaining &= 3; 1493 } 1494 if (remaining) { 1495 bus_space_read_multi_1(iot, ioh, 1496 EP_W1_RX_PIO_RD_1, 1497 (u_int8_t *) offset, remaining); 1498 } 1499 } else { 1500 u_long offset = mtod(m, u_long); 1501 if ((remaining > 1) && (offset & 1)) { 1502 bus_space_read_multi_1(iot, ioh, 1503 EP_W1_RX_PIO_RD_1, 1504 (u_int8_t *) offset, 1); 1505 remaining -= 1; 1506 offset += 1; 1507 } 1508 if (remaining > 1) { 1509 bus_space_read_multi_2(iot, ioh, 1510 EP_W1_RX_PIO_RD_1, 1511 (u_int16_t *) offset, remaining >> 1); 1512 offset += remaining & ~1; 1513 } 1514 if (remaining & 1) { 1515 bus_space_read_multi_1(iot, ioh, 1516 EP_W1_RX_PIO_RD_1, 1517 (u_int8_t *) offset, remaining & 1); 1518 } 1519 } 1520 m->m_len = len; 1521 totlen -= len; 1522 *mp = m; 1523 mp = &m->m_next; 1524 } 1525 1526 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1527 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1528 ; 1529 1530 splx(sh); 1531 1532 return top; 1533 } 1534 1535 int 1536 epioctl(ifp, cmd, data) 1537 register struct ifnet *ifp; 1538 u_long cmd; 1539 caddr_t data; 1540 { 1541 struct ep_softc *sc = ifp->if_softc; 1542 struct ifaddr *ifa = (struct ifaddr *)data; 1543 struct ifreq *ifr = (struct ifreq *)data; 1544 int s, error = 0; 1545 1546 s = splnet(); 1547 1548 switch (cmd) { 1549 1550 case SIOCSIFADDR: 1551 if ((error = epenable(sc)) != 0) 1552 break; 1553 /* epinit is called just below */ 1554 ifp->if_flags |= IFF_UP; 1555 switch (ifa->ifa_addr->sa_family) { 1556 #ifdef INET 1557 case AF_INET: 1558 epinit(sc); 1559 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1560 break; 1561 #endif 1562 #ifdef NS 1563 case AF_NS: 1564 { 1565 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1566 1567 if (ns_nullhost(*ina)) 1568 ina->x_host = *(union ns_host *) 1569 LLADDR(ifp->if_sadl); 1570 else 1571 bcopy(ina->x_host.c_host, 1572 LLADDR(ifp->if_sadl), 1573 ifp->if_addrlen); 1574 /* Set new address. */ 1575 epinit(sc); 1576 break; 1577 } 1578 #endif 1579 default: 1580 epinit(sc); 1581 break; 1582 } 1583 break; 1584 1585 case SIOCSIFMEDIA: 1586 case SIOCGIFMEDIA: 1587 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1588 break; 1589 1590 case SIOCSIFFLAGS: 1591 if ((ifp->if_flags & IFF_UP) == 0 && 1592 (ifp->if_flags & IFF_RUNNING) != 0) { 1593 /* 1594 * If interface is marked down and it is running, then 1595 * stop it. 1596 */ 1597 epstop(sc); 1598 ifp->if_flags &= ~IFF_RUNNING; 1599 epdisable(sc); 1600 } else if ((ifp->if_flags & IFF_UP) != 0 && 1601 (ifp->if_flags & IFF_RUNNING) == 0) { 1602 /* 1603 * If interface is marked up and it is stopped, then 1604 * start it. 1605 */ 1606 if ((error = epenable(sc)) != 0) 1607 break; 1608 epinit(sc); 1609 } else if (sc->enabled) { 1610 /* 1611 * deal with flags changes: 1612 * IFF_MULTICAST, IFF_PROMISC. 1613 */ 1614 epsetfilter(sc); 1615 } 1616 break; 1617 1618 case SIOCADDMULTI: 1619 case SIOCDELMULTI: 1620 if (sc->enabled == 0) { 1621 error = EIO; 1622 break; 1623 } 1624 1625 error = (cmd == SIOCADDMULTI) ? 1626 ether_addmulti(ifr, &sc->sc_ethercom) : 1627 ether_delmulti(ifr, &sc->sc_ethercom); 1628 1629 if (error == ENETRESET) { 1630 /* 1631 * Multicast list has changed; set the hardware filter 1632 * accordingly. 1633 */ 1634 epreset(sc); 1635 error = 0; 1636 } 1637 break; 1638 1639 default: 1640 error = EINVAL; 1641 break; 1642 } 1643 1644 splx(s); 1645 return (error); 1646 } 1647 1648 void 1649 epreset(sc) 1650 struct ep_softc *sc; 1651 { 1652 int s; 1653 1654 s = splnet(); 1655 epstop(sc); 1656 epinit(sc); 1657 splx(s); 1658 } 1659 1660 void 1661 epwatchdog(ifp) 1662 struct ifnet *ifp; 1663 { 1664 struct ep_softc *sc = ifp->if_softc; 1665 1666 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1667 ++sc->sc_ethercom.ec_if.if_oerrors; 1668 1669 epreset(sc); 1670 } 1671 1672 void 1673 epstop(sc) 1674 register struct ep_softc *sc; 1675 { 1676 bus_space_tag_t iot = sc->sc_iot; 1677 bus_space_handle_t ioh = sc->sc_ioh; 1678 1679 if (sc->ep_flags & EP_FLAGS_MII) { 1680 /* Stop the one second clock. */ 1681 untimeout(ep_tick, sc); 1682 } 1683 1684 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1685 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1686 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1687 ; 1688 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1689 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1690 1691 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 1692 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 1693 1694 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1695 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1696 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1697 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1698 1699 epmbufempty(sc); 1700 } 1701 1702 1703 /* 1704 * Before reboots, reset card completely. 1705 */ 1706 static void 1707 epshutdown(arg) 1708 void *arg; 1709 { 1710 register struct ep_softc *sc = arg; 1711 1712 if (sc->enabled) { 1713 epstop(sc); 1714 ep_complete_cmd(sc, EP_COMMAND, GLOBAL_RESET); 1715 } 1716 } 1717 1718 /* 1719 * We get eeprom data from the id_port given an offset into the 1720 * eeprom. Basically; after the ID_sequence is sent to all of 1721 * the cards; they enter the ID_CMD state where they will accept 1722 * command requests. 0x80-0xbf loads the eeprom data. We then 1723 * read the port 16 times and with every read; the cards check 1724 * for contention (ie: if one card writes a 0 bit and another 1725 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1726 * each card compares the data on the bus; if there is a difference 1727 * then that card goes into ID_WAIT state again). In the meantime; 1728 * one bit of data is returned in the AX register which is conveniently 1729 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1730 * bit of data with each read. 1731 * 1732 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1733 */ 1734 u_int16_t 1735 epreadeeprom(iot, ioh, offset) 1736 bus_space_tag_t iot; 1737 bus_space_handle_t ioh; 1738 int offset; 1739 { 1740 u_int16_t data = 0; 1741 int i; 1742 1743 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1744 delay(1000); 1745 for (i = 0; i < 16; i++) 1746 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1747 return (data); 1748 } 1749 1750 static int 1751 epbusyeeprom(sc) 1752 struct ep_softc *sc; 1753 { 1754 bus_space_tag_t iot = sc->sc_iot; 1755 bus_space_handle_t ioh = sc->sc_ioh; 1756 int i = 100, j; 1757 1758 if (sc->bustype == EP_BUS_PCMCIA) { 1759 delay(1000); 1760 return 0; 1761 } 1762 1763 j = 0; /* bad GCC flow analysis */ 1764 while (i--) { 1765 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1766 if (j & EEPROM_BUSY) 1767 delay(100); 1768 else 1769 break; 1770 } 1771 if (!i) { 1772 printf("\n%s: eeprom failed to come ready\n", 1773 sc->sc_dev.dv_xname); 1774 return (1); 1775 } 1776 if (j & EEPROM_TST_MODE) { 1777 /* XXX PnP mode? */ 1778 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1779 return (1); 1780 } 1781 return (0); 1782 } 1783 1784 void 1785 epmbuffill(v) 1786 void *v; 1787 { 1788 struct ep_softc *sc = v; 1789 int s, i; 1790 1791 s = splnet(); 1792 i = sc->last_mb; 1793 do { 1794 if (sc->mb[i] == NULL) 1795 MGET(sc->mb[i], M_DONTWAIT, MT_DATA); 1796 if (sc->mb[i] == NULL) 1797 break; 1798 i = (i + 1) % MAX_MBS; 1799 } while (i != sc->next_mb); 1800 sc->last_mb = i; 1801 /* If the queue was not filled, try again. */ 1802 if (sc->last_mb != sc->next_mb) 1803 timeout(epmbuffill, sc, 1); 1804 splx(s); 1805 } 1806 1807 void 1808 epmbufempty(sc) 1809 struct ep_softc *sc; 1810 { 1811 int s, i; 1812 1813 s = splnet(); 1814 for (i = 0; i<MAX_MBS; i++) { 1815 if (sc->mb[i]) { 1816 m_freem(sc->mb[i]); 1817 sc->mb[i] = NULL; 1818 } 1819 } 1820 sc->last_mb = sc->next_mb = 0; 1821 untimeout(epmbuffill, sc); 1822 splx(s); 1823 } 1824 1825 int 1826 epenable(sc) 1827 struct ep_softc *sc; 1828 { 1829 1830 if (sc->enabled == 0 && sc->enable != NULL) { 1831 if ((*sc->enable)(sc) != 0) { 1832 printf("%s: device enable failed\n", 1833 sc->sc_dev.dv_xname); 1834 return (EIO); 1835 } 1836 } 1837 1838 sc->enabled = 1; 1839 return (0); 1840 } 1841 1842 void 1843 epdisable(sc) 1844 struct ep_softc *sc; 1845 { 1846 1847 if (sc->enabled != 0 && sc->disable != NULL) { 1848 (*sc->disable)(sc); 1849 sc->enabled = 0; 1850 } 1851 } 1852 1853 void 1854 ep_mii_setbit(sc, bit) 1855 struct ep_softc *sc; 1856 u_int16_t bit; 1857 { 1858 u_int16_t val; 1859 1860 /* We assume we're already in Window 4 */ 1861 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1862 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1863 val | bit); 1864 } 1865 1866 void 1867 ep_mii_clrbit(sc, bit) 1868 struct ep_softc *sc; 1869 u_int16_t bit; 1870 { 1871 u_int16_t val; 1872 1873 /* We assume we're already in Window 4 */ 1874 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1875 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1876 val & ~bit); 1877 } 1878 1879 u_int16_t 1880 ep_mii_readbit(sc, bit) 1881 struct ep_softc *sc; 1882 u_int16_t bit; 1883 { 1884 1885 /* We assume we're already in Window 4 */ 1886 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 1887 bit); 1888 } 1889 1890 void 1891 ep_mii_sync(sc) 1892 struct ep_softc *sc; 1893 { 1894 int i; 1895 1896 /* We assume we're already in Window 4 */ 1897 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1898 for (i = 0; i < 32; i++) { 1899 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1900 ep_mii_setbit(sc, PHYSMGMT_CLK); 1901 } 1902 } 1903 1904 void 1905 ep_mii_sendbits(sc, data, nbits) 1906 struct ep_softc *sc; 1907 u_int32_t data; 1908 int nbits; 1909 { 1910 int i; 1911 1912 /* We assume we're already in Window 4 */ 1913 ep_mii_setbit(sc, PHYSMGMT_DIR); 1914 for (i = 1 << (nbits - 1); i; i = i >> 1) { 1915 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1916 ep_mii_readbit(sc, PHYSMGMT_CLK); 1917 if (data & i) 1918 ep_mii_setbit(sc, PHYSMGMT_DATA); 1919 else 1920 ep_mii_clrbit(sc, PHYSMGMT_DATA); 1921 ep_mii_setbit(sc, PHYSMGMT_CLK); 1922 ep_mii_readbit(sc, PHYSMGMT_CLK); 1923 } 1924 } 1925 1926 int 1927 ep_mii_readreg(self, phy, reg) 1928 struct device *self; 1929 int phy, reg; 1930 { 1931 struct ep_softc *sc = (struct ep_softc *)self; 1932 int val = 0, i, err; 1933 1934 /* 1935 * Read the PHY register by manually driving the MII control lines. 1936 */ 1937 1938 GO_WINDOW(4); 1939 1940 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 1941 1942 ep_mii_sync(sc); 1943 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1944 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 1945 ep_mii_sendbits(sc, phy, 5); 1946 ep_mii_sendbits(sc, reg, 5); 1947 1948 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1949 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1950 ep_mii_setbit(sc, PHYSMGMT_CLK); 1951 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1952 1953 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 1954 ep_mii_setbit(sc, PHYSMGMT_CLK); 1955 1956 /* Even if an error occurs, must still clock out the cycle. */ 1957 for (i = 0; i < 16; i++) { 1958 val <<= 1; 1959 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1960 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 1961 val |= 1; 1962 ep_mii_setbit(sc, PHYSMGMT_CLK); 1963 } 1964 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1965 ep_mii_setbit(sc, PHYSMGMT_CLK); 1966 1967 GO_WINDOW(1); /* back to operating window */ 1968 1969 return (err ? 0 : val); 1970 } 1971 1972 void 1973 ep_mii_writereg(self, phy, reg, val) 1974 struct device *self; 1975 int phy, reg, val; 1976 { 1977 struct ep_softc *sc = (struct ep_softc *)self; 1978 1979 /* 1980 * Write the PHY register by manually driving the MII control lines. 1981 */ 1982 1983 GO_WINDOW(4); 1984 1985 ep_mii_sync(sc); 1986 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1987 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 1988 ep_mii_sendbits(sc, phy, 5); 1989 ep_mii_sendbits(sc, reg, 5); 1990 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 1991 ep_mii_sendbits(sc, val, 16); 1992 1993 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1994 ep_mii_setbit(sc, PHYSMGMT_CLK); 1995 1996 GO_WINDOW(1); /* back to operating window */ 1997 } 1998 1999 void 2000 ep_statchg(self) 2001 struct device *self; 2002 { 2003 2004 /* XXX Update ifp->if_baudrate */ 2005 /* XXX Full-duplex control in MAC? */ 2006 } 2007
Indexes created Thu Sep 25 16:09:42 GMT 2025