elink3.c revision 1.43
1 /* $NetBSD: elink3.c,v 1.43 1998/08/16 01:16:57 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #define ETHER_MIN_LEN 64 124 #define ETHER_MAX_LEN 1518 125 #define ETHER_ADDR_LEN 6 126 127 #ifdef DEBUG 128 int epdebug = 0; 129 #endif 130 131 /* 132 * Structure to map media-present bits in boards to ifmedia codes and 133 * printable media names. Used for table-driven ifmedia initialization. 134 */ 135 struct ep_media { 136 int epm_mpbit; /* media present bit */ 137 const char *epm_name; /* name of medium */ 138 int epm_ifmedia; /* ifmedia word for medium */ 139 int epm_epmedia; /* EPMEDIA_* constant */ 140 }; 141 142 /* 143 * Media table for the Demon/Vortex/Boomerang chipsets. 144 * 145 * Note that MII on the Demon and Vortex (3c59x) indicates an external 146 * MII connector (for connecting an external PHY) ... I think. Treat 147 * it as `manual' on these chips. 148 * 149 * Any Boomerang (3c90x) chips with MII really do have an internal 150 * MII and real PHYs attached; no `native' media. 151 */ 152 struct ep_media ep_vortex_media[] = { 153 { EP_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 154 EPMEDIA_10BASE_T }, 155 { EP_PCI_AUI, "10base5/AUI", IFM_ETHER|IFM_10_5, 156 EPMEDIA_AUI }, 157 { EP_PCI_BNC, "10base2/BNC", IFM_ETHER|IFM_10_2, 158 EPMEDIA_10BASE_2 }, 159 { EP_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 160 EPMEDIA_100BASE_TX }, 161 { EP_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 162 EPMEDIA_100BASE_FX }, 163 { EP_PCI_100BASE_MII, "manual", IFM_ETHER|IFM_MANUAL, 164 EPMEDIA_MII }, 165 { EP_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 166 EPMEDIA_100BASE_T4 }, 167 { 0, NULL, 0, 168 0 }, 169 }; 170 171 /* 172 * Media table for the older 3Com Etherlink III chipset, used 173 * in the 3c509, 3c579, and 3c589. 174 */ 175 struct ep_media ep_509_media[] = { 176 { EP_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 177 EPMEDIA_10BASE_T }, 178 { EP_W0_CC_AUI, "10base5/AUI", IFM_ETHER|IFM_10_5, 179 EPMEDIA_AUI }, 180 { EP_W0_CC_BNC, "10base2/BNC", IFM_ETHER|IFM_10_2, 181 EPMEDIA_10BASE_2 }, 182 { 0, NULL, 0, 183 0 }, 184 }; 185 186 void ep_internalconfig __P((struct ep_softc *sc)); 187 void ep_vortex_probemedia __P((struct ep_softc *sc)); 188 void ep_509_probemedia __P((struct ep_softc *sc)); 189 190 static void eptxstat __P((struct ep_softc *)); 191 static int epstatus __P((struct ep_softc *)); 192 void epinit __P((struct ep_softc *)); 193 int epioctl __P((struct ifnet *, u_long, caddr_t)); 194 void epstart __P((struct ifnet *)); 195 void epwatchdog __P((struct ifnet *)); 196 void epreset __P((struct ep_softc *)); 197 static void epshutdown __P((void *)); 198 void epread __P((struct ep_softc *)); 199 struct mbuf *epget __P((struct ep_softc *, int)); 200 void epmbuffill __P((void *)); 201 void epmbufempty __P((struct ep_softc *)); 202 void epsetfilter __P((struct ep_softc *)); 203 void epsetmedia __P((struct ep_softc *)); 204 205 int epenable __P((struct ep_softc *)); 206 void epdisable __P((struct ep_softc *)); 207 208 /* ifmedia callbacks */ 209 int ep_media_change __P((struct ifnet *ifp)); 210 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 211 212 /* MII callbacks */ 213 int ep_mii_readreg __P((struct device *, int, int)); 214 void ep_mii_writereg __P((struct device *, int, int, int)); 215 void ep_statchg __P((struct device *)); 216 217 void ep_tick __P((void *)); 218 219 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 220 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 221 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 222 void ep_mii_sync __P((struct ep_softc *)); 223 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 224 225 static int epbusyeeprom __P((struct ep_softc *)); 226 static inline void ep_complete_cmd __P((struct ep_softc *sc, 227 u_int cmd, u_int arg)); 228 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 229 230 /* 231 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 232 * Window 1 registers offset! 233 */ 234 static __inline int 235 ep_w1_reg(sc, reg) 236 struct ep_softc *sc; 237 int reg; 238 { 239 240 switch (sc->ep_chipset) { 241 case EP_CHIPSET_CORKSCREW: 242 return (reg + 0x10); 243 244 case EP_CHIPSET_ROADRUNNER: 245 switch (reg) { 246 case EP_W1_FREE_TX: 247 case EP_W1_RUNNER_RDCTL: 248 case EP_W1_RUNNER_WRCTL: 249 return (reg); 250 } 251 return (reg + 0x10); 252 } 253 254 return (reg); 255 } 256 257 /* 258 * Issue a (reset) command, and be sure it has completed. 259 * Used for commands that reset part or all of the board. 260 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 261 * but older hardware doesn't implement it and we must delay. 262 * It's easiest to just delay always. 263 */ 264 static inline void 265 ep_complete_cmd(sc, cmd, arg) 266 struct ep_softc *sc; 267 u_int cmd, arg; 268 { 269 register bus_space_tag_t iot = sc->sc_iot; 270 register bus_space_handle_t ioh = sc->sc_ioh; 271 272 bus_space_write_2(iot, ioh, cmd, arg); 273 274 #ifdef notyet 275 /* if this adapter family has S_COMMAND_IN_PROGRESS, use it */ 276 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 277 ; 278 else 279 #else 280 DELAY(100000); /* need at least 1 ms, but be generous. */ 281 #endif 282 } 283 284 /* 285 * Back-end attach and configure. 286 */ 287 void 288 epconfig(sc, chipset, enaddr) 289 struct ep_softc *sc; 290 u_short chipset; 291 u_int8_t *enaddr; 292 { 293 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 294 bus_space_tag_t iot = sc->sc_iot; 295 bus_space_handle_t ioh = sc->sc_ioh; 296 u_int16_t i; 297 u_int8_t myla[6]; 298 299 sc->ep_chipset = chipset; 300 301 /* 302 * We could have been groveling around in other register 303 * windows in the front-end; make sure we're in window 0 304 * to read the EEPROM. 305 */ 306 GO_WINDOW(0); 307 308 if (enaddr == NULL) { 309 /* 310 * Read the station address from the eeprom 311 */ 312 for (i = 0; i < 3; i++) { 313 u_int16_t x; 314 if (epbusyeeprom(sc)) 315 return; /* XXX why is eeprom busy? */ 316 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 317 READ_EEPROM | i); 318 if (epbusyeeprom(sc)) 319 return; /* XXX why is eeprom busy? */ 320 x = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 321 myla[(i << 1)] = x >> 8; 322 myla[(i << 1) + 1] = x; 323 } 324 enaddr = myla; 325 } 326 327 /* 328 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 329 * allow FDDI-sized (4500) byte packets. Commands only take an 330 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 331 * packet length. 332 * Commands to these cards implicitly upshift a packet size 333 * or threshold by 2 bits. 334 * To detect cards with large-packet support, we probe by setting 335 * the transmit threshold register, then change windows and 336 * read back the threshold register directly, and see if the 337 * threshold value was shifted or not. 338 */ 339 bus_space_write_2(iot, ioh, EP_COMMAND, 340 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 341 GO_WINDOW(5); 342 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 343 GO_WINDOW(1); 344 switch (i) { 345 case EP_LARGEWIN_PROBE: 346 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 347 sc->ep_pktlenshift = 0; 348 break; 349 350 case (EP_LARGEWIN_PROBE << 2): 351 sc->ep_pktlenshift = 2; 352 break; 353 354 default: 355 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 356 "Interface disabled\n", 357 sc->sc_dev.dv_xname, EP_LARGEWIN_PROBE, (int) i); 358 return; 359 } 360 361 /* 362 * Ensure Tx-available interrupts are enabled for 363 * start the interface. 364 * XXX should be in epinit()? 365 */ 366 bus_space_write_2(iot, ioh, EP_COMMAND, 367 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 368 369 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 370 ifp->if_softc = sc; 371 ifp->if_start = epstart; 372 ifp->if_ioctl = epioctl; 373 ifp->if_watchdog = epwatchdog; 374 ifp->if_flags = 375 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 376 377 if_attach(ifp); 378 ether_ifattach(ifp, enaddr); 379 380 /* 381 * Finish configuration: 382 * determine chipset if the front-end couldn't do so, 383 * show board details, set media. 384 */ 385 386 /* 387 * Print RAM size. We also print the Ethernet address in here. 388 * It's extracted from the ifp, so we have to make sure it's 389 * been attached first. 390 */ 391 ep_internalconfig(sc); 392 GO_WINDOW(0); 393 394 /* 395 * Initialize our media structures and MII info. We'll 396 * probe the MII if we discover that we have one. 397 */ 398 sc->sc_mii.mii_ifp = ifp; 399 sc->sc_mii.mii_readreg = ep_mii_readreg; 400 sc->sc_mii.mii_writereg = ep_mii_writereg; 401 sc->sc_mii.mii_statchg = ep_statchg; 402 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 403 ep_media_status); 404 405 /* 406 * Now, determine which media we have. 407 */ 408 switch (sc->ep_chipset) { 409 case EP_CHIPSET_BOOMERANG: 410 case EP_CHIPSET_ROADRUNNER: 411 /* 412 * If the device has MII, probe it. We won't be using 413 * any `native' media in this case, only PHYs. If 414 * we don't, just treat the Boomerang like the Vortex. 415 */ 416 if (sc->ep_flags & EP_FLAGS_MII) { 417 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 418 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 419 ifmedia_add(&sc->sc_mii.mii_media, 420 IFM_ETHER|IFM_NONE, 0, NULL); 421 ifmedia_set(&sc->sc_mii.mii_media, 422 IFM_ETHER|IFM_NONE); 423 } else { 424 ifmedia_set(&sc->sc_mii.mii_media, 425 IFM_ETHER|IFM_AUTO); 426 } 427 break; 428 } 429 /* FALLTHROUGH */ 430 431 case EP_CHIPSET_VORTEX: 432 ep_vortex_probemedia(sc); 433 break; 434 435 default: 436 ep_509_probemedia(sc); 437 break; 438 } 439 440 GO_WINDOW(1); /* Window 1 is operating window */ 441 442 #if NBPFILTER > 0 443 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 444 sizeof(struct ether_header)); 445 #endif 446 447 #if NRND > 0 448 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET); 449 #endif 450 451 sc->tx_start_thresh = 20; /* probably a good starting point. */ 452 453 /* Establish callback to reset card when we reboot. */ 454 shutdownhook_establish(epshutdown, sc); 455 456 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 457 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 458 } 459 460 461 /* 462 * Show interface-model-independent info from window 3 463 * internal-configuration register. 464 */ 465 void 466 ep_internalconfig(sc) 467 struct ep_softc *sc; 468 { 469 bus_space_tag_t iot = sc->sc_iot; 470 bus_space_handle_t ioh = sc->sc_ioh; 471 472 u_int config0; 473 u_int config1; 474 475 int ram_size, ram_width, ram_speed, rom_size, ram_split; 476 /* 477 * NVRAM buffer Rx:Tx config names for busmastering cards 478 * (Demon, Vortex, and later). 479 */ 480 const char *onboard_ram_config[] = { 481 "5:3", "3:1", "1:1", "3:5" }; 482 483 GO_WINDOW(3); 484 config0 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG); 485 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 486 GO_WINDOW(0); 487 488 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 489 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 490 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 491 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 492 493 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 494 495 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 496 sc->sc_dev.dv_xname, 497 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 498 8 << ram_size, 499 (ram_width) ? "word" : "byte", 500 onboard_ram_config[ram_split]); 501 } 502 503 504 /* 505 * Find supported media on 3c509-generation hardware that doesn't have 506 * a "reset_options" register in window 3. 507 * Use the config_cntrl register in window 0 instead. 508 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 509 * that implement CONFIG_CTRL. We don't have a good way to set the 510 * default active mediuim; punt to ifconfig instead. 511 */ 512 void 513 ep_509_probemedia(sc) 514 struct ep_softc *sc; 515 { 516 bus_space_tag_t iot = sc->sc_iot; 517 bus_space_handle_t ioh = sc->sc_ioh; 518 struct ifmedia *ifm = &sc->sc_mii.mii_media; 519 u_int16_t ep_w0_config, port; 520 struct ep_media *epm; 521 const char *sep = "", *defmedianame = NULL; 522 int defmedia = 0; 523 524 GO_WINDOW(0); 525 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 526 527 printf("%s: ", sc->sc_dev.dv_xname); 528 529 /* Sanity check that there are any media! */ 530 if ((ep_w0_config & EP_W0_CC_MEDIAMASK) == 0) { 531 printf("no media present!\n"); 532 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 533 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 534 return; 535 } 536 537 /* 538 * Get the default media from the EEPROM. 539 */ 540 if (epbusyeeprom(sc)) 541 return; /* XXX why is eeprom busy? */ 542 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 543 READ_EEPROM | EEPROM_ADDR_CFG); 544 if (epbusyeeprom(sc)) 545 return; /* XXX why is eeprom busy? */ 546 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA) >> 14; 547 548 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 549 550 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 551 if (ep_w0_config & epm->epm_mpbit) { 552 if (epm->epm_epmedia == port || defmedia == 0) { 553 defmedia = epm->epm_ifmedia; 554 defmedianame = epm->epm_name; 555 } 556 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 557 NULL); 558 PRINT(epm->epm_name); 559 } 560 } 561 562 #undef PRINT 563 564 #ifdef DIAGNOSTIC 565 if (defmedia == 0) 566 panic("ep_509_probemedia: impossible"); 567 #endif 568 569 printf(" (default %s)\n", defmedianame); 570 ifmedia_set(ifm, defmedia); 571 } 572 573 /* 574 * Find media present on large-packet-capable elink3 devices. 575 * Show onboard configuration of large-packet-capable elink3 devices 576 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 577 * Use media and card-version info in window 3 instead. 578 */ 579 void 580 ep_vortex_probemedia(sc) 581 struct ep_softc *sc; 582 { 583 bus_space_tag_t iot = sc->sc_iot; 584 bus_space_handle_t ioh = sc->sc_ioh; 585 struct ifmedia *ifm = &sc->sc_mii.mii_media; 586 struct ep_media *epm; 587 u_int config1; 588 int reset_options; 589 int default_media; /* 3-bit encoding of default (EEPROM) media */ 590 int defmedia = 0; 591 const char *sep = "", *defmedianame = NULL; 592 593 GO_WINDOW(3); 594 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 595 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 596 GO_WINDOW(0); 597 598 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 599 600 printf("%s: ", sc->sc_dev.dv_xname); 601 602 /* Sanity check that there are any media! */ 603 if ((reset_options & EP_PCI_MEDIAMASK) == 0) { 604 printf("no media present!\n"); 605 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 606 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 607 return; 608 } 609 610 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 611 612 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 613 if (reset_options & epm->epm_mpbit) { 614 if (epm->epm_epmedia == default_media || 615 defmedia == 0) { 616 defmedia = epm->epm_ifmedia; 617 defmedianame = epm->epm_name; 618 } 619 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 620 NULL); 621 PRINT(epm->epm_name); 622 } 623 } 624 625 #undef PRINT 626 627 #ifdef DIAGNOSTIC 628 if (defmedia == 0) 629 panic("ep_vortex_probemedia: impossible"); 630 #endif 631 632 printf(" (default %s)\n", defmedianame); 633 ifmedia_set(ifm, defmedia); 634 } 635 636 /* 637 * One second timer, used to tick the MII. 638 */ 639 void 640 ep_tick(arg) 641 void *arg; 642 { 643 struct ep_softc *sc = arg; 644 int s; 645 646 #ifdef DIAGNOSTIC 647 if ((sc->ep_flags & EP_FLAGS_MII) == 0) 648 panic("ep_tick"); 649 #endif 650 651 s = splnet(); 652 mii_tick(&sc->sc_mii); 653 splx(s); 654 655 timeout(ep_tick, sc, hz); 656 } 657 658 /* 659 * Bring device up. 660 * 661 * The order in here seems important. Otherwise we may not receive 662 * interrupts. ?! 663 */ 664 void 665 epinit(sc) 666 register struct ep_softc *sc; 667 { 668 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 669 bus_space_tag_t iot = sc->sc_iot; 670 bus_space_handle_t ioh = sc->sc_ioh; 671 int i; 672 673 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 674 ; 675 676 if (sc->bustype != EP_BUS_PCI) { 677 GO_WINDOW(0); 678 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 679 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 680 } 681 682 if (sc->bustype == EP_BUS_PCMCIA) { 683 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 684 } 685 686 GO_WINDOW(2); 687 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 688 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 689 LLADDR(ifp->if_sadl)[i]); 690 691 /* 692 * Reset the station-address receive filter. 693 * A bug workaround for busmastering (Vortex, Demon) cards. 694 */ 695 for (i = 0; i < 6; i++) 696 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 697 698 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 699 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 700 701 GO_WINDOW(1); /* Window 1 is operating window */ 702 for (i = 0; i < 31; i++) 703 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS)); 704 705 /* Set threshhold for for Tx-space avaiable interrupt. */ 706 bus_space_write_2(iot, ioh, EP_COMMAND, 707 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 708 709 /* Enable interrupts. */ 710 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 711 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 712 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | 713 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 714 715 /* 716 * Attempt to get rid of any stray interrupts that occured during 717 * configuration. On the i386 this isn't possible because one may 718 * already be queued. However, a single stray interrupt is 719 * unimportant. 720 */ 721 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 722 723 epsetfilter(sc); 724 epsetmedia(sc); 725 726 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 727 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 728 729 epmbuffill(sc); 730 731 /* Interface is now `running', with no output active. */ 732 ifp->if_flags |= IFF_RUNNING; 733 ifp->if_flags &= ~IFF_OACTIVE; 734 735 if (sc->ep_flags & EP_FLAGS_MII) { 736 /* Start the one second clock. */ 737 timeout(ep_tick, sc, hz); 738 } 739 740 /* Attempt to start output, if any. */ 741 epstart(ifp); 742 } 743 744 745 /* 746 * Set multicast receive filter. 747 * elink3 hardware has no selective multicast filter in hardware. 748 * Enable reception of all multicasts and filter in software. 749 */ 750 void 751 epsetfilter(sc) 752 register struct ep_softc *sc; 753 { 754 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 755 756 GO_WINDOW(1); /* Window 1 is operating window */ 757 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 758 FIL_INDIVIDUAL | FIL_BRDCST | 759 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 760 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 761 } 762 763 int 764 ep_media_change(ifp) 765 struct ifnet *ifp; 766 { 767 register struct ep_softc *sc = ifp->if_softc; 768 769 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 770 epreset(sc); 771 772 return (0); 773 } 774 775 /* 776 * Set the card to use the specified media. 777 */ 778 void 779 epsetmedia(sc) 780 struct ep_softc *sc; 781 { 782 bus_space_tag_t iot = sc->sc_iot; 783 bus_space_handle_t ioh = sc->sc_ioh; 784 785 /* Turn everything off. First turn off linkbeat and UTP. */ 786 GO_WINDOW(4); 787 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 0x0); 788 789 /* Turn off coax */ 790 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 791 delay(1000); 792 793 /* 794 * If the device has MII, select it, and then tell the 795 * PHY which media to use. 796 */ 797 if (sc->ep_flags & EP_FLAGS_MII) { 798 int config0, config1; 799 800 GO_WINDOW(3); 801 config0 = (u_int)bus_space_read_2(iot, ioh, 802 EP_W3_INTERNAL_CONFIG); 803 config1 = (u_int)bus_space_read_2(iot, ioh, 804 EP_W3_INTERNAL_CONFIG + 2); 805 806 config1 = config1 & ~CONFIG_MEDIAMASK; 807 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 808 809 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 810 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 811 GO_WINDOW(1); /* back to operating window */ 812 813 mii_mediachg(&sc->sc_mii); 814 return; 815 } 816 817 /* 818 * Now turn on the selected media/transceiver. 819 */ 820 GO_WINDOW(4); 821 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 822 case IFM_10_T: 823 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 824 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 825 break; 826 827 case IFM_10_2: 828 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 829 DELAY(1000); /* 50ms not enmough? */ 830 break; 831 832 case IFM_100_TX: 833 case IFM_100_FX: 834 case IFM_100_T4: /* XXX check documentation */ 835 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 836 LINKBEAT_ENABLE); 837 DELAY(1000); /* not strictly necessary? */ 838 break; 839 840 case IFM_10_5: 841 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 842 SQE_ENABLE); 843 DELAY(1000); /* not strictly necessary? */ 844 break; 845 846 case IFM_MANUAL: 847 /* 848 * Nothing to do here; we are actually enabling the 849 * external PHY on the MII port. 850 */ 851 break; 852 853 case IFM_NONE: 854 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 855 return; 856 857 default: 858 panic("epsetmedia: impossible"); 859 } 860 861 /* 862 * Tell the chip which port to use. 863 */ 864 switch (sc->ep_chipset) { 865 case EP_CHIPSET_VORTEX: 866 case EP_CHIPSET_BOOMERANG: 867 { 868 int config0, config1; 869 870 GO_WINDOW(3); 871 config0 = (u_int)bus_space_read_2(iot, ioh, 872 EP_W3_INTERNAL_CONFIG); 873 config1 = (u_int)bus_space_read_2(iot, ioh, 874 EP_W3_INTERNAL_CONFIG + 2); 875 876 config1 = config1 & ~CONFIG_MEDIAMASK; 877 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 878 CONFIG_MEDIAMASK_SHIFT); 879 880 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 881 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 882 break; 883 } 884 default: 885 { 886 int w0_addr_cfg; 887 888 GO_WINDOW(0); 889 w0_addr_cfg = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 890 w0_addr_cfg &= 0x3fff; 891 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, w0_addr_cfg | 892 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 893 DELAY(1000); 894 break; 895 } 896 } 897 898 GO_WINDOW(1); /* Window 1 is operating window */ 899 } 900 901 /* 902 * Get currently-selected media from card. 903 * (if_media callback, may be called before interface is brought up). 904 */ 905 void 906 ep_media_status(ifp, req) 907 struct ifnet *ifp; 908 struct ifmediareq *req; 909 { 910 register struct ep_softc *sc = ifp->if_softc; 911 bus_space_tag_t iot = sc->sc_iot; 912 bus_space_handle_t ioh = sc->sc_ioh; 913 914 if (sc->enabled == 0) { 915 req->ifm_active = IFM_ETHER|IFM_NONE; 916 req->ifm_status = 0; 917 return; 918 } 919 920 /* 921 * If we have MII, go ask the PHY what's going on. 922 */ 923 if (sc->ep_flags & EP_FLAGS_MII) { 924 mii_pollstat(&sc->sc_mii); 925 req->ifm_active = sc->sc_mii.mii_media_active; 926 req->ifm_status = sc->sc_mii.mii_media_status; 927 return; 928 } 929 930 /* 931 * Ok, at this point we claim that our active media is 932 * the currently selected media. We'll update our status 933 * if our chipset allows us to detect link. 934 */ 935 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 936 req->ifm_status = 0; 937 938 switch (sc->ep_chipset) { 939 case EP_CHIPSET_VORTEX: 940 case EP_CHIPSET_BOOMERANG: 941 GO_WINDOW(4); 942 req->ifm_status = IFM_AVALID; 943 if (bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE) & 944 LINKBEAT_DETECT) 945 req->ifm_status |= IFM_ACTIVE; 946 GO_WINDOW(1); /* back to operating window */ 947 break; 948 } 949 } 950 951 952 953 /* 954 * Start outputting on the interface. 955 * Always called as splnet(). 956 */ 957 void 958 epstart(ifp) 959 struct ifnet *ifp; 960 { 961 register struct ep_softc *sc = ifp->if_softc; 962 bus_space_tag_t iot = sc->sc_iot; 963 bus_space_handle_t ioh = sc->sc_ioh; 964 struct mbuf *m, *m0; 965 int sh, len, pad; 966 bus_addr_t txreg; 967 968 /* Don't transmit if interface is busy or not running */ 969 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 970 return; 971 972 startagain: 973 /* Sneak a peek at the next packet */ 974 m0 = ifp->if_snd.ifq_head; 975 if (m0 == 0) 976 return; 977 978 /* We need to use m->m_pkthdr.len, so require the header */ 979 if ((m0->m_flags & M_PKTHDR) == 0) 980 panic("epstart: no header mbuf"); 981 len = m0->m_pkthdr.len; 982 983 pad = (4 - len) & 3; 984 985 /* 986 * The 3c509 automatically pads short packets to minimum ethernet 987 * length, but we drop packets that are too large. Perhaps we should 988 * truncate them instead? 989 */ 990 if (len + pad > ETHER_MAX_LEN) { 991 /* packet is obviously too large: toss it */ 992 ++ifp->if_oerrors; 993 IF_DEQUEUE(&ifp->if_snd, m0); 994 m_freem(m0); 995 goto readcheck; 996 } 997 998 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) < 999 len + pad + 4) { 1000 bus_space_write_2(iot, ioh, EP_COMMAND, 1001 SET_TX_AVAIL_THRESH | 1002 ((len + pad + 4) >> sc->ep_pktlenshift)); 1003 /* not enough room in FIFO */ 1004 ifp->if_flags |= IFF_OACTIVE; 1005 return; 1006 } else { 1007 bus_space_write_2(iot, ioh, EP_COMMAND, 1008 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE ); 1009 } 1010 1011 IF_DEQUEUE(&ifp->if_snd, m0); 1012 if (m0 == 0) /* not really needed */ 1013 return; 1014 1015 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 1016 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/) ); 1017 1018 #if NBPFILTER > 0 1019 if (ifp->if_bpf) 1020 bpf_mtap(ifp->if_bpf, m0); 1021 #endif 1022 1023 /* 1024 * Do the output at splhigh() so that an interrupt from another device 1025 * won't cause a FIFO underrun. 1026 */ 1027 sh = splhigh(); 1028 1029 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1); 1030 1031 bus_space_write_2(iot, ioh, txreg, len); 1032 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1033 if (EP_IS_BUS_32(sc->bustype)) { 1034 for (m = m0; m; ) { 1035 if (m->m_len > 3) { 1036 /* align our reads from core */ 1037 if (mtod(m, u_long) & 3) { 1038 u_long count = 1039 4 - (mtod(m, u_long) & 3); 1040 bus_space_write_multi_1(iot, ioh, 1041 txreg, mtod(m, u_int8_t *), count); 1042 m->m_data = 1043 (void *)(mtod(m, u_long) + count); 1044 m->m_len -= count; 1045 } 1046 bus_space_write_multi_4(iot, ioh, 1047 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1048 m->m_data = (void *)(mtod(m, u_long) + 1049 (u_long)(m->m_len & ~3)); 1050 m->m_len -= m->m_len & ~3; 1051 } 1052 if (m->m_len) { 1053 bus_space_write_multi_1(iot, ioh, 1054 txreg, mtod(m, u_int8_t *), m->m_len); 1055 } 1056 MFREE(m, m0); 1057 m = m0; 1058 } 1059 } else { 1060 for (m = m0; m; ) { 1061 if (m->m_len > 1) { 1062 if (mtod(m, u_long) & 1) { 1063 bus_space_write_1(iot, ioh, 1064 txreg, *(mtod(m, u_int8_t *))); 1065 m->m_data = 1066 (void *)(mtod(m, u_long) + 1); 1067 m->m_len -= 1; 1068 } 1069 bus_space_write_multi_2(iot, ioh, 1070 txreg, mtod(m, u_int16_t *), 1071 m->m_len >> 1); 1072 } 1073 if (m->m_len & 1) { 1074 bus_space_write_1(iot, ioh, txreg, 1075 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1076 } 1077 MFREE(m, m0); 1078 m = m0; 1079 } 1080 } 1081 while (pad--) 1082 bus_space_write_1(iot, ioh, txreg, 0); 1083 1084 splx(sh); 1085 1086 ++ifp->if_opackets; 1087 1088 readcheck: 1089 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) & 1090 ERR_INCOMPLETE) == 0) { 1091 /* We received a complete packet. */ 1092 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1093 1094 if ((status & S_INTR_LATCH) == 0) { 1095 /* 1096 * No interrupt, read the packet and continue 1097 * Is this supposed to happen? Is my motherboard 1098 * completely busted? 1099 */ 1100 epread(sc); 1101 } else { 1102 /* Got an interrupt, return so that it gets serviced. */ 1103 return; 1104 } 1105 } else { 1106 /* Check if we are stuck and reset [see XXX comment] */ 1107 if (epstatus(sc)) { 1108 if (ifp->if_flags & IFF_DEBUG) 1109 printf("%s: adapter reset\n", 1110 sc->sc_dev.dv_xname); 1111 epreset(sc); 1112 } 1113 } 1114 1115 goto startagain; 1116 } 1117 1118 1119 /* 1120 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1121 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1122 * We detect this situation and we reset the adapter. 1123 * It happens at times when there is a lot of broadcast traffic 1124 * on the cable (once in a blue moon). 1125 */ 1126 static int 1127 epstatus(sc) 1128 register struct ep_softc *sc; 1129 { 1130 bus_space_tag_t iot = sc->sc_iot; 1131 bus_space_handle_t ioh = sc->sc_ioh; 1132 u_int16_t fifost; 1133 1134 /* 1135 * Check the FIFO status and act accordingly 1136 */ 1137 GO_WINDOW(4); 1138 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1139 GO_WINDOW(1); 1140 1141 if (fifost & FIFOS_RX_UNDERRUN) { 1142 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1143 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1144 epreset(sc); 1145 return 0; 1146 } 1147 1148 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1149 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1150 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1151 return 1; 1152 } 1153 1154 if (fifost & FIFOS_RX_OVERRUN) { 1155 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1156 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1157 return 1; 1158 } 1159 1160 if (fifost & FIFOS_TX_OVERRUN) { 1161 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1162 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1163 epreset(sc); 1164 return 0; 1165 } 1166 1167 return 0; 1168 } 1169 1170 1171 static void 1172 eptxstat(sc) 1173 register struct ep_softc *sc; 1174 { 1175 bus_space_tag_t iot = sc->sc_iot; 1176 bus_space_handle_t ioh = sc->sc_ioh; 1177 int i; 1178 1179 /* 1180 * We need to read+write TX_STATUS until we get a 0 status 1181 * in order to turn off the interrupt flag. 1182 */ 1183 while ((i = bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS))) 1184 & TXS_COMPLETE) { 1185 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS), 1186 0x0); 1187 1188 if (i & TXS_JABBER) { 1189 ++sc->sc_ethercom.ec_if.if_oerrors; 1190 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1191 printf("%s: jabber (%x)\n", 1192 sc->sc_dev.dv_xname, i); 1193 epreset(sc); 1194 } else if (i & TXS_UNDERRUN) { 1195 ++sc->sc_ethercom.ec_if.if_oerrors; 1196 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1197 printf("%s: fifo underrun (%x) @%d\n", 1198 sc->sc_dev.dv_xname, i, 1199 sc->tx_start_thresh); 1200 if (sc->tx_succ_ok < 100) 1201 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1202 sc->tx_start_thresh + 20); 1203 sc->tx_succ_ok = 0; 1204 epreset(sc); 1205 } else if (i & TXS_MAX_COLLISION) { 1206 ++sc->sc_ethercom.ec_if.if_collisions; 1207 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1208 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1209 } else 1210 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1211 } 1212 } 1213 1214 int 1215 epintr(arg) 1216 void *arg; 1217 { 1218 register struct ep_softc *sc = arg; 1219 bus_space_tag_t iot = sc->sc_iot; 1220 bus_space_handle_t ioh = sc->sc_ioh; 1221 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1222 u_int16_t status; 1223 int ret = 0; 1224 int addrandom = 0; 1225 1226 if (sc->enabled == 0) 1227 return (0); 1228 1229 for (;;) { 1230 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1231 1232 status = bus_space_read_2(iot, ioh, EP_STATUS); 1233 1234 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1235 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1236 if ((status & S_INTR_LATCH) == 0) { 1237 #if 0 1238 printf("%s: intr latch cleared\n", 1239 sc->sc_dev.dv_xname); 1240 #endif 1241 break; 1242 } 1243 } 1244 1245 ret = 1; 1246 1247 /* 1248 * Acknowledge any interrupts. It's important that we do this 1249 * first, since there would otherwise be a race condition. 1250 * Due to the i386 interrupt queueing, we may get spurious 1251 * interrupts occasionally. 1252 */ 1253 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 1254 (status & (C_INTR_LATCH | 1255 C_CARD_FAILURE | 1256 C_TX_COMPLETE | 1257 C_TX_AVAIL | 1258 C_RX_COMPLETE | 1259 C_RX_EARLY | 1260 C_INT_RQD | 1261 C_UPD_STATS))); 1262 1263 #if 0 1264 status = bus_space_read_2(iot, ioh, EP_STATUS); 1265 1266 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1267 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1268 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1269 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1270 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1271 #endif 1272 1273 if (status & S_RX_COMPLETE) { 1274 epread(sc); 1275 addrandom = 1; 1276 } 1277 if (status & S_TX_AVAIL) { 1278 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1279 epstart(&sc->sc_ethercom.ec_if); 1280 addrandom = 1; 1281 } 1282 if (status & S_CARD_FAILURE) { 1283 printf("%s: adapter failure (%x)\n", 1284 sc->sc_dev.dv_xname, status); 1285 epreset(sc); 1286 return (1); 1287 } 1288 if (status & S_TX_COMPLETE) { 1289 eptxstat(sc); 1290 epstart(ifp); 1291 addrandom = 1; 1292 } 1293 1294 #if NRND > 0 1295 if (status) 1296 rnd_add_uint32(&sc->rnd_source, status); 1297 #endif 1298 } 1299 1300 /* no more interrupts */ 1301 return (ret); 1302 } 1303 1304 void 1305 epread(sc) 1306 register struct ep_softc *sc; 1307 { 1308 bus_space_tag_t iot = sc->sc_iot; 1309 bus_space_handle_t ioh = sc->sc_ioh; 1310 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1311 struct mbuf *m; 1312 struct ether_header *eh; 1313 int len; 1314 1315 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)); 1316 1317 again: 1318 if (ifp->if_flags & IFF_DEBUG) { 1319 int err = len & ERR_MASK; 1320 char *s = NULL; 1321 1322 if (len & ERR_INCOMPLETE) 1323 s = "incomplete packet"; 1324 else if (err == ERR_OVERRUN) 1325 s = "packet overrun"; 1326 else if (err == ERR_RUNT) 1327 s = "runt packet"; 1328 else if (err == ERR_ALIGNMENT) 1329 s = "bad alignment"; 1330 else if (err == ERR_CRC) 1331 s = "bad crc"; 1332 else if (err == ERR_OVERSIZE) 1333 s = "oversized packet"; 1334 else if (err == ERR_DRIBBLE) 1335 s = "dribble bits"; 1336 1337 if (s) 1338 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1339 } 1340 1341 if (len & ERR_INCOMPLETE) 1342 return; 1343 1344 if (len & ERR_RX) { 1345 ++ifp->if_ierrors; 1346 goto abort; 1347 } 1348 1349 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1350 1351 /* Pull packet off interface. */ 1352 m = epget(sc, len); 1353 if (m == 0) { 1354 ifp->if_ierrors++; 1355 goto abort; 1356 } 1357 1358 ++ifp->if_ipackets; 1359 1360 /* We assume the header fit entirely in one mbuf. */ 1361 eh = mtod(m, struct ether_header *); 1362 1363 #if NBPFILTER > 0 1364 /* 1365 * Check if there's a BPF listener on this interface. 1366 * If so, hand off the raw packet to BPF. 1367 */ 1368 if (ifp->if_bpf) { 1369 bpf_mtap(ifp->if_bpf, m); 1370 1371 /* 1372 * Note that the interface cannot be in promiscuous mode if 1373 * there are no BPF listeners. And if we are in promiscuous 1374 * mode, we have to check if this packet is really ours. 1375 */ 1376 if ((ifp->if_flags & IFF_PROMISC) && 1377 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1378 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1379 sizeof(eh->ether_dhost)) != 0) { 1380 m_freem(m); 1381 return; 1382 } 1383 } 1384 #endif 1385 1386 /* We assume the header fit entirely in one mbuf. */ 1387 m_adj(m, sizeof(struct ether_header)); 1388 ether_input(ifp, eh, m); 1389 1390 /* 1391 * In periods of high traffic we can actually receive enough 1392 * packets so that the fifo overrun bit will be set at this point, 1393 * even though we just read a packet. In this case we 1394 * are not going to receive any more interrupts. We check for 1395 * this condition and read again until the fifo is not full. 1396 * We could simplify this test by not using epstatus(), but 1397 * rechecking the RX_STATUS register directly. This test could 1398 * result in unnecessary looping in cases where there is a new 1399 * packet but the fifo is not full, but it will not fix the 1400 * stuck behavior. 1401 * 1402 * Even with this improvement, we still get packet overrun errors 1403 * which are hurting performance. Maybe when I get some more time 1404 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1405 */ 1406 if (epstatus(sc)) { 1407 len = bus_space_read_2(iot, ioh, 1408 ep_w1_reg(sc, EP_W1_RX_STATUS)); 1409 /* Check if we are stuck and reset [see XXX comment] */ 1410 if (len & ERR_INCOMPLETE) { 1411 if (ifp->if_flags & IFF_DEBUG) 1412 printf("%s: adapter reset\n", 1413 sc->sc_dev.dv_xname); 1414 epreset(sc); 1415 return; 1416 } 1417 goto again; 1418 } 1419 1420 return; 1421 1422 abort: 1423 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1424 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1425 ; 1426 } 1427 1428 struct mbuf * 1429 epget(sc, totlen) 1430 struct ep_softc *sc; 1431 int totlen; 1432 { 1433 bus_space_tag_t iot = sc->sc_iot; 1434 bus_space_handle_t ioh = sc->sc_ioh; 1435 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1436 struct mbuf *top, **mp, *m; 1437 bus_addr_t rxreg; 1438 int len, remaining; 1439 int sh; 1440 1441 m = sc->mb[sc->next_mb]; 1442 sc->mb[sc->next_mb] = 0; 1443 if (m == 0) { 1444 MGETHDR(m, M_DONTWAIT, MT_DATA); 1445 if (m == 0) 1446 return 0; 1447 } else { 1448 /* If the queue is no longer full, refill. */ 1449 if (sc->last_mb == sc->next_mb) 1450 timeout(epmbuffill, sc, 1); 1451 /* Convert one of our saved mbuf's. */ 1452 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1453 m->m_data = m->m_pktdat; 1454 m->m_flags = M_PKTHDR; 1455 } 1456 m->m_pkthdr.rcvif = ifp; 1457 m->m_pkthdr.len = totlen; 1458 len = MHLEN; 1459 top = 0; 1460 mp = ⊤ 1461 1462 /* 1463 * We read the packet at splhigh() so that an interrupt from another 1464 * device doesn't cause the card's buffer to overflow while we're 1465 * reading it. We may still lose packets at other times. 1466 */ 1467 sh = splhigh(); 1468 1469 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1); 1470 1471 while (totlen > 0) { 1472 if (top) { 1473 m = sc->mb[sc->next_mb]; 1474 sc->mb[sc->next_mb] = 0; 1475 if (m == 0) { 1476 MGET(m, M_DONTWAIT, MT_DATA); 1477 if (m == 0) { 1478 splx(sh); 1479 m_freem(top); 1480 return 0; 1481 } 1482 } else { 1483 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1484 } 1485 len = MLEN; 1486 } 1487 if (totlen >= MINCLSIZE) { 1488 MCLGET(m, M_DONTWAIT); 1489 if ((m->m_flags & M_EXT) == 0) { 1490 splx(sh); 1491 m_free(m); 1492 m_freem(top); 1493 return 0; 1494 } 1495 len = MCLBYTES; 1496 } 1497 if (top == 0) { 1498 /* align the struct ip header */ 1499 caddr_t newdata = (caddr_t) 1500 ALIGN(m->m_data + sizeof(struct ether_header)) 1501 - sizeof(struct ether_header); 1502 len -= newdata - m->m_data; 1503 m->m_data = newdata; 1504 } 1505 remaining = len = min(totlen, len); 1506 if (EP_IS_BUS_32(sc->bustype)) { 1507 u_long offset = mtod(m, u_long); 1508 /* 1509 * Read bytes up to the point where we are aligned. 1510 * (We can align to 4 bytes, rather than ALIGNBYTES, 1511 * here because we're later reading 4-byte chunks.) 1512 */ 1513 if ((remaining > 3) && (offset & 3)) { 1514 int count = (4 - (offset & 3)); 1515 bus_space_read_multi_1(iot, ioh, 1516 rxreg, (u_int8_t *) offset, count); 1517 offset += count; 1518 remaining -= count; 1519 } 1520 if (remaining > 3) { 1521 bus_space_read_multi_4(iot, ioh, 1522 rxreg, (u_int32_t *) offset, 1523 remaining >> 2); 1524 offset += remaining & ~3; 1525 remaining &= 3; 1526 } 1527 if (remaining) { 1528 bus_space_read_multi_1(iot, ioh, 1529 rxreg, (u_int8_t *) offset, remaining); 1530 } 1531 } else { 1532 u_long offset = mtod(m, u_long); 1533 if ((remaining > 1) && (offset & 1)) { 1534 bus_space_read_multi_1(iot, ioh, 1535 rxreg, (u_int8_t *) offset, 1); 1536 remaining -= 1; 1537 offset += 1; 1538 } 1539 if (remaining > 1) { 1540 bus_space_read_multi_2(iot, ioh, 1541 rxreg, (u_int16_t *) offset, 1542 remaining >> 1); 1543 offset += remaining & ~1; 1544 } 1545 if (remaining & 1) { 1546 bus_space_read_multi_1(iot, ioh, 1547 rxreg, (u_int8_t *) offset, remaining & 1); 1548 } 1549 } 1550 m->m_len = len; 1551 totlen -= len; 1552 *mp = m; 1553 mp = &m->m_next; 1554 } 1555 1556 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1557 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1558 ; 1559 1560 splx(sh); 1561 1562 return top; 1563 } 1564 1565 int 1566 epioctl(ifp, cmd, data) 1567 register struct ifnet *ifp; 1568 u_long cmd; 1569 caddr_t data; 1570 { 1571 struct ep_softc *sc = ifp->if_softc; 1572 struct ifaddr *ifa = (struct ifaddr *)data; 1573 struct ifreq *ifr = (struct ifreq *)data; 1574 int s, error = 0; 1575 1576 s = splnet(); 1577 1578 switch (cmd) { 1579 1580 case SIOCSIFADDR: 1581 if ((error = epenable(sc)) != 0) 1582 break; 1583 /* epinit is called just below */ 1584 ifp->if_flags |= IFF_UP; 1585 switch (ifa->ifa_addr->sa_family) { 1586 #ifdef INET 1587 case AF_INET: 1588 epinit(sc); 1589 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1590 break; 1591 #endif 1592 #ifdef NS 1593 case AF_NS: 1594 { 1595 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1596 1597 if (ns_nullhost(*ina)) 1598 ina->x_host = *(union ns_host *) 1599 LLADDR(ifp->if_sadl); 1600 else 1601 bcopy(ina->x_host.c_host, 1602 LLADDR(ifp->if_sadl), 1603 ifp->if_addrlen); 1604 /* Set new address. */ 1605 epinit(sc); 1606 break; 1607 } 1608 #endif 1609 default: 1610 epinit(sc); 1611 break; 1612 } 1613 break; 1614 1615 case SIOCSIFMEDIA: 1616 case SIOCGIFMEDIA: 1617 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1618 break; 1619 1620 case SIOCSIFFLAGS: 1621 if ((ifp->if_flags & IFF_UP) == 0 && 1622 (ifp->if_flags & IFF_RUNNING) != 0) { 1623 /* 1624 * If interface is marked down and it is running, then 1625 * stop it. 1626 */ 1627 epstop(sc); 1628 ifp->if_flags &= ~IFF_RUNNING; 1629 epdisable(sc); 1630 } else if ((ifp->if_flags & IFF_UP) != 0 && 1631 (ifp->if_flags & IFF_RUNNING) == 0) { 1632 /* 1633 * If interface is marked up and it is stopped, then 1634 * start it. 1635 */ 1636 if ((error = epenable(sc)) != 0) 1637 break; 1638 epinit(sc); 1639 } else if (sc->enabled) { 1640 /* 1641 * deal with flags changes: 1642 * IFF_MULTICAST, IFF_PROMISC. 1643 */ 1644 epsetfilter(sc); 1645 } 1646 break; 1647 1648 case SIOCADDMULTI: 1649 case SIOCDELMULTI: 1650 if (sc->enabled == 0) { 1651 error = EIO; 1652 break; 1653 } 1654 1655 error = (cmd == SIOCADDMULTI) ? 1656 ether_addmulti(ifr, &sc->sc_ethercom) : 1657 ether_delmulti(ifr, &sc->sc_ethercom); 1658 1659 if (error == ENETRESET) { 1660 /* 1661 * Multicast list has changed; set the hardware filter 1662 * accordingly. 1663 */ 1664 epreset(sc); 1665 error = 0; 1666 } 1667 break; 1668 1669 default: 1670 error = EINVAL; 1671 break; 1672 } 1673 1674 splx(s); 1675 return (error); 1676 } 1677 1678 void 1679 epreset(sc) 1680 struct ep_softc *sc; 1681 { 1682 int s; 1683 1684 s = splnet(); 1685 epstop(sc); 1686 epinit(sc); 1687 splx(s); 1688 } 1689 1690 void 1691 epwatchdog(ifp) 1692 struct ifnet *ifp; 1693 { 1694 struct ep_softc *sc = ifp->if_softc; 1695 1696 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1697 ++sc->sc_ethercom.ec_if.if_oerrors; 1698 1699 epreset(sc); 1700 } 1701 1702 void 1703 epstop(sc) 1704 register struct ep_softc *sc; 1705 { 1706 bus_space_tag_t iot = sc->sc_iot; 1707 bus_space_handle_t ioh = sc->sc_ioh; 1708 1709 if (sc->ep_flags & EP_FLAGS_MII) { 1710 /* Stop the one second clock. */ 1711 untimeout(ep_tick, sc); 1712 } 1713 1714 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1715 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1716 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1717 ; 1718 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1719 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1720 1721 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 1722 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 1723 1724 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1725 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1726 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1727 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1728 1729 epmbufempty(sc); 1730 } 1731 1732 1733 /* 1734 * Before reboots, reset card completely. 1735 */ 1736 static void 1737 epshutdown(arg) 1738 void *arg; 1739 { 1740 register struct ep_softc *sc = arg; 1741 1742 if (sc->enabled) { 1743 epstop(sc); 1744 ep_complete_cmd(sc, EP_COMMAND, GLOBAL_RESET); 1745 } 1746 } 1747 1748 /* 1749 * We get eeprom data from the id_port given an offset into the 1750 * eeprom. Basically; after the ID_sequence is sent to all of 1751 * the cards; they enter the ID_CMD state where they will accept 1752 * command requests. 0x80-0xbf loads the eeprom data. We then 1753 * read the port 16 times and with every read; the cards check 1754 * for contention (ie: if one card writes a 0 bit and another 1755 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1756 * each card compares the data on the bus; if there is a difference 1757 * then that card goes into ID_WAIT state again). In the meantime; 1758 * one bit of data is returned in the AX register which is conveniently 1759 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1760 * bit of data with each read. 1761 * 1762 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1763 */ 1764 u_int16_t 1765 epreadeeprom(iot, ioh, offset) 1766 bus_space_tag_t iot; 1767 bus_space_handle_t ioh; 1768 int offset; 1769 { 1770 u_int16_t data = 0; 1771 int i; 1772 1773 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1774 delay(1000); 1775 for (i = 0; i < 16; i++) 1776 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1777 return (data); 1778 } 1779 1780 static int 1781 epbusyeeprom(sc) 1782 struct ep_softc *sc; 1783 { 1784 bus_space_tag_t iot = sc->sc_iot; 1785 bus_space_handle_t ioh = sc->sc_ioh; 1786 int i = 100, j; 1787 1788 if (sc->bustype == EP_BUS_PCMCIA) { 1789 delay(1000); 1790 return 0; 1791 } 1792 1793 j = 0; /* bad GCC flow analysis */ 1794 while (i--) { 1795 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1796 if (j & EEPROM_BUSY) 1797 delay(100); 1798 else 1799 break; 1800 } 1801 if (!i) { 1802 printf("\n%s: eeprom failed to come ready\n", 1803 sc->sc_dev.dv_xname); 1804 return (1); 1805 } 1806 if (j & EEPROM_TST_MODE) { 1807 /* XXX PnP mode? */ 1808 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1809 return (1); 1810 } 1811 return (0); 1812 } 1813 1814 void 1815 epmbuffill(v) 1816 void *v; 1817 { 1818 struct ep_softc *sc = v; 1819 int s, i; 1820 1821 s = splnet(); 1822 i = sc->last_mb; 1823 do { 1824 if (sc->mb[i] == NULL) 1825 MGET(sc->mb[i], M_DONTWAIT, MT_DATA); 1826 if (sc->mb[i] == NULL) 1827 break; 1828 i = (i + 1) % MAX_MBS; 1829 } while (i != sc->next_mb); 1830 sc->last_mb = i; 1831 /* If the queue was not filled, try again. */ 1832 if (sc->last_mb != sc->next_mb) 1833 timeout(epmbuffill, sc, 1); 1834 splx(s); 1835 } 1836 1837 void 1838 epmbufempty(sc) 1839 struct ep_softc *sc; 1840 { 1841 int s, i; 1842 1843 s = splnet(); 1844 for (i = 0; i<MAX_MBS; i++) { 1845 if (sc->mb[i]) { 1846 m_freem(sc->mb[i]); 1847 sc->mb[i] = NULL; 1848 } 1849 } 1850 sc->last_mb = sc->next_mb = 0; 1851 untimeout(epmbuffill, sc); 1852 splx(s); 1853 } 1854 1855 int 1856 epenable(sc) 1857 struct ep_softc *sc; 1858 { 1859 1860 if (sc->enabled == 0 && sc->enable != NULL) { 1861 if ((*sc->enable)(sc) != 0) { 1862 printf("%s: device enable failed\n", 1863 sc->sc_dev.dv_xname); 1864 return (EIO); 1865 } 1866 } 1867 1868 sc->enabled = 1; 1869 return (0); 1870 } 1871 1872 void 1873 epdisable(sc) 1874 struct ep_softc *sc; 1875 { 1876 1877 if (sc->enabled != 0 && sc->disable != NULL) { 1878 (*sc->disable)(sc); 1879 sc->enabled = 0; 1880 } 1881 } 1882 1883 void 1884 ep_mii_setbit(sc, bit) 1885 struct ep_softc *sc; 1886 u_int16_t bit; 1887 { 1888 u_int16_t val; 1889 1890 /* We assume we're already in Window 4 */ 1891 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1892 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1893 val | bit); 1894 } 1895 1896 void 1897 ep_mii_clrbit(sc, bit) 1898 struct ep_softc *sc; 1899 u_int16_t bit; 1900 { 1901 u_int16_t val; 1902 1903 /* We assume we're already in Window 4 */ 1904 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1905 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1906 val & ~bit); 1907 } 1908 1909 u_int16_t 1910 ep_mii_readbit(sc, bit) 1911 struct ep_softc *sc; 1912 u_int16_t bit; 1913 { 1914 1915 /* We assume we're already in Window 4 */ 1916 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 1917 bit); 1918 } 1919 1920 void 1921 ep_mii_sync(sc) 1922 struct ep_softc *sc; 1923 { 1924 int i; 1925 1926 /* We assume we're already in Window 4 */ 1927 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1928 for (i = 0; i < 32; i++) { 1929 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1930 ep_mii_setbit(sc, PHYSMGMT_CLK); 1931 } 1932 } 1933 1934 void 1935 ep_mii_sendbits(sc, data, nbits) 1936 struct ep_softc *sc; 1937 u_int32_t data; 1938 int nbits; 1939 { 1940 int i; 1941 1942 /* We assume we're already in Window 4 */ 1943 ep_mii_setbit(sc, PHYSMGMT_DIR); 1944 for (i = 1 << (nbits - 1); i; i = i >> 1) { 1945 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1946 ep_mii_readbit(sc, PHYSMGMT_CLK); 1947 if (data & i) 1948 ep_mii_setbit(sc, PHYSMGMT_DATA); 1949 else 1950 ep_mii_clrbit(sc, PHYSMGMT_DATA); 1951 ep_mii_setbit(sc, PHYSMGMT_CLK); 1952 ep_mii_readbit(sc, PHYSMGMT_CLK); 1953 } 1954 } 1955 1956 int 1957 ep_mii_readreg(self, phy, reg) 1958 struct device *self; 1959 int phy, reg; 1960 { 1961 struct ep_softc *sc = (struct ep_softc *)self; 1962 int val = 0, i, err; 1963 1964 /* 1965 * Read the PHY register by manually driving the MII control lines. 1966 */ 1967 1968 GO_WINDOW(4); 1969 1970 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 1971 1972 ep_mii_sync(sc); 1973 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 1974 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 1975 ep_mii_sendbits(sc, phy, 5); 1976 ep_mii_sendbits(sc, reg, 5); 1977 1978 ep_mii_clrbit(sc, PHYSMGMT_DIR); 1979 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1980 ep_mii_setbit(sc, PHYSMGMT_CLK); 1981 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1982 1983 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 1984 ep_mii_setbit(sc, PHYSMGMT_CLK); 1985 1986 /* Even if an error occurs, must still clock out the cycle. */ 1987 for (i = 0; i < 16; i++) { 1988 val <<= 1; 1989 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1990 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 1991 val |= 1; 1992 ep_mii_setbit(sc, PHYSMGMT_CLK); 1993 } 1994 ep_mii_clrbit(sc, PHYSMGMT_CLK); 1995 ep_mii_setbit(sc, PHYSMGMT_CLK); 1996 1997 GO_WINDOW(1); /* back to operating window */ 1998 1999 return (err ? 0 : val); 2000 } 2001 2002 void 2003 ep_mii_writereg(self, phy, reg, val) 2004 struct device *self; 2005 int phy, reg, val; 2006 { 2007 struct ep_softc *sc = (struct ep_softc *)self; 2008 2009 /* 2010 * Write the PHY register by manually driving the MII control lines. 2011 */ 2012 2013 GO_WINDOW(4); 2014 2015 ep_mii_sync(sc); 2016 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2017 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2018 ep_mii_sendbits(sc, phy, 5); 2019 ep_mii_sendbits(sc, reg, 5); 2020 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2021 ep_mii_sendbits(sc, val, 16); 2022 2023 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2024 ep_mii_setbit(sc, PHYSMGMT_CLK); 2025 2026 GO_WINDOW(1); /* back to operating window */ 2027 } 2028 2029 void 2030 ep_statchg(self) 2031 struct device *self; 2032 { 2033 2034 /* XXX Update ifp->if_baudrate */ 2035 /* XXX Full-duplex control in MAC? */ 2036 } 2037
Indexes created Fri Sep 26 20:09:58 GMT 2025