elink3.c revision 1.44
1 /* $NetBSD: elink3.c,v 1.44 1998/08/17 23:20:39 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #define ETHER_MIN_LEN 64 124 #define ETHER_MAX_LEN 1518 125 #define ETHER_ADDR_LEN 6 126 127 #ifdef DEBUG 128 int epdebug = 0; 129 #endif 130 131 /* 132 * Structure to map media-present bits in boards to ifmedia codes and 133 * printable media names. Used for table-driven ifmedia initialization. 134 */ 135 struct ep_media { 136 int epm_mpbit; /* media present bit */ 137 const char *epm_name; /* name of medium */ 138 int epm_ifmedia; /* ifmedia word for medium */ 139 int epm_epmedia; /* EPMEDIA_* constant */ 140 }; 141 142 /* 143 * Media table for the Demon/Vortex/Boomerang chipsets. 144 * 145 * Note that MII on the Demon and Vortex (3c59x) indicates an external 146 * MII connector (for connecting an external PHY) ... I think. Treat 147 * it as `manual' on these chips. 148 * 149 * Any Boomerang (3c90x) chips with MII really do have an internal 150 * MII and real PHYs attached; no `native' media. 151 */ 152 struct ep_media ep_vortex_media[] = { 153 { EP_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 154 EPMEDIA_10BASE_T }, 155 { EP_PCI_AUI, "10base5/AUI", IFM_ETHER|IFM_10_5, 156 EPMEDIA_AUI }, 157 { EP_PCI_BNC, "10base2/BNC", IFM_ETHER|IFM_10_2, 158 EPMEDIA_10BASE_2 }, 159 { EP_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 160 EPMEDIA_100BASE_TX }, 161 { EP_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 162 EPMEDIA_100BASE_FX }, 163 { EP_PCI_100BASE_MII, "manual", IFM_ETHER|IFM_MANUAL, 164 EPMEDIA_MII }, 165 { EP_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 166 EPMEDIA_100BASE_T4 }, 167 { 0, NULL, 0, 168 0 }, 169 }; 170 171 /* 172 * Media table for the older 3Com Etherlink III chipset, used 173 * in the 3c509, 3c579, and 3c589. 174 */ 175 struct ep_media ep_509_media[] = { 176 { EP_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 177 EPMEDIA_10BASE_T }, 178 { EP_W0_CC_AUI, "10base5/AUI", IFM_ETHER|IFM_10_5, 179 EPMEDIA_AUI }, 180 { EP_W0_CC_BNC, "10base2/BNC", IFM_ETHER|IFM_10_2, 181 EPMEDIA_10BASE_2 }, 182 { 0, NULL, 0, 183 0 }, 184 }; 185 186 void ep_internalconfig __P((struct ep_softc *sc)); 187 void ep_vortex_probemedia __P((struct ep_softc *sc)); 188 void ep_509_probemedia __P((struct ep_softc *sc)); 189 190 static void eptxstat __P((struct ep_softc *)); 191 static int epstatus __P((struct ep_softc *)); 192 void epinit __P((struct ep_softc *)); 193 int epioctl __P((struct ifnet *, u_long, caddr_t)); 194 void epstart __P((struct ifnet *)); 195 void epwatchdog __P((struct ifnet *)); 196 void epreset __P((struct ep_softc *)); 197 static void epshutdown __P((void *)); 198 void epread __P((struct ep_softc *)); 199 struct mbuf *epget __P((struct ep_softc *, int)); 200 void epmbuffill __P((void *)); 201 void epmbufempty __P((struct ep_softc *)); 202 void epsetfilter __P((struct ep_softc *)); 203 void epsetmedia __P((struct ep_softc *)); 204 205 int epenable __P((struct ep_softc *)); 206 void epdisable __P((struct ep_softc *)); 207 208 /* ifmedia callbacks */ 209 int ep_media_change __P((struct ifnet *ifp)); 210 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 211 212 /* MII callbacks */ 213 int ep_mii_readreg __P((struct device *, int, int)); 214 void ep_mii_writereg __P((struct device *, int, int, int)); 215 void ep_statchg __P((struct device *)); 216 217 void ep_tick __P((void *)); 218 219 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 220 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 221 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 222 void ep_mii_sync __P((struct ep_softc *)); 223 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 224 225 static int epbusyeeprom __P((struct ep_softc *)); 226 static inline void ep_complete_cmd __P((struct ep_softc *sc, 227 u_int cmd, u_int arg)); 228 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 229 230 /* 231 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 232 * Window 1 registers offset! 233 */ 234 static __inline int 235 ep_w1_reg(sc, reg) 236 struct ep_softc *sc; 237 int reg; 238 { 239 240 switch (sc->ep_chipset) { 241 case EP_CHIPSET_CORKSCREW: 242 return (reg + 0x10); 243 244 case EP_CHIPSET_ROADRUNNER: 245 switch (reg) { 246 case EP_W1_FREE_TX: 247 case EP_W1_RUNNER_RDCTL: 248 case EP_W1_RUNNER_WRCTL: 249 return (reg); 250 } 251 return (reg + 0x10); 252 } 253 254 return (reg); 255 } 256 257 /* 258 * Issue a (reset) command, and be sure it has completed. 259 * Used for commands that reset part or all of the board. 260 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 261 * but older hardware doesn't implement it and we must delay. 262 * It's easiest to just delay always. 263 */ 264 static inline void 265 ep_complete_cmd(sc, cmd, arg) 266 struct ep_softc *sc; 267 u_int cmd, arg; 268 { 269 register bus_space_tag_t iot = sc->sc_iot; 270 register bus_space_handle_t ioh = sc->sc_ioh; 271 272 bus_space_write_2(iot, ioh, cmd, arg); 273 274 #ifdef notyet 275 /* if this adapter family has S_COMMAND_IN_PROGRESS, use it */ 276 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 277 ; 278 else 279 #else 280 DELAY(100000); /* need at least 1 ms, but be generous. */ 281 #endif 282 } 283 284 /* 285 * Back-end attach and configure. 286 */ 287 void 288 epconfig(sc, chipset, enaddr) 289 struct ep_softc *sc; 290 u_short chipset; 291 u_int8_t *enaddr; 292 { 293 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 294 bus_space_tag_t iot = sc->sc_iot; 295 bus_space_handle_t ioh = sc->sc_ioh; 296 u_int16_t i; 297 u_int8_t myla[6]; 298 299 sc->ep_chipset = chipset; 300 301 /* 302 * We could have been groveling around in other register 303 * windows in the front-end; make sure we're in window 0 304 * to read the EEPROM. 305 */ 306 GO_WINDOW(0); 307 308 if (enaddr == NULL) { 309 /* 310 * Read the station address from the eeprom 311 */ 312 for (i = 0; i < 3; i++) { 313 u_int16_t x; 314 if (epbusyeeprom(sc)) 315 return; /* XXX why is eeprom busy? */ 316 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 317 READ_EEPROM | i); 318 if (epbusyeeprom(sc)) 319 return; /* XXX why is eeprom busy? */ 320 x = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 321 myla[(i << 1)] = x >> 8; 322 myla[(i << 1) + 1] = x; 323 } 324 enaddr = myla; 325 } 326 327 /* 328 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 329 * allow FDDI-sized (4500) byte packets. Commands only take an 330 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 331 * packet length. 332 * Commands to these cards implicitly upshift a packet size 333 * or threshold by 2 bits. 334 * To detect cards with large-packet support, we probe by setting 335 * the transmit threshold register, then change windows and 336 * read back the threshold register directly, and see if the 337 * threshold value was shifted or not. 338 */ 339 bus_space_write_2(iot, ioh, EP_COMMAND, 340 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 341 GO_WINDOW(5); 342 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 343 GO_WINDOW(1); 344 switch (i) { 345 case EP_LARGEWIN_PROBE: 346 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 347 sc->ep_pktlenshift = 0; 348 break; 349 350 case (EP_LARGEWIN_PROBE << 2): 351 sc->ep_pktlenshift = 2; 352 break; 353 354 default: 355 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 356 "Interface disabled\n", 357 sc->sc_dev.dv_xname, EP_LARGEWIN_PROBE, (int) i); 358 return; 359 } 360 361 /* 362 * Ensure Tx-available interrupts are enabled for 363 * start the interface. 364 * XXX should be in epinit()? 365 */ 366 bus_space_write_2(iot, ioh, EP_COMMAND, 367 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 368 369 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 370 ifp->if_softc = sc; 371 ifp->if_start = epstart; 372 ifp->if_ioctl = epioctl; 373 ifp->if_watchdog = epwatchdog; 374 ifp->if_flags = 375 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 376 377 if_attach(ifp); 378 ether_ifattach(ifp, enaddr); 379 380 /* 381 * Finish configuration: 382 * determine chipset if the front-end couldn't do so, 383 * show board details, set media. 384 */ 385 386 /* 387 * Print RAM size. We also print the Ethernet address in here. 388 * It's extracted from the ifp, so we have to make sure it's 389 * been attached first. 390 */ 391 ep_internalconfig(sc); 392 GO_WINDOW(0); 393 394 /* 395 * Display some additional information, if pertinent. 396 */ 397 if (sc->ep_flags & EP_FLAGS_USEFIFOBUFFER) 398 printf("%s: RoadRunner FIFO buffer enabled\n", 399 sc->sc_dev.dv_xname); 400 401 /* 402 * Initialize our media structures and MII info. We'll 403 * probe the MII if we discover that we have one. 404 */ 405 sc->sc_mii.mii_ifp = ifp; 406 sc->sc_mii.mii_readreg = ep_mii_readreg; 407 sc->sc_mii.mii_writereg = ep_mii_writereg; 408 sc->sc_mii.mii_statchg = ep_statchg; 409 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 410 ep_media_status); 411 412 /* 413 * Now, determine which media we have. 414 */ 415 switch (sc->ep_chipset) { 416 case EP_CHIPSET_BOOMERANG: 417 case EP_CHIPSET_ROADRUNNER: 418 /* 419 * If the device has MII, probe it. We won't be using 420 * any `native' media in this case, only PHYs. If 421 * we don't, just treat the Boomerang like the Vortex. 422 */ 423 if (sc->ep_flags & EP_FLAGS_MII) { 424 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 425 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 426 ifmedia_add(&sc->sc_mii.mii_media, 427 IFM_ETHER|IFM_NONE, 0, NULL); 428 ifmedia_set(&sc->sc_mii.mii_media, 429 IFM_ETHER|IFM_NONE); 430 } else { 431 ifmedia_set(&sc->sc_mii.mii_media, 432 IFM_ETHER|IFM_AUTO); 433 } 434 break; 435 } 436 /* FALLTHROUGH */ 437 438 case EP_CHIPSET_VORTEX: 439 ep_vortex_probemedia(sc); 440 break; 441 442 default: 443 ep_509_probemedia(sc); 444 break; 445 } 446 447 GO_WINDOW(1); /* Window 1 is operating window */ 448 449 #if NBPFILTER > 0 450 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 451 sizeof(struct ether_header)); 452 #endif 453 454 #if NRND > 0 455 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET); 456 #endif 457 458 sc->tx_start_thresh = 20; /* probably a good starting point. */ 459 460 /* Establish callback to reset card when we reboot. */ 461 shutdownhook_establish(epshutdown, sc); 462 463 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 464 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 465 } 466 467 468 /* 469 * Show interface-model-independent info from window 3 470 * internal-configuration register. 471 */ 472 void 473 ep_internalconfig(sc) 474 struct ep_softc *sc; 475 { 476 bus_space_tag_t iot = sc->sc_iot; 477 bus_space_handle_t ioh = sc->sc_ioh; 478 479 u_int config0; 480 u_int config1; 481 482 int ram_size, ram_width, ram_speed, rom_size, ram_split; 483 /* 484 * NVRAM buffer Rx:Tx config names for busmastering cards 485 * (Demon, Vortex, and later). 486 */ 487 const char *onboard_ram_config[] = { 488 "5:3", "3:1", "1:1", "3:5" }; 489 490 GO_WINDOW(3); 491 config0 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG); 492 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 493 GO_WINDOW(0); 494 495 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 496 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 497 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 498 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 499 500 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 501 502 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 503 sc->sc_dev.dv_xname, 504 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 505 8 << ram_size, 506 (ram_width) ? "word" : "byte", 507 onboard_ram_config[ram_split]); 508 } 509 510 511 /* 512 * Find supported media on 3c509-generation hardware that doesn't have 513 * a "reset_options" register in window 3. 514 * Use the config_cntrl register in window 0 instead. 515 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 516 * that implement CONFIG_CTRL. We don't have a good way to set the 517 * default active mediuim; punt to ifconfig instead. 518 */ 519 void 520 ep_509_probemedia(sc) 521 struct ep_softc *sc; 522 { 523 bus_space_tag_t iot = sc->sc_iot; 524 bus_space_handle_t ioh = sc->sc_ioh; 525 struct ifmedia *ifm = &sc->sc_mii.mii_media; 526 u_int16_t ep_w0_config, port; 527 struct ep_media *epm; 528 const char *sep = "", *defmedianame = NULL; 529 int defmedia = 0; 530 531 GO_WINDOW(0); 532 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 533 534 printf("%s: ", sc->sc_dev.dv_xname); 535 536 /* Sanity check that there are any media! */ 537 if ((ep_w0_config & EP_W0_CC_MEDIAMASK) == 0) { 538 printf("no media present!\n"); 539 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 540 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 541 return; 542 } 543 544 /* 545 * Get the default media from the EEPROM. 546 */ 547 if (epbusyeeprom(sc)) 548 return; /* XXX why is eeprom busy? */ 549 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 550 READ_EEPROM | EEPROM_ADDR_CFG); 551 if (epbusyeeprom(sc)) 552 return; /* XXX why is eeprom busy? */ 553 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA) >> 14; 554 555 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 556 557 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 558 if (ep_w0_config & epm->epm_mpbit) { 559 if (epm->epm_epmedia == port || defmedia == 0) { 560 defmedia = epm->epm_ifmedia; 561 defmedianame = epm->epm_name; 562 } 563 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 564 NULL); 565 PRINT(epm->epm_name); 566 } 567 } 568 569 #undef PRINT 570 571 #ifdef DIAGNOSTIC 572 if (defmedia == 0) 573 panic("ep_509_probemedia: impossible"); 574 #endif 575 576 printf(" (default %s)\n", defmedianame); 577 ifmedia_set(ifm, defmedia); 578 } 579 580 /* 581 * Find media present on large-packet-capable elink3 devices. 582 * Show onboard configuration of large-packet-capable elink3 devices 583 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 584 * Use media and card-version info in window 3 instead. 585 */ 586 void 587 ep_vortex_probemedia(sc) 588 struct ep_softc *sc; 589 { 590 bus_space_tag_t iot = sc->sc_iot; 591 bus_space_handle_t ioh = sc->sc_ioh; 592 struct ifmedia *ifm = &sc->sc_mii.mii_media; 593 struct ep_media *epm; 594 u_int config1; 595 int reset_options; 596 int default_media; /* 3-bit encoding of default (EEPROM) media */ 597 int defmedia = 0; 598 const char *sep = "", *defmedianame = NULL; 599 600 GO_WINDOW(3); 601 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 602 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 603 GO_WINDOW(0); 604 605 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 606 607 printf("%s: ", sc->sc_dev.dv_xname); 608 609 /* Sanity check that there are any media! */ 610 if ((reset_options & EP_PCI_MEDIAMASK) == 0) { 611 printf("no media present!\n"); 612 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 613 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 614 return; 615 } 616 617 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 618 619 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 620 if (reset_options & epm->epm_mpbit) { 621 if (epm->epm_epmedia == default_media || 622 defmedia == 0) { 623 defmedia = epm->epm_ifmedia; 624 defmedianame = epm->epm_name; 625 } 626 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 627 NULL); 628 PRINT(epm->epm_name); 629 } 630 } 631 632 #undef PRINT 633 634 #ifdef DIAGNOSTIC 635 if (defmedia == 0) 636 panic("ep_vortex_probemedia: impossible"); 637 #endif 638 639 printf(" (default %s)\n", defmedianame); 640 ifmedia_set(ifm, defmedia); 641 } 642 643 /* 644 * One second timer, used to tick the MII. 645 */ 646 void 647 ep_tick(arg) 648 void *arg; 649 { 650 struct ep_softc *sc = arg; 651 int s; 652 653 #ifdef DIAGNOSTIC 654 if ((sc->ep_flags & EP_FLAGS_MII) == 0) 655 panic("ep_tick"); 656 #endif 657 658 s = splnet(); 659 mii_tick(&sc->sc_mii); 660 splx(s); 661 662 timeout(ep_tick, sc, hz); 663 } 664 665 /* 666 * Bring device up. 667 * 668 * The order in here seems important. Otherwise we may not receive 669 * interrupts. ?! 670 */ 671 void 672 epinit(sc) 673 register struct ep_softc *sc; 674 { 675 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 676 bus_space_tag_t iot = sc->sc_iot; 677 bus_space_handle_t ioh = sc->sc_ioh; 678 int i; 679 680 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 681 ; 682 683 if (sc->bustype != EP_BUS_PCI) { 684 GO_WINDOW(0); 685 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 686 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 687 } 688 689 if (sc->bustype == EP_BUS_PCMCIA) { 690 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 691 } 692 693 GO_WINDOW(2); 694 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 695 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 696 LLADDR(ifp->if_sadl)[i]); 697 698 /* 699 * Reset the station-address receive filter. 700 * A bug workaround for busmastering (Vortex, Demon) cards. 701 */ 702 for (i = 0; i < 6; i++) 703 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 704 705 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 706 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 707 708 GO_WINDOW(1); /* Window 1 is operating window */ 709 for (i = 0; i < 31; i++) 710 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS)); 711 712 /* Set threshhold for for Tx-space avaiable interrupt. */ 713 bus_space_write_2(iot, ioh, EP_COMMAND, 714 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 715 716 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 717 /* 718 * Enable options in the PCMCIA LAN COR register, via 719 * RoadRunner Window 1. 720 * 721 * XXX MAGIC CONSTANTS! 722 */ 723 u_int16_t cor; 724 725 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11)); 726 727 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 728 if (sc->ep_flags & EP_FLAGS_USESHAREDMEM) 729 cor |= 0x10; 730 if (sc->ep_flags & EP_FLAGS_FORCENOWAIT) 731 cor |= 0x20; 732 bus_space_write_2(iot, ioh, 0, cor); 733 734 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 735 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 736 } 737 738 /* Enable interrupts. */ 739 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 740 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 741 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | 742 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 743 744 /* 745 * Attempt to get rid of any stray interrupts that occured during 746 * configuration. On the i386 this isn't possible because one may 747 * already be queued. However, a single stray interrupt is 748 * unimportant. 749 */ 750 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 751 752 epsetfilter(sc); 753 epsetmedia(sc); 754 755 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 756 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 757 758 epmbuffill(sc); 759 760 /* Interface is now `running', with no output active. */ 761 ifp->if_flags |= IFF_RUNNING; 762 ifp->if_flags &= ~IFF_OACTIVE; 763 764 if (sc->ep_flags & EP_FLAGS_MII) { 765 /* Start the one second clock. */ 766 timeout(ep_tick, sc, hz); 767 } 768 769 /* Attempt to start output, if any. */ 770 epstart(ifp); 771 } 772 773 774 /* 775 * Set multicast receive filter. 776 * elink3 hardware has no selective multicast filter in hardware. 777 * Enable reception of all multicasts and filter in software. 778 */ 779 void 780 epsetfilter(sc) 781 register struct ep_softc *sc; 782 { 783 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 784 785 GO_WINDOW(1); /* Window 1 is operating window */ 786 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 787 FIL_INDIVIDUAL | FIL_BRDCST | 788 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 789 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 790 } 791 792 int 793 ep_media_change(ifp) 794 struct ifnet *ifp; 795 { 796 register struct ep_softc *sc = ifp->if_softc; 797 798 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 799 epreset(sc); 800 801 return (0); 802 } 803 804 /* 805 * Set the card to use the specified media. 806 */ 807 void 808 epsetmedia(sc) 809 struct ep_softc *sc; 810 { 811 bus_space_tag_t iot = sc->sc_iot; 812 bus_space_handle_t ioh = sc->sc_ioh; 813 814 /* Turn everything off. First turn off linkbeat and UTP. */ 815 GO_WINDOW(4); 816 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 0x0); 817 818 /* Turn off coax */ 819 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 820 delay(1000); 821 822 /* 823 * If the device has MII, select it, and then tell the 824 * PHY which media to use. 825 */ 826 if (sc->ep_flags & EP_FLAGS_MII) { 827 int config0, config1; 828 829 GO_WINDOW(3); 830 831 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 832 int resopt; 833 834 resopt = bus_space_read_2(iot, ioh, 835 EP_W3_RESET_OPTIONS); 836 bus_space_write_2(iot, ioh, 837 EP_W3_RESET_OPTIONS, resopt|EP_RUNNER_ENABLE_MII); 838 } 839 840 config0 = (u_int)bus_space_read_2(iot, ioh, 841 EP_W3_INTERNAL_CONFIG); 842 config1 = (u_int)bus_space_read_2(iot, ioh, 843 EP_W3_INTERNAL_CONFIG + 2); 844 845 config1 = config1 & ~CONFIG_MEDIAMASK; 846 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 847 848 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 849 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 850 GO_WINDOW(1); /* back to operating window */ 851 852 mii_mediachg(&sc->sc_mii); 853 return; 854 } 855 856 /* 857 * Now turn on the selected media/transceiver. 858 */ 859 GO_WINDOW(4); 860 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 861 case IFM_10_T: 862 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 863 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 864 break; 865 866 case IFM_10_2: 867 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 868 DELAY(1000); /* 50ms not enmough? */ 869 break; 870 871 case IFM_100_TX: 872 case IFM_100_FX: 873 case IFM_100_T4: /* XXX check documentation */ 874 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 875 LINKBEAT_ENABLE); 876 DELAY(1000); /* not strictly necessary? */ 877 break; 878 879 case IFM_10_5: 880 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 881 SQE_ENABLE); 882 DELAY(1000); /* not strictly necessary? */ 883 break; 884 885 case IFM_MANUAL: 886 /* 887 * Nothing to do here; we are actually enabling the 888 * external PHY on the MII port. 889 */ 890 break; 891 892 case IFM_NONE: 893 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 894 return; 895 896 default: 897 panic("epsetmedia: impossible"); 898 } 899 900 /* 901 * Tell the chip which port to use. 902 */ 903 switch (sc->ep_chipset) { 904 case EP_CHIPSET_VORTEX: 905 case EP_CHIPSET_BOOMERANG: 906 { 907 int config0, config1; 908 909 GO_WINDOW(3); 910 config0 = (u_int)bus_space_read_2(iot, ioh, 911 EP_W3_INTERNAL_CONFIG); 912 config1 = (u_int)bus_space_read_2(iot, ioh, 913 EP_W3_INTERNAL_CONFIG + 2); 914 915 config1 = config1 & ~CONFIG_MEDIAMASK; 916 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 917 CONFIG_MEDIAMASK_SHIFT); 918 919 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 920 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 921 break; 922 } 923 default: 924 { 925 int w0_addr_cfg; 926 927 GO_WINDOW(0); 928 w0_addr_cfg = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 929 w0_addr_cfg &= 0x3fff; 930 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, w0_addr_cfg | 931 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 932 DELAY(1000); 933 break; 934 } 935 } 936 937 GO_WINDOW(1); /* Window 1 is operating window */ 938 } 939 940 /* 941 * Get currently-selected media from card. 942 * (if_media callback, may be called before interface is brought up). 943 */ 944 void 945 ep_media_status(ifp, req) 946 struct ifnet *ifp; 947 struct ifmediareq *req; 948 { 949 register struct ep_softc *sc = ifp->if_softc; 950 bus_space_tag_t iot = sc->sc_iot; 951 bus_space_handle_t ioh = sc->sc_ioh; 952 953 if (sc->enabled == 0) { 954 req->ifm_active = IFM_ETHER|IFM_NONE; 955 req->ifm_status = 0; 956 return; 957 } 958 959 /* 960 * If we have MII, go ask the PHY what's going on. 961 */ 962 if (sc->ep_flags & EP_FLAGS_MII) { 963 mii_pollstat(&sc->sc_mii); 964 req->ifm_active = sc->sc_mii.mii_media_active; 965 req->ifm_status = sc->sc_mii.mii_media_status; 966 return; 967 } 968 969 /* 970 * Ok, at this point we claim that our active media is 971 * the currently selected media. We'll update our status 972 * if our chipset allows us to detect link. 973 */ 974 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 975 req->ifm_status = 0; 976 977 switch (sc->ep_chipset) { 978 case EP_CHIPSET_VORTEX: 979 case EP_CHIPSET_BOOMERANG: 980 GO_WINDOW(4); 981 req->ifm_status = IFM_AVALID; 982 if (bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE) & 983 LINKBEAT_DETECT) 984 req->ifm_status |= IFM_ACTIVE; 985 GO_WINDOW(1); /* back to operating window */ 986 break; 987 } 988 } 989 990 991 992 /* 993 * Start outputting on the interface. 994 * Always called as splnet(). 995 */ 996 void 997 epstart(ifp) 998 struct ifnet *ifp; 999 { 1000 register struct ep_softc *sc = ifp->if_softc; 1001 bus_space_tag_t iot = sc->sc_iot; 1002 bus_space_handle_t ioh = sc->sc_ioh; 1003 struct mbuf *m, *m0; 1004 int sh, len, pad; 1005 bus_addr_t txreg; 1006 1007 /* Don't transmit if interface is busy or not running */ 1008 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1009 return; 1010 1011 startagain: 1012 /* Sneak a peek at the next packet */ 1013 m0 = ifp->if_snd.ifq_head; 1014 if (m0 == 0) 1015 return; 1016 1017 /* We need to use m->m_pkthdr.len, so require the header */ 1018 if ((m0->m_flags & M_PKTHDR) == 0) 1019 panic("epstart: no header mbuf"); 1020 len = m0->m_pkthdr.len; 1021 1022 pad = (4 - len) & 3; 1023 1024 /* 1025 * The 3c509 automatically pads short packets to minimum ethernet 1026 * length, but we drop packets that are too large. Perhaps we should 1027 * truncate them instead? 1028 */ 1029 if (len + pad > ETHER_MAX_LEN) { 1030 /* packet is obviously too large: toss it */ 1031 ++ifp->if_oerrors; 1032 IF_DEQUEUE(&ifp->if_snd, m0); 1033 m_freem(m0); 1034 goto readcheck; 1035 } 1036 1037 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) < 1038 len + pad + 4) { 1039 bus_space_write_2(iot, ioh, EP_COMMAND, 1040 SET_TX_AVAIL_THRESH | 1041 ((len + pad + 4) >> sc->ep_pktlenshift)); 1042 /* not enough room in FIFO */ 1043 ifp->if_flags |= IFF_OACTIVE; 1044 return; 1045 } else { 1046 bus_space_write_2(iot, ioh, EP_COMMAND, 1047 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE ); 1048 } 1049 1050 IF_DEQUEUE(&ifp->if_snd, m0); 1051 if (m0 == 0) /* not really needed */ 1052 return; 1053 1054 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 1055 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/) ); 1056 1057 #if NBPFILTER > 0 1058 if (ifp->if_bpf) 1059 bpf_mtap(ifp->if_bpf, m0); 1060 #endif 1061 1062 /* 1063 * Do the output at splhigh() so that an interrupt from another device 1064 * won't cause a FIFO underrun. 1065 */ 1066 sh = splhigh(); 1067 1068 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1); 1069 1070 if (sc->ep_flags & EP_FLAGS_USEFIFOBUFFER) { 1071 /* 1072 * Prime the FIFO buffer counter (number of 16-bit 1073 * words about to be written to the FIFO). 1074 * 1075 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1076 * COUNTER IS NON-ZERO! 1077 */ 1078 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 1079 (len + pad) >> 1); 1080 } 1081 1082 bus_space_write_2(iot, ioh, txreg, len); 1083 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1084 if (EP_IS_BUS_32(sc->bustype)) { 1085 for (m = m0; m; ) { 1086 if (m->m_len > 3) { 1087 /* align our reads from core */ 1088 if (mtod(m, u_long) & 3) { 1089 u_long count = 1090 4 - (mtod(m, u_long) & 3); 1091 bus_space_write_multi_1(iot, ioh, 1092 txreg, mtod(m, u_int8_t *), count); 1093 m->m_data = 1094 (void *)(mtod(m, u_long) + count); 1095 m->m_len -= count; 1096 } 1097 bus_space_write_multi_4(iot, ioh, 1098 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1099 m->m_data = (void *)(mtod(m, u_long) + 1100 (u_long)(m->m_len & ~3)); 1101 m->m_len -= m->m_len & ~3; 1102 } 1103 if (m->m_len) { 1104 bus_space_write_multi_1(iot, ioh, 1105 txreg, mtod(m, u_int8_t *), m->m_len); 1106 } 1107 MFREE(m, m0); 1108 m = m0; 1109 } 1110 } else { 1111 for (m = m0; m; ) { 1112 if (m->m_len > 1) { 1113 if (mtod(m, u_long) & 1) { 1114 bus_space_write_1(iot, ioh, 1115 txreg, *(mtod(m, u_int8_t *))); 1116 m->m_data = 1117 (void *)(mtod(m, u_long) + 1); 1118 m->m_len -= 1; 1119 } 1120 bus_space_write_multi_2(iot, ioh, 1121 txreg, mtod(m, u_int16_t *), 1122 m->m_len >> 1); 1123 } 1124 if (m->m_len & 1) { 1125 bus_space_write_1(iot, ioh, txreg, 1126 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1127 } 1128 MFREE(m, m0); 1129 m = m0; 1130 } 1131 } 1132 while (pad--) 1133 bus_space_write_1(iot, ioh, txreg, 0); 1134 1135 splx(sh); 1136 1137 ++ifp->if_opackets; 1138 1139 readcheck: 1140 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) & 1141 ERR_INCOMPLETE) == 0) { 1142 /* We received a complete packet. */ 1143 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1144 1145 if ((status & S_INTR_LATCH) == 0) { 1146 /* 1147 * No interrupt, read the packet and continue 1148 * Is this supposed to happen? Is my motherboard 1149 * completely busted? 1150 */ 1151 epread(sc); 1152 } else { 1153 /* Got an interrupt, return so that it gets serviced. */ 1154 return; 1155 } 1156 } else { 1157 /* Check if we are stuck and reset [see XXX comment] */ 1158 if (epstatus(sc)) { 1159 if (ifp->if_flags & IFF_DEBUG) 1160 printf("%s: adapter reset\n", 1161 sc->sc_dev.dv_xname); 1162 epreset(sc); 1163 } 1164 } 1165 1166 goto startagain; 1167 } 1168 1169 1170 /* 1171 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1172 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1173 * We detect this situation and we reset the adapter. 1174 * It happens at times when there is a lot of broadcast traffic 1175 * on the cable (once in a blue moon). 1176 */ 1177 static int 1178 epstatus(sc) 1179 register struct ep_softc *sc; 1180 { 1181 bus_space_tag_t iot = sc->sc_iot; 1182 bus_space_handle_t ioh = sc->sc_ioh; 1183 u_int16_t fifost; 1184 1185 /* 1186 * Check the FIFO status and act accordingly 1187 */ 1188 GO_WINDOW(4); 1189 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1190 GO_WINDOW(1); 1191 1192 if (fifost & FIFOS_RX_UNDERRUN) { 1193 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1194 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1195 epreset(sc); 1196 return 0; 1197 } 1198 1199 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1200 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1201 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1202 return 1; 1203 } 1204 1205 if (fifost & FIFOS_RX_OVERRUN) { 1206 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1207 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1208 return 1; 1209 } 1210 1211 if (fifost & FIFOS_TX_OVERRUN) { 1212 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1213 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1214 epreset(sc); 1215 return 0; 1216 } 1217 1218 return 0; 1219 } 1220 1221 1222 static void 1223 eptxstat(sc) 1224 register struct ep_softc *sc; 1225 { 1226 bus_space_tag_t iot = sc->sc_iot; 1227 bus_space_handle_t ioh = sc->sc_ioh; 1228 int i; 1229 1230 /* 1231 * We need to read+write TX_STATUS until we get a 0 status 1232 * in order to turn off the interrupt flag. 1233 */ 1234 while ((i = bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS))) 1235 & TXS_COMPLETE) { 1236 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS), 1237 0x0); 1238 1239 if (i & TXS_JABBER) { 1240 ++sc->sc_ethercom.ec_if.if_oerrors; 1241 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1242 printf("%s: jabber (%x)\n", 1243 sc->sc_dev.dv_xname, i); 1244 epreset(sc); 1245 } else if (i & TXS_UNDERRUN) { 1246 ++sc->sc_ethercom.ec_if.if_oerrors; 1247 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1248 printf("%s: fifo underrun (%x) @%d\n", 1249 sc->sc_dev.dv_xname, i, 1250 sc->tx_start_thresh); 1251 if (sc->tx_succ_ok < 100) 1252 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1253 sc->tx_start_thresh + 20); 1254 sc->tx_succ_ok = 0; 1255 epreset(sc); 1256 } else if (i & TXS_MAX_COLLISION) { 1257 ++sc->sc_ethercom.ec_if.if_collisions; 1258 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1259 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1260 } else 1261 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1262 } 1263 } 1264 1265 int 1266 epintr(arg) 1267 void *arg; 1268 { 1269 register struct ep_softc *sc = arg; 1270 bus_space_tag_t iot = sc->sc_iot; 1271 bus_space_handle_t ioh = sc->sc_ioh; 1272 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1273 u_int16_t status; 1274 int ret = 0; 1275 int addrandom = 0; 1276 1277 if (sc->enabled == 0) 1278 return (0); 1279 1280 for (;;) { 1281 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1282 1283 status = bus_space_read_2(iot, ioh, EP_STATUS); 1284 1285 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1286 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1287 if ((status & S_INTR_LATCH) == 0) { 1288 #if 0 1289 printf("%s: intr latch cleared\n", 1290 sc->sc_dev.dv_xname); 1291 #endif 1292 break; 1293 } 1294 } 1295 1296 ret = 1; 1297 1298 /* 1299 * Acknowledge any interrupts. It's important that we do this 1300 * first, since there would otherwise be a race condition. 1301 * Due to the i386 interrupt queueing, we may get spurious 1302 * interrupts occasionally. 1303 */ 1304 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 1305 (status & (C_INTR_LATCH | 1306 C_CARD_FAILURE | 1307 C_TX_COMPLETE | 1308 C_TX_AVAIL | 1309 C_RX_COMPLETE | 1310 C_RX_EARLY | 1311 C_INT_RQD | 1312 C_UPD_STATS))); 1313 1314 #if 0 1315 status = bus_space_read_2(iot, ioh, EP_STATUS); 1316 1317 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1318 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1319 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1320 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1321 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1322 #endif 1323 1324 if (status & S_RX_COMPLETE) { 1325 epread(sc); 1326 addrandom = 1; 1327 } 1328 if (status & S_TX_AVAIL) { 1329 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1330 epstart(&sc->sc_ethercom.ec_if); 1331 addrandom = 1; 1332 } 1333 if (status & S_CARD_FAILURE) { 1334 printf("%s: adapter failure (%x)\n", 1335 sc->sc_dev.dv_xname, status); 1336 epreset(sc); 1337 return (1); 1338 } 1339 if (status & S_TX_COMPLETE) { 1340 eptxstat(sc); 1341 epstart(ifp); 1342 addrandom = 1; 1343 } 1344 1345 #if NRND > 0 1346 if (status) 1347 rnd_add_uint32(&sc->rnd_source, status); 1348 #endif 1349 } 1350 1351 /* no more interrupts */ 1352 return (ret); 1353 } 1354 1355 void 1356 epread(sc) 1357 register struct ep_softc *sc; 1358 { 1359 bus_space_tag_t iot = sc->sc_iot; 1360 bus_space_handle_t ioh = sc->sc_ioh; 1361 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1362 struct mbuf *m; 1363 struct ether_header *eh; 1364 int len; 1365 1366 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)); 1367 1368 again: 1369 if (ifp->if_flags & IFF_DEBUG) { 1370 int err = len & ERR_MASK; 1371 char *s = NULL; 1372 1373 if (len & ERR_INCOMPLETE) 1374 s = "incomplete packet"; 1375 else if (err == ERR_OVERRUN) 1376 s = "packet overrun"; 1377 else if (err == ERR_RUNT) 1378 s = "runt packet"; 1379 else if (err == ERR_ALIGNMENT) 1380 s = "bad alignment"; 1381 else if (err == ERR_CRC) 1382 s = "bad crc"; 1383 else if (err == ERR_OVERSIZE) 1384 s = "oversized packet"; 1385 else if (err == ERR_DRIBBLE) 1386 s = "dribble bits"; 1387 1388 if (s) 1389 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1390 } 1391 1392 if (len & ERR_INCOMPLETE) 1393 return; 1394 1395 if (len & ERR_RX) { 1396 ++ifp->if_ierrors; 1397 goto abort; 1398 } 1399 1400 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1401 1402 /* Pull packet off interface. */ 1403 m = epget(sc, len); 1404 if (m == 0) { 1405 ifp->if_ierrors++; 1406 goto abort; 1407 } 1408 1409 ++ifp->if_ipackets; 1410 1411 /* We assume the header fit entirely in one mbuf. */ 1412 eh = mtod(m, struct ether_header *); 1413 1414 #if NBPFILTER > 0 1415 /* 1416 * Check if there's a BPF listener on this interface. 1417 * If so, hand off the raw packet to BPF. 1418 */ 1419 if (ifp->if_bpf) { 1420 bpf_mtap(ifp->if_bpf, m); 1421 1422 /* 1423 * Note that the interface cannot be in promiscuous mode if 1424 * there are no BPF listeners. And if we are in promiscuous 1425 * mode, we have to check if this packet is really ours. 1426 */ 1427 if ((ifp->if_flags & IFF_PROMISC) && 1428 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1429 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1430 sizeof(eh->ether_dhost)) != 0) { 1431 m_freem(m); 1432 return; 1433 } 1434 } 1435 #endif 1436 1437 /* We assume the header fit entirely in one mbuf. */ 1438 m_adj(m, sizeof(struct ether_header)); 1439 ether_input(ifp, eh, m); 1440 1441 /* 1442 * In periods of high traffic we can actually receive enough 1443 * packets so that the fifo overrun bit will be set at this point, 1444 * even though we just read a packet. In this case we 1445 * are not going to receive any more interrupts. We check for 1446 * this condition and read again until the fifo is not full. 1447 * We could simplify this test by not using epstatus(), but 1448 * rechecking the RX_STATUS register directly. This test could 1449 * result in unnecessary looping in cases where there is a new 1450 * packet but the fifo is not full, but it will not fix the 1451 * stuck behavior. 1452 * 1453 * Even with this improvement, we still get packet overrun errors 1454 * which are hurting performance. Maybe when I get some more time 1455 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1456 */ 1457 if (epstatus(sc)) { 1458 len = bus_space_read_2(iot, ioh, 1459 ep_w1_reg(sc, EP_W1_RX_STATUS)); 1460 /* Check if we are stuck and reset [see XXX comment] */ 1461 if (len & ERR_INCOMPLETE) { 1462 if (ifp->if_flags & IFF_DEBUG) 1463 printf("%s: adapter reset\n", 1464 sc->sc_dev.dv_xname); 1465 epreset(sc); 1466 return; 1467 } 1468 goto again; 1469 } 1470 1471 return; 1472 1473 abort: 1474 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1475 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1476 ; 1477 } 1478 1479 struct mbuf * 1480 epget(sc, totlen) 1481 struct ep_softc *sc; 1482 int totlen; 1483 { 1484 bus_space_tag_t iot = sc->sc_iot; 1485 bus_space_handle_t ioh = sc->sc_ioh; 1486 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1487 struct mbuf *top, **mp, *m, *rv = NULL; 1488 bus_addr_t rxreg; 1489 int len, remaining; 1490 int sh; 1491 1492 m = sc->mb[sc->next_mb]; 1493 sc->mb[sc->next_mb] = 0; 1494 if (m == 0) { 1495 MGETHDR(m, M_DONTWAIT, MT_DATA); 1496 if (m == 0) 1497 return 0; 1498 } else { 1499 /* If the queue is no longer full, refill. */ 1500 if (sc->last_mb == sc->next_mb) 1501 timeout(epmbuffill, sc, 1); 1502 /* Convert one of our saved mbuf's. */ 1503 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1504 m->m_data = m->m_pktdat; 1505 m->m_flags = M_PKTHDR; 1506 } 1507 m->m_pkthdr.rcvif = ifp; 1508 m->m_pkthdr.len = totlen; 1509 len = MHLEN; 1510 top = 0; 1511 mp = ⊤ 1512 1513 /* 1514 * We read the packet at splhigh() so that an interrupt from another 1515 * device doesn't cause the card's buffer to overflow while we're 1516 * reading it. We may still lose packets at other times. 1517 */ 1518 sh = splhigh(); 1519 1520 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1); 1521 1522 if (sc->ep_flags & EP_FLAGS_USEFIFOBUFFER) { 1523 /* 1524 * Prime the FIFO buffer counter (number of 16-bit 1525 * words about to be read from the FIFO). 1526 * 1527 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1528 * COUNTER IS NON-ZERO! 1529 */ 1530 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, totlen >> 1); 1531 } 1532 1533 while (totlen > 0) { 1534 if (top) { 1535 m = sc->mb[sc->next_mb]; 1536 sc->mb[sc->next_mb] = 0; 1537 if (m == 0) { 1538 MGET(m, M_DONTWAIT, MT_DATA); 1539 if (m == 0) { 1540 m_freem(top); 1541 goto out; 1542 } 1543 } else { 1544 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1545 } 1546 len = MLEN; 1547 } 1548 if (totlen >= MINCLSIZE) { 1549 MCLGET(m, M_DONTWAIT); 1550 if ((m->m_flags & M_EXT) == 0) { 1551 m_free(m); 1552 m_freem(top); 1553 goto out; 1554 } 1555 len = MCLBYTES; 1556 } 1557 if (top == 0) { 1558 /* align the struct ip header */ 1559 caddr_t newdata = (caddr_t) 1560 ALIGN(m->m_data + sizeof(struct ether_header)) 1561 - sizeof(struct ether_header); 1562 len -= newdata - m->m_data; 1563 m->m_data = newdata; 1564 } 1565 remaining = len = min(totlen, len); 1566 if (EP_IS_BUS_32(sc->bustype)) { 1567 u_long offset = mtod(m, u_long); 1568 /* 1569 * Read bytes up to the point where we are aligned. 1570 * (We can align to 4 bytes, rather than ALIGNBYTES, 1571 * here because we're later reading 4-byte chunks.) 1572 */ 1573 if ((remaining > 3) && (offset & 3)) { 1574 int count = (4 - (offset & 3)); 1575 bus_space_read_multi_1(iot, ioh, 1576 rxreg, (u_int8_t *) offset, count); 1577 offset += count; 1578 remaining -= count; 1579 } 1580 if (remaining > 3) { 1581 bus_space_read_multi_4(iot, ioh, 1582 rxreg, (u_int32_t *) offset, 1583 remaining >> 2); 1584 offset += remaining & ~3; 1585 remaining &= 3; 1586 } 1587 if (remaining) { 1588 bus_space_read_multi_1(iot, ioh, 1589 rxreg, (u_int8_t *) offset, remaining); 1590 } 1591 } else { 1592 u_long offset = mtod(m, u_long); 1593 if ((remaining > 1) && (offset & 1)) { 1594 bus_space_read_multi_1(iot, ioh, 1595 rxreg, (u_int8_t *) offset, 1); 1596 remaining -= 1; 1597 offset += 1; 1598 } 1599 if (remaining > 1) { 1600 bus_space_read_multi_2(iot, ioh, 1601 rxreg, (u_int16_t *) offset, 1602 remaining >> 1); 1603 offset += remaining & ~1; 1604 } 1605 if (remaining & 1) { 1606 bus_space_read_multi_1(iot, ioh, 1607 rxreg, (u_int8_t *) offset, remaining & 1); 1608 } 1609 } 1610 m->m_len = len; 1611 totlen -= len; 1612 *mp = m; 1613 mp = &m->m_next; 1614 } 1615 1616 rv = top; 1617 1618 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1619 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1620 ; 1621 1622 out: 1623 if (sc->ep_flags & EP_FLAGS_USEFIFOBUFFER) 1624 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1625 splx(sh); 1626 1627 return rv; 1628 } 1629 1630 int 1631 epioctl(ifp, cmd, data) 1632 register struct ifnet *ifp; 1633 u_long cmd; 1634 caddr_t data; 1635 { 1636 struct ep_softc *sc = ifp->if_softc; 1637 struct ifaddr *ifa = (struct ifaddr *)data; 1638 struct ifreq *ifr = (struct ifreq *)data; 1639 int s, error = 0; 1640 1641 s = splnet(); 1642 1643 switch (cmd) { 1644 1645 case SIOCSIFADDR: 1646 if ((error = epenable(sc)) != 0) 1647 break; 1648 /* epinit is called just below */ 1649 ifp->if_flags |= IFF_UP; 1650 switch (ifa->ifa_addr->sa_family) { 1651 #ifdef INET 1652 case AF_INET: 1653 epinit(sc); 1654 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1655 break; 1656 #endif 1657 #ifdef NS 1658 case AF_NS: 1659 { 1660 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1661 1662 if (ns_nullhost(*ina)) 1663 ina->x_host = *(union ns_host *) 1664 LLADDR(ifp->if_sadl); 1665 else 1666 bcopy(ina->x_host.c_host, 1667 LLADDR(ifp->if_sadl), 1668 ifp->if_addrlen); 1669 /* Set new address. */ 1670 epinit(sc); 1671 break; 1672 } 1673 #endif 1674 default: 1675 epinit(sc); 1676 break; 1677 } 1678 break; 1679 1680 case SIOCSIFMEDIA: 1681 case SIOCGIFMEDIA: 1682 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1683 break; 1684 1685 case SIOCSIFFLAGS: 1686 if ((ifp->if_flags & IFF_UP) == 0 && 1687 (ifp->if_flags & IFF_RUNNING) != 0) { 1688 /* 1689 * If interface is marked down and it is running, then 1690 * stop it. 1691 */ 1692 epstop(sc); 1693 ifp->if_flags &= ~IFF_RUNNING; 1694 epdisable(sc); 1695 } else if ((ifp->if_flags & IFF_UP) != 0 && 1696 (ifp->if_flags & IFF_RUNNING) == 0) { 1697 /* 1698 * If interface is marked up and it is stopped, then 1699 * start it. 1700 */ 1701 if ((error = epenable(sc)) != 0) 1702 break; 1703 epinit(sc); 1704 } else if (sc->enabled) { 1705 /* 1706 * deal with flags changes: 1707 * IFF_MULTICAST, IFF_PROMISC. 1708 */ 1709 epsetfilter(sc); 1710 } 1711 break; 1712 1713 case SIOCADDMULTI: 1714 case SIOCDELMULTI: 1715 if (sc->enabled == 0) { 1716 error = EIO; 1717 break; 1718 } 1719 1720 error = (cmd == SIOCADDMULTI) ? 1721 ether_addmulti(ifr, &sc->sc_ethercom) : 1722 ether_delmulti(ifr, &sc->sc_ethercom); 1723 1724 if (error == ENETRESET) { 1725 /* 1726 * Multicast list has changed; set the hardware filter 1727 * accordingly. 1728 */ 1729 epreset(sc); 1730 error = 0; 1731 } 1732 break; 1733 1734 default: 1735 error = EINVAL; 1736 break; 1737 } 1738 1739 splx(s); 1740 return (error); 1741 } 1742 1743 void 1744 epreset(sc) 1745 struct ep_softc *sc; 1746 { 1747 int s; 1748 1749 s = splnet(); 1750 epstop(sc); 1751 epinit(sc); 1752 splx(s); 1753 } 1754 1755 void 1756 epwatchdog(ifp) 1757 struct ifnet *ifp; 1758 { 1759 struct ep_softc *sc = ifp->if_softc; 1760 1761 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1762 ++sc->sc_ethercom.ec_if.if_oerrors; 1763 1764 epreset(sc); 1765 } 1766 1767 void 1768 epstop(sc) 1769 register struct ep_softc *sc; 1770 { 1771 bus_space_tag_t iot = sc->sc_iot; 1772 bus_space_handle_t ioh = sc->sc_ioh; 1773 1774 if (sc->ep_flags & EP_FLAGS_MII) { 1775 /* Stop the one second clock. */ 1776 untimeout(ep_tick, sc); 1777 } 1778 1779 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 1780 /* 1781 * Clear the FIFO buffer count, thus halting 1782 * any currently-running transactions. 1783 */ 1784 GO_WINDOW(1); /* sanity */ 1785 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 1786 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1787 } 1788 1789 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1790 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1791 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1792 ; 1793 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1794 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1795 1796 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 1797 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 1798 1799 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1800 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1801 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1802 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1803 1804 epmbufempty(sc); 1805 } 1806 1807 1808 /* 1809 * Before reboots, reset card completely. 1810 */ 1811 static void 1812 epshutdown(arg) 1813 void *arg; 1814 { 1815 register struct ep_softc *sc = arg; 1816 1817 if (sc->enabled) { 1818 epstop(sc); 1819 ep_complete_cmd(sc, EP_COMMAND, GLOBAL_RESET); 1820 } 1821 } 1822 1823 /* 1824 * We get eeprom data from the id_port given an offset into the 1825 * eeprom. Basically; after the ID_sequence is sent to all of 1826 * the cards; they enter the ID_CMD state where they will accept 1827 * command requests. 0x80-0xbf loads the eeprom data. We then 1828 * read the port 16 times and with every read; the cards check 1829 * for contention (ie: if one card writes a 0 bit and another 1830 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1831 * each card compares the data on the bus; if there is a difference 1832 * then that card goes into ID_WAIT state again). In the meantime; 1833 * one bit of data is returned in the AX register which is conveniently 1834 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1835 * bit of data with each read. 1836 * 1837 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1838 */ 1839 u_int16_t 1840 epreadeeprom(iot, ioh, offset) 1841 bus_space_tag_t iot; 1842 bus_space_handle_t ioh; 1843 int offset; 1844 { 1845 u_int16_t data = 0; 1846 int i; 1847 1848 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1849 delay(1000); 1850 for (i = 0; i < 16; i++) 1851 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1852 return (data); 1853 } 1854 1855 static int 1856 epbusyeeprom(sc) 1857 struct ep_softc *sc; 1858 { 1859 bus_space_tag_t iot = sc->sc_iot; 1860 bus_space_handle_t ioh = sc->sc_ioh; 1861 int i = 100, j; 1862 1863 if (sc->bustype == EP_BUS_PCMCIA) { 1864 delay(1000); 1865 return 0; 1866 } 1867 1868 j = 0; /* bad GCC flow analysis */ 1869 while (i--) { 1870 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1871 if (j & EEPROM_BUSY) 1872 delay(100); 1873 else 1874 break; 1875 } 1876 if (!i) { 1877 printf("\n%s: eeprom failed to come ready\n", 1878 sc->sc_dev.dv_xname); 1879 return (1); 1880 } 1881 if (j & EEPROM_TST_MODE) { 1882 /* XXX PnP mode? */ 1883 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1884 return (1); 1885 } 1886 return (0); 1887 } 1888 1889 void 1890 epmbuffill(v) 1891 void *v; 1892 { 1893 struct ep_softc *sc = v; 1894 int s, i; 1895 1896 s = splnet(); 1897 i = sc->last_mb; 1898 do { 1899 if (sc->mb[i] == NULL) 1900 MGET(sc->mb[i], M_DONTWAIT, MT_DATA); 1901 if (sc->mb[i] == NULL) 1902 break; 1903 i = (i + 1) % MAX_MBS; 1904 } while (i != sc->next_mb); 1905 sc->last_mb = i; 1906 /* If the queue was not filled, try again. */ 1907 if (sc->last_mb != sc->next_mb) 1908 timeout(epmbuffill, sc, 1); 1909 splx(s); 1910 } 1911 1912 void 1913 epmbufempty(sc) 1914 struct ep_softc *sc; 1915 { 1916 int s, i; 1917 1918 s = splnet(); 1919 for (i = 0; i<MAX_MBS; i++) { 1920 if (sc->mb[i]) { 1921 m_freem(sc->mb[i]); 1922 sc->mb[i] = NULL; 1923 } 1924 } 1925 sc->last_mb = sc->next_mb = 0; 1926 untimeout(epmbuffill, sc); 1927 splx(s); 1928 } 1929 1930 int 1931 epenable(sc) 1932 struct ep_softc *sc; 1933 { 1934 1935 if (sc->enabled == 0 && sc->enable != NULL) { 1936 if ((*sc->enable)(sc) != 0) { 1937 printf("%s: device enable failed\n", 1938 sc->sc_dev.dv_xname); 1939 return (EIO); 1940 } 1941 } 1942 1943 sc->enabled = 1; 1944 return (0); 1945 } 1946 1947 void 1948 epdisable(sc) 1949 struct ep_softc *sc; 1950 { 1951 1952 if (sc->enabled != 0 && sc->disable != NULL) { 1953 (*sc->disable)(sc); 1954 sc->enabled = 0; 1955 } 1956 } 1957 1958 void 1959 ep_mii_setbit(sc, bit) 1960 struct ep_softc *sc; 1961 u_int16_t bit; 1962 { 1963 u_int16_t val; 1964 1965 /* We assume we're already in Window 4 */ 1966 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1967 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1968 val | bit); 1969 } 1970 1971 void 1972 ep_mii_clrbit(sc, bit) 1973 struct ep_softc *sc; 1974 u_int16_t bit; 1975 { 1976 u_int16_t val; 1977 1978 /* We assume we're already in Window 4 */ 1979 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1980 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1981 val & ~bit); 1982 } 1983 1984 u_int16_t 1985 ep_mii_readbit(sc, bit) 1986 struct ep_softc *sc; 1987 u_int16_t bit; 1988 { 1989 1990 /* We assume we're already in Window 4 */ 1991 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 1992 bit); 1993 } 1994 1995 void 1996 ep_mii_sync(sc) 1997 struct ep_softc *sc; 1998 { 1999 int i; 2000 2001 /* We assume we're already in Window 4 */ 2002 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2003 for (i = 0; i < 32; i++) { 2004 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2005 ep_mii_setbit(sc, PHYSMGMT_CLK); 2006 } 2007 } 2008 2009 void 2010 ep_mii_sendbits(sc, data, nbits) 2011 struct ep_softc *sc; 2012 u_int32_t data; 2013 int nbits; 2014 { 2015 int i; 2016 2017 /* We assume we're already in Window 4 */ 2018 ep_mii_setbit(sc, PHYSMGMT_DIR); 2019 for (i = 1 << (nbits - 1); i; i = i >> 1) { 2020 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2021 ep_mii_readbit(sc, PHYSMGMT_CLK); 2022 if (data & i) 2023 ep_mii_setbit(sc, PHYSMGMT_DATA); 2024 else 2025 ep_mii_clrbit(sc, PHYSMGMT_DATA); 2026 ep_mii_setbit(sc, PHYSMGMT_CLK); 2027 ep_mii_readbit(sc, PHYSMGMT_CLK); 2028 } 2029 } 2030 2031 int 2032 ep_mii_readreg(self, phy, reg) 2033 struct device *self; 2034 int phy, reg; 2035 { 2036 struct ep_softc *sc = (struct ep_softc *)self; 2037 int val = 0, i, err; 2038 2039 /* 2040 * Read the PHY register by manually driving the MII control lines. 2041 */ 2042 2043 GO_WINDOW(4); 2044 2045 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 2046 2047 ep_mii_sync(sc); 2048 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2049 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 2050 ep_mii_sendbits(sc, phy, 5); 2051 ep_mii_sendbits(sc, reg, 5); 2052 2053 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2054 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2055 ep_mii_setbit(sc, PHYSMGMT_CLK); 2056 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2057 2058 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 2059 ep_mii_setbit(sc, PHYSMGMT_CLK); 2060 2061 /* Even if an error occurs, must still clock out the cycle. */ 2062 for (i = 0; i < 16; i++) { 2063 val <<= 1; 2064 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2065 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 2066 val |= 1; 2067 ep_mii_setbit(sc, PHYSMGMT_CLK); 2068 } 2069 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2070 ep_mii_setbit(sc, PHYSMGMT_CLK); 2071 2072 GO_WINDOW(1); /* back to operating window */ 2073 2074 return (err ? 0 : val); 2075 } 2076 2077 void 2078 ep_mii_writereg(self, phy, reg, val) 2079 struct device *self; 2080 int phy, reg, val; 2081 { 2082 struct ep_softc *sc = (struct ep_softc *)self; 2083 2084 /* 2085 * Write the PHY register by manually driving the MII control lines. 2086 */ 2087 2088 GO_WINDOW(4); 2089 2090 ep_mii_sync(sc); 2091 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2092 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2093 ep_mii_sendbits(sc, phy, 5); 2094 ep_mii_sendbits(sc, reg, 5); 2095 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2096 ep_mii_sendbits(sc, val, 16); 2097 2098 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2099 ep_mii_setbit(sc, PHYSMGMT_CLK); 2100 2101 GO_WINDOW(1); /* back to operating window */ 2102 } 2103 2104 void 2105 ep_statchg(self) 2106 struct device *self; 2107 { 2108 2109 /* XXX Update ifp->if_baudrate */ 2110 /* XXX Full-duplex control in MAC? */ 2111 } 2112
Indexes created Fri Sep 26 20:09:58 GMT 2025