elink3.c revision 1.46
1 /* $NetBSD: elink3.c,v 1.46 1998/08/28 18:16:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #define ETHER_MIN_LEN 64 124 #define ETHER_MAX_LEN 1518 125 #define ETHER_ADDR_LEN 6 126 127 #ifdef DEBUG 128 int epdebug = 0; 129 #endif 130 131 /* 132 * Structure to map media-present bits in boards to ifmedia codes and 133 * printable media names. Used for table-driven ifmedia initialization. 134 */ 135 struct ep_media { 136 int epm_mpbit; /* media present bit */ 137 const char *epm_name; /* name of medium */ 138 int epm_ifmedia; /* ifmedia word for medium */ 139 int epm_epmedia; /* EPMEDIA_* constant */ 140 }; 141 142 /* 143 * Media table for the Demon/Vortex/Boomerang chipsets. 144 * 145 * Note that MII on the Demon and Vortex (3c59x) indicates an external 146 * MII connector (for connecting an external PHY) ... I think. Treat 147 * it as `manual' on these chips. 148 * 149 * Any Boomerang (3c90x) chips with MII really do have an internal 150 * MII and real PHYs attached; no `native' media. 151 */ 152 struct ep_media ep_vortex_media[] = { 153 { EP_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 154 EPMEDIA_10BASE_T }, 155 { EP_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 156 EPMEDIA_10BASE_T }, 157 { EP_PCI_AUI, "10base5/AUI", IFM_ETHER|IFM_10_5, 158 EPMEDIA_AUI }, 159 { EP_PCI_BNC, "10base2/BNC", IFM_ETHER|IFM_10_2, 160 EPMEDIA_10BASE_2 }, 161 { EP_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 162 EPMEDIA_100BASE_TX }, 163 { EP_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 164 EPMEDIA_100BASE_TX }, 165 { EP_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 166 EPMEDIA_100BASE_FX }, 167 { EP_PCI_100BASE_MII, "manual", IFM_ETHER|IFM_MANUAL, 168 EPMEDIA_MII }, 169 { EP_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 170 EPMEDIA_100BASE_T4 }, 171 { 0, NULL, 0, 172 0 }, 173 }; 174 175 /* 176 * Media table for the older 3Com Etherlink III chipset, used 177 * in the 3c509, 3c579, and 3c589. 178 */ 179 struct ep_media ep_509_media[] = { 180 { EP_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 181 EPMEDIA_10BASE_T }, 182 { EP_W0_CC_AUI, "10base5/AUI", IFM_ETHER|IFM_10_5, 183 EPMEDIA_AUI }, 184 { EP_W0_CC_BNC, "10base2/BNC", IFM_ETHER|IFM_10_2, 185 EPMEDIA_10BASE_2 }, 186 { 0, NULL, 0, 187 0 }, 188 }; 189 190 void ep_internalconfig __P((struct ep_softc *sc)); 191 void ep_vortex_probemedia __P((struct ep_softc *sc)); 192 void ep_509_probemedia __P((struct ep_softc *sc)); 193 194 static void eptxstat __P((struct ep_softc *)); 195 static int epstatus __P((struct ep_softc *)); 196 void epinit __P((struct ep_softc *)); 197 int epioctl __P((struct ifnet *, u_long, caddr_t)); 198 void epstart __P((struct ifnet *)); 199 void epwatchdog __P((struct ifnet *)); 200 void epreset __P((struct ep_softc *)); 201 static void epshutdown __P((void *)); 202 void epread __P((struct ep_softc *)); 203 struct mbuf *epget __P((struct ep_softc *, int)); 204 void epmbuffill __P((void *)); 205 void epmbufempty __P((struct ep_softc *)); 206 void epsetfilter __P((struct ep_softc *)); 207 void epsetmedia __P((struct ep_softc *)); 208 209 int epenable __P((struct ep_softc *)); 210 void epdisable __P((struct ep_softc *)); 211 212 /* ifmedia callbacks */ 213 int ep_media_change __P((struct ifnet *ifp)); 214 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 215 216 /* MII callbacks */ 217 int ep_mii_readreg __P((struct device *, int, int)); 218 void ep_mii_writereg __P((struct device *, int, int, int)); 219 void ep_statchg __P((struct device *)); 220 221 void ep_tick __P((void *)); 222 223 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 224 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 225 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 226 void ep_mii_sync __P((struct ep_softc *)); 227 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 228 229 static int epbusyeeprom __P((struct ep_softc *)); 230 static inline void ep_complete_cmd __P((struct ep_softc *sc, 231 u_int cmd, u_int arg)); 232 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 233 234 /* 235 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 236 * Window 1 registers offset! 237 */ 238 static __inline int 239 ep_w1_reg(sc, reg) 240 struct ep_softc *sc; 241 int reg; 242 { 243 244 switch (sc->ep_chipset) { 245 case EP_CHIPSET_CORKSCREW: 246 return (reg + 0x10); 247 248 case EP_CHIPSET_ROADRUNNER: 249 switch (reg) { 250 case EP_W1_FREE_TX: 251 case EP_W1_RUNNER_RDCTL: 252 case EP_W1_RUNNER_WRCTL: 253 return (reg); 254 } 255 return (reg + 0x10); 256 } 257 258 return (reg); 259 } 260 261 /* 262 * Issue a (reset) command, and be sure it has completed. 263 * Used for commands that reset part or all of the board. 264 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 265 * but older hardware doesn't implement it and we must delay. 266 * It's easiest to just delay always. 267 */ 268 static inline void 269 ep_complete_cmd(sc, cmd, arg) 270 struct ep_softc *sc; 271 u_int cmd, arg; 272 { 273 register bus_space_tag_t iot = sc->sc_iot; 274 register bus_space_handle_t ioh = sc->sc_ioh; 275 276 bus_space_write_2(iot, ioh, cmd, arg); 277 278 #ifdef notyet 279 /* if this adapter family has S_COMMAND_IN_PROGRESS, use it */ 280 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 281 ; 282 else 283 #else 284 DELAY(100000); /* need at least 1 ms, but be generous. */ 285 #endif 286 } 287 288 /* 289 * Back-end attach and configure. 290 */ 291 void 292 epconfig(sc, chipset, enaddr) 293 struct ep_softc *sc; 294 u_short chipset; 295 u_int8_t *enaddr; 296 { 297 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 298 bus_space_tag_t iot = sc->sc_iot; 299 bus_space_handle_t ioh = sc->sc_ioh; 300 u_int16_t i; 301 u_int8_t myla[6]; 302 303 sc->ep_chipset = chipset; 304 305 /* 306 * We could have been groveling around in other register 307 * windows in the front-end; make sure we're in window 0 308 * to read the EEPROM. 309 */ 310 GO_WINDOW(0); 311 312 if (enaddr == NULL) { 313 /* 314 * Read the station address from the eeprom 315 */ 316 for (i = 0; i < 3; i++) { 317 u_int16_t x; 318 if (epbusyeeprom(sc)) 319 return; /* XXX why is eeprom busy? */ 320 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 321 READ_EEPROM | i); 322 if (epbusyeeprom(sc)) 323 return; /* XXX why is eeprom busy? */ 324 x = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA); 325 myla[(i << 1)] = x >> 8; 326 myla[(i << 1) + 1] = x; 327 } 328 enaddr = myla; 329 } 330 331 /* 332 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 333 * allow FDDI-sized (4500) byte packets. Commands only take an 334 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 335 * packet length. 336 * Commands to these cards implicitly upshift a packet size 337 * or threshold by 2 bits. 338 * To detect cards with large-packet support, we probe by setting 339 * the transmit threshold register, then change windows and 340 * read back the threshold register directly, and see if the 341 * threshold value was shifted or not. 342 */ 343 bus_space_write_2(iot, ioh, EP_COMMAND, 344 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE ); 345 GO_WINDOW(5); 346 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH); 347 GO_WINDOW(1); 348 switch (i) { 349 case EP_LARGEWIN_PROBE: 350 case (EP_LARGEWIN_PROBE & EP_LARGEWIN_MASK): 351 sc->ep_pktlenshift = 0; 352 break; 353 354 case (EP_LARGEWIN_PROBE << 2): 355 sc->ep_pktlenshift = 2; 356 break; 357 358 default: 359 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 360 "Interface disabled\n", 361 sc->sc_dev.dv_xname, EP_LARGEWIN_PROBE, (int) i); 362 return; 363 } 364 365 /* 366 * Ensure Tx-available interrupts are enabled for 367 * start the interface. 368 * XXX should be in epinit()? 369 */ 370 bus_space_write_2(iot, ioh, EP_COMMAND, 371 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 372 373 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 374 ifp->if_softc = sc; 375 ifp->if_start = epstart; 376 ifp->if_ioctl = epioctl; 377 ifp->if_watchdog = epwatchdog; 378 ifp->if_flags = 379 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 380 381 if_attach(ifp); 382 ether_ifattach(ifp, enaddr); 383 384 /* 385 * Finish configuration: 386 * determine chipset if the front-end couldn't do so, 387 * show board details, set media. 388 */ 389 390 /* 391 * Print RAM size. We also print the Ethernet address in here. 392 * It's extracted from the ifp, so we have to make sure it's 393 * been attached first. 394 */ 395 ep_internalconfig(sc); 396 GO_WINDOW(0); 397 398 /* 399 * Display some additional information, if pertinent. 400 */ 401 if (sc->ep_flags & EP_FLAGS_USEFIFOBUFFER) 402 printf("%s: RoadRunner FIFO buffer enabled\n", 403 sc->sc_dev.dv_xname); 404 405 /* 406 * Initialize our media structures and MII info. We'll 407 * probe the MII if we discover that we have one. 408 */ 409 sc->sc_mii.mii_ifp = ifp; 410 sc->sc_mii.mii_readreg = ep_mii_readreg; 411 sc->sc_mii.mii_writereg = ep_mii_writereg; 412 sc->sc_mii.mii_statchg = ep_statchg; 413 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 414 ep_media_status); 415 416 /* 417 * Now, determine which media we have. 418 */ 419 switch (sc->ep_chipset) { 420 case EP_CHIPSET_BOOMERANG: 421 case EP_CHIPSET_ROADRUNNER: 422 /* 423 * If the device has MII, probe it. We won't be using 424 * any `native' media in this case, only PHYs. If 425 * we don't, just treat the Boomerang like the Vortex. 426 */ 427 if (sc->ep_flags & EP_FLAGS_MII) { 428 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 429 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 430 ifmedia_add(&sc->sc_mii.mii_media, 431 IFM_ETHER|IFM_NONE, 0, NULL); 432 ifmedia_set(&sc->sc_mii.mii_media, 433 IFM_ETHER|IFM_NONE); 434 } else { 435 ifmedia_set(&sc->sc_mii.mii_media, 436 IFM_ETHER|IFM_AUTO); 437 } 438 break; 439 } 440 /* FALLTHROUGH */ 441 442 case EP_CHIPSET_VORTEX: 443 ep_vortex_probemedia(sc); 444 break; 445 446 default: 447 ep_509_probemedia(sc); 448 break; 449 } 450 451 GO_WINDOW(1); /* Window 1 is operating window */ 452 453 #if NBPFILTER > 0 454 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 455 sizeof(struct ether_header)); 456 #endif 457 458 #if NRND > 0 459 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET); 460 #endif 461 462 sc->tx_start_thresh = 20; /* probably a good starting point. */ 463 464 /* Establish callback to reset card when we reboot. */ 465 shutdownhook_establish(epshutdown, sc); 466 467 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 468 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 469 } 470 471 472 /* 473 * Show interface-model-independent info from window 3 474 * internal-configuration register. 475 */ 476 void 477 ep_internalconfig(sc) 478 struct ep_softc *sc; 479 { 480 bus_space_tag_t iot = sc->sc_iot; 481 bus_space_handle_t ioh = sc->sc_ioh; 482 483 u_int config0; 484 u_int config1; 485 486 int ram_size, ram_width, ram_speed, rom_size, ram_split; 487 /* 488 * NVRAM buffer Rx:Tx config names for busmastering cards 489 * (Demon, Vortex, and later). 490 */ 491 const char *onboard_ram_config[] = { 492 "5:3", "3:1", "1:1", "3:5" }; 493 494 GO_WINDOW(3); 495 config0 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG); 496 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 497 GO_WINDOW(0); 498 499 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 500 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 501 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 502 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 503 504 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 505 506 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 507 sc->sc_dev.dv_xname, 508 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 509 8 << ram_size, 510 (ram_width) ? "word" : "byte", 511 onboard_ram_config[ram_split]); 512 } 513 514 515 /* 516 * Find supported media on 3c509-generation hardware that doesn't have 517 * a "reset_options" register in window 3. 518 * Use the config_cntrl register in window 0 instead. 519 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 520 * that implement CONFIG_CTRL. We don't have a good way to set the 521 * default active mediuim; punt to ifconfig instead. 522 */ 523 void 524 ep_509_probemedia(sc) 525 struct ep_softc *sc; 526 { 527 bus_space_tag_t iot = sc->sc_iot; 528 bus_space_handle_t ioh = sc->sc_ioh; 529 struct ifmedia *ifm = &sc->sc_mii.mii_media; 530 u_int16_t ep_w0_config, port; 531 struct ep_media *epm; 532 const char *sep = "", *defmedianame = NULL; 533 int defmedia = 0; 534 535 GO_WINDOW(0); 536 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL); 537 538 printf("%s: ", sc->sc_dev.dv_xname); 539 540 /* Sanity check that there are any media! */ 541 if ((ep_w0_config & EP_W0_CC_MEDIAMASK) == 0) { 542 printf("no media present!\n"); 543 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 544 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 545 return; 546 } 547 548 /* 549 * Get the default media from the EEPROM. 550 */ 551 if (epbusyeeprom(sc)) 552 return; /* XXX why is eeprom busy? */ 553 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND, 554 READ_EEPROM | EEPROM_ADDR_CFG); 555 if (epbusyeeprom(sc)) 556 return; /* XXX why is eeprom busy? */ 557 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA) >> 14; 558 559 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 560 561 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 562 if (ep_w0_config & epm->epm_mpbit) { 563 /* 564 * This simple test works because 509 chipsets 565 * don't do full-duplex. 566 */ 567 if (epm->epm_epmedia == port || defmedia == 0) { 568 defmedia = epm->epm_ifmedia; 569 defmedianame = epm->epm_name; 570 } 571 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 572 NULL); 573 PRINT(epm->epm_name); 574 } 575 } 576 577 #undef PRINT 578 579 #ifdef DIAGNOSTIC 580 if (defmedia == 0) 581 panic("ep_509_probemedia: impossible"); 582 #endif 583 584 printf(" (default %s)\n", defmedianame); 585 ifmedia_set(ifm, defmedia); 586 } 587 588 /* 589 * Find media present on large-packet-capable elink3 devices. 590 * Show onboard configuration of large-packet-capable elink3 devices 591 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 592 * Use media and card-version info in window 3 instead. 593 */ 594 void 595 ep_vortex_probemedia(sc) 596 struct ep_softc *sc; 597 { 598 bus_space_tag_t iot = sc->sc_iot; 599 bus_space_handle_t ioh = sc->sc_ioh; 600 struct ifmedia *ifm = &sc->sc_mii.mii_media; 601 struct ep_media *epm; 602 u_int config1; 603 int reset_options; 604 int default_media; /* 3-bit encoding of default (EEPROM) media */ 605 int defmedia = 0; 606 const char *sep = "", *defmedianame = NULL; 607 608 GO_WINDOW(3); 609 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2); 610 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS); 611 GO_WINDOW(0); 612 613 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 614 615 printf("%s: ", sc->sc_dev.dv_xname); 616 617 /* Sanity check that there are any media! */ 618 if ((reset_options & EP_PCI_MEDIAMASK) == 0) { 619 printf("no media present!\n"); 620 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 621 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 622 return; 623 } 624 625 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 626 627 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 628 if (reset_options & epm->epm_mpbit) { 629 /* 630 * Default media is a little more complicated 631 * on the Vortex. We support full-duplex which 632 * uses the same reset options bit. 633 * 634 * XXX Check EEPROM for default to FDX? 635 */ 636 if (epm->epm_epmedia == default_media) { 637 if ((epm->epm_ifmedia & IFM_FDX) == 0) { 638 defmedia = epm->epm_ifmedia; 639 defmedianame = epm->epm_name; 640 } 641 } else if (defmedia == 0) { 642 defmedia = epm->epm_ifmedia; 643 defmedianame = epm->epm_name; 644 } 645 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 646 NULL); 647 PRINT(epm->epm_name); 648 } 649 } 650 651 #undef PRINT 652 653 #ifdef DIAGNOSTIC 654 if (defmedia == 0) 655 panic("ep_vortex_probemedia: impossible"); 656 #endif 657 658 printf(" (default %s)\n", defmedianame); 659 ifmedia_set(ifm, defmedia); 660 } 661 662 /* 663 * One second timer, used to tick the MII. 664 */ 665 void 666 ep_tick(arg) 667 void *arg; 668 { 669 struct ep_softc *sc = arg; 670 int s; 671 672 #ifdef DIAGNOSTIC 673 if ((sc->ep_flags & EP_FLAGS_MII) == 0) 674 panic("ep_tick"); 675 #endif 676 677 s = splnet(); 678 mii_tick(&sc->sc_mii); 679 splx(s); 680 681 timeout(ep_tick, sc, hz); 682 } 683 684 /* 685 * Bring device up. 686 * 687 * The order in here seems important. Otherwise we may not receive 688 * interrupts. ?! 689 */ 690 void 691 epinit(sc) 692 register struct ep_softc *sc; 693 { 694 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 695 bus_space_tag_t iot = sc->sc_iot; 696 bus_space_handle_t ioh = sc->sc_ioh; 697 int i; 698 699 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 700 ; 701 702 if (sc->bustype != EP_BUS_PCI) { 703 GO_WINDOW(0); 704 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0); 705 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 706 } 707 708 if (sc->bustype == EP_BUS_PCMCIA) { 709 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00); 710 } 711 712 GO_WINDOW(2); 713 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 714 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i, 715 LLADDR(ifp->if_sadl)[i]); 716 717 /* 718 * Reset the station-address receive filter. 719 * A bug workaround for busmastering (Vortex, Demon) cards. 720 */ 721 for (i = 0; i < 6; i++) 722 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0); 723 724 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 725 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 726 727 GO_WINDOW(1); /* Window 1 is operating window */ 728 for (i = 0; i < 31; i++) 729 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS)); 730 731 /* Set threshhold for for Tx-space avaiable interrupt. */ 732 bus_space_write_2(iot, ioh, EP_COMMAND, 733 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 734 735 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 736 /* 737 * Enable options in the PCMCIA LAN COR register, via 738 * RoadRunner Window 1. 739 * 740 * XXX MAGIC CONSTANTS! 741 */ 742 u_int16_t cor; 743 744 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11)); 745 746 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 747 if (sc->ep_flags & EP_FLAGS_USESHAREDMEM) 748 cor |= 0x10; 749 if (sc->ep_flags & EP_FLAGS_FORCENOWAIT) 750 cor |= 0x20; 751 bus_space_write_2(iot, ioh, 0, cor); 752 753 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 754 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 755 } 756 757 /* Enable interrupts. */ 758 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 759 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 760 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | 761 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 762 763 /* 764 * Attempt to get rid of any stray interrupts that occured during 765 * configuration. On the i386 this isn't possible because one may 766 * already be queued. However, a single stray interrupt is 767 * unimportant. 768 */ 769 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff); 770 771 epsetfilter(sc); 772 epsetmedia(sc); 773 774 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE); 775 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 776 777 epmbuffill(sc); 778 779 /* Interface is now `running', with no output active. */ 780 ifp->if_flags |= IFF_RUNNING; 781 ifp->if_flags &= ~IFF_OACTIVE; 782 783 if (sc->ep_flags & EP_FLAGS_MII) { 784 /* Start the one second clock. */ 785 timeout(ep_tick, sc, hz); 786 } 787 788 /* Attempt to start output, if any. */ 789 epstart(ifp); 790 } 791 792 793 /* 794 * Set multicast receive filter. 795 * elink3 hardware has no selective multicast filter in hardware. 796 * Enable reception of all multicasts and filter in software. 797 */ 798 void 799 epsetfilter(sc) 800 register struct ep_softc *sc; 801 { 802 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 803 804 GO_WINDOW(1); /* Window 1 is operating window */ 805 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER | 806 FIL_INDIVIDUAL | FIL_BRDCST | 807 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 808 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 809 } 810 811 int 812 ep_media_change(ifp) 813 struct ifnet *ifp; 814 { 815 register struct ep_softc *sc = ifp->if_softc; 816 817 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 818 epreset(sc); 819 820 return (0); 821 } 822 823 /* 824 * Set the card to use the specified media. 825 */ 826 void 827 epsetmedia(sc) 828 struct ep_softc *sc; 829 { 830 bus_space_tag_t iot = sc->sc_iot; 831 bus_space_handle_t ioh = sc->sc_ioh; 832 833 /* Turn everything off. First turn off linkbeat and UTP. */ 834 GO_WINDOW(4); 835 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 0x0); 836 837 /* Turn off coax */ 838 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 839 delay(1000); 840 841 /* 842 * If the device has MII, select it, and then tell the 843 * PHY which media to use. 844 */ 845 if (sc->ep_flags & EP_FLAGS_MII) { 846 int config0, config1; 847 848 GO_WINDOW(3); 849 850 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 851 int resopt; 852 853 resopt = bus_space_read_2(iot, ioh, 854 EP_W3_RESET_OPTIONS); 855 bus_space_write_2(iot, ioh, 856 EP_W3_RESET_OPTIONS, resopt|EP_RUNNER_ENABLE_MII); 857 } 858 859 config0 = (u_int)bus_space_read_2(iot, ioh, 860 EP_W3_INTERNAL_CONFIG); 861 config1 = (u_int)bus_space_read_2(iot, ioh, 862 EP_W3_INTERNAL_CONFIG + 2); 863 864 config1 = config1 & ~CONFIG_MEDIAMASK; 865 config1 |= (EPMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 866 867 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 868 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 869 GO_WINDOW(1); /* back to operating window */ 870 871 mii_mediachg(&sc->sc_mii); 872 return; 873 } 874 875 /* 876 * Now turn on the selected media/transceiver. 877 */ 878 GO_WINDOW(4); 879 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 880 case IFM_10_T: 881 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 882 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 883 break; 884 885 case IFM_10_2: 886 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER); 887 DELAY(1000); /* 50ms not enmough? */ 888 break; 889 890 case IFM_100_TX: 891 case IFM_100_FX: 892 case IFM_100_T4: /* XXX check documentation */ 893 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 894 LINKBEAT_ENABLE); 895 DELAY(1000); /* not strictly necessary? */ 896 break; 897 898 case IFM_10_5: 899 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, 900 SQE_ENABLE); 901 DELAY(1000); /* not strictly necessary? */ 902 break; 903 904 case IFM_MANUAL: 905 /* 906 * Nothing to do here; we are actually enabling the 907 * external PHY on the MII port. 908 */ 909 break; 910 911 case IFM_NONE: 912 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 913 return; 914 915 default: 916 panic("epsetmedia: impossible"); 917 } 918 919 /* 920 * Tell the chip which port to use. 921 */ 922 switch (sc->ep_chipset) { 923 case EP_CHIPSET_VORTEX: 924 case EP_CHIPSET_BOOMERANG: 925 { 926 int mctl, config0, config1; 927 928 GO_WINDOW(3); 929 config0 = (u_int)bus_space_read_2(iot, ioh, 930 EP_W3_INTERNAL_CONFIG); 931 config1 = (u_int)bus_space_read_2(iot, ioh, 932 EP_W3_INTERNAL_CONFIG + 2); 933 934 config1 = config1 & ~CONFIG_MEDIAMASK; 935 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 936 CONFIG_MEDIAMASK_SHIFT); 937 938 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0); 939 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1); 940 941 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL); 942 if (sc->sc_mii.mii_media.ifm_cur->ifm_media & IFM_FDX) 943 mctl |= MAC_CONTROL_FDX; 944 else 945 mctl &= ~MAC_CONTROL_FDX; 946 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl); 947 break; 948 } 949 default: 950 { 951 int w0_addr_cfg; 952 953 GO_WINDOW(0); 954 w0_addr_cfg = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG); 955 w0_addr_cfg &= 0x3fff; 956 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG, w0_addr_cfg | 957 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 958 DELAY(1000); 959 break; 960 } 961 } 962 963 GO_WINDOW(1); /* Window 1 is operating window */ 964 } 965 966 /* 967 * Get currently-selected media from card. 968 * (if_media callback, may be called before interface is brought up). 969 */ 970 void 971 ep_media_status(ifp, req) 972 struct ifnet *ifp; 973 struct ifmediareq *req; 974 { 975 register struct ep_softc *sc = ifp->if_softc; 976 bus_space_tag_t iot = sc->sc_iot; 977 bus_space_handle_t ioh = sc->sc_ioh; 978 979 if (sc->enabled == 0) { 980 req->ifm_active = IFM_ETHER|IFM_NONE; 981 req->ifm_status = 0; 982 return; 983 } 984 985 /* 986 * If we have MII, go ask the PHY what's going on. 987 */ 988 if (sc->ep_flags & EP_FLAGS_MII) { 989 mii_pollstat(&sc->sc_mii); 990 req->ifm_active = sc->sc_mii.mii_media_active; 991 req->ifm_status = sc->sc_mii.mii_media_status; 992 return; 993 } 994 995 /* 996 * Ok, at this point we claim that our active media is 997 * the currently selected media. We'll update our status 998 * if our chipset allows us to detect link. 999 */ 1000 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1001 req->ifm_status = 0; 1002 1003 switch (sc->ep_chipset) { 1004 case EP_CHIPSET_VORTEX: 1005 case EP_CHIPSET_BOOMERANG: 1006 GO_WINDOW(4); 1007 req->ifm_status = IFM_AVALID; 1008 if (bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE) & 1009 LINKBEAT_DETECT) 1010 req->ifm_status |= IFM_ACTIVE; 1011 GO_WINDOW(1); /* back to operating window */ 1012 break; 1013 } 1014 } 1015 1016 1017 1018 /* 1019 * Start outputting on the interface. 1020 * Always called as splnet(). 1021 */ 1022 void 1023 epstart(ifp) 1024 struct ifnet *ifp; 1025 { 1026 register struct ep_softc *sc = ifp->if_softc; 1027 bus_space_tag_t iot = sc->sc_iot; 1028 bus_space_handle_t ioh = sc->sc_ioh; 1029 struct mbuf *m, *m0; 1030 int sh, len, pad; 1031 bus_addr_t txreg; 1032 1033 /* Don't transmit if interface is busy or not running */ 1034 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1035 return; 1036 1037 startagain: 1038 /* Sneak a peek at the next packet */ 1039 m0 = ifp->if_snd.ifq_head; 1040 if (m0 == 0) 1041 return; 1042 1043 /* We need to use m->m_pkthdr.len, so require the header */ 1044 if ((m0->m_flags & M_PKTHDR) == 0) 1045 panic("epstart: no header mbuf"); 1046 len = m0->m_pkthdr.len; 1047 1048 pad = (4 - len) & 3; 1049 1050 /* 1051 * The 3c509 automatically pads short packets to minimum ethernet 1052 * length, but we drop packets that are too large. Perhaps we should 1053 * truncate them instead? 1054 */ 1055 if (len + pad > ETHER_MAX_LEN) { 1056 /* packet is obviously too large: toss it */ 1057 ++ifp->if_oerrors; 1058 IF_DEQUEUE(&ifp->if_snd, m0); 1059 m_freem(m0); 1060 goto readcheck; 1061 } 1062 1063 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX)) < 1064 len + pad + 4) { 1065 bus_space_write_2(iot, ioh, EP_COMMAND, 1066 SET_TX_AVAIL_THRESH | 1067 ((len + pad + 4) >> sc->ep_pktlenshift)); 1068 /* not enough room in FIFO */ 1069 ifp->if_flags |= IFF_OACTIVE; 1070 return; 1071 } else { 1072 bus_space_write_2(iot, ioh, EP_COMMAND, 1073 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE ); 1074 } 1075 1076 IF_DEQUEUE(&ifp->if_snd, m0); 1077 if (m0 == 0) /* not really needed */ 1078 return; 1079 1080 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH | 1081 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/) ); 1082 1083 #if NBPFILTER > 0 1084 if (ifp->if_bpf) 1085 bpf_mtap(ifp->if_bpf, m0); 1086 #endif 1087 1088 /* 1089 * Do the output at splhigh() so that an interrupt from another device 1090 * won't cause a FIFO underrun. 1091 */ 1092 sh = splhigh(); 1093 1094 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_1); 1095 1096 if (sc->ep_flags & EP_FLAGS_USEFIFOBUFFER) { 1097 /* 1098 * Prime the FIFO buffer counter (number of 16-bit 1099 * words about to be written to the FIFO). 1100 * 1101 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1102 * COUNTER IS NON-ZERO! 1103 */ 1104 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 1105 (len + pad) >> 1); 1106 } 1107 1108 bus_space_write_2(iot, ioh, txreg, len); 1109 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1110 if (EP_IS_BUS_32(sc->bustype)) { 1111 for (m = m0; m; ) { 1112 if (m->m_len > 3) { 1113 /* align our reads from core */ 1114 if (mtod(m, u_long) & 3) { 1115 u_long count = 1116 4 - (mtod(m, u_long) & 3); 1117 bus_space_write_multi_1(iot, ioh, 1118 txreg, mtod(m, u_int8_t *), count); 1119 m->m_data = 1120 (void *)(mtod(m, u_long) + count); 1121 m->m_len -= count; 1122 } 1123 bus_space_write_multi_4(iot, ioh, 1124 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1125 m->m_data = (void *)(mtod(m, u_long) + 1126 (u_long)(m->m_len & ~3)); 1127 m->m_len -= m->m_len & ~3; 1128 } 1129 if (m->m_len) { 1130 bus_space_write_multi_1(iot, ioh, 1131 txreg, mtod(m, u_int8_t *), m->m_len); 1132 } 1133 MFREE(m, m0); 1134 m = m0; 1135 } 1136 } else { 1137 for (m = m0; m; ) { 1138 if (m->m_len > 1) { 1139 if (mtod(m, u_long) & 1) { 1140 bus_space_write_1(iot, ioh, 1141 txreg, *(mtod(m, u_int8_t *))); 1142 m->m_data = 1143 (void *)(mtod(m, u_long) + 1); 1144 m->m_len -= 1; 1145 } 1146 bus_space_write_multi_2(iot, ioh, 1147 txreg, mtod(m, u_int16_t *), 1148 m->m_len >> 1); 1149 } 1150 if (m->m_len & 1) { 1151 bus_space_write_1(iot, ioh, txreg, 1152 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1153 } 1154 MFREE(m, m0); 1155 m = m0; 1156 } 1157 } 1158 while (pad--) 1159 bus_space_write_1(iot, ioh, txreg, 0); 1160 1161 splx(sh); 1162 1163 ++ifp->if_opackets; 1164 1165 readcheck: 1166 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)) & 1167 ERR_INCOMPLETE) == 0) { 1168 /* We received a complete packet. */ 1169 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS); 1170 1171 if ((status & S_INTR_LATCH) == 0) { 1172 /* 1173 * No interrupt, read the packet and continue 1174 * Is this supposed to happen? Is my motherboard 1175 * completely busted? 1176 */ 1177 epread(sc); 1178 } else { 1179 /* Got an interrupt, return so that it gets serviced. */ 1180 return; 1181 } 1182 } else { 1183 /* Check if we are stuck and reset [see XXX comment] */ 1184 if (epstatus(sc)) { 1185 if (ifp->if_flags & IFF_DEBUG) 1186 printf("%s: adapter reset\n", 1187 sc->sc_dev.dv_xname); 1188 epreset(sc); 1189 } 1190 } 1191 1192 goto startagain; 1193 } 1194 1195 1196 /* 1197 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1198 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1199 * We detect this situation and we reset the adapter. 1200 * It happens at times when there is a lot of broadcast traffic 1201 * on the cable (once in a blue moon). 1202 */ 1203 static int 1204 epstatus(sc) 1205 register struct ep_softc *sc; 1206 { 1207 bus_space_tag_t iot = sc->sc_iot; 1208 bus_space_handle_t ioh = sc->sc_ioh; 1209 u_int16_t fifost; 1210 1211 /* 1212 * Check the FIFO status and act accordingly 1213 */ 1214 GO_WINDOW(4); 1215 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG); 1216 GO_WINDOW(1); 1217 1218 if (fifost & FIFOS_RX_UNDERRUN) { 1219 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1220 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1221 epreset(sc); 1222 return 0; 1223 } 1224 1225 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1226 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1227 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1228 return 1; 1229 } 1230 1231 if (fifost & FIFOS_RX_OVERRUN) { 1232 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1233 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1234 return 1; 1235 } 1236 1237 if (fifost & FIFOS_TX_OVERRUN) { 1238 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1239 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1240 epreset(sc); 1241 return 0; 1242 } 1243 1244 return 0; 1245 } 1246 1247 1248 static void 1249 eptxstat(sc) 1250 register struct ep_softc *sc; 1251 { 1252 bus_space_tag_t iot = sc->sc_iot; 1253 bus_space_handle_t ioh = sc->sc_ioh; 1254 int i; 1255 1256 /* 1257 * We need to read+write TX_STATUS until we get a 0 status 1258 * in order to turn off the interrupt flag. 1259 */ 1260 while ((i = bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS))) 1261 & TXS_COMPLETE) { 1262 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS), 1263 0x0); 1264 1265 if (i & TXS_JABBER) { 1266 ++sc->sc_ethercom.ec_if.if_oerrors; 1267 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1268 printf("%s: jabber (%x)\n", 1269 sc->sc_dev.dv_xname, i); 1270 epreset(sc); 1271 } else if (i & TXS_UNDERRUN) { 1272 ++sc->sc_ethercom.ec_if.if_oerrors; 1273 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1274 printf("%s: fifo underrun (%x) @%d\n", 1275 sc->sc_dev.dv_xname, i, 1276 sc->tx_start_thresh); 1277 if (sc->tx_succ_ok < 100) 1278 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1279 sc->tx_start_thresh + 20); 1280 sc->tx_succ_ok = 0; 1281 epreset(sc); 1282 } else if (i & TXS_MAX_COLLISION) { 1283 ++sc->sc_ethercom.ec_if.if_collisions; 1284 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE); 1285 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1286 } else 1287 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1288 } 1289 } 1290 1291 int 1292 epintr(arg) 1293 void *arg; 1294 { 1295 register struct ep_softc *sc = arg; 1296 bus_space_tag_t iot = sc->sc_iot; 1297 bus_space_handle_t ioh = sc->sc_ioh; 1298 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1299 u_int16_t status; 1300 int ret = 0; 1301 int addrandom = 0; 1302 1303 if (sc->enabled == 0) 1304 return (0); 1305 1306 for (;;) { 1307 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1308 1309 status = bus_space_read_2(iot, ioh, EP_STATUS); 1310 1311 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1312 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1313 if ((status & S_INTR_LATCH) == 0) { 1314 #if 0 1315 printf("%s: intr latch cleared\n", 1316 sc->sc_dev.dv_xname); 1317 #endif 1318 break; 1319 } 1320 } 1321 1322 ret = 1; 1323 1324 /* 1325 * Acknowledge any interrupts. It's important that we do this 1326 * first, since there would otherwise be a race condition. 1327 * Due to the i386 interrupt queueing, we may get spurious 1328 * interrupts occasionally. 1329 */ 1330 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 1331 (status & (C_INTR_LATCH | 1332 C_CARD_FAILURE | 1333 C_TX_COMPLETE | 1334 C_TX_AVAIL | 1335 C_RX_COMPLETE | 1336 C_RX_EARLY | 1337 C_INT_RQD | 1338 C_UPD_STATS))); 1339 1340 #if 0 1341 status = bus_space_read_2(iot, ioh, EP_STATUS); 1342 1343 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1344 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1345 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1346 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1347 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1348 #endif 1349 1350 if (status & S_RX_COMPLETE) { 1351 epread(sc); 1352 addrandom = 1; 1353 } 1354 if (status & S_TX_AVAIL) { 1355 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1356 epstart(&sc->sc_ethercom.ec_if); 1357 addrandom = 1; 1358 } 1359 if (status & S_CARD_FAILURE) { 1360 printf("%s: adapter failure (%x)\n", 1361 sc->sc_dev.dv_xname, status); 1362 epreset(sc); 1363 return (1); 1364 } 1365 if (status & S_TX_COMPLETE) { 1366 eptxstat(sc); 1367 epstart(ifp); 1368 addrandom = 1; 1369 } 1370 1371 #if NRND > 0 1372 if (status) 1373 rnd_add_uint32(&sc->rnd_source, status); 1374 #endif 1375 } 1376 1377 /* no more interrupts */ 1378 return (ret); 1379 } 1380 1381 void 1382 epread(sc) 1383 register struct ep_softc *sc; 1384 { 1385 bus_space_tag_t iot = sc->sc_iot; 1386 bus_space_handle_t ioh = sc->sc_ioh; 1387 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1388 struct mbuf *m; 1389 struct ether_header *eh; 1390 int len; 1391 1392 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS)); 1393 1394 again: 1395 if (ifp->if_flags & IFF_DEBUG) { 1396 int err = len & ERR_MASK; 1397 char *s = NULL; 1398 1399 if (len & ERR_INCOMPLETE) 1400 s = "incomplete packet"; 1401 else if (err == ERR_OVERRUN) 1402 s = "packet overrun"; 1403 else if (err == ERR_RUNT) 1404 s = "runt packet"; 1405 else if (err == ERR_ALIGNMENT) 1406 s = "bad alignment"; 1407 else if (err == ERR_CRC) 1408 s = "bad crc"; 1409 else if (err == ERR_OVERSIZE) 1410 s = "oversized packet"; 1411 else if (err == ERR_DRIBBLE) 1412 s = "dribble bits"; 1413 1414 if (s) 1415 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1416 } 1417 1418 if (len & ERR_INCOMPLETE) 1419 return; 1420 1421 if (len & ERR_RX) { 1422 ++ifp->if_ierrors; 1423 goto abort; 1424 } 1425 1426 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1427 1428 /* Pull packet off interface. */ 1429 m = epget(sc, len); 1430 if (m == 0) { 1431 ifp->if_ierrors++; 1432 goto abort; 1433 } 1434 1435 ++ifp->if_ipackets; 1436 1437 /* We assume the header fit entirely in one mbuf. */ 1438 eh = mtod(m, struct ether_header *); 1439 1440 #if NBPFILTER > 0 1441 /* 1442 * Check if there's a BPF listener on this interface. 1443 * If so, hand off the raw packet to BPF. 1444 */ 1445 if (ifp->if_bpf) { 1446 bpf_mtap(ifp->if_bpf, m); 1447 1448 /* 1449 * Note that the interface cannot be in promiscuous mode if 1450 * there are no BPF listeners. And if we are in promiscuous 1451 * mode, we have to check if this packet is really ours. 1452 */ 1453 if ((ifp->if_flags & IFF_PROMISC) && 1454 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1455 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1456 sizeof(eh->ether_dhost)) != 0) { 1457 m_freem(m); 1458 return; 1459 } 1460 } 1461 #endif 1462 1463 /* We assume the header fit entirely in one mbuf. */ 1464 m_adj(m, sizeof(struct ether_header)); 1465 ether_input(ifp, eh, m); 1466 1467 /* 1468 * In periods of high traffic we can actually receive enough 1469 * packets so that the fifo overrun bit will be set at this point, 1470 * even though we just read a packet. In this case we 1471 * are not going to receive any more interrupts. We check for 1472 * this condition and read again until the fifo is not full. 1473 * We could simplify this test by not using epstatus(), but 1474 * rechecking the RX_STATUS register directly. This test could 1475 * result in unnecessary looping in cases where there is a new 1476 * packet but the fifo is not full, but it will not fix the 1477 * stuck behavior. 1478 * 1479 * Even with this improvement, we still get packet overrun errors 1480 * which are hurting performance. Maybe when I get some more time 1481 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1482 */ 1483 if (epstatus(sc)) { 1484 len = bus_space_read_2(iot, ioh, 1485 ep_w1_reg(sc, EP_W1_RX_STATUS)); 1486 /* Check if we are stuck and reset [see XXX comment] */ 1487 if (len & ERR_INCOMPLETE) { 1488 if (ifp->if_flags & IFF_DEBUG) 1489 printf("%s: adapter reset\n", 1490 sc->sc_dev.dv_xname); 1491 epreset(sc); 1492 return; 1493 } 1494 goto again; 1495 } 1496 1497 return; 1498 1499 abort: 1500 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1501 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1502 ; 1503 } 1504 1505 struct mbuf * 1506 epget(sc, totlen) 1507 struct ep_softc *sc; 1508 int totlen; 1509 { 1510 bus_space_tag_t iot = sc->sc_iot; 1511 bus_space_handle_t ioh = sc->sc_ioh; 1512 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1513 struct mbuf *top, **mp, *m, *rv = NULL; 1514 bus_addr_t rxreg; 1515 int len, remaining; 1516 int sh; 1517 1518 m = sc->mb[sc->next_mb]; 1519 sc->mb[sc->next_mb] = 0; 1520 if (m == 0) { 1521 MGETHDR(m, M_DONTWAIT, MT_DATA); 1522 if (m == 0) 1523 return 0; 1524 } else { 1525 /* If the queue is no longer full, refill. */ 1526 if (sc->last_mb == sc->next_mb) 1527 timeout(epmbuffill, sc, 1); 1528 /* Convert one of our saved mbuf's. */ 1529 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1530 m->m_data = m->m_pktdat; 1531 m->m_flags = M_PKTHDR; 1532 } 1533 m->m_pkthdr.rcvif = ifp; 1534 m->m_pkthdr.len = totlen; 1535 len = MHLEN; 1536 top = 0; 1537 mp = ⊤ 1538 1539 /* 1540 * We read the packet at splhigh() so that an interrupt from another 1541 * device doesn't cause the card's buffer to overflow while we're 1542 * reading it. We may still lose packets at other times. 1543 */ 1544 sh = splhigh(); 1545 1546 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_1); 1547 1548 if (sc->ep_flags & EP_FLAGS_USEFIFOBUFFER) { 1549 /* 1550 * Prime the FIFO buffer counter (number of 16-bit 1551 * words about to be read from the FIFO). 1552 * 1553 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1554 * COUNTER IS NON-ZERO! 1555 */ 1556 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, totlen >> 1); 1557 } 1558 1559 while (totlen > 0) { 1560 if (top) { 1561 m = sc->mb[sc->next_mb]; 1562 sc->mb[sc->next_mb] = 0; 1563 if (m == 0) { 1564 MGET(m, M_DONTWAIT, MT_DATA); 1565 if (m == 0) { 1566 m_freem(top); 1567 goto out; 1568 } 1569 } else { 1570 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1571 } 1572 len = MLEN; 1573 } 1574 if (totlen >= MINCLSIZE) { 1575 MCLGET(m, M_DONTWAIT); 1576 if ((m->m_flags & M_EXT) == 0) { 1577 m_free(m); 1578 m_freem(top); 1579 goto out; 1580 } 1581 len = MCLBYTES; 1582 } 1583 if (top == 0) { 1584 /* align the struct ip header */ 1585 caddr_t newdata = (caddr_t) 1586 ALIGN(m->m_data + sizeof(struct ether_header)) 1587 - sizeof(struct ether_header); 1588 len -= newdata - m->m_data; 1589 m->m_data = newdata; 1590 } 1591 remaining = len = min(totlen, len); 1592 if (EP_IS_BUS_32(sc->bustype)) { 1593 u_long offset = mtod(m, u_long); 1594 /* 1595 * Read bytes up to the point where we are aligned. 1596 * (We can align to 4 bytes, rather than ALIGNBYTES, 1597 * here because we're later reading 4-byte chunks.) 1598 */ 1599 if ((remaining > 3) && (offset & 3)) { 1600 int count = (4 - (offset & 3)); 1601 bus_space_read_multi_1(iot, ioh, 1602 rxreg, (u_int8_t *) offset, count); 1603 offset += count; 1604 remaining -= count; 1605 } 1606 if (remaining > 3) { 1607 bus_space_read_multi_4(iot, ioh, 1608 rxreg, (u_int32_t *) offset, 1609 remaining >> 2); 1610 offset += remaining & ~3; 1611 remaining &= 3; 1612 } 1613 if (remaining) { 1614 bus_space_read_multi_1(iot, ioh, 1615 rxreg, (u_int8_t *) offset, remaining); 1616 } 1617 } else { 1618 u_long offset = mtod(m, u_long); 1619 if ((remaining > 1) && (offset & 1)) { 1620 bus_space_read_multi_1(iot, ioh, 1621 rxreg, (u_int8_t *) offset, 1); 1622 remaining -= 1; 1623 offset += 1; 1624 } 1625 if (remaining > 1) { 1626 bus_space_read_multi_2(iot, ioh, 1627 rxreg, (u_int16_t *) offset, 1628 remaining >> 1); 1629 offset += remaining & ~1; 1630 } 1631 if (remaining & 1) { 1632 bus_space_read_multi_1(iot, ioh, 1633 rxreg, (u_int8_t *) offset, remaining & 1); 1634 } 1635 } 1636 m->m_len = len; 1637 totlen -= len; 1638 *mp = m; 1639 mp = &m->m_next; 1640 } 1641 1642 rv = top; 1643 1644 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1645 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1646 ; 1647 1648 out: 1649 if (sc->ep_flags & EP_FLAGS_USEFIFOBUFFER) 1650 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1651 splx(sh); 1652 1653 return rv; 1654 } 1655 1656 int 1657 epioctl(ifp, cmd, data) 1658 register struct ifnet *ifp; 1659 u_long cmd; 1660 caddr_t data; 1661 { 1662 struct ep_softc *sc = ifp->if_softc; 1663 struct ifaddr *ifa = (struct ifaddr *)data; 1664 struct ifreq *ifr = (struct ifreq *)data; 1665 int s, error = 0; 1666 1667 s = splnet(); 1668 1669 switch (cmd) { 1670 1671 case SIOCSIFADDR: 1672 if ((error = epenable(sc)) != 0) 1673 break; 1674 /* epinit is called just below */ 1675 ifp->if_flags |= IFF_UP; 1676 switch (ifa->ifa_addr->sa_family) { 1677 #ifdef INET 1678 case AF_INET: 1679 epinit(sc); 1680 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1681 break; 1682 #endif 1683 #ifdef NS 1684 case AF_NS: 1685 { 1686 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1687 1688 if (ns_nullhost(*ina)) 1689 ina->x_host = *(union ns_host *) 1690 LLADDR(ifp->if_sadl); 1691 else 1692 bcopy(ina->x_host.c_host, 1693 LLADDR(ifp->if_sadl), 1694 ifp->if_addrlen); 1695 /* Set new address. */ 1696 epinit(sc); 1697 break; 1698 } 1699 #endif 1700 default: 1701 epinit(sc); 1702 break; 1703 } 1704 break; 1705 1706 case SIOCSIFMEDIA: 1707 case SIOCGIFMEDIA: 1708 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1709 break; 1710 1711 case SIOCSIFFLAGS: 1712 if ((ifp->if_flags & IFF_UP) == 0 && 1713 (ifp->if_flags & IFF_RUNNING) != 0) { 1714 /* 1715 * If interface is marked down and it is running, then 1716 * stop it. 1717 */ 1718 epstop(sc); 1719 ifp->if_flags &= ~IFF_RUNNING; 1720 epdisable(sc); 1721 } else if ((ifp->if_flags & IFF_UP) != 0 && 1722 (ifp->if_flags & IFF_RUNNING) == 0) { 1723 /* 1724 * If interface is marked up and it is stopped, then 1725 * start it. 1726 */ 1727 if ((error = epenable(sc)) != 0) 1728 break; 1729 epinit(sc); 1730 } else if (sc->enabled) { 1731 /* 1732 * deal with flags changes: 1733 * IFF_MULTICAST, IFF_PROMISC. 1734 */ 1735 epsetfilter(sc); 1736 } 1737 break; 1738 1739 case SIOCADDMULTI: 1740 case SIOCDELMULTI: 1741 if (sc->enabled == 0) { 1742 error = EIO; 1743 break; 1744 } 1745 1746 error = (cmd == SIOCADDMULTI) ? 1747 ether_addmulti(ifr, &sc->sc_ethercom) : 1748 ether_delmulti(ifr, &sc->sc_ethercom); 1749 1750 if (error == ENETRESET) { 1751 /* 1752 * Multicast list has changed; set the hardware filter 1753 * accordingly. 1754 */ 1755 epreset(sc); 1756 error = 0; 1757 } 1758 break; 1759 1760 default: 1761 error = EINVAL; 1762 break; 1763 } 1764 1765 splx(s); 1766 return (error); 1767 } 1768 1769 void 1770 epreset(sc) 1771 struct ep_softc *sc; 1772 { 1773 int s; 1774 1775 s = splnet(); 1776 epstop(sc); 1777 epinit(sc); 1778 splx(s); 1779 } 1780 1781 void 1782 epwatchdog(ifp) 1783 struct ifnet *ifp; 1784 { 1785 struct ep_softc *sc = ifp->if_softc; 1786 1787 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1788 ++sc->sc_ethercom.ec_if.if_oerrors; 1789 1790 epreset(sc); 1791 } 1792 1793 void 1794 epstop(sc) 1795 register struct ep_softc *sc; 1796 { 1797 bus_space_tag_t iot = sc->sc_iot; 1798 bus_space_handle_t ioh = sc->sc_ioh; 1799 1800 if (sc->ep_flags & EP_FLAGS_MII) { 1801 /* Stop the one second clock. */ 1802 untimeout(ep_tick, sc); 1803 } 1804 1805 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER) { 1806 /* 1807 * Clear the FIFO buffer count, thus halting 1808 * any currently-running transactions. 1809 */ 1810 GO_WINDOW(1); /* sanity */ 1811 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0); 1812 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0); 1813 } 1814 1815 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE); 1816 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK); 1817 while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS) 1818 ; 1819 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE); 1820 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER); 1821 1822 ep_complete_cmd(sc, EP_COMMAND, RX_RESET); 1823 ep_complete_cmd(sc, EP_COMMAND, TX_RESET); 1824 1825 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH); 1826 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK); 1827 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK); 1828 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER); 1829 1830 epmbufempty(sc); 1831 } 1832 1833 1834 /* 1835 * Before reboots, reset card completely. 1836 */ 1837 static void 1838 epshutdown(arg) 1839 void *arg; 1840 { 1841 register struct ep_softc *sc = arg; 1842 1843 if (sc->enabled) { 1844 epstop(sc); 1845 ep_complete_cmd(sc, EP_COMMAND, GLOBAL_RESET); 1846 } 1847 } 1848 1849 /* 1850 * We get eeprom data from the id_port given an offset into the 1851 * eeprom. Basically; after the ID_sequence is sent to all of 1852 * the cards; they enter the ID_CMD state where they will accept 1853 * command requests. 0x80-0xbf loads the eeprom data. We then 1854 * read the port 16 times and with every read; the cards check 1855 * for contention (ie: if one card writes a 0 bit and another 1856 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1857 * each card compares the data on the bus; if there is a difference 1858 * then that card goes into ID_WAIT state again). In the meantime; 1859 * one bit of data is returned in the AX register which is conveniently 1860 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1861 * bit of data with each read. 1862 * 1863 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1864 */ 1865 u_int16_t 1866 epreadeeprom(iot, ioh, offset) 1867 bus_space_tag_t iot; 1868 bus_space_handle_t ioh; 1869 int offset; 1870 { 1871 u_int16_t data = 0; 1872 int i; 1873 1874 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1875 delay(1000); 1876 for (i = 0; i < 16; i++) 1877 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1878 return (data); 1879 } 1880 1881 static int 1882 epbusyeeprom(sc) 1883 struct ep_softc *sc; 1884 { 1885 bus_space_tag_t iot = sc->sc_iot; 1886 bus_space_handle_t ioh = sc->sc_ioh; 1887 int i = 100, j; 1888 1889 if (sc->bustype == EP_BUS_PCMCIA) { 1890 delay(1000); 1891 return 0; 1892 } 1893 1894 j = 0; /* bad GCC flow analysis */ 1895 while (i--) { 1896 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND); 1897 if (j & EEPROM_BUSY) 1898 delay(100); 1899 else 1900 break; 1901 } 1902 if (!i) { 1903 printf("\n%s: eeprom failed to come ready\n", 1904 sc->sc_dev.dv_xname); 1905 return (1); 1906 } 1907 if (j & EEPROM_TST_MODE) { 1908 /* XXX PnP mode? */ 1909 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1910 return (1); 1911 } 1912 return (0); 1913 } 1914 1915 void 1916 epmbuffill(v) 1917 void *v; 1918 { 1919 struct ep_softc *sc = v; 1920 int s, i; 1921 1922 s = splnet(); 1923 i = sc->last_mb; 1924 do { 1925 if (sc->mb[i] == NULL) 1926 MGET(sc->mb[i], M_DONTWAIT, MT_DATA); 1927 if (sc->mb[i] == NULL) 1928 break; 1929 i = (i + 1) % MAX_MBS; 1930 } while (i != sc->next_mb); 1931 sc->last_mb = i; 1932 /* If the queue was not filled, try again. */ 1933 if (sc->last_mb != sc->next_mb) 1934 timeout(epmbuffill, sc, 1); 1935 splx(s); 1936 } 1937 1938 void 1939 epmbufempty(sc) 1940 struct ep_softc *sc; 1941 { 1942 int s, i; 1943 1944 s = splnet(); 1945 for (i = 0; i<MAX_MBS; i++) { 1946 if (sc->mb[i]) { 1947 m_freem(sc->mb[i]); 1948 sc->mb[i] = NULL; 1949 } 1950 } 1951 sc->last_mb = sc->next_mb = 0; 1952 untimeout(epmbuffill, sc); 1953 splx(s); 1954 } 1955 1956 int 1957 epenable(sc) 1958 struct ep_softc *sc; 1959 { 1960 1961 if (sc->enabled == 0 && sc->enable != NULL) { 1962 if ((*sc->enable)(sc) != 0) { 1963 printf("%s: device enable failed\n", 1964 sc->sc_dev.dv_xname); 1965 return (EIO); 1966 } 1967 } 1968 1969 sc->enabled = 1; 1970 return (0); 1971 } 1972 1973 void 1974 epdisable(sc) 1975 struct ep_softc *sc; 1976 { 1977 1978 if (sc->enabled != 0 && sc->disable != NULL) { 1979 (*sc->disable)(sc); 1980 sc->enabled = 0; 1981 } 1982 } 1983 1984 void 1985 ep_mii_setbit(sc, bit) 1986 struct ep_softc *sc; 1987 u_int16_t bit; 1988 { 1989 u_int16_t val; 1990 1991 /* We assume we're already in Window 4 */ 1992 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 1993 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 1994 val | bit); 1995 } 1996 1997 void 1998 ep_mii_clrbit(sc, bit) 1999 struct ep_softc *sc; 2000 u_int16_t bit; 2001 { 2002 u_int16_t val; 2003 2004 /* We assume we're already in Window 4 */ 2005 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT); 2006 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 2007 val & ~bit); 2008 } 2009 2010 u_int16_t 2011 ep_mii_readbit(sc, bit) 2012 struct ep_softc *sc; 2013 u_int16_t bit; 2014 { 2015 2016 /* We assume we're already in Window 4 */ 2017 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT) & 2018 bit); 2019 } 2020 2021 void 2022 ep_mii_sync(sc) 2023 struct ep_softc *sc; 2024 { 2025 int i; 2026 2027 /* We assume we're already in Window 4 */ 2028 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2029 for (i = 0; i < 32; i++) { 2030 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2031 ep_mii_setbit(sc, PHYSMGMT_CLK); 2032 } 2033 } 2034 2035 void 2036 ep_mii_sendbits(sc, data, nbits) 2037 struct ep_softc *sc; 2038 u_int32_t data; 2039 int nbits; 2040 { 2041 int i; 2042 2043 /* We assume we're already in Window 4 */ 2044 ep_mii_setbit(sc, PHYSMGMT_DIR); 2045 for (i = 1 << (nbits - 1); i; i = i >> 1) { 2046 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2047 ep_mii_readbit(sc, PHYSMGMT_CLK); 2048 if (data & i) 2049 ep_mii_setbit(sc, PHYSMGMT_DATA); 2050 else 2051 ep_mii_clrbit(sc, PHYSMGMT_DATA); 2052 ep_mii_setbit(sc, PHYSMGMT_CLK); 2053 ep_mii_readbit(sc, PHYSMGMT_CLK); 2054 } 2055 } 2056 2057 int 2058 ep_mii_readreg(self, phy, reg) 2059 struct device *self; 2060 int phy, reg; 2061 { 2062 struct ep_softc *sc = (struct ep_softc *)self; 2063 int val = 0, i, err; 2064 2065 /* 2066 * Read the PHY register by manually driving the MII control lines. 2067 */ 2068 2069 GO_WINDOW(4); 2070 2071 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0); 2072 2073 ep_mii_sync(sc); 2074 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2075 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 2076 ep_mii_sendbits(sc, phy, 5); 2077 ep_mii_sendbits(sc, reg, 5); 2078 2079 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2080 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2081 ep_mii_setbit(sc, PHYSMGMT_CLK); 2082 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2083 2084 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 2085 ep_mii_setbit(sc, PHYSMGMT_CLK); 2086 2087 /* Even if an error occurs, must still clock out the cycle. */ 2088 for (i = 0; i < 16; i++) { 2089 val <<= 1; 2090 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2091 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 2092 val |= 1; 2093 ep_mii_setbit(sc, PHYSMGMT_CLK); 2094 } 2095 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2096 ep_mii_setbit(sc, PHYSMGMT_CLK); 2097 2098 GO_WINDOW(1); /* back to operating window */ 2099 2100 return (err ? 0 : val); 2101 } 2102 2103 void 2104 ep_mii_writereg(self, phy, reg, val) 2105 struct device *self; 2106 int phy, reg, val; 2107 { 2108 struct ep_softc *sc = (struct ep_softc *)self; 2109 2110 /* 2111 * Write the PHY register by manually driving the MII control lines. 2112 */ 2113 2114 GO_WINDOW(4); 2115 2116 ep_mii_sync(sc); 2117 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2118 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2119 ep_mii_sendbits(sc, phy, 5); 2120 ep_mii_sendbits(sc, reg, 5); 2121 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2122 ep_mii_sendbits(sc, val, 16); 2123 2124 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2125 ep_mii_setbit(sc, PHYSMGMT_CLK); 2126 2127 GO_WINDOW(1); /* back to operating window */ 2128 } 2129 2130 void 2131 ep_statchg(self) 2132 struct device *self; 2133 { 2134 struct ep_softc *sc = (struct ep_softc *)self; 2135 bus_space_tag_t iot = sc->sc_iot; 2136 bus_space_handle_t ioh = sc->sc_ioh; 2137 int mctl; 2138 2139 /* XXX Update ifp->if_baudrate */ 2140 2141 GO_WINDOW(3); 2142 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL); 2143 if (sc->sc_mii.mii_media_active & IFM_FDX) 2144 mctl |= MAC_CONTROL_FDX; 2145 else 2146 mctl &= ~MAC_CONTROL_FDX; 2147 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl); 2148 GO_WINDOW(1); /* back to operating window */ 2149 } 2150
Indexes created Fri Sep 26 20:09:58 GMT 2025