elink3.c revision 1.52
1 /* $NetBSD: elink3.c,v 1.52 1999/02/17 03:41:00 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #define ETHER_MIN_LEN 64 124 #define ETHER_MAX_LEN 1518 125 #define ETHER_ADDR_LEN 6 126 127 #ifdef DEBUG 128 int epdebug = 0; 129 #endif 130 131 /* 132 * Structure to map media-present bits in boards to ifmedia codes and 133 * printable media names. Used for table-driven ifmedia initialization. 134 */ 135 struct ep_media { 136 int epm_mpbit; /* media present bit */ 137 const char *epm_name; /* name of medium */ 138 int epm_ifmedia; /* ifmedia word for medium */ 139 int epm_epmedia; /* ELINKMEDIA_* constant */ 140 }; 141 142 /* 143 * Media table for the Demon/Vortex/Boomerang chipsets. 144 * 145 * Note that MII on the Demon and Vortex (3c59x) indicates an external 146 * MII connector (for connecting an external PHY) ... I think. Treat 147 * it as `manual' on these chips. 148 * 149 * Any Boomerang (3c90x) chips with MII really do have an internal 150 * MII and real PHYs attached; no `native' media. 151 */ 152 struct ep_media ep_vortex_media[] = { 153 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 154 ELINKMEDIA_10BASE_T }, 155 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 156 ELINKMEDIA_10BASE_T }, 157 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 158 ELINKMEDIA_AUI }, 159 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 160 ELINKMEDIA_10BASE_2 }, 161 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 162 ELINKMEDIA_100BASE_TX }, 163 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 164 ELINKMEDIA_100BASE_TX }, 165 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 166 ELINKMEDIA_100BASE_FX }, 167 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 168 ELINKMEDIA_MII }, 169 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 170 ELINKMEDIA_100BASE_T4 }, 171 { 0, NULL, 0, 172 0 }, 173 }; 174 175 /* 176 * Media table for the older 3Com Etherlink III chipset, used 177 * in the 3c509, 3c579, and 3c589. 178 */ 179 struct ep_media ep_509_media[] = { 180 { ELINK_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 181 ELINKMEDIA_10BASE_T }, 182 { ELINK_W0_CC_AUI, "10base5", IFM_ETHER|IFM_10_5, 183 ELINKMEDIA_AUI }, 184 { ELINK_W0_CC_BNC, "10base2", IFM_ETHER|IFM_10_2, 185 ELINKMEDIA_10BASE_2 }, 186 { 0, NULL, 0, 187 0 }, 188 }; 189 190 void ep_internalconfig __P((struct ep_softc *sc)); 191 void ep_vortex_probemedia __P((struct ep_softc *sc)); 192 void ep_509_probemedia __P((struct ep_softc *sc)); 193 194 static void eptxstat __P((struct ep_softc *)); 195 static int epstatus __P((struct ep_softc *)); 196 void epinit __P((struct ep_softc *)); 197 int epioctl __P((struct ifnet *, u_long, caddr_t)); 198 void epstart __P((struct ifnet *)); 199 void epwatchdog __P((struct ifnet *)); 200 void epreset __P((struct ep_softc *)); 201 static void epshutdown __P((void *)); 202 void epread __P((struct ep_softc *)); 203 struct mbuf *epget __P((struct ep_softc *, int)); 204 void epmbuffill __P((void *)); 205 void epmbufempty __P((struct ep_softc *)); 206 void epsetfilter __P((struct ep_softc *)); 207 void epsetmedia __P((struct ep_softc *)); 208 209 /* ifmedia callbacks */ 210 int ep_media_change __P((struct ifnet *ifp)); 211 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 212 213 /* MII callbacks */ 214 int ep_mii_readreg __P((struct device *, int, int)); 215 void ep_mii_writereg __P((struct device *, int, int, int)); 216 void ep_statchg __P((struct device *)); 217 218 void ep_tick __P((void *)); 219 220 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 221 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 222 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 223 void ep_mii_sync __P((struct ep_softc *)); 224 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 225 226 static int epbusyeeprom __P((struct ep_softc *)); 227 static inline void ep_complete_cmd __P((struct ep_softc *sc, 228 u_int cmd, u_int arg)); 229 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 230 231 /* 232 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 233 * Window 1 registers offset! 234 */ 235 static __inline int 236 ep_w1_reg(sc, reg) 237 struct ep_softc *sc; 238 int reg; 239 { 240 241 switch (sc->ep_chipset) { 242 case ELINK_CHIPSET_CORKSCREW: 243 return (reg + 0x10); 244 245 case ELINK_CHIPSET_ROADRUNNER: 246 switch (reg) { 247 case ELINK_W1_FREE_TX: 248 case ELINK_W1_RUNNER_RDCTL: 249 case ELINK_W1_RUNNER_WRCTL: 250 return (reg); 251 } 252 return (reg + 0x10); 253 } 254 255 return (reg); 256 } 257 258 /* 259 * Issue a (reset) command, and be sure it has completed. 260 * Used for commands that reset part or all of the board. 261 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 262 * but older hardware doesn't implement it and we must delay. 263 * It's easiest to just delay always. 264 */ 265 static inline void 266 ep_complete_cmd(sc, cmd, arg) 267 struct ep_softc *sc; 268 u_int cmd, arg; 269 { 270 register bus_space_tag_t iot = sc->sc_iot; 271 register bus_space_handle_t ioh = sc->sc_ioh; 272 273 bus_space_write_2(iot, ioh, cmd, arg); 274 275 #ifdef notyet 276 /* if this adapter family has S_COMMAND_IN_PROGRESS, use it */ 277 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 278 ; 279 else 280 #else 281 DELAY(100000); /* need at least 1 ms, but be generous. */ 282 #endif 283 } 284 285 /* 286 * Back-end attach and configure. 287 */ 288 void 289 epconfig(sc, chipset, enaddr) 290 struct ep_softc *sc; 291 u_short chipset; 292 u_int8_t *enaddr; 293 { 294 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 295 bus_space_tag_t iot = sc->sc_iot; 296 bus_space_handle_t ioh = sc->sc_ioh; 297 u_int16_t i; 298 u_int8_t myla[6]; 299 300 sc->ep_chipset = chipset; 301 302 /* 303 * We could have been groveling around in other register 304 * windows in the front-end; make sure we're in window 0 305 * to read the EEPROM. 306 */ 307 GO_WINDOW(0); 308 309 if (enaddr == NULL) { 310 /* 311 * Read the station address from the eeprom 312 */ 313 for (i = 0; i < 3; i++) { 314 u_int16_t x; 315 if (epbusyeeprom(sc)) 316 return; /* XXX why is eeprom busy? */ 317 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 318 READ_EEPROM | i); 319 if (epbusyeeprom(sc)) 320 return; /* XXX why is eeprom busy? */ 321 x = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 322 myla[(i << 1)] = x >> 8; 323 myla[(i << 1) + 1] = x; 324 } 325 enaddr = myla; 326 } 327 328 /* 329 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 330 * allow FDDI-sized (4500) byte packets. Commands only take an 331 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 332 * packet length. 333 * Commands to these cards implicitly upshift a packet size 334 * or threshold by 2 bits. 335 * To detect cards with large-packet support, we probe by setting 336 * the transmit threshold register, then change windows and 337 * read back the threshold register directly, and see if the 338 * threshold value was shifted or not. 339 */ 340 bus_space_write_2(iot, ioh, ELINK_COMMAND, 341 SET_TX_AVAIL_THRESH | ELINK_LARGEWIN_PROBE ); 342 GO_WINDOW(5); 343 i = bus_space_read_2(iot, ioh, ELINK_W5_TX_AVAIL_THRESH); 344 GO_WINDOW(1); 345 switch (i) { 346 case ELINK_LARGEWIN_PROBE: 347 case (ELINK_LARGEWIN_PROBE & ELINK_LARGEWIN_MASK): 348 sc->ep_pktlenshift = 0; 349 break; 350 351 case (ELINK_LARGEWIN_PROBE << 2): 352 sc->ep_pktlenshift = 2; 353 break; 354 355 default: 356 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 357 "Interface disabled\n", 358 sc->sc_dev.dv_xname, ELINK_LARGEWIN_PROBE, (int) i); 359 return; 360 } 361 362 /* 363 * Ensure Tx-available interrupts are enabled for 364 * start the interface. 365 * XXX should be in epinit()? 366 */ 367 bus_space_write_2(iot, ioh, ELINK_COMMAND, 368 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 369 370 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 371 ifp->if_softc = sc; 372 ifp->if_start = epstart; 373 ifp->if_ioctl = epioctl; 374 ifp->if_watchdog = epwatchdog; 375 ifp->if_flags = 376 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 377 378 if_attach(ifp); 379 ether_ifattach(ifp, enaddr); 380 381 /* 382 * Finish configuration: 383 * determine chipset if the front-end couldn't do so, 384 * show board details, set media. 385 */ 386 387 /* 388 * Print RAM size. We also print the Ethernet address in here. 389 * It's extracted from the ifp, so we have to make sure it's 390 * been attached first. 391 */ 392 ep_internalconfig(sc); 393 GO_WINDOW(0); 394 395 /* 396 * Display some additional information, if pertinent. 397 */ 398 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 399 printf("%s: RoadRunner FIFO buffer enabled\n", 400 sc->sc_dev.dv_xname); 401 402 /* 403 * Initialize our media structures and MII info. We'll 404 * probe the MII if we discover that we have one. 405 */ 406 sc->sc_mii.mii_ifp = ifp; 407 sc->sc_mii.mii_readreg = ep_mii_readreg; 408 sc->sc_mii.mii_writereg = ep_mii_writereg; 409 sc->sc_mii.mii_statchg = ep_statchg; 410 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 411 ep_media_status); 412 413 /* 414 * Now, determine which media we have. 415 */ 416 switch (sc->ep_chipset) { 417 case ELINK_CHIPSET_BOOMERANG: 418 case ELINK_CHIPSET_ROADRUNNER: 419 /* 420 * If the device has MII, probe it. We won't be using 421 * any `native' media in this case, only PHYs. If 422 * we don't, just treat the Boomerang like the Vortex. 423 */ 424 if (sc->ep_flags & ELINK_FLAGS_MII) { 425 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 426 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 427 ifmedia_add(&sc->sc_mii.mii_media, 428 IFM_ETHER|IFM_NONE, 0, NULL); 429 ifmedia_set(&sc->sc_mii.mii_media, 430 IFM_ETHER|IFM_NONE); 431 } else { 432 ifmedia_set(&sc->sc_mii.mii_media, 433 IFM_ETHER|IFM_AUTO); 434 } 435 break; 436 } 437 /* FALLTHROUGH */ 438 439 case ELINK_CHIPSET_VORTEX: 440 ep_vortex_probemedia(sc); 441 break; 442 443 default: 444 ep_509_probemedia(sc); 445 break; 446 } 447 448 GO_WINDOW(1); /* Window 1 is operating window */ 449 450 #if NBPFILTER > 0 451 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 452 sizeof(struct ether_header)); 453 #endif 454 455 #if NRND > 0 456 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET); 457 #endif 458 459 sc->tx_start_thresh = 20; /* probably a good starting point. */ 460 461 /* Establish callback to reset card when we reboot. */ 462 shutdownhook_establish(epshutdown, sc); 463 464 ep_complete_cmd(sc, ELINK_COMMAND, RX_RESET); 465 ep_complete_cmd(sc, ELINK_COMMAND, TX_RESET); 466 } 467 468 469 /* 470 * Show interface-model-independent info from window 3 471 * internal-configuration register. 472 */ 473 void 474 ep_internalconfig(sc) 475 struct ep_softc *sc; 476 { 477 bus_space_tag_t iot = sc->sc_iot; 478 bus_space_handle_t ioh = sc->sc_ioh; 479 480 u_int config0; 481 u_int config1; 482 483 int ram_size, ram_width, ram_speed, rom_size, ram_split; 484 /* 485 * NVRAM buffer Rx:Tx config names for busmastering cards 486 * (Demon, Vortex, and later). 487 */ 488 const char *onboard_ram_config[] = { 489 "5:3", "3:1", "1:1", "3:5" }; 490 491 GO_WINDOW(3); 492 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 493 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 494 GO_WINDOW(0); 495 496 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 497 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 498 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 499 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 500 501 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 502 503 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 504 sc->sc_dev.dv_xname, 505 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 506 8 << ram_size, 507 (ram_width) ? "word" : "byte", 508 onboard_ram_config[ram_split]); 509 } 510 511 512 /* 513 * Find supported media on 3c509-generation hardware that doesn't have 514 * a "reset_options" register in window 3. 515 * Use the config_cntrl register in window 0 instead. 516 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 517 * that implement CONFIG_CTRL. We don't have a good way to set the 518 * default active mediuim; punt to ifconfig instead. 519 */ 520 void 521 ep_509_probemedia(sc) 522 struct ep_softc *sc; 523 { 524 bus_space_tag_t iot = sc->sc_iot; 525 bus_space_handle_t ioh = sc->sc_ioh; 526 struct ifmedia *ifm = &sc->sc_mii.mii_media; 527 u_int16_t ep_w0_config, port; 528 struct ep_media *epm; 529 const char *sep = "", *defmedianame = NULL; 530 int defmedia = 0; 531 532 GO_WINDOW(0); 533 ep_w0_config = bus_space_read_2(iot, ioh, ELINK_W0_CONFIG_CTRL); 534 535 printf("%s: ", sc->sc_dev.dv_xname); 536 537 /* Sanity check that there are any media! */ 538 if ((ep_w0_config & ELINK_W0_CC_MEDIAMASK) == 0) { 539 printf("no media present!\n"); 540 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 541 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 542 return; 543 } 544 545 /* 546 * Get the default media from the EEPROM. 547 */ 548 if (epbusyeeprom(sc)) 549 return; /* XXX why is eeprom busy? */ 550 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 551 READ_EEPROM | EEPROM_ADDR_CFG); 552 if (epbusyeeprom(sc)) 553 return; /* XXX why is eeprom busy? */ 554 port = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA) >> 14; 555 556 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 557 558 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 559 if (ep_w0_config & epm->epm_mpbit) { 560 /* 561 * This simple test works because 509 chipsets 562 * don't do full-duplex. 563 */ 564 if (epm->epm_epmedia == port || defmedia == 0) { 565 defmedia = epm->epm_ifmedia; 566 defmedianame = epm->epm_name; 567 } 568 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 569 NULL); 570 PRINT(epm->epm_name); 571 } 572 } 573 574 #undef PRINT 575 576 #ifdef DIAGNOSTIC 577 if (defmedia == 0) 578 panic("ep_509_probemedia: impossible"); 579 #endif 580 581 printf(" (default %s)\n", defmedianame); 582 ifmedia_set(ifm, defmedia); 583 } 584 585 /* 586 * Find media present on large-packet-capable elink3 devices. 587 * Show onboard configuration of large-packet-capable elink3 devices 588 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 589 * Use media and card-version info in window 3 instead. 590 */ 591 void 592 ep_vortex_probemedia(sc) 593 struct ep_softc *sc; 594 { 595 bus_space_tag_t iot = sc->sc_iot; 596 bus_space_handle_t ioh = sc->sc_ioh; 597 struct ifmedia *ifm = &sc->sc_mii.mii_media; 598 struct ep_media *epm; 599 u_int config1; 600 int reset_options; 601 int default_media; /* 3-bit encoding of default (EEPROM) media */ 602 int defmedia = 0; 603 const char *sep = "", *defmedianame = NULL; 604 605 GO_WINDOW(3); 606 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 607 reset_options = (int)bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 608 GO_WINDOW(0); 609 610 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 611 612 printf("%s: ", sc->sc_dev.dv_xname); 613 614 /* Sanity check that there are any media! */ 615 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 616 printf("no media present!\n"); 617 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 618 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 619 return; 620 } 621 622 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 623 624 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 625 if (reset_options & epm->epm_mpbit) { 626 /* 627 * Default media is a little more complicated 628 * on the Vortex. We support full-duplex which 629 * uses the same reset options bit. 630 * 631 * XXX Check EEPROM for default to FDX? 632 */ 633 if (epm->epm_epmedia == default_media) { 634 if ((epm->epm_ifmedia & IFM_FDX) == 0) { 635 defmedia = epm->epm_ifmedia; 636 defmedianame = epm->epm_name; 637 } 638 } else if (defmedia == 0) { 639 defmedia = epm->epm_ifmedia; 640 defmedianame = epm->epm_name; 641 } 642 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 643 NULL); 644 PRINT(epm->epm_name); 645 } 646 } 647 648 #undef PRINT 649 650 #ifdef DIAGNOSTIC 651 if (defmedia == 0) 652 panic("ep_vortex_probemedia: impossible"); 653 #endif 654 655 printf(" (default %s)\n", defmedianame); 656 ifmedia_set(ifm, defmedia); 657 } 658 659 /* 660 * One second timer, used to tick the MII. 661 */ 662 void 663 ep_tick(arg) 664 void *arg; 665 { 666 struct ep_softc *sc = arg; 667 int s; 668 669 #ifdef DIAGNOSTIC 670 if ((sc->ep_flags & ELINK_FLAGS_MII) == 0) 671 panic("ep_tick"); 672 #endif 673 674 s = splnet(); 675 mii_tick(&sc->sc_mii); 676 splx(s); 677 678 timeout(ep_tick, sc, hz); 679 } 680 681 /* 682 * Bring device up. 683 * 684 * The order in here seems important. Otherwise we may not receive 685 * interrupts. ?! 686 */ 687 void 688 epinit(sc) 689 register struct ep_softc *sc; 690 { 691 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 692 bus_space_tag_t iot = sc->sc_iot; 693 bus_space_handle_t ioh = sc->sc_ioh; 694 int i; 695 696 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 697 ; 698 699 if (sc->bustype != ELINK_BUS_PCI) { 700 GO_WINDOW(0); 701 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, 0); 702 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 703 } 704 705 if (sc->bustype == ELINK_BUS_PCMCIA) { 706 bus_space_write_2(iot, ioh, ELINK_W0_RESOURCE_CFG, 0x3f00); 707 } 708 709 GO_WINDOW(2); 710 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 711 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 712 LLADDR(ifp->if_sadl)[i]); 713 714 /* 715 * Reset the station-address receive filter. 716 * A bug workaround for busmastering (Vortex, Demon) cards. 717 */ 718 for (i = 0; i < 6; i++) 719 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 720 721 ep_complete_cmd(sc, ELINK_COMMAND, RX_RESET); 722 ep_complete_cmd(sc, ELINK_COMMAND, TX_RESET); 723 724 GO_WINDOW(1); /* Window 1 is operating window */ 725 for (i = 0; i < 31; i++) 726 bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS)); 727 728 /* Set threshhold for for Tx-space avaiable interrupt. */ 729 bus_space_write_2(iot, ioh, ELINK_COMMAND, 730 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 731 732 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 733 /* 734 * Enable options in the PCMCIA LAN COR register, via 735 * RoadRunner Window 1. 736 * 737 * XXX MAGIC CONSTANTS! 738 */ 739 u_int16_t cor; 740 741 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, (1 << 11)); 742 743 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 744 if (sc->ep_flags & ELINK_FLAGS_USESHAREDMEM) 745 cor |= 0x10; 746 if (sc->ep_flags & ELINK_FLAGS_FORCENOWAIT) 747 cor |= 0x20; 748 bus_space_write_2(iot, ioh, 0, cor); 749 750 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 751 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 752 } 753 754 /* Enable interrupts. */ 755 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 756 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 757 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | 758 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 759 760 /* 761 * Attempt to get rid of any stray interrupts that occured during 762 * configuration. On the i386 this isn't possible because one may 763 * already be queued. However, a single stray interrupt is 764 * unimportant. 765 */ 766 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 767 768 epsetfilter(sc); 769 epsetmedia(sc); 770 771 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 772 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 773 774 epmbuffill(sc); 775 776 /* Interface is now `running', with no output active. */ 777 ifp->if_flags |= IFF_RUNNING; 778 ifp->if_flags &= ~IFF_OACTIVE; 779 780 if (sc->ep_flags & ELINK_FLAGS_MII) { 781 /* Start the one second clock. */ 782 timeout(ep_tick, sc, hz); 783 } 784 785 /* Attempt to start output, if any. */ 786 epstart(ifp); 787 } 788 789 790 /* 791 * Set multicast receive filter. 792 * elink3 hardware has no selective multicast filter in hardware. 793 * Enable reception of all multicasts and filter in software. 794 */ 795 void 796 epsetfilter(sc) 797 register struct ep_softc *sc; 798 { 799 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 800 801 GO_WINDOW(1); /* Window 1 is operating window */ 802 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, SET_RX_FILTER | 803 FIL_INDIVIDUAL | FIL_BRDCST | 804 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 805 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 806 } 807 808 int 809 ep_media_change(ifp) 810 struct ifnet *ifp; 811 { 812 register struct ep_softc *sc = ifp->if_softc; 813 814 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 815 epreset(sc); 816 817 return (0); 818 } 819 820 /* 821 * Set the card to use the specified media. 822 */ 823 void 824 epsetmedia(sc) 825 struct ep_softc *sc; 826 { 827 bus_space_tag_t iot = sc->sc_iot; 828 bus_space_handle_t ioh = sc->sc_ioh; 829 830 /* Turn everything off. First turn off linkbeat and UTP. */ 831 GO_WINDOW(4); 832 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0x0); 833 834 /* Turn off coax */ 835 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 836 delay(1000); 837 838 /* 839 * If the device has MII, select it, and then tell the 840 * PHY which media to use. 841 */ 842 if (sc->ep_flags & ELINK_FLAGS_MII) { 843 int config0, config1; 844 845 GO_WINDOW(3); 846 847 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 848 int resopt; 849 850 resopt = bus_space_read_2(iot, ioh, 851 ELINK_W3_RESET_OPTIONS); 852 bus_space_write_2(iot, ioh, 853 ELINK_W3_RESET_OPTIONS, resopt|ELINK_RUNNER_ENABLE_MII); 854 } 855 856 config0 = (u_int)bus_space_read_2(iot, ioh, 857 ELINK_W3_INTERNAL_CONFIG); 858 config1 = (u_int)bus_space_read_2(iot, ioh, 859 ELINK_W3_INTERNAL_CONFIG + 2); 860 861 config1 = config1 & ~CONFIG_MEDIAMASK; 862 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 863 864 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 865 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 866 GO_WINDOW(1); /* back to operating window */ 867 868 mii_mediachg(&sc->sc_mii); 869 return; 870 } 871 872 /* 873 * Now turn on the selected media/transceiver. 874 */ 875 GO_WINDOW(4); 876 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 877 case IFM_10_T: 878 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 879 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 880 break; 881 882 case IFM_10_2: 883 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 884 DELAY(1000); /* 50ms not enmough? */ 885 break; 886 887 case IFM_100_TX: 888 case IFM_100_FX: 889 case IFM_100_T4: /* XXX check documentation */ 890 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 891 LINKBEAT_ENABLE); 892 DELAY(1000); /* not strictly necessary? */ 893 break; 894 895 case IFM_10_5: 896 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 897 SQE_ENABLE); 898 DELAY(1000); /* not strictly necessary? */ 899 break; 900 901 case IFM_MANUAL: 902 /* 903 * Nothing to do here; we are actually enabling the 904 * external PHY on the MII port. 905 */ 906 break; 907 908 case IFM_NONE: 909 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 910 return; 911 912 default: 913 panic("epsetmedia: impossible"); 914 } 915 916 /* 917 * Tell the chip which port to use. 918 */ 919 switch (sc->ep_chipset) { 920 case ELINK_CHIPSET_VORTEX: 921 case ELINK_CHIPSET_BOOMERANG: 922 { 923 int mctl, config0, config1; 924 925 GO_WINDOW(3); 926 config0 = (u_int)bus_space_read_2(iot, ioh, 927 ELINK_W3_INTERNAL_CONFIG); 928 config1 = (u_int)bus_space_read_2(iot, ioh, 929 ELINK_W3_INTERNAL_CONFIG + 2); 930 931 config1 = config1 & ~CONFIG_MEDIAMASK; 932 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 933 CONFIG_MEDIAMASK_SHIFT); 934 935 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 936 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, 937 config1); 938 939 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 940 if (sc->sc_mii.mii_media.ifm_cur->ifm_media & IFM_FDX) 941 mctl |= MAC_CONTROL_FDX; 942 else 943 mctl &= ~MAC_CONTROL_FDX; 944 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 945 break; 946 } 947 default: 948 { 949 int w0_addr_cfg; 950 951 GO_WINDOW(0); 952 w0_addr_cfg = bus_space_read_2(iot, ioh, ELINK_W0_ADDRESS_CFG); 953 w0_addr_cfg &= 0x3fff; 954 bus_space_write_2(iot, ioh, ELINK_W0_ADDRESS_CFG, w0_addr_cfg | 955 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 956 DELAY(1000); 957 break; 958 } 959 } 960 961 GO_WINDOW(1); /* Window 1 is operating window */ 962 } 963 964 /* 965 * Get currently-selected media from card. 966 * (if_media callback, may be called before interface is brought up). 967 */ 968 void 969 ep_media_status(ifp, req) 970 struct ifnet *ifp; 971 struct ifmediareq *req; 972 { 973 register struct ep_softc *sc = ifp->if_softc; 974 bus_space_tag_t iot = sc->sc_iot; 975 bus_space_handle_t ioh = sc->sc_ioh; 976 977 if (sc->enabled == 0) { 978 req->ifm_active = IFM_ETHER|IFM_NONE; 979 req->ifm_status = 0; 980 return; 981 } 982 983 /* 984 * If we have MII, go ask the PHY what's going on. 985 */ 986 if (sc->ep_flags & ELINK_FLAGS_MII) { 987 mii_pollstat(&sc->sc_mii); 988 req->ifm_active = sc->sc_mii.mii_media_active; 989 req->ifm_status = sc->sc_mii.mii_media_status; 990 return; 991 } 992 993 /* 994 * Ok, at this point we claim that our active media is 995 * the currently selected media. We'll update our status 996 * if our chipset allows us to detect link. 997 */ 998 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 999 req->ifm_status = 0; 1000 1001 switch (sc->ep_chipset) { 1002 case ELINK_CHIPSET_VORTEX: 1003 case ELINK_CHIPSET_BOOMERANG: 1004 GO_WINDOW(4); 1005 req->ifm_status = IFM_AVALID; 1006 if (bus_space_read_2(iot, ioh, ELINK_W4_MEDIA_TYPE) & 1007 LINKBEAT_DETECT) 1008 req->ifm_status |= IFM_ACTIVE; 1009 GO_WINDOW(1); /* back to operating window */ 1010 break; 1011 } 1012 } 1013 1014 1015 1016 /* 1017 * Start outputting on the interface. 1018 * Always called as splnet(). 1019 */ 1020 void 1021 epstart(ifp) 1022 struct ifnet *ifp; 1023 { 1024 register struct ep_softc *sc = ifp->if_softc; 1025 bus_space_tag_t iot = sc->sc_iot; 1026 bus_space_handle_t ioh = sc->sc_ioh; 1027 struct mbuf *m, *m0; 1028 int sh, len, pad; 1029 bus_addr_t txreg; 1030 1031 /* Don't transmit if interface is busy or not running */ 1032 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1033 return; 1034 1035 startagain: 1036 /* Sneak a peek at the next packet */ 1037 m0 = ifp->if_snd.ifq_head; 1038 if (m0 == 0) 1039 return; 1040 1041 /* We need to use m->m_pkthdr.len, so require the header */ 1042 if ((m0->m_flags & M_PKTHDR) == 0) 1043 panic("epstart: no header mbuf"); 1044 len = m0->m_pkthdr.len; 1045 1046 pad = (4 - len) & 3; 1047 1048 /* 1049 * The 3c509 automatically pads short packets to minimum ethernet 1050 * length, but we drop packets that are too large. Perhaps we should 1051 * truncate them instead? 1052 */ 1053 if (len + pad > ETHER_MAX_LEN) { 1054 /* packet is obviously too large: toss it */ 1055 ++ifp->if_oerrors; 1056 IF_DEQUEUE(&ifp->if_snd, m0); 1057 m_freem(m0); 1058 goto readcheck; 1059 } 1060 1061 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_FREE_TX)) < 1062 len + pad + 4) { 1063 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1064 SET_TX_AVAIL_THRESH | 1065 ((len + pad + 4) >> sc->ep_pktlenshift)); 1066 /* not enough room in FIFO */ 1067 ifp->if_flags |= IFF_OACTIVE; 1068 return; 1069 } else { 1070 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1071 SET_TX_AVAIL_THRESH | ELINK_THRESH_DISABLE ); 1072 } 1073 1074 IF_DEQUEUE(&ifp->if_snd, m0); 1075 if (m0 == 0) /* not really needed */ 1076 return; 1077 1078 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_TX_START_THRESH | 1079 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/) ); 1080 1081 #if NBPFILTER > 0 1082 if (ifp->if_bpf) 1083 bpf_mtap(ifp->if_bpf, m0); 1084 #endif 1085 1086 /* 1087 * Do the output at splhigh() so that an interrupt from another device 1088 * won't cause a FIFO underrun. 1089 */ 1090 sh = splhigh(); 1091 1092 txreg = ep_w1_reg(sc, ELINK_W1_TX_PIO_WR_1); 1093 1094 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1095 /* 1096 * Prime the FIFO buffer counter (number of 16-bit 1097 * words about to be written to the FIFO). 1098 * 1099 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1100 * COUNTER IS NON-ZERO! 1101 */ 1102 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 1103 (len + pad) >> 1); 1104 } 1105 1106 bus_space_write_2(iot, ioh, txreg, len); 1107 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1108 if (ELINK_IS_BUS_32(sc->bustype)) { 1109 for (m = m0; m; ) { 1110 if (m->m_len > 3) { 1111 /* align our reads from core */ 1112 if (mtod(m, u_long) & 3) { 1113 u_long count = 1114 4 - (mtod(m, u_long) & 3); 1115 bus_space_write_multi_1(iot, ioh, 1116 txreg, mtod(m, u_int8_t *), count); 1117 m->m_data = 1118 (void *)(mtod(m, u_long) + count); 1119 m->m_len -= count; 1120 } 1121 bus_space_write_multi_4(iot, ioh, 1122 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1123 m->m_data = (void *)(mtod(m, u_long) + 1124 (u_long)(m->m_len & ~3)); 1125 m->m_len -= m->m_len & ~3; 1126 } 1127 if (m->m_len) { 1128 bus_space_write_multi_1(iot, ioh, 1129 txreg, mtod(m, u_int8_t *), m->m_len); 1130 } 1131 MFREE(m, m0); 1132 m = m0; 1133 } 1134 } else { 1135 for (m = m0; m; ) { 1136 if (m->m_len > 1) { 1137 if (mtod(m, u_long) & 1) { 1138 bus_space_write_1(iot, ioh, 1139 txreg, *(mtod(m, u_int8_t *))); 1140 m->m_data = 1141 (void *)(mtod(m, u_long) + 1); 1142 m->m_len -= 1; 1143 } 1144 bus_space_write_multi_2(iot, ioh, 1145 txreg, mtod(m, u_int16_t *), 1146 m->m_len >> 1); 1147 } 1148 if (m->m_len & 1) { 1149 bus_space_write_1(iot, ioh, txreg, 1150 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1151 } 1152 MFREE(m, m0); 1153 m = m0; 1154 } 1155 } 1156 while (pad--) 1157 bus_space_write_1(iot, ioh, txreg, 0); 1158 1159 splx(sh); 1160 1161 ++ifp->if_opackets; 1162 1163 readcheck: 1164 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)) & 1165 ERR_INCOMPLETE) == 0) { 1166 /* We received a complete packet. */ 1167 u_int16_t status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1168 1169 if ((status & S_INTR_LATCH) == 0) { 1170 /* 1171 * No interrupt, read the packet and continue 1172 * Is this supposed to happen? Is my motherboard 1173 * completely busted? 1174 */ 1175 epread(sc); 1176 } else { 1177 /* Got an interrupt, return so that it gets serviced. */ 1178 return; 1179 } 1180 } else { 1181 /* Check if we are stuck and reset [see XXX comment] */ 1182 if (epstatus(sc)) { 1183 if (ifp->if_flags & IFF_DEBUG) 1184 printf("%s: adapter reset\n", 1185 sc->sc_dev.dv_xname); 1186 epreset(sc); 1187 } 1188 } 1189 1190 goto startagain; 1191 } 1192 1193 1194 /* 1195 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1196 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1197 * We detect this situation and we reset the adapter. 1198 * It happens at times when there is a lot of broadcast traffic 1199 * on the cable (once in a blue moon). 1200 */ 1201 static int 1202 epstatus(sc) 1203 register struct ep_softc *sc; 1204 { 1205 bus_space_tag_t iot = sc->sc_iot; 1206 bus_space_handle_t ioh = sc->sc_ioh; 1207 u_int16_t fifost; 1208 1209 /* 1210 * Check the FIFO status and act accordingly 1211 */ 1212 GO_WINDOW(4); 1213 fifost = bus_space_read_2(iot, ioh, ELINK_W4_FIFO_DIAG); 1214 GO_WINDOW(1); 1215 1216 if (fifost & FIFOS_RX_UNDERRUN) { 1217 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1218 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1219 epreset(sc); 1220 return 0; 1221 } 1222 1223 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1224 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1225 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1226 return 1; 1227 } 1228 1229 if (fifost & FIFOS_RX_OVERRUN) { 1230 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1231 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1232 return 1; 1233 } 1234 1235 if (fifost & FIFOS_TX_OVERRUN) { 1236 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1237 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1238 epreset(sc); 1239 return 0; 1240 } 1241 1242 return 0; 1243 } 1244 1245 1246 static void 1247 eptxstat(sc) 1248 register struct ep_softc *sc; 1249 { 1250 bus_space_tag_t iot = sc->sc_iot; 1251 bus_space_handle_t ioh = sc->sc_ioh; 1252 int i; 1253 1254 /* 1255 * We need to read+write TX_STATUS until we get a 0 status 1256 * in order to turn off the interrupt flag. 1257 */ 1258 while ((i = bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS))) 1259 & TXS_COMPLETE) { 1260 bus_space_write_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS), 1261 0x0); 1262 1263 if (i & TXS_JABBER) { 1264 ++sc->sc_ethercom.ec_if.if_oerrors; 1265 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1266 printf("%s: jabber (%x)\n", 1267 sc->sc_dev.dv_xname, i); 1268 epreset(sc); 1269 } else if (i & TXS_UNDERRUN) { 1270 ++sc->sc_ethercom.ec_if.if_oerrors; 1271 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1272 printf("%s: fifo underrun (%x) @%d\n", 1273 sc->sc_dev.dv_xname, i, 1274 sc->tx_start_thresh); 1275 if (sc->tx_succ_ok < 100) 1276 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1277 sc->tx_start_thresh + 20); 1278 sc->tx_succ_ok = 0; 1279 epreset(sc); 1280 } else if (i & TXS_MAX_COLLISION) { 1281 ++sc->sc_ethercom.ec_if.if_collisions; 1282 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 1283 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1284 } else 1285 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1286 } 1287 } 1288 1289 int 1290 epintr(arg) 1291 void *arg; 1292 { 1293 register struct ep_softc *sc = arg; 1294 bus_space_tag_t iot = sc->sc_iot; 1295 bus_space_handle_t ioh = sc->sc_ioh; 1296 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1297 u_int16_t status; 1298 int ret = 0; 1299 int addrandom = 0; 1300 1301 if (sc->enabled == 0) 1302 return (0); 1303 1304 for (;;) { 1305 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1306 1307 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1308 1309 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1310 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1311 if ((status & S_INTR_LATCH) == 0) { 1312 #if 0 1313 printf("%s: intr latch cleared\n", 1314 sc->sc_dev.dv_xname); 1315 #endif 1316 break; 1317 } 1318 } 1319 1320 ret = 1; 1321 1322 /* 1323 * Acknowledge any interrupts. It's important that we do this 1324 * first, since there would otherwise be a race condition. 1325 * Due to the i386 interrupt queueing, we may get spurious 1326 * interrupts occasionally. 1327 */ 1328 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1329 (status & (C_INTR_LATCH | 1330 C_CARD_FAILURE | 1331 C_TX_COMPLETE | 1332 C_TX_AVAIL | 1333 C_RX_COMPLETE | 1334 C_RX_EARLY | 1335 C_INT_RQD | 1336 C_UPD_STATS))); 1337 1338 #if 0 1339 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1340 1341 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1342 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1343 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1344 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1345 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1346 #endif 1347 1348 if (status & S_RX_COMPLETE) { 1349 epread(sc); 1350 addrandom = 1; 1351 } 1352 if (status & S_TX_AVAIL) { 1353 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1354 epstart(&sc->sc_ethercom.ec_if); 1355 addrandom = 1; 1356 } 1357 if (status & S_CARD_FAILURE) { 1358 printf("%s: adapter failure (%x)\n", 1359 sc->sc_dev.dv_xname, status); 1360 epreset(sc); 1361 return (1); 1362 } 1363 if (status & S_TX_COMPLETE) { 1364 eptxstat(sc); 1365 epstart(ifp); 1366 addrandom = 1; 1367 } 1368 1369 #if NRND > 0 1370 if (status) 1371 rnd_add_uint32(&sc->rnd_source, status); 1372 #endif 1373 } 1374 1375 /* no more interrupts */ 1376 return (ret); 1377 } 1378 1379 void 1380 epread(sc) 1381 register struct ep_softc *sc; 1382 { 1383 bus_space_tag_t iot = sc->sc_iot; 1384 bus_space_handle_t ioh = sc->sc_ioh; 1385 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1386 struct mbuf *m; 1387 struct ether_header *eh; 1388 int len; 1389 1390 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1391 1392 again: 1393 if (ifp->if_flags & IFF_DEBUG) { 1394 int err = len & ERR_MASK; 1395 char *s = NULL; 1396 1397 if (len & ERR_INCOMPLETE) 1398 s = "incomplete packet"; 1399 else if (err == ERR_OVERRUN) 1400 s = "packet overrun"; 1401 else if (err == ERR_RUNT) 1402 s = "runt packet"; 1403 else if (err == ERR_ALIGNMENT) 1404 s = "bad alignment"; 1405 else if (err == ERR_CRC) 1406 s = "bad crc"; 1407 else if (err == ERR_OVERSIZE) 1408 s = "oversized packet"; 1409 else if (err == ERR_DRIBBLE) 1410 s = "dribble bits"; 1411 1412 if (s) 1413 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1414 } 1415 1416 if (len & ERR_INCOMPLETE) 1417 return; 1418 1419 if (len & ERR_RX) { 1420 ++ifp->if_ierrors; 1421 goto abort; 1422 } 1423 1424 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1425 1426 /* Pull packet off interface. */ 1427 m = epget(sc, len); 1428 if (m == 0) { 1429 ifp->if_ierrors++; 1430 goto abort; 1431 } 1432 1433 ++ifp->if_ipackets; 1434 1435 /* We assume the header fit entirely in one mbuf. */ 1436 eh = mtod(m, struct ether_header *); 1437 1438 #if NBPFILTER > 0 1439 /* 1440 * Check if there's a BPF listener on this interface. 1441 * If so, hand off the raw packet to BPF. 1442 */ 1443 if (ifp->if_bpf) { 1444 bpf_mtap(ifp->if_bpf, m); 1445 1446 /* 1447 * Note that the interface cannot be in promiscuous mode if 1448 * there are no BPF listeners. And if we are in promiscuous 1449 * mode, we have to check if this packet is really ours. 1450 */ 1451 if ((ifp->if_flags & IFF_PROMISC) && 1452 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1453 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1454 sizeof(eh->ether_dhost)) != 0) { 1455 m_freem(m); 1456 return; 1457 } 1458 } 1459 #endif 1460 1461 /* We assume the header fit entirely in one mbuf. */ 1462 m_adj(m, sizeof(struct ether_header)); 1463 ether_input(ifp, eh, m); 1464 1465 /* 1466 * In periods of high traffic we can actually receive enough 1467 * packets so that the fifo overrun bit will be set at this point, 1468 * even though we just read a packet. In this case we 1469 * are not going to receive any more interrupts. We check for 1470 * this condition and read again until the fifo is not full. 1471 * We could simplify this test by not using epstatus(), but 1472 * rechecking the RX_STATUS register directly. This test could 1473 * result in unnecessary looping in cases where there is a new 1474 * packet but the fifo is not full, but it will not fix the 1475 * stuck behavior. 1476 * 1477 * Even with this improvement, we still get packet overrun errors 1478 * which are hurting performance. Maybe when I get some more time 1479 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1480 */ 1481 if (epstatus(sc)) { 1482 len = bus_space_read_2(iot, ioh, 1483 ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1484 /* Check if we are stuck and reset [see XXX comment] */ 1485 if (len & ERR_INCOMPLETE) { 1486 if (ifp->if_flags & IFF_DEBUG) 1487 printf("%s: adapter reset\n", 1488 sc->sc_dev.dv_xname); 1489 epreset(sc); 1490 return; 1491 } 1492 goto again; 1493 } 1494 1495 return; 1496 1497 abort: 1498 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 1499 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 1500 ; 1501 } 1502 1503 struct mbuf * 1504 epget(sc, totlen) 1505 struct ep_softc *sc; 1506 int totlen; 1507 { 1508 bus_space_tag_t iot = sc->sc_iot; 1509 bus_space_handle_t ioh = sc->sc_ioh; 1510 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1511 struct mbuf *top, **mp, *m, *rv = NULL; 1512 bus_addr_t rxreg; 1513 int len, remaining; 1514 int sh; 1515 1516 m = sc->mb[sc->next_mb]; 1517 sc->mb[sc->next_mb] = 0; 1518 if (m == 0) { 1519 MGETHDR(m, M_DONTWAIT, MT_DATA); 1520 if (m == 0) 1521 return 0; 1522 } else { 1523 /* If the queue is no longer full, refill. */ 1524 if (sc->last_mb == sc->next_mb) 1525 timeout(epmbuffill, sc, 1); 1526 /* Convert one of our saved mbuf's. */ 1527 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1528 m->m_data = m->m_pktdat; 1529 m->m_flags = M_PKTHDR; 1530 } 1531 m->m_pkthdr.rcvif = ifp; 1532 m->m_pkthdr.len = totlen; 1533 len = MHLEN; 1534 top = 0; 1535 mp = ⊤ 1536 1537 /* 1538 * We read the packet at splhigh() so that an interrupt from another 1539 * device doesn't cause the card's buffer to overflow while we're 1540 * reading it. We may still lose packets at other times. 1541 */ 1542 sh = splhigh(); 1543 1544 rxreg = ep_w1_reg(sc, ELINK_W1_RX_PIO_RD_1); 1545 1546 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1547 /* 1548 * Prime the FIFO buffer counter (number of 16-bit 1549 * words about to be read from the FIFO). 1550 * 1551 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1552 * COUNTER IS NON-ZERO! 1553 */ 1554 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, totlen >> 1); 1555 } 1556 1557 while (totlen > 0) { 1558 if (top) { 1559 m = sc->mb[sc->next_mb]; 1560 sc->mb[sc->next_mb] = 0; 1561 if (m == 0) { 1562 MGET(m, M_DONTWAIT, MT_DATA); 1563 if (m == 0) { 1564 m_freem(top); 1565 goto out; 1566 } 1567 } else { 1568 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1569 } 1570 len = MLEN; 1571 } 1572 if (totlen >= MINCLSIZE) { 1573 MCLGET(m, M_DONTWAIT); 1574 if ((m->m_flags & M_EXT) == 0) { 1575 m_free(m); 1576 m_freem(top); 1577 goto out; 1578 } 1579 len = MCLBYTES; 1580 } 1581 if (top == 0) { 1582 /* align the struct ip header */ 1583 caddr_t newdata = (caddr_t) 1584 ALIGN(m->m_data + sizeof(struct ether_header)) 1585 - sizeof(struct ether_header); 1586 len -= newdata - m->m_data; 1587 m->m_data = newdata; 1588 } 1589 remaining = len = min(totlen, len); 1590 if (ELINK_IS_BUS_32(sc->bustype)) { 1591 u_long offset = mtod(m, u_long); 1592 /* 1593 * Read bytes up to the point where we are aligned. 1594 * (We can align to 4 bytes, rather than ALIGNBYTES, 1595 * here because we're later reading 4-byte chunks.) 1596 */ 1597 if ((remaining > 3) && (offset & 3)) { 1598 int count = (4 - (offset & 3)); 1599 bus_space_read_multi_1(iot, ioh, 1600 rxreg, (u_int8_t *) offset, count); 1601 offset += count; 1602 remaining -= count; 1603 } 1604 if (remaining > 3) { 1605 bus_space_read_multi_4(iot, ioh, 1606 rxreg, (u_int32_t *) offset, 1607 remaining >> 2); 1608 offset += remaining & ~3; 1609 remaining &= 3; 1610 } 1611 if (remaining) { 1612 bus_space_read_multi_1(iot, ioh, 1613 rxreg, (u_int8_t *) offset, remaining); 1614 } 1615 } else { 1616 u_long offset = mtod(m, u_long); 1617 if ((remaining > 1) && (offset & 1)) { 1618 bus_space_read_multi_1(iot, ioh, 1619 rxreg, (u_int8_t *) offset, 1); 1620 remaining -= 1; 1621 offset += 1; 1622 } 1623 if (remaining > 1) { 1624 bus_space_read_multi_2(iot, ioh, 1625 rxreg, (u_int16_t *) offset, 1626 remaining >> 1); 1627 offset += remaining & ~1; 1628 } 1629 if (remaining & 1) { 1630 bus_space_read_multi_1(iot, ioh, 1631 rxreg, (u_int8_t *) offset, remaining & 1); 1632 } 1633 } 1634 m->m_len = len; 1635 totlen -= len; 1636 *mp = m; 1637 mp = &m->m_next; 1638 } 1639 1640 rv = top; 1641 1642 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 1643 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 1644 ; 1645 1646 out: 1647 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 1648 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1649 splx(sh); 1650 1651 return rv; 1652 } 1653 1654 int 1655 epioctl(ifp, cmd, data) 1656 register struct ifnet *ifp; 1657 u_long cmd; 1658 caddr_t data; 1659 { 1660 struct ep_softc *sc = ifp->if_softc; 1661 struct ifaddr *ifa = (struct ifaddr *)data; 1662 struct ifreq *ifr = (struct ifreq *)data; 1663 int s, error = 0; 1664 1665 s = splnet(); 1666 1667 switch (cmd) { 1668 1669 case SIOCSIFADDR: 1670 if ((error = epenable(sc)) != 0) 1671 break; 1672 /* epinit is called just below */ 1673 ifp->if_flags |= IFF_UP; 1674 switch (ifa->ifa_addr->sa_family) { 1675 #ifdef INET 1676 case AF_INET: 1677 epinit(sc); 1678 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1679 break; 1680 #endif 1681 #ifdef NS 1682 case AF_NS: 1683 { 1684 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1685 1686 if (ns_nullhost(*ina)) 1687 ina->x_host = *(union ns_host *) 1688 LLADDR(ifp->if_sadl); 1689 else 1690 bcopy(ina->x_host.c_host, 1691 LLADDR(ifp->if_sadl), 1692 ifp->if_addrlen); 1693 /* Set new address. */ 1694 epinit(sc); 1695 break; 1696 } 1697 #endif 1698 default: 1699 epinit(sc); 1700 break; 1701 } 1702 break; 1703 1704 case SIOCSIFMEDIA: 1705 case SIOCGIFMEDIA: 1706 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1707 break; 1708 1709 case SIOCSIFFLAGS: 1710 if ((ifp->if_flags & IFF_UP) == 0 && 1711 (ifp->if_flags & IFF_RUNNING) != 0) { 1712 /* 1713 * If interface is marked down and it is running, then 1714 * stop it. 1715 */ 1716 epstop(sc); 1717 ifp->if_flags &= ~IFF_RUNNING; 1718 epdisable(sc); 1719 } else if ((ifp->if_flags & IFF_UP) != 0 && 1720 (ifp->if_flags & IFF_RUNNING) == 0) { 1721 /* 1722 * If interface is marked up and it is stopped, then 1723 * start it. 1724 */ 1725 if ((error = epenable(sc)) != 0) 1726 break; 1727 epinit(sc); 1728 } else if ((ifp->if_flags & IFF_UP) != 0) { 1729 /* 1730 * deal with flags changes: 1731 * IFF_MULTICAST, IFF_PROMISC. 1732 */ 1733 epsetfilter(sc); 1734 } 1735 break; 1736 1737 case SIOCADDMULTI: 1738 case SIOCDELMULTI: 1739 if (sc->enabled == 0) { 1740 error = EIO; 1741 break; 1742 } 1743 1744 error = (cmd == SIOCADDMULTI) ? 1745 ether_addmulti(ifr, &sc->sc_ethercom) : 1746 ether_delmulti(ifr, &sc->sc_ethercom); 1747 1748 if (error == ENETRESET) { 1749 /* 1750 * Multicast list has changed; set the hardware filter 1751 * accordingly. 1752 */ 1753 epreset(sc); 1754 error = 0; 1755 } 1756 break; 1757 1758 default: 1759 error = EINVAL; 1760 break; 1761 } 1762 1763 splx(s); 1764 return (error); 1765 } 1766 1767 void 1768 epreset(sc) 1769 struct ep_softc *sc; 1770 { 1771 int s; 1772 1773 s = splnet(); 1774 epstop(sc); 1775 epinit(sc); 1776 splx(s); 1777 } 1778 1779 void 1780 epwatchdog(ifp) 1781 struct ifnet *ifp; 1782 { 1783 struct ep_softc *sc = ifp->if_softc; 1784 1785 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1786 ++sc->sc_ethercom.ec_if.if_oerrors; 1787 1788 epreset(sc); 1789 } 1790 1791 void 1792 epstop(sc) 1793 register struct ep_softc *sc; 1794 { 1795 bus_space_tag_t iot = sc->sc_iot; 1796 bus_space_handle_t ioh = sc->sc_ioh; 1797 1798 if (sc->ep_flags & ELINK_FLAGS_MII) { 1799 /* Stop the one second clock. */ 1800 untimeout(ep_tick, sc); 1801 } 1802 1803 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 1804 /* 1805 * Clear the FIFO buffer count, thus halting 1806 * any currently-running transactions. 1807 */ 1808 GO_WINDOW(1); /* sanity */ 1809 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 1810 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1811 } 1812 1813 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1814 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 1815 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 1816 ; 1817 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1818 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1819 1820 ep_complete_cmd(sc, ELINK_COMMAND, RX_RESET); 1821 ep_complete_cmd(sc, ELINK_COMMAND, TX_RESET); 1822 1823 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1824 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK); 1825 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK); 1826 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RX_FILTER); 1827 1828 epmbufempty(sc); 1829 } 1830 1831 1832 /* 1833 * Before reboots, reset card completely. 1834 */ 1835 static void 1836 epshutdown(arg) 1837 void *arg; 1838 { 1839 register struct ep_softc *sc = arg; 1840 1841 if (sc->enabled) { 1842 epstop(sc); 1843 ep_complete_cmd(sc, ELINK_COMMAND, GLOBAL_RESET); 1844 } 1845 } 1846 1847 /* 1848 * We get eeprom data from the id_port given an offset into the 1849 * eeprom. Basically; after the ID_sequence is sent to all of 1850 * the cards; they enter the ID_CMD state where they will accept 1851 * command requests. 0x80-0xbf loads the eeprom data. We then 1852 * read the port 16 times and with every read; the cards check 1853 * for contention (ie: if one card writes a 0 bit and another 1854 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1855 * each card compares the data on the bus; if there is a difference 1856 * then that card goes into ID_WAIT state again). In the meantime; 1857 * one bit of data is returned in the AX register which is conveniently 1858 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1859 * bit of data with each read. 1860 * 1861 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1862 */ 1863 u_int16_t 1864 epreadeeprom(iot, ioh, offset) 1865 bus_space_tag_t iot; 1866 bus_space_handle_t ioh; 1867 int offset; 1868 { 1869 u_int16_t data = 0; 1870 int i; 1871 1872 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1873 delay(1000); 1874 for (i = 0; i < 16; i++) 1875 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1876 return (data); 1877 } 1878 1879 static int 1880 epbusyeeprom(sc) 1881 struct ep_softc *sc; 1882 { 1883 bus_space_tag_t iot = sc->sc_iot; 1884 bus_space_handle_t ioh = sc->sc_ioh; 1885 int i = 100, j; 1886 1887 if (sc->bustype == ELINK_BUS_PCMCIA) { 1888 delay(1000); 1889 return 0; 1890 } 1891 1892 j = 0; /* bad GCC flow analysis */ 1893 while (i--) { 1894 j = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND); 1895 if (j & EEPROM_BUSY) 1896 delay(100); 1897 else 1898 break; 1899 } 1900 if (!i) { 1901 printf("\n%s: eeprom failed to come ready\n", 1902 sc->sc_dev.dv_xname); 1903 return (1); 1904 } 1905 if (j & EEPROM_TST_MODE) { 1906 /* XXX PnP mode? */ 1907 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1908 return (1); 1909 } 1910 return (0); 1911 } 1912 1913 void 1914 epmbuffill(v) 1915 void *v; 1916 { 1917 struct ep_softc *sc = v; 1918 struct mbuf *m; 1919 int s, i; 1920 1921 s = splnet(); 1922 i = sc->last_mb; 1923 do { 1924 if (sc->mb[i] == 0) { 1925 MGET(m, M_DONTWAIT, MT_DATA); 1926 if (m == 0) 1927 break; 1928 sc->mb[i] = m; 1929 } 1930 i = (i + 1) % MAX_MBS; 1931 } while (i != sc->next_mb); 1932 sc->last_mb = i; 1933 /* If the queue was not filled, try again. */ 1934 if (sc->last_mb != sc->next_mb) 1935 timeout(epmbuffill, sc, 1); 1936 splx(s); 1937 } 1938 1939 void 1940 epmbufempty(sc) 1941 struct ep_softc *sc; 1942 { 1943 int s, i; 1944 1945 s = splnet(); 1946 for (i = 0; i<MAX_MBS; i++) { 1947 if (sc->mb[i]) { 1948 m_freem(sc->mb[i]); 1949 sc->mb[i] = NULL; 1950 } 1951 } 1952 sc->last_mb = sc->next_mb = 0; 1953 untimeout(epmbuffill, sc); 1954 splx(s); 1955 } 1956 1957 int 1958 epenable(sc) 1959 struct ep_softc *sc; 1960 { 1961 1962 if (sc->enabled == 0 && sc->enable != NULL) { 1963 if ((*sc->enable)(sc) != 0) { 1964 printf("%s: device enable failed\n", 1965 sc->sc_dev.dv_xname); 1966 return (EIO); 1967 } 1968 } 1969 1970 sc->enabled = 1; 1971 return (0); 1972 } 1973 1974 void 1975 epdisable(sc) 1976 struct ep_softc *sc; 1977 { 1978 1979 if (sc->enabled != 0 && sc->disable != NULL) { 1980 (*sc->disable)(sc); 1981 sc->enabled = 0; 1982 } 1983 } 1984 1985 int 1986 ep_activate(self, act) 1987 struct device *self; 1988 enum devact act; 1989 { 1990 struct ep_softc *sc = (struct ep_softc *)self; 1991 int rv = 0, s; 1992 1993 s = splnet(); 1994 switch (act) { 1995 case DVACT_ACTIVATE: 1996 rv = EOPNOTSUPP; 1997 break; 1998 1999 case DVACT_DEACTIVATE: 2000 #ifdef notyet 2001 /* First, kill off the interface. */ 2002 if_detach(sc->sc_ethercom.ec_if); 2003 #endif 2004 2005 /* Now disable the interface. */ 2006 epdisable(sc); 2007 break; 2008 } 2009 splx(s); 2010 return (rv); 2011 } 2012 2013 void 2014 ep_mii_setbit(sc, bit) 2015 struct ep_softc *sc; 2016 u_int16_t bit; 2017 { 2018 u_int16_t val; 2019 2020 /* We assume we're already in Window 4 */ 2021 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2022 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2023 val | bit); 2024 } 2025 2026 void 2027 ep_mii_clrbit(sc, bit) 2028 struct ep_softc *sc; 2029 u_int16_t bit; 2030 { 2031 u_int16_t val; 2032 2033 /* We assume we're already in Window 4 */ 2034 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2035 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2036 val & ~bit); 2037 } 2038 2039 u_int16_t 2040 ep_mii_readbit(sc, bit) 2041 struct ep_softc *sc; 2042 u_int16_t bit; 2043 { 2044 2045 /* We assume we're already in Window 4 */ 2046 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT) & 2047 bit); 2048 } 2049 2050 void 2051 ep_mii_sync(sc) 2052 struct ep_softc *sc; 2053 { 2054 int i; 2055 2056 /* We assume we're already in Window 4 */ 2057 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2058 for (i = 0; i < 32; i++) { 2059 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2060 ep_mii_setbit(sc, PHYSMGMT_CLK); 2061 } 2062 } 2063 2064 void 2065 ep_mii_sendbits(sc, data, nbits) 2066 struct ep_softc *sc; 2067 u_int32_t data; 2068 int nbits; 2069 { 2070 int i; 2071 2072 /* We assume we're already in Window 4 */ 2073 ep_mii_setbit(sc, PHYSMGMT_DIR); 2074 for (i = 1 << (nbits - 1); i; i = i >> 1) { 2075 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2076 ep_mii_readbit(sc, PHYSMGMT_CLK); 2077 if (data & i) 2078 ep_mii_setbit(sc, PHYSMGMT_DATA); 2079 else 2080 ep_mii_clrbit(sc, PHYSMGMT_DATA); 2081 ep_mii_setbit(sc, PHYSMGMT_CLK); 2082 ep_mii_readbit(sc, PHYSMGMT_CLK); 2083 } 2084 } 2085 2086 int 2087 ep_mii_readreg(self, phy, reg) 2088 struct device *self; 2089 int phy, reg; 2090 { 2091 struct ep_softc *sc = (struct ep_softc *)self; 2092 int val = 0, i, err; 2093 2094 /* 2095 * Read the PHY register by manually driving the MII control lines. 2096 */ 2097 2098 GO_WINDOW(4); 2099 2100 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 0); 2101 2102 ep_mii_sync(sc); 2103 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2104 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 2105 ep_mii_sendbits(sc, phy, 5); 2106 ep_mii_sendbits(sc, reg, 5); 2107 2108 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2109 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2110 ep_mii_setbit(sc, PHYSMGMT_CLK); 2111 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2112 2113 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 2114 ep_mii_setbit(sc, PHYSMGMT_CLK); 2115 2116 /* Even if an error occurs, must still clock out the cycle. */ 2117 for (i = 0; i < 16; i++) { 2118 val <<= 1; 2119 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2120 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 2121 val |= 1; 2122 ep_mii_setbit(sc, PHYSMGMT_CLK); 2123 } 2124 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2125 ep_mii_setbit(sc, PHYSMGMT_CLK); 2126 2127 GO_WINDOW(1); /* back to operating window */ 2128 2129 return (err ? 0 : val); 2130 } 2131 2132 void 2133 ep_mii_writereg(self, phy, reg, val) 2134 struct device *self; 2135 int phy, reg, val; 2136 { 2137 struct ep_softc *sc = (struct ep_softc *)self; 2138 2139 /* 2140 * Write the PHY register by manually driving the MII control lines. 2141 */ 2142 2143 GO_WINDOW(4); 2144 2145 ep_mii_sync(sc); 2146 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2147 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2148 ep_mii_sendbits(sc, phy, 5); 2149 ep_mii_sendbits(sc, reg, 5); 2150 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2151 ep_mii_sendbits(sc, val, 16); 2152 2153 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2154 ep_mii_setbit(sc, PHYSMGMT_CLK); 2155 2156 GO_WINDOW(1); /* back to operating window */ 2157 } 2158 2159 void 2160 ep_statchg(self) 2161 struct device *self; 2162 { 2163 struct ep_softc *sc = (struct ep_softc *)self; 2164 bus_space_tag_t iot = sc->sc_iot; 2165 bus_space_handle_t ioh = sc->sc_ioh; 2166 int mctl; 2167 2168 /* XXX Update ifp->if_baudrate */ 2169 2170 GO_WINDOW(3); 2171 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 2172 if (sc->sc_mii.mii_media_active & IFM_FDX) 2173 mctl |= MAC_CONTROL_FDX; 2174 else 2175 mctl &= ~MAC_CONTROL_FDX; 2176 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 2177 GO_WINDOW(1); /* back to operating window */ 2178 } 2179
Indexes created Fri Sep 26 08:10:20 GMT 2025