elink3.c revision 1.53
1 /* $NetBSD: elink3.c,v 1.53 1999/02/28 17:10:53 explorer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #define ETHER_MIN_LEN 64 124 #define ETHER_MAX_LEN 1518 125 #define ETHER_ADDR_LEN 6 126 127 #ifdef DEBUG 128 int epdebug = 0; 129 #endif 130 131 /* 132 * Structure to map media-present bits in boards to ifmedia codes and 133 * printable media names. Used for table-driven ifmedia initialization. 134 */ 135 struct ep_media { 136 int epm_mpbit; /* media present bit */ 137 const char *epm_name; /* name of medium */ 138 int epm_ifmedia; /* ifmedia word for medium */ 139 int epm_epmedia; /* ELINKMEDIA_* constant */ 140 }; 141 142 /* 143 * Media table for the Demon/Vortex/Boomerang chipsets. 144 * 145 * Note that MII on the Demon and Vortex (3c59x) indicates an external 146 * MII connector (for connecting an external PHY) ... I think. Treat 147 * it as `manual' on these chips. 148 * 149 * Any Boomerang (3c90x) chips with MII really do have an internal 150 * MII and real PHYs attached; no `native' media. 151 */ 152 struct ep_media ep_vortex_media[] = { 153 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 154 ELINKMEDIA_10BASE_T }, 155 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 156 ELINKMEDIA_10BASE_T }, 157 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 158 ELINKMEDIA_AUI }, 159 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 160 ELINKMEDIA_10BASE_2 }, 161 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 162 ELINKMEDIA_100BASE_TX }, 163 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 164 ELINKMEDIA_100BASE_TX }, 165 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 166 ELINKMEDIA_100BASE_FX }, 167 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 168 ELINKMEDIA_MII }, 169 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 170 ELINKMEDIA_100BASE_T4 }, 171 { 0, NULL, 0, 172 0 }, 173 }; 174 175 /* 176 * Media table for the older 3Com Etherlink III chipset, used 177 * in the 3c509, 3c579, and 3c589. 178 */ 179 struct ep_media ep_509_media[] = { 180 { ELINK_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 181 ELINKMEDIA_10BASE_T }, 182 { ELINK_W0_CC_AUI, "10base5", IFM_ETHER|IFM_10_5, 183 ELINKMEDIA_AUI }, 184 { ELINK_W0_CC_BNC, "10base2", IFM_ETHER|IFM_10_2, 185 ELINKMEDIA_10BASE_2 }, 186 { 0, NULL, 0, 187 0 }, 188 }; 189 190 void ep_internalconfig __P((struct ep_softc *sc)); 191 void ep_vortex_probemedia __P((struct ep_softc *sc)); 192 void ep_509_probemedia __P((struct ep_softc *sc)); 193 194 static void eptxstat __P((struct ep_softc *)); 195 static int epstatus __P((struct ep_softc *)); 196 void epinit __P((struct ep_softc *)); 197 int epioctl __P((struct ifnet *, u_long, caddr_t)); 198 void epstart __P((struct ifnet *)); 199 void epwatchdog __P((struct ifnet *)); 200 void epreset __P((struct ep_softc *)); 201 static void epshutdown __P((void *)); 202 void epread __P((struct ep_softc *)); 203 struct mbuf *epget __P((struct ep_softc *, int)); 204 void epmbuffill __P((void *)); 205 void epmbufempty __P((struct ep_softc *)); 206 void epsetfilter __P((struct ep_softc *)); 207 void epsetmedia __P((struct ep_softc *)); 208 209 /* ifmedia callbacks */ 210 int ep_media_change __P((struct ifnet *ifp)); 211 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 212 213 /* MII callbacks */ 214 int ep_mii_readreg __P((struct device *, int, int)); 215 void ep_mii_writereg __P((struct device *, int, int, int)); 216 void ep_statchg __P((struct device *)); 217 218 void ep_tick __P((void *)); 219 220 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 221 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 222 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 223 void ep_mii_sync __P((struct ep_softc *)); 224 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 225 226 static int epbusyeeprom __P((struct ep_softc *)); 227 static inline void ep_complete_cmd __P((struct ep_softc *sc, 228 u_int cmd, u_int arg)); 229 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 230 231 /* 232 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 233 * Window 1 registers offset! 234 */ 235 static __inline int 236 ep_w1_reg(sc, reg) 237 struct ep_softc *sc; 238 int reg; 239 { 240 241 switch (sc->ep_chipset) { 242 case ELINK_CHIPSET_CORKSCREW: 243 return (reg + 0x10); 244 245 case ELINK_CHIPSET_ROADRUNNER: 246 switch (reg) { 247 case ELINK_W1_FREE_TX: 248 case ELINK_W1_RUNNER_RDCTL: 249 case ELINK_W1_RUNNER_WRCTL: 250 return (reg); 251 } 252 return (reg + 0x10); 253 } 254 255 return (reg); 256 } 257 258 /* 259 * Issue a (reset) command, and be sure it has completed. 260 * Used for commands that reset part or all of the board. 261 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 262 * but older hardware doesn't implement it and we must delay. 263 * It's easiest to just delay always. 264 */ 265 static inline void 266 ep_complete_cmd(sc, cmd, arg) 267 struct ep_softc *sc; 268 u_int cmd, arg; 269 { 270 register bus_space_tag_t iot = sc->sc_iot; 271 register bus_space_handle_t ioh = sc->sc_ioh; 272 273 bus_space_write_2(iot, ioh, cmd, arg); 274 275 #ifdef notyet 276 /* if this adapter family has S_COMMAND_IN_PROGRESS, use it */ 277 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 278 ; 279 else 280 #else 281 DELAY(100000); /* need at least 1 ms, but be generous. */ 282 #endif 283 } 284 285 /* 286 * Back-end attach and configure. 287 */ 288 void 289 epconfig(sc, chipset, enaddr) 290 struct ep_softc *sc; 291 u_short chipset; 292 u_int8_t *enaddr; 293 { 294 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 295 bus_space_tag_t iot = sc->sc_iot; 296 bus_space_handle_t ioh = sc->sc_ioh; 297 u_int16_t i; 298 u_int8_t myla[6]; 299 300 sc->ep_chipset = chipset; 301 302 /* 303 * We could have been groveling around in other register 304 * windows in the front-end; make sure we're in window 0 305 * to read the EEPROM. 306 */ 307 GO_WINDOW(0); 308 309 if (enaddr == NULL) { 310 /* 311 * Read the station address from the eeprom 312 */ 313 for (i = 0; i < 3; i++) { 314 u_int16_t x; 315 if (epbusyeeprom(sc)) 316 return; /* XXX why is eeprom busy? */ 317 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 318 READ_EEPROM | i); 319 if (epbusyeeprom(sc)) 320 return; /* XXX why is eeprom busy? */ 321 x = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 322 myla[(i << 1)] = x >> 8; 323 myla[(i << 1) + 1] = x; 324 } 325 enaddr = myla; 326 } 327 328 /* 329 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 330 * allow FDDI-sized (4500) byte packets. Commands only take an 331 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 332 * packet length. 333 * Commands to these cards implicitly upshift a packet size 334 * or threshold by 2 bits. 335 * To detect cards with large-packet support, we probe by setting 336 * the transmit threshold register, then change windows and 337 * read back the threshold register directly, and see if the 338 * threshold value was shifted or not. 339 */ 340 bus_space_write_2(iot, ioh, ELINK_COMMAND, 341 SET_TX_AVAIL_THRESH | ELINK_LARGEWIN_PROBE ); 342 GO_WINDOW(5); 343 i = bus_space_read_2(iot, ioh, ELINK_W5_TX_AVAIL_THRESH); 344 GO_WINDOW(1); 345 switch (i) { 346 case ELINK_LARGEWIN_PROBE: 347 case (ELINK_LARGEWIN_PROBE & ELINK_LARGEWIN_MASK): 348 sc->ep_pktlenshift = 0; 349 break; 350 351 case (ELINK_LARGEWIN_PROBE << 2): 352 sc->ep_pktlenshift = 2; 353 break; 354 355 default: 356 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 357 "Interface disabled\n", 358 sc->sc_dev.dv_xname, ELINK_LARGEWIN_PROBE, (int) i); 359 return; 360 } 361 362 /* 363 * Ensure Tx-available interrupts are enabled for 364 * start the interface. 365 * XXX should be in epinit()? 366 */ 367 bus_space_write_2(iot, ioh, ELINK_COMMAND, 368 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 369 370 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 371 ifp->if_softc = sc; 372 ifp->if_start = epstart; 373 ifp->if_ioctl = epioctl; 374 ifp->if_watchdog = epwatchdog; 375 ifp->if_flags = 376 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 377 378 if_attach(ifp); 379 ether_ifattach(ifp, enaddr); 380 381 /* 382 * Finish configuration: 383 * determine chipset if the front-end couldn't do so, 384 * show board details, set media. 385 */ 386 387 /* 388 * Print RAM size. We also print the Ethernet address in here. 389 * It's extracted from the ifp, so we have to make sure it's 390 * been attached first. 391 */ 392 ep_internalconfig(sc); 393 GO_WINDOW(0); 394 395 /* 396 * Display some additional information, if pertinent. 397 */ 398 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 399 printf("%s: RoadRunner FIFO buffer enabled\n", 400 sc->sc_dev.dv_xname); 401 402 /* 403 * Initialize our media structures and MII info. We'll 404 * probe the MII if we discover that we have one. 405 */ 406 sc->sc_mii.mii_ifp = ifp; 407 sc->sc_mii.mii_readreg = ep_mii_readreg; 408 sc->sc_mii.mii_writereg = ep_mii_writereg; 409 sc->sc_mii.mii_statchg = ep_statchg; 410 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 411 ep_media_status); 412 413 /* 414 * Now, determine which media we have. 415 */ 416 switch (sc->ep_chipset) { 417 case ELINK_CHIPSET_BOOMERANG: 418 case ELINK_CHIPSET_ROADRUNNER: 419 /* 420 * If the device has MII, probe it. We won't be using 421 * any `native' media in this case, only PHYs. If 422 * we don't, just treat the Boomerang like the Vortex. 423 */ 424 if (sc->ep_flags & ELINK_FLAGS_MII) { 425 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 426 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 427 ifmedia_add(&sc->sc_mii.mii_media, 428 IFM_ETHER|IFM_NONE, 0, NULL); 429 ifmedia_set(&sc->sc_mii.mii_media, 430 IFM_ETHER|IFM_NONE); 431 } else { 432 ifmedia_set(&sc->sc_mii.mii_media, 433 IFM_ETHER|IFM_AUTO); 434 } 435 break; 436 } 437 /* FALLTHROUGH */ 438 439 case ELINK_CHIPSET_VORTEX: 440 ep_vortex_probemedia(sc); 441 break; 442 443 default: 444 ep_509_probemedia(sc); 445 break; 446 } 447 448 GO_WINDOW(1); /* Window 1 is operating window */ 449 450 #if NBPFILTER > 0 451 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 452 sizeof(struct ether_header)); 453 #endif 454 455 #if NRND > 0 456 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 457 RND_TYPE_NET, 0); 458 #endif 459 460 sc->tx_start_thresh = 20; /* probably a good starting point. */ 461 462 /* Establish callback to reset card when we reboot. */ 463 shutdownhook_establish(epshutdown, sc); 464 465 ep_complete_cmd(sc, ELINK_COMMAND, RX_RESET); 466 ep_complete_cmd(sc, ELINK_COMMAND, TX_RESET); 467 } 468 469 470 /* 471 * Show interface-model-independent info from window 3 472 * internal-configuration register. 473 */ 474 void 475 ep_internalconfig(sc) 476 struct ep_softc *sc; 477 { 478 bus_space_tag_t iot = sc->sc_iot; 479 bus_space_handle_t ioh = sc->sc_ioh; 480 481 u_int config0; 482 u_int config1; 483 484 int ram_size, ram_width, ram_speed, rom_size, ram_split; 485 /* 486 * NVRAM buffer Rx:Tx config names for busmastering cards 487 * (Demon, Vortex, and later). 488 */ 489 const char *onboard_ram_config[] = { 490 "5:3", "3:1", "1:1", "3:5" }; 491 492 GO_WINDOW(3); 493 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 494 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 495 GO_WINDOW(0); 496 497 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 498 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 499 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 500 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 501 502 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 503 504 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 505 sc->sc_dev.dv_xname, 506 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 507 8 << ram_size, 508 (ram_width) ? "word" : "byte", 509 onboard_ram_config[ram_split]); 510 } 511 512 513 /* 514 * Find supported media on 3c509-generation hardware that doesn't have 515 * a "reset_options" register in window 3. 516 * Use the config_cntrl register in window 0 instead. 517 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 518 * that implement CONFIG_CTRL. We don't have a good way to set the 519 * default active mediuim; punt to ifconfig instead. 520 */ 521 void 522 ep_509_probemedia(sc) 523 struct ep_softc *sc; 524 { 525 bus_space_tag_t iot = sc->sc_iot; 526 bus_space_handle_t ioh = sc->sc_ioh; 527 struct ifmedia *ifm = &sc->sc_mii.mii_media; 528 u_int16_t ep_w0_config, port; 529 struct ep_media *epm; 530 const char *sep = "", *defmedianame = NULL; 531 int defmedia = 0; 532 533 GO_WINDOW(0); 534 ep_w0_config = bus_space_read_2(iot, ioh, ELINK_W0_CONFIG_CTRL); 535 536 printf("%s: ", sc->sc_dev.dv_xname); 537 538 /* Sanity check that there are any media! */ 539 if ((ep_w0_config & ELINK_W0_CC_MEDIAMASK) == 0) { 540 printf("no media present!\n"); 541 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 542 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 543 return; 544 } 545 546 /* 547 * Get the default media from the EEPROM. 548 */ 549 if (epbusyeeprom(sc)) 550 return; /* XXX why is eeprom busy? */ 551 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 552 READ_EEPROM | EEPROM_ADDR_CFG); 553 if (epbusyeeprom(sc)) 554 return; /* XXX why is eeprom busy? */ 555 port = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA) >> 14; 556 557 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 558 559 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 560 if (ep_w0_config & epm->epm_mpbit) { 561 /* 562 * This simple test works because 509 chipsets 563 * don't do full-duplex. 564 */ 565 if (epm->epm_epmedia == port || defmedia == 0) { 566 defmedia = epm->epm_ifmedia; 567 defmedianame = epm->epm_name; 568 } 569 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 570 NULL); 571 PRINT(epm->epm_name); 572 } 573 } 574 575 #undef PRINT 576 577 #ifdef DIAGNOSTIC 578 if (defmedia == 0) 579 panic("ep_509_probemedia: impossible"); 580 #endif 581 582 printf(" (default %s)\n", defmedianame); 583 ifmedia_set(ifm, defmedia); 584 } 585 586 /* 587 * Find media present on large-packet-capable elink3 devices. 588 * Show onboard configuration of large-packet-capable elink3 devices 589 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 590 * Use media and card-version info in window 3 instead. 591 */ 592 void 593 ep_vortex_probemedia(sc) 594 struct ep_softc *sc; 595 { 596 bus_space_tag_t iot = sc->sc_iot; 597 bus_space_handle_t ioh = sc->sc_ioh; 598 struct ifmedia *ifm = &sc->sc_mii.mii_media; 599 struct ep_media *epm; 600 u_int config1; 601 int reset_options; 602 int default_media; /* 3-bit encoding of default (EEPROM) media */ 603 int defmedia = 0; 604 const char *sep = "", *defmedianame = NULL; 605 606 GO_WINDOW(3); 607 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 608 reset_options = (int)bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 609 GO_WINDOW(0); 610 611 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 612 613 printf("%s: ", sc->sc_dev.dv_xname); 614 615 /* Sanity check that there are any media! */ 616 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 617 printf("no media present!\n"); 618 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 619 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 620 return; 621 } 622 623 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 624 625 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 626 if (reset_options & epm->epm_mpbit) { 627 /* 628 * Default media is a little more complicated 629 * on the Vortex. We support full-duplex which 630 * uses the same reset options bit. 631 * 632 * XXX Check EEPROM for default to FDX? 633 */ 634 if (epm->epm_epmedia == default_media) { 635 if ((epm->epm_ifmedia & IFM_FDX) == 0) { 636 defmedia = epm->epm_ifmedia; 637 defmedianame = epm->epm_name; 638 } 639 } else if (defmedia == 0) { 640 defmedia = epm->epm_ifmedia; 641 defmedianame = epm->epm_name; 642 } 643 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 644 NULL); 645 PRINT(epm->epm_name); 646 } 647 } 648 649 #undef PRINT 650 651 #ifdef DIAGNOSTIC 652 if (defmedia == 0) 653 panic("ep_vortex_probemedia: impossible"); 654 #endif 655 656 printf(" (default %s)\n", defmedianame); 657 ifmedia_set(ifm, defmedia); 658 } 659 660 /* 661 * One second timer, used to tick the MII. 662 */ 663 void 664 ep_tick(arg) 665 void *arg; 666 { 667 struct ep_softc *sc = arg; 668 int s; 669 670 #ifdef DIAGNOSTIC 671 if ((sc->ep_flags & ELINK_FLAGS_MII) == 0) 672 panic("ep_tick"); 673 #endif 674 675 s = splnet(); 676 mii_tick(&sc->sc_mii); 677 splx(s); 678 679 timeout(ep_tick, sc, hz); 680 } 681 682 /* 683 * Bring device up. 684 * 685 * The order in here seems important. Otherwise we may not receive 686 * interrupts. ?! 687 */ 688 void 689 epinit(sc) 690 register struct ep_softc *sc; 691 { 692 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 693 bus_space_tag_t iot = sc->sc_iot; 694 bus_space_handle_t ioh = sc->sc_ioh; 695 int i; 696 697 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 698 ; 699 700 if (sc->bustype != ELINK_BUS_PCI) { 701 GO_WINDOW(0); 702 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, 0); 703 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 704 } 705 706 if (sc->bustype == ELINK_BUS_PCMCIA) { 707 bus_space_write_2(iot, ioh, ELINK_W0_RESOURCE_CFG, 0x3f00); 708 } 709 710 GO_WINDOW(2); 711 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 712 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 713 LLADDR(ifp->if_sadl)[i]); 714 715 /* 716 * Reset the station-address receive filter. 717 * A bug workaround for busmastering (Vortex, Demon) cards. 718 */ 719 for (i = 0; i < 6; i++) 720 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 721 722 ep_complete_cmd(sc, ELINK_COMMAND, RX_RESET); 723 ep_complete_cmd(sc, ELINK_COMMAND, TX_RESET); 724 725 GO_WINDOW(1); /* Window 1 is operating window */ 726 for (i = 0; i < 31; i++) 727 bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS)); 728 729 /* Set threshhold for for Tx-space avaiable interrupt. */ 730 bus_space_write_2(iot, ioh, ELINK_COMMAND, 731 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 732 733 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 734 /* 735 * Enable options in the PCMCIA LAN COR register, via 736 * RoadRunner Window 1. 737 * 738 * XXX MAGIC CONSTANTS! 739 */ 740 u_int16_t cor; 741 742 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, (1 << 11)); 743 744 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 745 if (sc->ep_flags & ELINK_FLAGS_USESHAREDMEM) 746 cor |= 0x10; 747 if (sc->ep_flags & ELINK_FLAGS_FORCENOWAIT) 748 cor |= 0x20; 749 bus_space_write_2(iot, ioh, 0, cor); 750 751 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 752 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 753 } 754 755 /* Enable interrupts. */ 756 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 757 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 758 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | 759 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 760 761 /* 762 * Attempt to get rid of any stray interrupts that occured during 763 * configuration. On the i386 this isn't possible because one may 764 * already be queued. However, a single stray interrupt is 765 * unimportant. 766 */ 767 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 768 769 epsetfilter(sc); 770 epsetmedia(sc); 771 772 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 773 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 774 775 epmbuffill(sc); 776 777 /* Interface is now `running', with no output active. */ 778 ifp->if_flags |= IFF_RUNNING; 779 ifp->if_flags &= ~IFF_OACTIVE; 780 781 if (sc->ep_flags & ELINK_FLAGS_MII) { 782 /* Start the one second clock. */ 783 timeout(ep_tick, sc, hz); 784 } 785 786 /* Attempt to start output, if any. */ 787 epstart(ifp); 788 } 789 790 791 /* 792 * Set multicast receive filter. 793 * elink3 hardware has no selective multicast filter in hardware. 794 * Enable reception of all multicasts and filter in software. 795 */ 796 void 797 epsetfilter(sc) 798 register struct ep_softc *sc; 799 { 800 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 801 802 GO_WINDOW(1); /* Window 1 is operating window */ 803 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, SET_RX_FILTER | 804 FIL_INDIVIDUAL | FIL_BRDCST | 805 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 806 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 807 } 808 809 int 810 ep_media_change(ifp) 811 struct ifnet *ifp; 812 { 813 register struct ep_softc *sc = ifp->if_softc; 814 815 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 816 epreset(sc); 817 818 return (0); 819 } 820 821 /* 822 * Set the card to use the specified media. 823 */ 824 void 825 epsetmedia(sc) 826 struct ep_softc *sc; 827 { 828 bus_space_tag_t iot = sc->sc_iot; 829 bus_space_handle_t ioh = sc->sc_ioh; 830 831 /* Turn everything off. First turn off linkbeat and UTP. */ 832 GO_WINDOW(4); 833 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0x0); 834 835 /* Turn off coax */ 836 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 837 delay(1000); 838 839 /* 840 * If the device has MII, select it, and then tell the 841 * PHY which media to use. 842 */ 843 if (sc->ep_flags & ELINK_FLAGS_MII) { 844 int config0, config1; 845 846 GO_WINDOW(3); 847 848 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 849 int resopt; 850 851 resopt = bus_space_read_2(iot, ioh, 852 ELINK_W3_RESET_OPTIONS); 853 bus_space_write_2(iot, ioh, 854 ELINK_W3_RESET_OPTIONS, resopt|ELINK_RUNNER_ENABLE_MII); 855 } 856 857 config0 = (u_int)bus_space_read_2(iot, ioh, 858 ELINK_W3_INTERNAL_CONFIG); 859 config1 = (u_int)bus_space_read_2(iot, ioh, 860 ELINK_W3_INTERNAL_CONFIG + 2); 861 862 config1 = config1 & ~CONFIG_MEDIAMASK; 863 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 864 865 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 866 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 867 GO_WINDOW(1); /* back to operating window */ 868 869 mii_mediachg(&sc->sc_mii); 870 return; 871 } 872 873 /* 874 * Now turn on the selected media/transceiver. 875 */ 876 GO_WINDOW(4); 877 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 878 case IFM_10_T: 879 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 880 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 881 break; 882 883 case IFM_10_2: 884 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 885 DELAY(1000); /* 50ms not enmough? */ 886 break; 887 888 case IFM_100_TX: 889 case IFM_100_FX: 890 case IFM_100_T4: /* XXX check documentation */ 891 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 892 LINKBEAT_ENABLE); 893 DELAY(1000); /* not strictly necessary? */ 894 break; 895 896 case IFM_10_5: 897 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 898 SQE_ENABLE); 899 DELAY(1000); /* not strictly necessary? */ 900 break; 901 902 case IFM_MANUAL: 903 /* 904 * Nothing to do here; we are actually enabling the 905 * external PHY on the MII port. 906 */ 907 break; 908 909 case IFM_NONE: 910 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 911 return; 912 913 default: 914 panic("epsetmedia: impossible"); 915 } 916 917 /* 918 * Tell the chip which port to use. 919 */ 920 switch (sc->ep_chipset) { 921 case ELINK_CHIPSET_VORTEX: 922 case ELINK_CHIPSET_BOOMERANG: 923 { 924 int mctl, config0, config1; 925 926 GO_WINDOW(3); 927 config0 = (u_int)bus_space_read_2(iot, ioh, 928 ELINK_W3_INTERNAL_CONFIG); 929 config1 = (u_int)bus_space_read_2(iot, ioh, 930 ELINK_W3_INTERNAL_CONFIG + 2); 931 932 config1 = config1 & ~CONFIG_MEDIAMASK; 933 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 934 CONFIG_MEDIAMASK_SHIFT); 935 936 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 937 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, 938 config1); 939 940 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 941 if (sc->sc_mii.mii_media.ifm_cur->ifm_media & IFM_FDX) 942 mctl |= MAC_CONTROL_FDX; 943 else 944 mctl &= ~MAC_CONTROL_FDX; 945 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 946 break; 947 } 948 default: 949 { 950 int w0_addr_cfg; 951 952 GO_WINDOW(0); 953 w0_addr_cfg = bus_space_read_2(iot, ioh, ELINK_W0_ADDRESS_CFG); 954 w0_addr_cfg &= 0x3fff; 955 bus_space_write_2(iot, ioh, ELINK_W0_ADDRESS_CFG, w0_addr_cfg | 956 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 957 DELAY(1000); 958 break; 959 } 960 } 961 962 GO_WINDOW(1); /* Window 1 is operating window */ 963 } 964 965 /* 966 * Get currently-selected media from card. 967 * (if_media callback, may be called before interface is brought up). 968 */ 969 void 970 ep_media_status(ifp, req) 971 struct ifnet *ifp; 972 struct ifmediareq *req; 973 { 974 register struct ep_softc *sc = ifp->if_softc; 975 bus_space_tag_t iot = sc->sc_iot; 976 bus_space_handle_t ioh = sc->sc_ioh; 977 978 if (sc->enabled == 0) { 979 req->ifm_active = IFM_ETHER|IFM_NONE; 980 req->ifm_status = 0; 981 return; 982 } 983 984 /* 985 * If we have MII, go ask the PHY what's going on. 986 */ 987 if (sc->ep_flags & ELINK_FLAGS_MII) { 988 mii_pollstat(&sc->sc_mii); 989 req->ifm_active = sc->sc_mii.mii_media_active; 990 req->ifm_status = sc->sc_mii.mii_media_status; 991 return; 992 } 993 994 /* 995 * Ok, at this point we claim that our active media is 996 * the currently selected media. We'll update our status 997 * if our chipset allows us to detect link. 998 */ 999 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1000 req->ifm_status = 0; 1001 1002 switch (sc->ep_chipset) { 1003 case ELINK_CHIPSET_VORTEX: 1004 case ELINK_CHIPSET_BOOMERANG: 1005 GO_WINDOW(4); 1006 req->ifm_status = IFM_AVALID; 1007 if (bus_space_read_2(iot, ioh, ELINK_W4_MEDIA_TYPE) & 1008 LINKBEAT_DETECT) 1009 req->ifm_status |= IFM_ACTIVE; 1010 GO_WINDOW(1); /* back to operating window */ 1011 break; 1012 } 1013 } 1014 1015 1016 1017 /* 1018 * Start outputting on the interface. 1019 * Always called as splnet(). 1020 */ 1021 void 1022 epstart(ifp) 1023 struct ifnet *ifp; 1024 { 1025 register struct ep_softc *sc = ifp->if_softc; 1026 bus_space_tag_t iot = sc->sc_iot; 1027 bus_space_handle_t ioh = sc->sc_ioh; 1028 struct mbuf *m, *m0; 1029 int sh, len, pad; 1030 bus_addr_t txreg; 1031 1032 /* Don't transmit if interface is busy or not running */ 1033 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1034 return; 1035 1036 startagain: 1037 /* Sneak a peek at the next packet */ 1038 m0 = ifp->if_snd.ifq_head; 1039 if (m0 == 0) 1040 return; 1041 1042 /* We need to use m->m_pkthdr.len, so require the header */ 1043 if ((m0->m_flags & M_PKTHDR) == 0) 1044 panic("epstart: no header mbuf"); 1045 len = m0->m_pkthdr.len; 1046 1047 pad = (4 - len) & 3; 1048 1049 /* 1050 * The 3c509 automatically pads short packets to minimum ethernet 1051 * length, but we drop packets that are too large. Perhaps we should 1052 * truncate them instead? 1053 */ 1054 if (len + pad > ETHER_MAX_LEN) { 1055 /* packet is obviously too large: toss it */ 1056 ++ifp->if_oerrors; 1057 IF_DEQUEUE(&ifp->if_snd, m0); 1058 m_freem(m0); 1059 goto readcheck; 1060 } 1061 1062 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_FREE_TX)) < 1063 len + pad + 4) { 1064 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1065 SET_TX_AVAIL_THRESH | 1066 ((len + pad + 4) >> sc->ep_pktlenshift)); 1067 /* not enough room in FIFO */ 1068 ifp->if_flags |= IFF_OACTIVE; 1069 return; 1070 } else { 1071 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1072 SET_TX_AVAIL_THRESH | ELINK_THRESH_DISABLE ); 1073 } 1074 1075 IF_DEQUEUE(&ifp->if_snd, m0); 1076 if (m0 == 0) /* not really needed */ 1077 return; 1078 1079 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_TX_START_THRESH | 1080 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/) ); 1081 1082 #if NBPFILTER > 0 1083 if (ifp->if_bpf) 1084 bpf_mtap(ifp->if_bpf, m0); 1085 #endif 1086 1087 /* 1088 * Do the output at splhigh() so that an interrupt from another device 1089 * won't cause a FIFO underrun. 1090 */ 1091 sh = splhigh(); 1092 1093 txreg = ep_w1_reg(sc, ELINK_W1_TX_PIO_WR_1); 1094 1095 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1096 /* 1097 * Prime the FIFO buffer counter (number of 16-bit 1098 * words about to be written to the FIFO). 1099 * 1100 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1101 * COUNTER IS NON-ZERO! 1102 */ 1103 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 1104 (len + pad) >> 1); 1105 } 1106 1107 bus_space_write_2(iot, ioh, txreg, len); 1108 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1109 if (ELINK_IS_BUS_32(sc->bustype)) { 1110 for (m = m0; m; ) { 1111 if (m->m_len > 3) { 1112 /* align our reads from core */ 1113 if (mtod(m, u_long) & 3) { 1114 u_long count = 1115 4 - (mtod(m, u_long) & 3); 1116 bus_space_write_multi_1(iot, ioh, 1117 txreg, mtod(m, u_int8_t *), count); 1118 m->m_data = 1119 (void *)(mtod(m, u_long) + count); 1120 m->m_len -= count; 1121 } 1122 bus_space_write_multi_4(iot, ioh, 1123 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1124 m->m_data = (void *)(mtod(m, u_long) + 1125 (u_long)(m->m_len & ~3)); 1126 m->m_len -= m->m_len & ~3; 1127 } 1128 if (m->m_len) { 1129 bus_space_write_multi_1(iot, ioh, 1130 txreg, mtod(m, u_int8_t *), m->m_len); 1131 } 1132 MFREE(m, m0); 1133 m = m0; 1134 } 1135 } else { 1136 for (m = m0; m; ) { 1137 if (m->m_len > 1) { 1138 if (mtod(m, u_long) & 1) { 1139 bus_space_write_1(iot, ioh, 1140 txreg, *(mtod(m, u_int8_t *))); 1141 m->m_data = 1142 (void *)(mtod(m, u_long) + 1); 1143 m->m_len -= 1; 1144 } 1145 bus_space_write_multi_2(iot, ioh, 1146 txreg, mtod(m, u_int16_t *), 1147 m->m_len >> 1); 1148 } 1149 if (m->m_len & 1) { 1150 bus_space_write_1(iot, ioh, txreg, 1151 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1152 } 1153 MFREE(m, m0); 1154 m = m0; 1155 } 1156 } 1157 while (pad--) 1158 bus_space_write_1(iot, ioh, txreg, 0); 1159 1160 splx(sh); 1161 1162 ++ifp->if_opackets; 1163 1164 readcheck: 1165 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)) & 1166 ERR_INCOMPLETE) == 0) { 1167 /* We received a complete packet. */ 1168 u_int16_t status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1169 1170 if ((status & S_INTR_LATCH) == 0) { 1171 /* 1172 * No interrupt, read the packet and continue 1173 * Is this supposed to happen? Is my motherboard 1174 * completely busted? 1175 */ 1176 epread(sc); 1177 } else { 1178 /* Got an interrupt, return so that it gets serviced. */ 1179 return; 1180 } 1181 } else { 1182 /* Check if we are stuck and reset [see XXX comment] */ 1183 if (epstatus(sc)) { 1184 if (ifp->if_flags & IFF_DEBUG) 1185 printf("%s: adapter reset\n", 1186 sc->sc_dev.dv_xname); 1187 epreset(sc); 1188 } 1189 } 1190 1191 goto startagain; 1192 } 1193 1194 1195 /* 1196 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1197 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1198 * We detect this situation and we reset the adapter. 1199 * It happens at times when there is a lot of broadcast traffic 1200 * on the cable (once in a blue moon). 1201 */ 1202 static int 1203 epstatus(sc) 1204 register struct ep_softc *sc; 1205 { 1206 bus_space_tag_t iot = sc->sc_iot; 1207 bus_space_handle_t ioh = sc->sc_ioh; 1208 u_int16_t fifost; 1209 1210 /* 1211 * Check the FIFO status and act accordingly 1212 */ 1213 GO_WINDOW(4); 1214 fifost = bus_space_read_2(iot, ioh, ELINK_W4_FIFO_DIAG); 1215 GO_WINDOW(1); 1216 1217 if (fifost & FIFOS_RX_UNDERRUN) { 1218 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1219 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1220 epreset(sc); 1221 return 0; 1222 } 1223 1224 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1225 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1226 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1227 return 1; 1228 } 1229 1230 if (fifost & FIFOS_RX_OVERRUN) { 1231 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1232 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1233 return 1; 1234 } 1235 1236 if (fifost & FIFOS_TX_OVERRUN) { 1237 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1238 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1239 epreset(sc); 1240 return 0; 1241 } 1242 1243 return 0; 1244 } 1245 1246 1247 static void 1248 eptxstat(sc) 1249 register struct ep_softc *sc; 1250 { 1251 bus_space_tag_t iot = sc->sc_iot; 1252 bus_space_handle_t ioh = sc->sc_ioh; 1253 int i; 1254 1255 /* 1256 * We need to read+write TX_STATUS until we get a 0 status 1257 * in order to turn off the interrupt flag. 1258 */ 1259 while ((i = bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS))) 1260 & TXS_COMPLETE) { 1261 bus_space_write_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS), 1262 0x0); 1263 1264 if (i & TXS_JABBER) { 1265 ++sc->sc_ethercom.ec_if.if_oerrors; 1266 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1267 printf("%s: jabber (%x)\n", 1268 sc->sc_dev.dv_xname, i); 1269 epreset(sc); 1270 } else if (i & TXS_UNDERRUN) { 1271 ++sc->sc_ethercom.ec_if.if_oerrors; 1272 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1273 printf("%s: fifo underrun (%x) @%d\n", 1274 sc->sc_dev.dv_xname, i, 1275 sc->tx_start_thresh); 1276 if (sc->tx_succ_ok < 100) 1277 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1278 sc->tx_start_thresh + 20); 1279 sc->tx_succ_ok = 0; 1280 epreset(sc); 1281 } else if (i & TXS_MAX_COLLISION) { 1282 ++sc->sc_ethercom.ec_if.if_collisions; 1283 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 1284 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1285 } else 1286 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1287 } 1288 } 1289 1290 int 1291 epintr(arg) 1292 void *arg; 1293 { 1294 register struct ep_softc *sc = arg; 1295 bus_space_tag_t iot = sc->sc_iot; 1296 bus_space_handle_t ioh = sc->sc_ioh; 1297 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1298 u_int16_t status; 1299 int ret = 0; 1300 int addrandom = 0; 1301 1302 if (sc->enabled == 0) 1303 return (0); 1304 1305 for (;;) { 1306 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1307 1308 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1309 1310 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1311 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1312 if ((status & S_INTR_LATCH) == 0) { 1313 #if 0 1314 printf("%s: intr latch cleared\n", 1315 sc->sc_dev.dv_xname); 1316 #endif 1317 break; 1318 } 1319 } 1320 1321 ret = 1; 1322 1323 /* 1324 * Acknowledge any interrupts. It's important that we do this 1325 * first, since there would otherwise be a race condition. 1326 * Due to the i386 interrupt queueing, we may get spurious 1327 * interrupts occasionally. 1328 */ 1329 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1330 (status & (C_INTR_LATCH | 1331 C_CARD_FAILURE | 1332 C_TX_COMPLETE | 1333 C_TX_AVAIL | 1334 C_RX_COMPLETE | 1335 C_RX_EARLY | 1336 C_INT_RQD | 1337 C_UPD_STATS))); 1338 1339 #if 0 1340 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1341 1342 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1343 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1344 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1345 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1346 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1347 #endif 1348 1349 if (status & S_RX_COMPLETE) { 1350 epread(sc); 1351 addrandom = 1; 1352 } 1353 if (status & S_TX_AVAIL) { 1354 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1355 epstart(&sc->sc_ethercom.ec_if); 1356 addrandom = 1; 1357 } 1358 if (status & S_CARD_FAILURE) { 1359 printf("%s: adapter failure (%x)\n", 1360 sc->sc_dev.dv_xname, status); 1361 epreset(sc); 1362 return (1); 1363 } 1364 if (status & S_TX_COMPLETE) { 1365 eptxstat(sc); 1366 epstart(ifp); 1367 addrandom = 1; 1368 } 1369 1370 #if NRND > 0 1371 if (status) 1372 rnd_add_uint32(&sc->rnd_source, status); 1373 #endif 1374 } 1375 1376 /* no more interrupts */ 1377 return (ret); 1378 } 1379 1380 void 1381 epread(sc) 1382 register struct ep_softc *sc; 1383 { 1384 bus_space_tag_t iot = sc->sc_iot; 1385 bus_space_handle_t ioh = sc->sc_ioh; 1386 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1387 struct mbuf *m; 1388 struct ether_header *eh; 1389 int len; 1390 1391 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1392 1393 again: 1394 if (ifp->if_flags & IFF_DEBUG) { 1395 int err = len & ERR_MASK; 1396 char *s = NULL; 1397 1398 if (len & ERR_INCOMPLETE) 1399 s = "incomplete packet"; 1400 else if (err == ERR_OVERRUN) 1401 s = "packet overrun"; 1402 else if (err == ERR_RUNT) 1403 s = "runt packet"; 1404 else if (err == ERR_ALIGNMENT) 1405 s = "bad alignment"; 1406 else if (err == ERR_CRC) 1407 s = "bad crc"; 1408 else if (err == ERR_OVERSIZE) 1409 s = "oversized packet"; 1410 else if (err == ERR_DRIBBLE) 1411 s = "dribble bits"; 1412 1413 if (s) 1414 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1415 } 1416 1417 if (len & ERR_INCOMPLETE) 1418 return; 1419 1420 if (len & ERR_RX) { 1421 ++ifp->if_ierrors; 1422 goto abort; 1423 } 1424 1425 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1426 1427 /* Pull packet off interface. */ 1428 m = epget(sc, len); 1429 if (m == 0) { 1430 ifp->if_ierrors++; 1431 goto abort; 1432 } 1433 1434 ++ifp->if_ipackets; 1435 1436 /* We assume the header fit entirely in one mbuf. */ 1437 eh = mtod(m, struct ether_header *); 1438 1439 #if NBPFILTER > 0 1440 /* 1441 * Check if there's a BPF listener on this interface. 1442 * If so, hand off the raw packet to BPF. 1443 */ 1444 if (ifp->if_bpf) { 1445 bpf_mtap(ifp->if_bpf, m); 1446 1447 /* 1448 * Note that the interface cannot be in promiscuous mode if 1449 * there are no BPF listeners. And if we are in promiscuous 1450 * mode, we have to check if this packet is really ours. 1451 */ 1452 if ((ifp->if_flags & IFF_PROMISC) && 1453 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1454 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1455 sizeof(eh->ether_dhost)) != 0) { 1456 m_freem(m); 1457 return; 1458 } 1459 } 1460 #endif 1461 1462 /* We assume the header fit entirely in one mbuf. */ 1463 m_adj(m, sizeof(struct ether_header)); 1464 ether_input(ifp, eh, m); 1465 1466 /* 1467 * In periods of high traffic we can actually receive enough 1468 * packets so that the fifo overrun bit will be set at this point, 1469 * even though we just read a packet. In this case we 1470 * are not going to receive any more interrupts. We check for 1471 * this condition and read again until the fifo is not full. 1472 * We could simplify this test by not using epstatus(), but 1473 * rechecking the RX_STATUS register directly. This test could 1474 * result in unnecessary looping in cases where there is a new 1475 * packet but the fifo is not full, but it will not fix the 1476 * stuck behavior. 1477 * 1478 * Even with this improvement, we still get packet overrun errors 1479 * which are hurting performance. Maybe when I get some more time 1480 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1481 */ 1482 if (epstatus(sc)) { 1483 len = bus_space_read_2(iot, ioh, 1484 ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1485 /* Check if we are stuck and reset [see XXX comment] */ 1486 if (len & ERR_INCOMPLETE) { 1487 if (ifp->if_flags & IFF_DEBUG) 1488 printf("%s: adapter reset\n", 1489 sc->sc_dev.dv_xname); 1490 epreset(sc); 1491 return; 1492 } 1493 goto again; 1494 } 1495 1496 return; 1497 1498 abort: 1499 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 1500 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 1501 ; 1502 } 1503 1504 struct mbuf * 1505 epget(sc, totlen) 1506 struct ep_softc *sc; 1507 int totlen; 1508 { 1509 bus_space_tag_t iot = sc->sc_iot; 1510 bus_space_handle_t ioh = sc->sc_ioh; 1511 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1512 struct mbuf *top, **mp, *m, *rv = NULL; 1513 bus_addr_t rxreg; 1514 int len, remaining; 1515 int sh; 1516 1517 m = sc->mb[sc->next_mb]; 1518 sc->mb[sc->next_mb] = 0; 1519 if (m == 0) { 1520 MGETHDR(m, M_DONTWAIT, MT_DATA); 1521 if (m == 0) 1522 return 0; 1523 } else { 1524 /* If the queue is no longer full, refill. */ 1525 if (sc->last_mb == sc->next_mb) 1526 timeout(epmbuffill, sc, 1); 1527 /* Convert one of our saved mbuf's. */ 1528 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1529 m->m_data = m->m_pktdat; 1530 m->m_flags = M_PKTHDR; 1531 } 1532 m->m_pkthdr.rcvif = ifp; 1533 m->m_pkthdr.len = totlen; 1534 len = MHLEN; 1535 top = 0; 1536 mp = ⊤ 1537 1538 /* 1539 * We read the packet at splhigh() so that an interrupt from another 1540 * device doesn't cause the card's buffer to overflow while we're 1541 * reading it. We may still lose packets at other times. 1542 */ 1543 sh = splhigh(); 1544 1545 rxreg = ep_w1_reg(sc, ELINK_W1_RX_PIO_RD_1); 1546 1547 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1548 /* 1549 * Prime the FIFO buffer counter (number of 16-bit 1550 * words about to be read from the FIFO). 1551 * 1552 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1553 * COUNTER IS NON-ZERO! 1554 */ 1555 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, totlen >> 1); 1556 } 1557 1558 while (totlen > 0) { 1559 if (top) { 1560 m = sc->mb[sc->next_mb]; 1561 sc->mb[sc->next_mb] = 0; 1562 if (m == 0) { 1563 MGET(m, M_DONTWAIT, MT_DATA); 1564 if (m == 0) { 1565 m_freem(top); 1566 goto out; 1567 } 1568 } else { 1569 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1570 } 1571 len = MLEN; 1572 } 1573 if (totlen >= MINCLSIZE) { 1574 MCLGET(m, M_DONTWAIT); 1575 if ((m->m_flags & M_EXT) == 0) { 1576 m_free(m); 1577 m_freem(top); 1578 goto out; 1579 } 1580 len = MCLBYTES; 1581 } 1582 if (top == 0) { 1583 /* align the struct ip header */ 1584 caddr_t newdata = (caddr_t) 1585 ALIGN(m->m_data + sizeof(struct ether_header)) 1586 - sizeof(struct ether_header); 1587 len -= newdata - m->m_data; 1588 m->m_data = newdata; 1589 } 1590 remaining = len = min(totlen, len); 1591 if (ELINK_IS_BUS_32(sc->bustype)) { 1592 u_long offset = mtod(m, u_long); 1593 /* 1594 * Read bytes up to the point where we are aligned. 1595 * (We can align to 4 bytes, rather than ALIGNBYTES, 1596 * here because we're later reading 4-byte chunks.) 1597 */ 1598 if ((remaining > 3) && (offset & 3)) { 1599 int count = (4 - (offset & 3)); 1600 bus_space_read_multi_1(iot, ioh, 1601 rxreg, (u_int8_t *) offset, count); 1602 offset += count; 1603 remaining -= count; 1604 } 1605 if (remaining > 3) { 1606 bus_space_read_multi_4(iot, ioh, 1607 rxreg, (u_int32_t *) offset, 1608 remaining >> 2); 1609 offset += remaining & ~3; 1610 remaining &= 3; 1611 } 1612 if (remaining) { 1613 bus_space_read_multi_1(iot, ioh, 1614 rxreg, (u_int8_t *) offset, remaining); 1615 } 1616 } else { 1617 u_long offset = mtod(m, u_long); 1618 if ((remaining > 1) && (offset & 1)) { 1619 bus_space_read_multi_1(iot, ioh, 1620 rxreg, (u_int8_t *) offset, 1); 1621 remaining -= 1; 1622 offset += 1; 1623 } 1624 if (remaining > 1) { 1625 bus_space_read_multi_2(iot, ioh, 1626 rxreg, (u_int16_t *) offset, 1627 remaining >> 1); 1628 offset += remaining & ~1; 1629 } 1630 if (remaining & 1) { 1631 bus_space_read_multi_1(iot, ioh, 1632 rxreg, (u_int8_t *) offset, remaining & 1); 1633 } 1634 } 1635 m->m_len = len; 1636 totlen -= len; 1637 *mp = m; 1638 mp = &m->m_next; 1639 } 1640 1641 rv = top; 1642 1643 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 1644 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 1645 ; 1646 1647 out: 1648 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 1649 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1650 splx(sh); 1651 1652 return rv; 1653 } 1654 1655 int 1656 epioctl(ifp, cmd, data) 1657 register struct ifnet *ifp; 1658 u_long cmd; 1659 caddr_t data; 1660 { 1661 struct ep_softc *sc = ifp->if_softc; 1662 struct ifaddr *ifa = (struct ifaddr *)data; 1663 struct ifreq *ifr = (struct ifreq *)data; 1664 int s, error = 0; 1665 1666 s = splnet(); 1667 1668 switch (cmd) { 1669 1670 case SIOCSIFADDR: 1671 if ((error = epenable(sc)) != 0) 1672 break; 1673 /* epinit is called just below */ 1674 ifp->if_flags |= IFF_UP; 1675 switch (ifa->ifa_addr->sa_family) { 1676 #ifdef INET 1677 case AF_INET: 1678 epinit(sc); 1679 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1680 break; 1681 #endif 1682 #ifdef NS 1683 case AF_NS: 1684 { 1685 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1686 1687 if (ns_nullhost(*ina)) 1688 ina->x_host = *(union ns_host *) 1689 LLADDR(ifp->if_sadl); 1690 else 1691 bcopy(ina->x_host.c_host, 1692 LLADDR(ifp->if_sadl), 1693 ifp->if_addrlen); 1694 /* Set new address. */ 1695 epinit(sc); 1696 break; 1697 } 1698 #endif 1699 default: 1700 epinit(sc); 1701 break; 1702 } 1703 break; 1704 1705 case SIOCSIFMEDIA: 1706 case SIOCGIFMEDIA: 1707 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1708 break; 1709 1710 case SIOCSIFFLAGS: 1711 if ((ifp->if_flags & IFF_UP) == 0 && 1712 (ifp->if_flags & IFF_RUNNING) != 0) { 1713 /* 1714 * If interface is marked down and it is running, then 1715 * stop it. 1716 */ 1717 epstop(sc); 1718 ifp->if_flags &= ~IFF_RUNNING; 1719 epdisable(sc); 1720 } else if ((ifp->if_flags & IFF_UP) != 0 && 1721 (ifp->if_flags & IFF_RUNNING) == 0) { 1722 /* 1723 * If interface is marked up and it is stopped, then 1724 * start it. 1725 */ 1726 if ((error = epenable(sc)) != 0) 1727 break; 1728 epinit(sc); 1729 } else if ((ifp->if_flags & IFF_UP) != 0) { 1730 /* 1731 * deal with flags changes: 1732 * IFF_MULTICAST, IFF_PROMISC. 1733 */ 1734 epsetfilter(sc); 1735 } 1736 break; 1737 1738 case SIOCADDMULTI: 1739 case SIOCDELMULTI: 1740 if (sc->enabled == 0) { 1741 error = EIO; 1742 break; 1743 } 1744 1745 error = (cmd == SIOCADDMULTI) ? 1746 ether_addmulti(ifr, &sc->sc_ethercom) : 1747 ether_delmulti(ifr, &sc->sc_ethercom); 1748 1749 if (error == ENETRESET) { 1750 /* 1751 * Multicast list has changed; set the hardware filter 1752 * accordingly. 1753 */ 1754 epreset(sc); 1755 error = 0; 1756 } 1757 break; 1758 1759 default: 1760 error = EINVAL; 1761 break; 1762 } 1763 1764 splx(s); 1765 return (error); 1766 } 1767 1768 void 1769 epreset(sc) 1770 struct ep_softc *sc; 1771 { 1772 int s; 1773 1774 s = splnet(); 1775 epstop(sc); 1776 epinit(sc); 1777 splx(s); 1778 } 1779 1780 void 1781 epwatchdog(ifp) 1782 struct ifnet *ifp; 1783 { 1784 struct ep_softc *sc = ifp->if_softc; 1785 1786 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1787 ++sc->sc_ethercom.ec_if.if_oerrors; 1788 1789 epreset(sc); 1790 } 1791 1792 void 1793 epstop(sc) 1794 register struct ep_softc *sc; 1795 { 1796 bus_space_tag_t iot = sc->sc_iot; 1797 bus_space_handle_t ioh = sc->sc_ioh; 1798 1799 if (sc->ep_flags & ELINK_FLAGS_MII) { 1800 /* Stop the one second clock. */ 1801 untimeout(ep_tick, sc); 1802 } 1803 1804 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 1805 /* 1806 * Clear the FIFO buffer count, thus halting 1807 * any currently-running transactions. 1808 */ 1809 GO_WINDOW(1); /* sanity */ 1810 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 1811 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1812 } 1813 1814 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1815 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 1816 while (bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) 1817 ; 1818 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1819 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1820 1821 ep_complete_cmd(sc, ELINK_COMMAND, RX_RESET); 1822 ep_complete_cmd(sc, ELINK_COMMAND, TX_RESET); 1823 1824 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1825 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK); 1826 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK); 1827 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RX_FILTER); 1828 1829 epmbufempty(sc); 1830 } 1831 1832 1833 /* 1834 * Before reboots, reset card completely. 1835 */ 1836 static void 1837 epshutdown(arg) 1838 void *arg; 1839 { 1840 register struct ep_softc *sc = arg; 1841 1842 if (sc->enabled) { 1843 epstop(sc); 1844 ep_complete_cmd(sc, ELINK_COMMAND, GLOBAL_RESET); 1845 } 1846 } 1847 1848 /* 1849 * We get eeprom data from the id_port given an offset into the 1850 * eeprom. Basically; after the ID_sequence is sent to all of 1851 * the cards; they enter the ID_CMD state where they will accept 1852 * command requests. 0x80-0xbf loads the eeprom data. We then 1853 * read the port 16 times and with every read; the cards check 1854 * for contention (ie: if one card writes a 0 bit and another 1855 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1856 * each card compares the data on the bus; if there is a difference 1857 * then that card goes into ID_WAIT state again). In the meantime; 1858 * one bit of data is returned in the AX register which is conveniently 1859 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1860 * bit of data with each read. 1861 * 1862 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1863 */ 1864 u_int16_t 1865 epreadeeprom(iot, ioh, offset) 1866 bus_space_tag_t iot; 1867 bus_space_handle_t ioh; 1868 int offset; 1869 { 1870 u_int16_t data = 0; 1871 int i; 1872 1873 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1874 delay(1000); 1875 for (i = 0; i < 16; i++) 1876 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1877 return (data); 1878 } 1879 1880 static int 1881 epbusyeeprom(sc) 1882 struct ep_softc *sc; 1883 { 1884 bus_space_tag_t iot = sc->sc_iot; 1885 bus_space_handle_t ioh = sc->sc_ioh; 1886 int i = 100, j; 1887 1888 if (sc->bustype == ELINK_BUS_PCMCIA) { 1889 delay(1000); 1890 return 0; 1891 } 1892 1893 j = 0; /* bad GCC flow analysis */ 1894 while (i--) { 1895 j = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND); 1896 if (j & EEPROM_BUSY) 1897 delay(100); 1898 else 1899 break; 1900 } 1901 if (!i) { 1902 printf("\n%s: eeprom failed to come ready\n", 1903 sc->sc_dev.dv_xname); 1904 return (1); 1905 } 1906 if (j & EEPROM_TST_MODE) { 1907 /* XXX PnP mode? */ 1908 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1909 return (1); 1910 } 1911 return (0); 1912 } 1913 1914 void 1915 epmbuffill(v) 1916 void *v; 1917 { 1918 struct ep_softc *sc = v; 1919 struct mbuf *m; 1920 int s, i; 1921 1922 s = splnet(); 1923 i = sc->last_mb; 1924 do { 1925 if (sc->mb[i] == 0) { 1926 MGET(m, M_DONTWAIT, MT_DATA); 1927 if (m == 0) 1928 break; 1929 sc->mb[i] = m; 1930 } 1931 i = (i + 1) % MAX_MBS; 1932 } while (i != sc->next_mb); 1933 sc->last_mb = i; 1934 /* If the queue was not filled, try again. */ 1935 if (sc->last_mb != sc->next_mb) 1936 timeout(epmbuffill, sc, 1); 1937 splx(s); 1938 } 1939 1940 void 1941 epmbufempty(sc) 1942 struct ep_softc *sc; 1943 { 1944 int s, i; 1945 1946 s = splnet(); 1947 for (i = 0; i<MAX_MBS; i++) { 1948 if (sc->mb[i]) { 1949 m_freem(sc->mb[i]); 1950 sc->mb[i] = NULL; 1951 } 1952 } 1953 sc->last_mb = sc->next_mb = 0; 1954 untimeout(epmbuffill, sc); 1955 splx(s); 1956 } 1957 1958 int 1959 epenable(sc) 1960 struct ep_softc *sc; 1961 { 1962 1963 if (sc->enabled == 0 && sc->enable != NULL) { 1964 if ((*sc->enable)(sc) != 0) { 1965 printf("%s: device enable failed\n", 1966 sc->sc_dev.dv_xname); 1967 return (EIO); 1968 } 1969 } 1970 1971 sc->enabled = 1; 1972 return (0); 1973 } 1974 1975 void 1976 epdisable(sc) 1977 struct ep_softc *sc; 1978 { 1979 1980 if (sc->enabled != 0 && sc->disable != NULL) { 1981 (*sc->disable)(sc); 1982 sc->enabled = 0; 1983 } 1984 } 1985 1986 int 1987 ep_activate(self, act) 1988 struct device *self; 1989 enum devact act; 1990 { 1991 struct ep_softc *sc = (struct ep_softc *)self; 1992 int rv = 0, s; 1993 1994 s = splnet(); 1995 switch (act) { 1996 case DVACT_ACTIVATE: 1997 rv = EOPNOTSUPP; 1998 break; 1999 2000 case DVACT_DEACTIVATE: 2001 #ifdef notyet 2002 /* First, kill off the interface. */ 2003 if_detach(sc->sc_ethercom.ec_if); 2004 #endif 2005 2006 /* Now disable the interface. */ 2007 epdisable(sc); 2008 break; 2009 } 2010 splx(s); 2011 return (rv); 2012 } 2013 2014 void 2015 ep_mii_setbit(sc, bit) 2016 struct ep_softc *sc; 2017 u_int16_t bit; 2018 { 2019 u_int16_t val; 2020 2021 /* We assume we're already in Window 4 */ 2022 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2023 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2024 val | bit); 2025 } 2026 2027 void 2028 ep_mii_clrbit(sc, bit) 2029 struct ep_softc *sc; 2030 u_int16_t bit; 2031 { 2032 u_int16_t val; 2033 2034 /* We assume we're already in Window 4 */ 2035 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2036 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2037 val & ~bit); 2038 } 2039 2040 u_int16_t 2041 ep_mii_readbit(sc, bit) 2042 struct ep_softc *sc; 2043 u_int16_t bit; 2044 { 2045 2046 /* We assume we're already in Window 4 */ 2047 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT) & 2048 bit); 2049 } 2050 2051 void 2052 ep_mii_sync(sc) 2053 struct ep_softc *sc; 2054 { 2055 int i; 2056 2057 /* We assume we're already in Window 4 */ 2058 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2059 for (i = 0; i < 32; i++) { 2060 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2061 ep_mii_setbit(sc, PHYSMGMT_CLK); 2062 } 2063 } 2064 2065 void 2066 ep_mii_sendbits(sc, data, nbits) 2067 struct ep_softc *sc; 2068 u_int32_t data; 2069 int nbits; 2070 { 2071 int i; 2072 2073 /* We assume we're already in Window 4 */ 2074 ep_mii_setbit(sc, PHYSMGMT_DIR); 2075 for (i = 1 << (nbits - 1); i; i = i >> 1) { 2076 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2077 ep_mii_readbit(sc, PHYSMGMT_CLK); 2078 if (data & i) 2079 ep_mii_setbit(sc, PHYSMGMT_DATA); 2080 else 2081 ep_mii_clrbit(sc, PHYSMGMT_DATA); 2082 ep_mii_setbit(sc, PHYSMGMT_CLK); 2083 ep_mii_readbit(sc, PHYSMGMT_CLK); 2084 } 2085 } 2086 2087 int 2088 ep_mii_readreg(self, phy, reg) 2089 struct device *self; 2090 int phy, reg; 2091 { 2092 struct ep_softc *sc = (struct ep_softc *)self; 2093 int val = 0, i, err; 2094 2095 /* 2096 * Read the PHY register by manually driving the MII control lines. 2097 */ 2098 2099 GO_WINDOW(4); 2100 2101 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 0); 2102 2103 ep_mii_sync(sc); 2104 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2105 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 2106 ep_mii_sendbits(sc, phy, 5); 2107 ep_mii_sendbits(sc, reg, 5); 2108 2109 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2110 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2111 ep_mii_setbit(sc, PHYSMGMT_CLK); 2112 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2113 2114 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 2115 ep_mii_setbit(sc, PHYSMGMT_CLK); 2116 2117 /* Even if an error occurs, must still clock out the cycle. */ 2118 for (i = 0; i < 16; i++) { 2119 val <<= 1; 2120 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2121 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 2122 val |= 1; 2123 ep_mii_setbit(sc, PHYSMGMT_CLK); 2124 } 2125 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2126 ep_mii_setbit(sc, PHYSMGMT_CLK); 2127 2128 GO_WINDOW(1); /* back to operating window */ 2129 2130 return (err ? 0 : val); 2131 } 2132 2133 void 2134 ep_mii_writereg(self, phy, reg, val) 2135 struct device *self; 2136 int phy, reg, val; 2137 { 2138 struct ep_softc *sc = (struct ep_softc *)self; 2139 2140 /* 2141 * Write the PHY register by manually driving the MII control lines. 2142 */ 2143 2144 GO_WINDOW(4); 2145 2146 ep_mii_sync(sc); 2147 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2148 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2149 ep_mii_sendbits(sc, phy, 5); 2150 ep_mii_sendbits(sc, reg, 5); 2151 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2152 ep_mii_sendbits(sc, val, 16); 2153 2154 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2155 ep_mii_setbit(sc, PHYSMGMT_CLK); 2156 2157 GO_WINDOW(1); /* back to operating window */ 2158 } 2159 2160 void 2161 ep_statchg(self) 2162 struct device *self; 2163 { 2164 struct ep_softc *sc = (struct ep_softc *)self; 2165 bus_space_tag_t iot = sc->sc_iot; 2166 bus_space_handle_t ioh = sc->sc_ioh; 2167 int mctl; 2168 2169 /* XXX Update ifp->if_baudrate */ 2170 2171 GO_WINDOW(3); 2172 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 2173 if (sc->sc_mii.mii_media_active & IFM_FDX) 2174 mctl |= MAC_CONTROL_FDX; 2175 else 2176 mctl &= ~MAC_CONTROL_FDX; 2177 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 2178 GO_WINDOW(1); /* back to operating window */ 2179 } 2180
Indexes created Sat Sep 27 22:09:54 GMT 2025