elink3.c revision 1.58
1 /* $NetBSD: elink3.c,v 1.58 1999/05/18 23:52:55 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #ifdef DEBUG 124 int epdebug = 0; 125 #endif 126 127 /* 128 * XXX endian workaround for big-endian CPUs with pcmcia: 129 * if stream methods for bus_space_multi are not provided, define them 130 * using non-stream bus_space_{read,write}_multi_. 131 * Assumes host CPU is same endian-ness as bus. 132 */ 133 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 134 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 135 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 136 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 137 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 138 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 139 140 /* 141 * Structure to map media-present bits in boards to ifmedia codes and 142 * printable media names. Used for table-driven ifmedia initialization. 143 */ 144 struct ep_media { 145 int epm_mpbit; /* media present bit */ 146 const char *epm_name; /* name of medium */ 147 int epm_ifmedia; /* ifmedia word for medium */ 148 int epm_epmedia; /* ELINKMEDIA_* constant */ 149 }; 150 151 /* 152 * Media table for the Demon/Vortex/Boomerang chipsets. 153 * 154 * Note that MII on the Demon and Vortex (3c59x) indicates an external 155 * MII connector (for connecting an external PHY) ... I think. Treat 156 * it as `manual' on these chips. 157 * 158 * Any Boomerang (3c90x) chips with MII really do have an internal 159 * MII and real PHYs attached; no `native' media. 160 */ 161 struct ep_media ep_vortex_media[] = { 162 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 163 ELINKMEDIA_10BASE_T }, 164 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 165 ELINKMEDIA_10BASE_T }, 166 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 167 ELINKMEDIA_AUI }, 168 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 169 ELINKMEDIA_10BASE_2 }, 170 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 171 ELINKMEDIA_100BASE_TX }, 172 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 173 ELINKMEDIA_100BASE_TX }, 174 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 175 ELINKMEDIA_100BASE_FX }, 176 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 177 ELINKMEDIA_MII }, 178 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 179 ELINKMEDIA_100BASE_T4 }, 180 { 0, NULL, 0, 181 0 }, 182 }; 183 184 /* 185 * Media table for the older 3Com Etherlink III chipset, used 186 * in the 3c509, 3c579, and 3c589. 187 */ 188 struct ep_media ep_509_media[] = { 189 { ELINK_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 190 ELINKMEDIA_10BASE_T }, 191 { ELINK_W0_CC_AUI, "10base5", IFM_ETHER|IFM_10_5, 192 ELINKMEDIA_AUI }, 193 { ELINK_W0_CC_BNC, "10base2", IFM_ETHER|IFM_10_2, 194 ELINKMEDIA_10BASE_2 }, 195 { 0, NULL, 0, 196 0 }, 197 }; 198 199 void ep_internalconfig __P((struct ep_softc *sc)); 200 void ep_vortex_probemedia __P((struct ep_softc *sc)); 201 void ep_509_probemedia __P((struct ep_softc *sc)); 202 203 static void eptxstat __P((struct ep_softc *)); 204 static int epstatus __P((struct ep_softc *)); 205 void epinit __P((struct ep_softc *)); 206 int epioctl __P((struct ifnet *, u_long, caddr_t)); 207 void epstart __P((struct ifnet *)); 208 void epwatchdog __P((struct ifnet *)); 209 void epreset __P((struct ep_softc *)); 210 static void epshutdown __P((void *)); 211 void epread __P((struct ep_softc *)); 212 struct mbuf *epget __P((struct ep_softc *, int)); 213 void epmbuffill __P((void *)); 214 void epmbufempty __P((struct ep_softc *)); 215 void epsetfilter __P((struct ep_softc *)); 216 void epsetmedia __P((struct ep_softc *)); 217 218 /* ifmedia callbacks */ 219 int ep_media_change __P((struct ifnet *ifp)); 220 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 221 222 /* MII callbacks */ 223 int ep_mii_readreg __P((struct device *, int, int)); 224 void ep_mii_writereg __P((struct device *, int, int, int)); 225 void ep_statchg __P((struct device *)); 226 227 void ep_tick __P((void *)); 228 229 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 230 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 231 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 232 void ep_mii_sync __P((struct ep_softc *)); 233 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 234 235 static int epbusyeeprom __P((struct ep_softc *)); 236 static inline void ep_reset_cmd __P((struct ep_softc *sc, 237 u_int cmd, u_int arg)); 238 static inline void ep_finish_reset __P((bus_space_tag_t, bus_space_handle_t)); 239 static inline void ep_discard_rxtop __P((bus_space_tag_t, bus_space_handle_t)); 240 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 241 242 /* 243 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 244 * Window 1 registers offset! 245 */ 246 static __inline int 247 ep_w1_reg(sc, reg) 248 struct ep_softc *sc; 249 int reg; 250 { 251 252 switch (sc->ep_chipset) { 253 case ELINK_CHIPSET_CORKSCREW: 254 return (reg + 0x10); 255 256 case ELINK_CHIPSET_ROADRUNNER: 257 switch (reg) { 258 case ELINK_W1_FREE_TX: 259 case ELINK_W1_RUNNER_RDCTL: 260 case ELINK_W1_RUNNER_WRCTL: 261 return (reg); 262 } 263 return (reg + 0x10); 264 } 265 266 return (reg); 267 } 268 269 /* 270 * Wait for any pending reset to complete. 271 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 272 * but older hardware doesn't implement it and we must delay. 273 */ 274 static inline void 275 ep_finish_reset(iot, ioh) 276 bus_space_tag_t iot; 277 bus_space_handle_t ioh; 278 279 { 280 int i; 281 282 for (i = 0; i < 10000; i++) { 283 if ((bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) == 0) 284 break; 285 DELAY(10); 286 } 287 } 288 289 /* 290 * Issue a (reset) command, and be sure it has completed. 291 * Used for global reset, TX_RESET, RX_RESET. 292 */ 293 static inline void 294 ep_reset_cmd(sc, cmd, arg) 295 struct ep_softc *sc; 296 u_int cmd, arg; 297 { 298 register bus_space_tag_t iot = sc->sc_iot; 299 register bus_space_handle_t ioh = sc->sc_ioh; 300 301 bus_space_write_2(iot, ioh, cmd, arg); 302 ep_finish_reset(iot, ioh); 303 } 304 305 306 static inline void 307 ep_discard_rxtop(iot, ioh) 308 register bus_space_tag_t iot; 309 register bus_space_handle_t ioh; 310 { 311 int i; 312 313 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 314 315 /* 316 * Spin for about 1 msec, to avoid forcing a DELAY() between 317 * every received packet (adding latency and limiting pkt-recv rate). 318 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 319 * is about right. 320 */ 321 for (i = 0; i < 8000; i++) { 322 if ((bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) == 0) 323 return; 324 } 325 326 /* Didn't complete in a hurry. Do DELAY()s. */ 327 ep_finish_reset(iot, ioh); 328 } 329 330 /* 331 * Back-end attach and configure. 332 */ 333 void 334 epconfig(sc, chipset, enaddr) 335 struct ep_softc *sc; 336 u_short chipset; 337 u_int8_t *enaddr; 338 { 339 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 340 bus_space_tag_t iot = sc->sc_iot; 341 bus_space_handle_t ioh = sc->sc_ioh; 342 u_int16_t i; 343 u_int8_t myla[6]; 344 345 sc->ep_chipset = chipset; 346 347 /* 348 * We could have been groveling around in other register 349 * windows in the front-end; make sure we're in window 0 350 * to read the EEPROM. 351 */ 352 GO_WINDOW(0); 353 354 if (enaddr == NULL) { 355 /* 356 * Read the station address from the eeprom 357 */ 358 for (i = 0; i < 3; i++) { 359 u_int16_t x; 360 if (epbusyeeprom(sc)) 361 return; /* XXX why is eeprom busy? */ 362 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 363 READ_EEPROM | i); 364 if (epbusyeeprom(sc)) 365 return; /* XXX why is eeprom busy? */ 366 x = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 367 myla[(i << 1)] = x >> 8; 368 myla[(i << 1) + 1] = x; 369 } 370 enaddr = myla; 371 } 372 373 /* 374 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 375 * allow FDDI-sized (4500) byte packets. Commands only take an 376 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 377 * packet length. 378 * Commands to these cards implicitly upshift a packet size 379 * or threshold by 2 bits. 380 * To detect cards with large-packet support, we probe by setting 381 * the transmit threshold register, then change windows and 382 * read back the threshold register directly, and see if the 383 * threshold value was shifted or not. 384 */ 385 bus_space_write_2(iot, ioh, ELINK_COMMAND, 386 SET_TX_AVAIL_THRESH | ELINK_LARGEWIN_PROBE ); 387 GO_WINDOW(5); 388 i = bus_space_read_2(iot, ioh, ELINK_W5_TX_AVAIL_THRESH); 389 GO_WINDOW(1); 390 switch (i) { 391 case ELINK_LARGEWIN_PROBE: 392 case (ELINK_LARGEWIN_PROBE & ELINK_LARGEWIN_MASK): 393 sc->ep_pktlenshift = 0; 394 break; 395 396 case (ELINK_LARGEWIN_PROBE << 2): 397 sc->ep_pktlenshift = 2; 398 break; 399 400 default: 401 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 402 "Interface disabled\n", 403 sc->sc_dev.dv_xname, ELINK_LARGEWIN_PROBE, (int) i); 404 return; 405 } 406 407 /* 408 * Ensure Tx-available interrupts are enabled for 409 * start the interface. 410 * XXX should be in epinit()? 411 */ 412 bus_space_write_2(iot, ioh, ELINK_COMMAND, 413 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 414 415 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 416 ifp->if_softc = sc; 417 ifp->if_start = epstart; 418 ifp->if_ioctl = epioctl; 419 ifp->if_watchdog = epwatchdog; 420 ifp->if_flags = 421 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 422 423 if_attach(ifp); 424 ether_ifattach(ifp, enaddr); 425 426 /* 427 * Finish configuration: 428 * determine chipset if the front-end couldn't do so, 429 * show board details, set media. 430 */ 431 432 /* 433 * Print RAM size. We also print the Ethernet address in here. 434 * It's extracted from the ifp, so we have to make sure it's 435 * been attached first. 436 */ 437 ep_internalconfig(sc); 438 GO_WINDOW(0); 439 440 /* 441 * Display some additional information, if pertinent. 442 */ 443 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 444 printf("%s: RoadRunner FIFO buffer enabled\n", 445 sc->sc_dev.dv_xname); 446 447 /* 448 * Initialize our media structures and MII info. We'll 449 * probe the MII if we discover that we have one. 450 */ 451 sc->sc_mii.mii_ifp = ifp; 452 sc->sc_mii.mii_readreg = ep_mii_readreg; 453 sc->sc_mii.mii_writereg = ep_mii_writereg; 454 sc->sc_mii.mii_statchg = ep_statchg; 455 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 456 ep_media_status); 457 458 /* 459 * Now, determine which media we have. 460 */ 461 switch (sc->ep_chipset) { 462 case ELINK_CHIPSET_BOOMERANG: 463 case ELINK_CHIPSET_ROADRUNNER: 464 /* 465 * If the device has MII, probe it. We won't be using 466 * any `native' media in this case, only PHYs. If 467 * we don't, just treat the Boomerang like the Vortex. 468 */ 469 if (sc->ep_flags & ELINK_FLAGS_MII) { 470 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 471 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 472 ifmedia_add(&sc->sc_mii.mii_media, 473 IFM_ETHER|IFM_NONE, 0, NULL); 474 ifmedia_set(&sc->sc_mii.mii_media, 475 IFM_ETHER|IFM_NONE); 476 } else { 477 ifmedia_set(&sc->sc_mii.mii_media, 478 IFM_ETHER|IFM_AUTO); 479 } 480 break; 481 } 482 /* FALLTHROUGH */ 483 484 case ELINK_CHIPSET_VORTEX: 485 ep_vortex_probemedia(sc); 486 break; 487 488 default: 489 ep_509_probemedia(sc); 490 break; 491 } 492 493 GO_WINDOW(1); /* Window 1 is operating window */ 494 495 #if NBPFILTER > 0 496 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 497 sizeof(struct ether_header)); 498 #endif 499 500 #if NRND > 0 501 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 502 RND_TYPE_NET, 0); 503 #endif 504 505 sc->tx_start_thresh = 20; /* probably a good starting point. */ 506 507 /* Establish callback to reset card when we reboot. */ 508 shutdownhook_establish(epshutdown, sc); 509 510 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 511 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 512 } 513 514 515 /* 516 * Show interface-model-independent info from window 3 517 * internal-configuration register. 518 */ 519 void 520 ep_internalconfig(sc) 521 struct ep_softc *sc; 522 { 523 bus_space_tag_t iot = sc->sc_iot; 524 bus_space_handle_t ioh = sc->sc_ioh; 525 526 u_int config0; 527 u_int config1; 528 529 int ram_size, ram_width, ram_speed, rom_size, ram_split; 530 /* 531 * NVRAM buffer Rx:Tx config names for busmastering cards 532 * (Demon, Vortex, and later). 533 */ 534 const char *onboard_ram_config[] = { 535 "5:3", "3:1", "1:1", "3:5" }; 536 537 GO_WINDOW(3); 538 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 539 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 540 GO_WINDOW(0); 541 542 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 543 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 544 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 545 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 546 547 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 548 549 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 550 sc->sc_dev.dv_xname, 551 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 552 8 << ram_size, 553 (ram_width) ? "word" : "byte", 554 onboard_ram_config[ram_split]); 555 } 556 557 558 /* 559 * Find supported media on 3c509-generation hardware that doesn't have 560 * a "reset_options" register in window 3. 561 * Use the config_cntrl register in window 0 instead. 562 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 563 * that implement CONFIG_CTRL. We don't have a good way to set the 564 * default active mediuim; punt to ifconfig instead. 565 */ 566 void 567 ep_509_probemedia(sc) 568 struct ep_softc *sc; 569 { 570 bus_space_tag_t iot = sc->sc_iot; 571 bus_space_handle_t ioh = sc->sc_ioh; 572 struct ifmedia *ifm = &sc->sc_mii.mii_media; 573 u_int16_t ep_w0_config, port; 574 struct ep_media *epm; 575 const char *sep = "", *defmedianame = NULL; 576 int defmedia = 0; 577 578 GO_WINDOW(0); 579 ep_w0_config = bus_space_read_2(iot, ioh, ELINK_W0_CONFIG_CTRL); 580 581 printf("%s: ", sc->sc_dev.dv_xname); 582 583 /* Sanity check that there are any media! */ 584 if ((ep_w0_config & ELINK_W0_CC_MEDIAMASK) == 0) { 585 printf("no media present!\n"); 586 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 587 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 588 return; 589 } 590 591 /* 592 * Get the default media from the EEPROM. 593 */ 594 if (epbusyeeprom(sc)) 595 return; /* XXX why is eeprom busy? */ 596 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 597 READ_EEPROM | EEPROM_ADDR_CFG); 598 if (epbusyeeprom(sc)) 599 return; /* XXX why is eeprom busy? */ 600 port = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA) >> 14; 601 602 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 603 604 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 605 if (ep_w0_config & epm->epm_mpbit) { 606 /* 607 * This simple test works because 509 chipsets 608 * don't do full-duplex. 609 */ 610 if (epm->epm_epmedia == port || defmedia == 0) { 611 defmedia = epm->epm_ifmedia; 612 defmedianame = epm->epm_name; 613 } 614 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 615 NULL); 616 PRINT(epm->epm_name); 617 } 618 } 619 620 #undef PRINT 621 622 #ifdef DIAGNOSTIC 623 if (defmedia == 0) 624 panic("ep_509_probemedia: impossible"); 625 #endif 626 627 printf(" (default %s)\n", defmedianame); 628 ifmedia_set(ifm, defmedia); 629 } 630 631 /* 632 * Find media present on large-packet-capable elink3 devices. 633 * Show onboard configuration of large-packet-capable elink3 devices 634 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 635 * Use media and card-version info in window 3 instead. 636 */ 637 void 638 ep_vortex_probemedia(sc) 639 struct ep_softc *sc; 640 { 641 bus_space_tag_t iot = sc->sc_iot; 642 bus_space_handle_t ioh = sc->sc_ioh; 643 struct ifmedia *ifm = &sc->sc_mii.mii_media; 644 struct ep_media *epm; 645 u_int config1; 646 int reset_options; 647 int default_media; /* 3-bit encoding of default (EEPROM) media */ 648 int defmedia = 0; 649 const char *sep = "", *defmedianame = NULL; 650 651 GO_WINDOW(3); 652 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 653 reset_options = (int)bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 654 GO_WINDOW(0); 655 656 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 657 658 printf("%s: ", sc->sc_dev.dv_xname); 659 660 /* Sanity check that there are any media! */ 661 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 662 printf("no media present!\n"); 663 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 664 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 665 return; 666 } 667 668 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 669 670 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 671 if (reset_options & epm->epm_mpbit) { 672 /* 673 * Default media is a little more complicated 674 * on the Vortex. We support full-duplex which 675 * uses the same reset options bit. 676 * 677 * XXX Check EEPROM for default to FDX? 678 */ 679 if (epm->epm_epmedia == default_media) { 680 if ((epm->epm_ifmedia & IFM_FDX) == 0) { 681 defmedia = epm->epm_ifmedia; 682 defmedianame = epm->epm_name; 683 } 684 } else if (defmedia == 0) { 685 defmedia = epm->epm_ifmedia; 686 defmedianame = epm->epm_name; 687 } 688 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 689 NULL); 690 PRINT(epm->epm_name); 691 } 692 } 693 694 #undef PRINT 695 696 #ifdef DIAGNOSTIC 697 if (defmedia == 0) 698 panic("ep_vortex_probemedia: impossible"); 699 #endif 700 701 printf(" (default %s)\n", defmedianame); 702 ifmedia_set(ifm, defmedia); 703 } 704 705 /* 706 * One second timer, used to tick the MII. 707 */ 708 void 709 ep_tick(arg) 710 void *arg; 711 { 712 struct ep_softc *sc = arg; 713 int s; 714 715 #ifdef DIAGNOSTIC 716 if ((sc->ep_flags & ELINK_FLAGS_MII) == 0) 717 panic("ep_tick"); 718 #endif 719 720 s = splnet(); 721 mii_tick(&sc->sc_mii); 722 splx(s); 723 724 timeout(ep_tick, sc, hz); 725 } 726 727 /* 728 * Bring device up. 729 * 730 * The order in here seems important. Otherwise we may not receive 731 * interrupts. ?! 732 */ 733 void 734 epinit(sc) 735 register struct ep_softc *sc; 736 { 737 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 738 bus_space_tag_t iot = sc->sc_iot; 739 bus_space_handle_t ioh = sc->sc_ioh; 740 int i; 741 742 /* Make sure any pending reset has completed before touching board. */ 743 ep_finish_reset(iot, ioh); 744 745 746 if (sc->bustype != ELINK_BUS_PCI) { 747 GO_WINDOW(0); 748 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, 0); 749 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 750 } 751 752 if (sc->bustype == ELINK_BUS_PCMCIA) { 753 bus_space_write_2(iot, ioh, ELINK_W0_RESOURCE_CFG, 0x3f00); 754 } 755 756 GO_WINDOW(2); 757 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 758 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 759 LLADDR(ifp->if_sadl)[i]); 760 761 /* 762 * Reset the station-address receive filter. 763 * A bug workaround for busmastering (Vortex, Demon) cards. 764 */ 765 for (i = 0; i < 6; i++) 766 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 767 768 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 769 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 770 771 GO_WINDOW(1); /* Window 1 is operating window */ 772 for (i = 0; i < 31; i++) 773 bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS)); 774 775 /* Set threshhold for for Tx-space avaiable interrupt. */ 776 bus_space_write_2(iot, ioh, ELINK_COMMAND, 777 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 778 779 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 780 /* 781 * Enable options in the PCMCIA LAN COR register, via 782 * RoadRunner Window 1. 783 * 784 * XXX MAGIC CONSTANTS! 785 */ 786 u_int16_t cor; 787 788 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, (1 << 11)); 789 790 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 791 if (sc->ep_flags & ELINK_FLAGS_USESHAREDMEM) 792 cor |= 0x10; 793 if (sc->ep_flags & ELINK_FLAGS_FORCENOWAIT) 794 cor |= 0x20; 795 bus_space_write_2(iot, ioh, 0, cor); 796 797 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 798 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 799 } 800 801 /* Enable interrupts. */ 802 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 803 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 804 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | 805 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 806 807 /* 808 * Attempt to get rid of any stray interrupts that occured during 809 * configuration. On the i386 this isn't possible because one may 810 * already be queued. However, a single stray interrupt is 811 * unimportant. 812 */ 813 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 814 815 epsetfilter(sc); 816 epsetmedia(sc); 817 818 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 819 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 820 821 epmbuffill(sc); 822 823 /* Interface is now `running', with no output active. */ 824 ifp->if_flags |= IFF_RUNNING; 825 ifp->if_flags &= ~IFF_OACTIVE; 826 827 if (sc->ep_flags & ELINK_FLAGS_MII) { 828 /* Start the one second clock. */ 829 timeout(ep_tick, sc, hz); 830 } 831 832 /* Attempt to start output, if any. */ 833 epstart(ifp); 834 } 835 836 837 /* 838 * Set multicast receive filter. 839 * elink3 hardware has no selective multicast filter in hardware. 840 * Enable reception of all multicasts and filter in software. 841 */ 842 void 843 epsetfilter(sc) 844 register struct ep_softc *sc; 845 { 846 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 847 848 GO_WINDOW(1); /* Window 1 is operating window */ 849 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, SET_RX_FILTER | 850 FIL_INDIVIDUAL | FIL_BRDCST | 851 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 852 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 853 } 854 855 int 856 ep_media_change(ifp) 857 struct ifnet *ifp; 858 { 859 register struct ep_softc *sc = ifp->if_softc; 860 861 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 862 epreset(sc); 863 864 return (0); 865 } 866 867 /* 868 * Set the card to use the specified media. 869 */ 870 void 871 epsetmedia(sc) 872 struct ep_softc *sc; 873 { 874 bus_space_tag_t iot = sc->sc_iot; 875 bus_space_handle_t ioh = sc->sc_ioh; 876 877 /* Turn everything off. First turn off linkbeat and UTP. */ 878 GO_WINDOW(4); 879 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0x0); 880 881 /* Turn off coax */ 882 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 883 delay(1000); 884 885 /* 886 * If the device has MII, select it, and then tell the 887 * PHY which media to use. 888 */ 889 if (sc->ep_flags & ELINK_FLAGS_MII) { 890 int config0, config1; 891 892 GO_WINDOW(3); 893 894 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 895 int resopt; 896 897 resopt = bus_space_read_2(iot, ioh, 898 ELINK_W3_RESET_OPTIONS); 899 bus_space_write_2(iot, ioh, 900 ELINK_W3_RESET_OPTIONS, resopt|ELINK_RUNNER_ENABLE_MII); 901 } 902 903 config0 = (u_int)bus_space_read_2(iot, ioh, 904 ELINK_W3_INTERNAL_CONFIG); 905 config1 = (u_int)bus_space_read_2(iot, ioh, 906 ELINK_W3_INTERNAL_CONFIG + 2); 907 908 config1 = config1 & ~CONFIG_MEDIAMASK; 909 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 910 911 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 912 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 913 GO_WINDOW(1); /* back to operating window */ 914 915 mii_mediachg(&sc->sc_mii); 916 return; 917 } 918 919 /* 920 * Now turn on the selected media/transceiver. 921 */ 922 GO_WINDOW(4); 923 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 924 case IFM_10_T: 925 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 926 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 927 break; 928 929 case IFM_10_2: 930 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 931 DELAY(1000); /* 50ms not enmough? */ 932 break; 933 934 case IFM_100_TX: 935 case IFM_100_FX: 936 case IFM_100_T4: /* XXX check documentation */ 937 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 938 LINKBEAT_ENABLE); 939 DELAY(1000); /* not strictly necessary? */ 940 break; 941 942 case IFM_10_5: 943 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 944 SQE_ENABLE); 945 DELAY(1000); /* not strictly necessary? */ 946 break; 947 948 case IFM_MANUAL: 949 /* 950 * Nothing to do here; we are actually enabling the 951 * external PHY on the MII port. 952 */ 953 break; 954 955 case IFM_NONE: 956 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 957 return; 958 959 default: 960 panic("epsetmedia: impossible"); 961 } 962 963 /* 964 * Tell the chip which port to use. 965 */ 966 switch (sc->ep_chipset) { 967 case ELINK_CHIPSET_VORTEX: 968 case ELINK_CHIPSET_BOOMERANG: 969 { 970 int mctl, config0, config1; 971 972 GO_WINDOW(3); 973 config0 = (u_int)bus_space_read_2(iot, ioh, 974 ELINK_W3_INTERNAL_CONFIG); 975 config1 = (u_int)bus_space_read_2(iot, ioh, 976 ELINK_W3_INTERNAL_CONFIG + 2); 977 978 config1 = config1 & ~CONFIG_MEDIAMASK; 979 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 980 CONFIG_MEDIAMASK_SHIFT); 981 982 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 983 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, 984 config1); 985 986 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 987 if (sc->sc_mii.mii_media.ifm_cur->ifm_media & IFM_FDX) 988 mctl |= MAC_CONTROL_FDX; 989 else 990 mctl &= ~MAC_CONTROL_FDX; 991 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 992 break; 993 } 994 default: 995 { 996 int w0_addr_cfg; 997 998 GO_WINDOW(0); 999 w0_addr_cfg = bus_space_read_2(iot, ioh, ELINK_W0_ADDRESS_CFG); 1000 w0_addr_cfg &= 0x3fff; 1001 bus_space_write_2(iot, ioh, ELINK_W0_ADDRESS_CFG, w0_addr_cfg | 1002 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 1003 DELAY(1000); 1004 break; 1005 } 1006 } 1007 1008 GO_WINDOW(1); /* Window 1 is operating window */ 1009 } 1010 1011 /* 1012 * Get currently-selected media from card. 1013 * (if_media callback, may be called before interface is brought up). 1014 */ 1015 void 1016 ep_media_status(ifp, req) 1017 struct ifnet *ifp; 1018 struct ifmediareq *req; 1019 { 1020 register struct ep_softc *sc = ifp->if_softc; 1021 bus_space_tag_t iot = sc->sc_iot; 1022 bus_space_handle_t ioh = sc->sc_ioh; 1023 1024 if (sc->enabled == 0) { 1025 req->ifm_active = IFM_ETHER|IFM_NONE; 1026 req->ifm_status = 0; 1027 return; 1028 } 1029 1030 /* 1031 * If we have MII, go ask the PHY what's going on. 1032 */ 1033 if (sc->ep_flags & ELINK_FLAGS_MII) { 1034 mii_pollstat(&sc->sc_mii); 1035 req->ifm_active = sc->sc_mii.mii_media_active; 1036 req->ifm_status = sc->sc_mii.mii_media_status; 1037 return; 1038 } 1039 1040 /* 1041 * Ok, at this point we claim that our active media is 1042 * the currently selected media. We'll update our status 1043 * if our chipset allows us to detect link. 1044 */ 1045 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1046 req->ifm_status = 0; 1047 1048 switch (sc->ep_chipset) { 1049 case ELINK_CHIPSET_VORTEX: 1050 case ELINK_CHIPSET_BOOMERANG: 1051 GO_WINDOW(4); 1052 req->ifm_status = IFM_AVALID; 1053 if (bus_space_read_2(iot, ioh, ELINK_W4_MEDIA_TYPE) & 1054 LINKBEAT_DETECT) 1055 req->ifm_status |= IFM_ACTIVE; 1056 GO_WINDOW(1); /* back to operating window */ 1057 break; 1058 } 1059 } 1060 1061 1062 1063 /* 1064 * Start outputting on the interface. 1065 * Always called as splnet(). 1066 */ 1067 void 1068 epstart(ifp) 1069 struct ifnet *ifp; 1070 { 1071 register struct ep_softc *sc = ifp->if_softc; 1072 bus_space_tag_t iot = sc->sc_iot; 1073 bus_space_handle_t ioh = sc->sc_ioh; 1074 struct mbuf *m, *m0; 1075 int sh, len, pad; 1076 bus_addr_t txreg; 1077 1078 /* Don't transmit if interface is busy or not running */ 1079 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1080 return; 1081 1082 startagain: 1083 /* Sneak a peek at the next packet */ 1084 m0 = ifp->if_snd.ifq_head; 1085 if (m0 == 0) 1086 return; 1087 1088 /* We need to use m->m_pkthdr.len, so require the header */ 1089 if ((m0->m_flags & M_PKTHDR) == 0) 1090 panic("epstart: no header mbuf"); 1091 len = m0->m_pkthdr.len; 1092 1093 pad = (4 - len) & 3; 1094 1095 /* 1096 * The 3c509 automatically pads short packets to minimum ethernet 1097 * length, but we drop packets that are too large. Perhaps we should 1098 * truncate them instead? 1099 */ 1100 if (len + pad > ETHER_MAX_LEN) { 1101 /* packet is obviously too large: toss it */ 1102 ++ifp->if_oerrors; 1103 IF_DEQUEUE(&ifp->if_snd, m0); 1104 m_freem(m0); 1105 goto readcheck; 1106 } 1107 1108 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_FREE_TX)) < 1109 len + pad + 4) { 1110 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1111 SET_TX_AVAIL_THRESH | 1112 ((len + pad + 4) >> sc->ep_pktlenshift)); 1113 /* not enough room in FIFO */ 1114 ifp->if_flags |= IFF_OACTIVE; 1115 return; 1116 } else { 1117 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1118 SET_TX_AVAIL_THRESH | ELINK_THRESH_DISABLE ); 1119 } 1120 1121 IF_DEQUEUE(&ifp->if_snd, m0); 1122 if (m0 == 0) /* not really needed */ 1123 return; 1124 1125 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_TX_START_THRESH | 1126 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/) ); 1127 1128 #if NBPFILTER > 0 1129 if (ifp->if_bpf) 1130 bpf_mtap(ifp->if_bpf, m0); 1131 #endif 1132 1133 /* 1134 * Do the output at splhigh() so that an interrupt from another device 1135 * won't cause a FIFO underrun. 1136 */ 1137 sh = splhigh(); 1138 1139 txreg = ep_w1_reg(sc, ELINK_W1_TX_PIO_WR_1); 1140 1141 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1142 /* 1143 * Prime the FIFO buffer counter (number of 16-bit 1144 * words about to be written to the FIFO). 1145 * 1146 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1147 * COUNTER IS NON-ZERO! 1148 */ 1149 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 1150 (len + pad) >> 1); 1151 } 1152 1153 bus_space_write_2(iot, ioh, txreg, len); 1154 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1155 if (ELINK_IS_BUS_32(sc->bustype)) { 1156 for (m = m0; m; ) { 1157 if (m->m_len > 3) { 1158 /* align our reads from core */ 1159 if (mtod(m, u_long) & 3) { 1160 u_long count = 1161 4 - (mtod(m, u_long) & 3); 1162 bus_space_write_multi_1(iot, ioh, 1163 txreg, mtod(m, u_int8_t *), count); 1164 m->m_data = 1165 (void *)(mtod(m, u_long) + count); 1166 m->m_len -= count; 1167 } 1168 bus_space_write_multi_stream_4(iot, ioh, 1169 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1170 m->m_data = (void *)(mtod(m, u_long) + 1171 (u_long)(m->m_len & ~3)); 1172 m->m_len -= m->m_len & ~3; 1173 } 1174 if (m->m_len) { 1175 bus_space_write_multi_1(iot, ioh, 1176 txreg, mtod(m, u_int8_t *), m->m_len); 1177 } 1178 MFREE(m, m0); 1179 m = m0; 1180 } 1181 } else { 1182 for (m = m0; m; ) { 1183 if (m->m_len > 1) { 1184 if (mtod(m, u_long) & 1) { 1185 bus_space_write_1(iot, ioh, 1186 txreg, *(mtod(m, u_int8_t *))); 1187 m->m_data = 1188 (void *)(mtod(m, u_long) + 1); 1189 m->m_len -= 1; 1190 } 1191 bus_space_write_multi_stream_2(iot, ioh, 1192 txreg, mtod(m, u_int16_t *), 1193 m->m_len >> 1); 1194 } 1195 if (m->m_len & 1) { 1196 bus_space_write_1(iot, ioh, txreg, 1197 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1198 } 1199 MFREE(m, m0); 1200 m = m0; 1201 } 1202 } 1203 while (pad--) 1204 bus_space_write_1(iot, ioh, txreg, 0); 1205 1206 splx(sh); 1207 1208 ++ifp->if_opackets; 1209 1210 readcheck: 1211 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)) & 1212 ERR_INCOMPLETE) == 0) { 1213 /* We received a complete packet. */ 1214 u_int16_t status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1215 1216 if ((status & S_INTR_LATCH) == 0) { 1217 /* 1218 * No interrupt, read the packet and continue 1219 * Is this supposed to happen? Is my motherboard 1220 * completely busted? 1221 */ 1222 epread(sc); 1223 } else { 1224 /* Got an interrupt, return so that it gets serviced. */ 1225 return; 1226 } 1227 } else { 1228 /* Check if we are stuck and reset [see XXX comment] */ 1229 if (epstatus(sc)) { 1230 if (ifp->if_flags & IFF_DEBUG) 1231 printf("%s: adapter reset\n", 1232 sc->sc_dev.dv_xname); 1233 epreset(sc); 1234 } 1235 } 1236 1237 goto startagain; 1238 } 1239 1240 1241 /* 1242 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1243 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1244 * We detect this situation and we reset the adapter. 1245 * It happens at times when there is a lot of broadcast traffic 1246 * on the cable (once in a blue moon). 1247 */ 1248 static int 1249 epstatus(sc) 1250 register struct ep_softc *sc; 1251 { 1252 bus_space_tag_t iot = sc->sc_iot; 1253 bus_space_handle_t ioh = sc->sc_ioh; 1254 u_int16_t fifost; 1255 1256 /* 1257 * Check the FIFO status and act accordingly 1258 */ 1259 GO_WINDOW(4); 1260 fifost = bus_space_read_2(iot, ioh, ELINK_W4_FIFO_DIAG); 1261 GO_WINDOW(1); 1262 1263 if (fifost & FIFOS_RX_UNDERRUN) { 1264 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1265 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1266 epreset(sc); 1267 return 0; 1268 } 1269 1270 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1271 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1272 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1273 return 1; 1274 } 1275 1276 if (fifost & FIFOS_RX_OVERRUN) { 1277 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1278 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1279 return 1; 1280 } 1281 1282 if (fifost & FIFOS_TX_OVERRUN) { 1283 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1284 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1285 epreset(sc); 1286 return 0; 1287 } 1288 1289 return 0; 1290 } 1291 1292 1293 static void 1294 eptxstat(sc) 1295 register struct ep_softc *sc; 1296 { 1297 bus_space_tag_t iot = sc->sc_iot; 1298 bus_space_handle_t ioh = sc->sc_ioh; 1299 int i; 1300 1301 /* 1302 * We need to read+write TX_STATUS until we get a 0 status 1303 * in order to turn off the interrupt flag. 1304 */ 1305 while ((i = bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS))) 1306 & TXS_COMPLETE) { 1307 bus_space_write_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS), 1308 0x0); 1309 1310 if (i & TXS_JABBER) { 1311 ++sc->sc_ethercom.ec_if.if_oerrors; 1312 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1313 printf("%s: jabber (%x)\n", 1314 sc->sc_dev.dv_xname, i); 1315 epreset(sc); 1316 } else if (i & TXS_UNDERRUN) { 1317 ++sc->sc_ethercom.ec_if.if_oerrors; 1318 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1319 printf("%s: fifo underrun (%x) @%d\n", 1320 sc->sc_dev.dv_xname, i, 1321 sc->tx_start_thresh); 1322 if (sc->tx_succ_ok < 100) 1323 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1324 sc->tx_start_thresh + 20); 1325 sc->tx_succ_ok = 0; 1326 epreset(sc); 1327 } else if (i & TXS_MAX_COLLISION) { 1328 ++sc->sc_ethercom.ec_if.if_collisions; 1329 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 1330 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1331 } else 1332 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1333 } 1334 } 1335 1336 int 1337 epintr(arg) 1338 void *arg; 1339 { 1340 register struct ep_softc *sc = arg; 1341 bus_space_tag_t iot = sc->sc_iot; 1342 bus_space_handle_t ioh = sc->sc_ioh; 1343 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1344 u_int16_t status; 1345 int ret = 0; 1346 int addrandom = 0; 1347 1348 if (sc->enabled == 0) 1349 return (0); 1350 1351 for (;;) { 1352 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1353 1354 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1355 1356 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1357 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1358 if ((status & S_INTR_LATCH) == 0) { 1359 #if 0 1360 printf("%s: intr latch cleared\n", 1361 sc->sc_dev.dv_xname); 1362 #endif 1363 break; 1364 } 1365 } 1366 1367 ret = 1; 1368 1369 /* 1370 * Acknowledge any interrupts. It's important that we do this 1371 * first, since there would otherwise be a race condition. 1372 * Due to the i386 interrupt queueing, we may get spurious 1373 * interrupts occasionally. 1374 */ 1375 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1376 (status & (C_INTR_LATCH | 1377 C_CARD_FAILURE | 1378 C_TX_COMPLETE | 1379 C_TX_AVAIL | 1380 C_RX_COMPLETE | 1381 C_RX_EARLY | 1382 C_INT_RQD | 1383 C_UPD_STATS))); 1384 1385 #if 0 1386 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1387 1388 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1389 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1390 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1391 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1392 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1393 #endif 1394 1395 if (status & S_RX_COMPLETE) { 1396 epread(sc); 1397 addrandom = 1; 1398 } 1399 if (status & S_TX_AVAIL) { 1400 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1401 epstart(&sc->sc_ethercom.ec_if); 1402 addrandom = 1; 1403 } 1404 if (status & S_CARD_FAILURE) { 1405 printf("%s: adapter failure (%x)\n", 1406 sc->sc_dev.dv_xname, status); 1407 epreset(sc); 1408 return (1); 1409 } 1410 if (status & S_TX_COMPLETE) { 1411 eptxstat(sc); 1412 epstart(ifp); 1413 addrandom = 1; 1414 } 1415 1416 #if NRND > 0 1417 if (status) 1418 rnd_add_uint32(&sc->rnd_source, status); 1419 #endif 1420 } 1421 1422 /* no more interrupts */ 1423 return (ret); 1424 } 1425 1426 void 1427 epread(sc) 1428 register struct ep_softc *sc; 1429 { 1430 bus_space_tag_t iot = sc->sc_iot; 1431 bus_space_handle_t ioh = sc->sc_ioh; 1432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1433 struct mbuf *m; 1434 struct ether_header *eh; 1435 int len; 1436 1437 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1438 1439 again: 1440 if (ifp->if_flags & IFF_DEBUG) { 1441 int err = len & ERR_MASK; 1442 char *s = NULL; 1443 1444 if (len & ERR_INCOMPLETE) 1445 s = "incomplete packet"; 1446 else if (err == ERR_OVERRUN) 1447 s = "packet overrun"; 1448 else if (err == ERR_RUNT) 1449 s = "runt packet"; 1450 else if (err == ERR_ALIGNMENT) 1451 s = "bad alignment"; 1452 else if (err == ERR_CRC) 1453 s = "bad crc"; 1454 else if (err == ERR_OVERSIZE) 1455 s = "oversized packet"; 1456 else if (err == ERR_DRIBBLE) 1457 s = "dribble bits"; 1458 1459 if (s) 1460 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1461 } 1462 1463 if (len & ERR_INCOMPLETE) 1464 return; 1465 1466 if (len & ERR_RX) { 1467 ++ifp->if_ierrors; 1468 goto abort; 1469 } 1470 1471 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1472 1473 /* Pull packet off interface. */ 1474 m = epget(sc, len); 1475 if (m == 0) { 1476 ifp->if_ierrors++; 1477 goto abort; 1478 } 1479 1480 ++ifp->if_ipackets; 1481 1482 /* We assume the header fit entirely in one mbuf. */ 1483 eh = mtod(m, struct ether_header *); 1484 1485 #if NBPFILTER > 0 1486 /* 1487 * Check if there's a BPF listener on this interface. 1488 * If so, hand off the raw packet to BPF. 1489 */ 1490 if (ifp->if_bpf) { 1491 bpf_mtap(ifp->if_bpf, m); 1492 1493 /* 1494 * Note that the interface cannot be in promiscuous mode if 1495 * there are no BPF listeners. And if we are in promiscuous 1496 * mode, we have to check if this packet is really ours. 1497 */ 1498 if ((ifp->if_flags & IFF_PROMISC) && 1499 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1500 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1501 sizeof(eh->ether_dhost)) != 0) { 1502 m_freem(m); 1503 return; 1504 } 1505 } 1506 #endif 1507 (*ifp->if_input)(ifp, m); 1508 1509 /* 1510 * In periods of high traffic we can actually receive enough 1511 * packets so that the fifo overrun bit will be set at this point, 1512 * even though we just read a packet. In this case we 1513 * are not going to receive any more interrupts. We check for 1514 * this condition and read again until the fifo is not full. 1515 * We could simplify this test by not using epstatus(), but 1516 * rechecking the RX_STATUS register directly. This test could 1517 * result in unnecessary looping in cases where there is a new 1518 * packet but the fifo is not full, but it will not fix the 1519 * stuck behavior. 1520 * 1521 * Even with this improvement, we still get packet overrun errors 1522 * which are hurting performance. Maybe when I get some more time 1523 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1524 */ 1525 if (epstatus(sc)) { 1526 len = bus_space_read_2(iot, ioh, 1527 ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1528 /* Check if we are stuck and reset [see XXX comment] */ 1529 if (len & ERR_INCOMPLETE) { 1530 if (ifp->if_flags & IFF_DEBUG) 1531 printf("%s: adapter reset\n", 1532 sc->sc_dev.dv_xname); 1533 epreset(sc); 1534 return; 1535 } 1536 goto again; 1537 } 1538 1539 return; 1540 1541 abort: 1542 ep_discard_rxtop(iot, ioh); 1543 1544 } 1545 1546 struct mbuf * 1547 epget(sc, totlen) 1548 struct ep_softc *sc; 1549 int totlen; 1550 { 1551 bus_space_tag_t iot = sc->sc_iot; 1552 bus_space_handle_t ioh = sc->sc_ioh; 1553 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1554 struct mbuf *top, **mp, *m, *rv = NULL; 1555 bus_addr_t rxreg; 1556 int len, remaining; 1557 int sh; 1558 1559 m = sc->mb[sc->next_mb]; 1560 sc->mb[sc->next_mb] = 0; 1561 if (m == 0) { 1562 MGETHDR(m, M_DONTWAIT, MT_DATA); 1563 if (m == 0) 1564 return 0; 1565 } else { 1566 /* If the queue is no longer full, refill. */ 1567 if (sc->last_mb == sc->next_mb) 1568 timeout(epmbuffill, sc, 1); 1569 /* Convert one of our saved mbuf's. */ 1570 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1571 m->m_data = m->m_pktdat; 1572 m->m_flags = M_PKTHDR; 1573 } 1574 m->m_pkthdr.rcvif = ifp; 1575 m->m_pkthdr.len = totlen; 1576 len = MHLEN; 1577 top = 0; 1578 mp = ⊤ 1579 1580 /* 1581 * We read the packet at splhigh() so that an interrupt from another 1582 * device doesn't cause the card's buffer to overflow while we're 1583 * reading it. We may still lose packets at other times. 1584 */ 1585 sh = splhigh(); 1586 1587 rxreg = ep_w1_reg(sc, ELINK_W1_RX_PIO_RD_1); 1588 1589 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1590 /* 1591 * Prime the FIFO buffer counter (number of 16-bit 1592 * words about to be read from the FIFO). 1593 * 1594 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1595 * COUNTER IS NON-ZERO! 1596 */ 1597 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, totlen >> 1); 1598 } 1599 1600 while (totlen > 0) { 1601 if (top) { 1602 m = sc->mb[sc->next_mb]; 1603 sc->mb[sc->next_mb] = 0; 1604 if (m == 0) { 1605 MGET(m, M_DONTWAIT, MT_DATA); 1606 if (m == 0) { 1607 m_freem(top); 1608 goto out; 1609 } 1610 } else { 1611 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1612 } 1613 len = MLEN; 1614 } 1615 if (totlen >= MINCLSIZE) { 1616 MCLGET(m, M_DONTWAIT); 1617 if ((m->m_flags & M_EXT) == 0) { 1618 m_free(m); 1619 m_freem(top); 1620 goto out; 1621 } 1622 len = MCLBYTES; 1623 } 1624 if (top == 0) { 1625 /* align the struct ip header */ 1626 caddr_t newdata = (caddr_t) 1627 ALIGN(m->m_data + sizeof(struct ether_header)) 1628 - sizeof(struct ether_header); 1629 len -= newdata - m->m_data; 1630 m->m_data = newdata; 1631 } 1632 remaining = len = min(totlen, len); 1633 if (ELINK_IS_BUS_32(sc->bustype)) { 1634 u_long offset = mtod(m, u_long); 1635 /* 1636 * Read bytes up to the point where we are aligned. 1637 * (We can align to 4 bytes, rather than ALIGNBYTES, 1638 * here because we're later reading 4-byte chunks.) 1639 */ 1640 if ((remaining > 3) && (offset & 3)) { 1641 int count = (4 - (offset & 3)); 1642 bus_space_read_multi_1(iot, ioh, 1643 rxreg, (u_int8_t *) offset, count); 1644 offset += count; 1645 remaining -= count; 1646 } 1647 if (remaining > 3) { 1648 bus_space_read_multi_stream_4(iot, ioh, 1649 rxreg, (u_int32_t *) offset, 1650 remaining >> 2); 1651 offset += remaining & ~3; 1652 remaining &= 3; 1653 } 1654 if (remaining) { 1655 bus_space_read_multi_1(iot, ioh, 1656 rxreg, (u_int8_t *) offset, remaining); 1657 } 1658 } else { 1659 u_long offset = mtod(m, u_long); 1660 if ((remaining > 1) && (offset & 1)) { 1661 bus_space_read_multi_1(iot, ioh, 1662 rxreg, (u_int8_t *) offset, 1); 1663 remaining -= 1; 1664 offset += 1; 1665 } 1666 if (remaining > 1) { 1667 bus_space_read_multi_stream_2(iot, ioh, 1668 rxreg, (u_int16_t *) offset, 1669 remaining >> 1); 1670 offset += remaining & ~1; 1671 } 1672 if (remaining & 1) { 1673 bus_space_read_multi_1(iot, ioh, 1674 rxreg, (u_int8_t *) offset, remaining & 1); 1675 } 1676 } 1677 m->m_len = len; 1678 totlen -= len; 1679 *mp = m; 1680 mp = &m->m_next; 1681 } 1682 1683 rv = top; 1684 1685 ep_discard_rxtop(iot, ioh); 1686 1687 out: 1688 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 1689 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1690 splx(sh); 1691 1692 return rv; 1693 } 1694 1695 int 1696 epioctl(ifp, cmd, data) 1697 register struct ifnet *ifp; 1698 u_long cmd; 1699 caddr_t data; 1700 { 1701 struct ep_softc *sc = ifp->if_softc; 1702 struct ifaddr *ifa = (struct ifaddr *)data; 1703 struct ifreq *ifr = (struct ifreq *)data; 1704 int s, error = 0; 1705 1706 s = splnet(); 1707 1708 switch (cmd) { 1709 1710 case SIOCSIFADDR: 1711 if ((error = epenable(sc)) != 0) 1712 break; 1713 /* epinit is called just below */ 1714 ifp->if_flags |= IFF_UP; 1715 switch (ifa->ifa_addr->sa_family) { 1716 #ifdef INET 1717 case AF_INET: 1718 epinit(sc); 1719 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1720 break; 1721 #endif 1722 #ifdef NS 1723 case AF_NS: 1724 { 1725 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1726 1727 if (ns_nullhost(*ina)) 1728 ina->x_host = *(union ns_host *) 1729 LLADDR(ifp->if_sadl); 1730 else 1731 bcopy(ina->x_host.c_host, 1732 LLADDR(ifp->if_sadl), 1733 ifp->if_addrlen); 1734 /* Set new address. */ 1735 epinit(sc); 1736 break; 1737 } 1738 #endif 1739 default: 1740 epinit(sc); 1741 break; 1742 } 1743 break; 1744 1745 case SIOCSIFMEDIA: 1746 case SIOCGIFMEDIA: 1747 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1748 break; 1749 1750 case SIOCSIFFLAGS: 1751 if ((ifp->if_flags & IFF_UP) == 0 && 1752 (ifp->if_flags & IFF_RUNNING) != 0) { 1753 /* 1754 * If interface is marked down and it is running, then 1755 * stop it. 1756 */ 1757 epstop(sc); 1758 ifp->if_flags &= ~IFF_RUNNING; 1759 epdisable(sc); 1760 } else if ((ifp->if_flags & IFF_UP) != 0 && 1761 (ifp->if_flags & IFF_RUNNING) == 0) { 1762 /* 1763 * If interface is marked up and it is stopped, then 1764 * start it. 1765 */ 1766 if ((error = epenable(sc)) != 0) 1767 break; 1768 epinit(sc); 1769 } else if ((ifp->if_flags & IFF_UP) != 0) { 1770 /* 1771 * deal with flags changes: 1772 * IFF_MULTICAST, IFF_PROMISC. 1773 */ 1774 epsetfilter(sc); 1775 } 1776 break; 1777 1778 case SIOCADDMULTI: 1779 case SIOCDELMULTI: 1780 if (sc->enabled == 0) { 1781 error = EIO; 1782 break; 1783 } 1784 1785 error = (cmd == SIOCADDMULTI) ? 1786 ether_addmulti(ifr, &sc->sc_ethercom) : 1787 ether_delmulti(ifr, &sc->sc_ethercom); 1788 1789 if (error == ENETRESET) { 1790 /* 1791 * Multicast list has changed; set the hardware filter 1792 * accordingly. 1793 */ 1794 epreset(sc); 1795 error = 0; 1796 } 1797 break; 1798 1799 default: 1800 error = EINVAL; 1801 break; 1802 } 1803 1804 splx(s); 1805 return (error); 1806 } 1807 1808 void 1809 epreset(sc) 1810 struct ep_softc *sc; 1811 { 1812 int s; 1813 1814 s = splnet(); 1815 epstop(sc); 1816 epinit(sc); 1817 splx(s); 1818 } 1819 1820 void 1821 epwatchdog(ifp) 1822 struct ifnet *ifp; 1823 { 1824 struct ep_softc *sc = ifp->if_softc; 1825 1826 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1827 ++sc->sc_ethercom.ec_if.if_oerrors; 1828 1829 epreset(sc); 1830 } 1831 1832 void 1833 epstop(sc) 1834 register struct ep_softc *sc; 1835 { 1836 bus_space_tag_t iot = sc->sc_iot; 1837 bus_space_handle_t ioh = sc->sc_ioh; 1838 1839 if (sc->ep_flags & ELINK_FLAGS_MII) { 1840 /* Stop the one second clock. */ 1841 untimeout(ep_tick, sc); 1842 } 1843 1844 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 1845 /* 1846 * Clear the FIFO buffer count, thus halting 1847 * any currently-running transactions. 1848 */ 1849 GO_WINDOW(1); /* sanity */ 1850 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 1851 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1852 } 1853 1854 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1855 ep_discard_rxtop(iot, ioh); 1856 1857 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1858 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1859 1860 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 1861 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1862 1863 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1864 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK); 1865 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK); 1866 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RX_FILTER); 1867 1868 epmbufempty(sc); 1869 } 1870 1871 1872 /* 1873 * Before reboots, reset card completely. 1874 */ 1875 static void 1876 epshutdown(arg) 1877 void *arg; 1878 { 1879 register struct ep_softc *sc = arg; 1880 int s = splnet(); 1881 1882 if (sc->enabled) { 1883 epstop(sc); 1884 ep_reset_cmd(sc, ELINK_COMMAND, GLOBAL_RESET); 1885 sc->enabled = 0; 1886 } 1887 splx(s); 1888 } 1889 1890 /* 1891 * We get eeprom data from the id_port given an offset into the 1892 * eeprom. Basically; after the ID_sequence is sent to all of 1893 * the cards; they enter the ID_CMD state where they will accept 1894 * command requests. 0x80-0xbf loads the eeprom data. We then 1895 * read the port 16 times and with every read; the cards check 1896 * for contention (ie: if one card writes a 0 bit and another 1897 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1898 * each card compares the data on the bus; if there is a difference 1899 * then that card goes into ID_WAIT state again). In the meantime; 1900 * one bit of data is returned in the AX register which is conveniently 1901 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1902 * bit of data with each read. 1903 * 1904 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1905 */ 1906 u_int16_t 1907 epreadeeprom(iot, ioh, offset) 1908 bus_space_tag_t iot; 1909 bus_space_handle_t ioh; 1910 int offset; 1911 { 1912 u_int16_t data = 0; 1913 int i; 1914 1915 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1916 delay(1000); 1917 for (i = 0; i < 16; i++) 1918 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1919 return (data); 1920 } 1921 1922 static int 1923 epbusyeeprom(sc) 1924 struct ep_softc *sc; 1925 { 1926 bus_space_tag_t iot = sc->sc_iot; 1927 bus_space_handle_t ioh = sc->sc_ioh; 1928 int i = 100, j; 1929 1930 if (sc->bustype == ELINK_BUS_PCMCIA) { 1931 delay(1000); 1932 return 0; 1933 } 1934 1935 j = 0; /* bad GCC flow analysis */ 1936 while (i--) { 1937 j = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND); 1938 if (j & EEPROM_BUSY) 1939 delay(100); 1940 else 1941 break; 1942 } 1943 if (!i) { 1944 printf("\n%s: eeprom failed to come ready\n", 1945 sc->sc_dev.dv_xname); 1946 return (1); 1947 } 1948 if (j & EEPROM_TST_MODE) { 1949 /* XXX PnP mode? */ 1950 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1951 return (1); 1952 } 1953 return (0); 1954 } 1955 1956 void 1957 epmbuffill(v) 1958 void *v; 1959 { 1960 struct ep_softc *sc = v; 1961 struct mbuf *m; 1962 int s, i; 1963 1964 s = splnet(); 1965 i = sc->last_mb; 1966 do { 1967 if (sc->mb[i] == 0) { 1968 MGET(m, M_DONTWAIT, MT_DATA); 1969 if (m == 0) 1970 break; 1971 sc->mb[i] = m; 1972 } 1973 i = (i + 1) % MAX_MBS; 1974 } while (i != sc->next_mb); 1975 sc->last_mb = i; 1976 /* If the queue was not filled, try again. */ 1977 if (sc->last_mb != sc->next_mb) 1978 timeout(epmbuffill, sc, 1); 1979 splx(s); 1980 } 1981 1982 void 1983 epmbufempty(sc) 1984 struct ep_softc *sc; 1985 { 1986 int s, i; 1987 1988 s = splnet(); 1989 for (i = 0; i<MAX_MBS; i++) { 1990 if (sc->mb[i]) { 1991 m_freem(sc->mb[i]); 1992 sc->mb[i] = NULL; 1993 } 1994 } 1995 sc->last_mb = sc->next_mb = 0; 1996 untimeout(epmbuffill, sc); 1997 splx(s); 1998 } 1999 2000 int 2001 epenable(sc) 2002 struct ep_softc *sc; 2003 { 2004 2005 if (sc->enabled == 0 && sc->enable != NULL) { 2006 if ((*sc->enable)(sc) != 0) { 2007 printf("%s: device enable failed\n", 2008 sc->sc_dev.dv_xname); 2009 return (EIO); 2010 } 2011 } 2012 2013 sc->enabled = 1; 2014 return (0); 2015 } 2016 2017 void 2018 epdisable(sc) 2019 struct ep_softc *sc; 2020 { 2021 2022 if (sc->enabled != 0 && sc->disable != NULL) { 2023 (*sc->disable)(sc); 2024 sc->enabled = 0; 2025 } 2026 } 2027 2028 int 2029 ep_activate(self, act) 2030 struct device *self; 2031 enum devact act; 2032 { 2033 struct ep_softc *sc = (struct ep_softc *)self; 2034 int rv = 0, s; 2035 2036 s = splnet(); 2037 switch (act) { 2038 case DVACT_ACTIVATE: 2039 rv = EOPNOTSUPP; 2040 break; 2041 2042 case DVACT_DEACTIVATE: 2043 #ifdef notyet 2044 /* First, kill off the interface. */ 2045 if_detach(sc->sc_ethercom.ec_if); 2046 #endif 2047 2048 /* Now disable the interface. */ 2049 epdisable(sc); 2050 break; 2051 } 2052 splx(s); 2053 return (rv); 2054 } 2055 2056 void 2057 ep_mii_setbit(sc, bit) 2058 struct ep_softc *sc; 2059 u_int16_t bit; 2060 { 2061 u_int16_t val; 2062 2063 /* We assume we're already in Window 4 */ 2064 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2065 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2066 val | bit); 2067 } 2068 2069 void 2070 ep_mii_clrbit(sc, bit) 2071 struct ep_softc *sc; 2072 u_int16_t bit; 2073 { 2074 u_int16_t val; 2075 2076 /* We assume we're already in Window 4 */ 2077 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2078 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2079 val & ~bit); 2080 } 2081 2082 u_int16_t 2083 ep_mii_readbit(sc, bit) 2084 struct ep_softc *sc; 2085 u_int16_t bit; 2086 { 2087 2088 /* We assume we're already in Window 4 */ 2089 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT) & 2090 bit); 2091 } 2092 2093 void 2094 ep_mii_sync(sc) 2095 struct ep_softc *sc; 2096 { 2097 int i; 2098 2099 /* We assume we're already in Window 4 */ 2100 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2101 for (i = 0; i < 32; i++) { 2102 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2103 ep_mii_setbit(sc, PHYSMGMT_CLK); 2104 } 2105 } 2106 2107 void 2108 ep_mii_sendbits(sc, data, nbits) 2109 struct ep_softc *sc; 2110 u_int32_t data; 2111 int nbits; 2112 { 2113 int i; 2114 2115 /* We assume we're already in Window 4 */ 2116 ep_mii_setbit(sc, PHYSMGMT_DIR); 2117 for (i = 1 << (nbits - 1); i; i = i >> 1) { 2118 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2119 ep_mii_readbit(sc, PHYSMGMT_CLK); 2120 if (data & i) 2121 ep_mii_setbit(sc, PHYSMGMT_DATA); 2122 else 2123 ep_mii_clrbit(sc, PHYSMGMT_DATA); 2124 ep_mii_setbit(sc, PHYSMGMT_CLK); 2125 ep_mii_readbit(sc, PHYSMGMT_CLK); 2126 } 2127 } 2128 2129 int 2130 ep_mii_readreg(self, phy, reg) 2131 struct device *self; 2132 int phy, reg; 2133 { 2134 struct ep_softc *sc = (struct ep_softc *)self; 2135 int val = 0, i, err; 2136 2137 /* 2138 * Read the PHY register by manually driving the MII control lines. 2139 */ 2140 2141 GO_WINDOW(4); 2142 2143 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 0); 2144 2145 ep_mii_sync(sc); 2146 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2147 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 2148 ep_mii_sendbits(sc, phy, 5); 2149 ep_mii_sendbits(sc, reg, 5); 2150 2151 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2152 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2153 ep_mii_setbit(sc, PHYSMGMT_CLK); 2154 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2155 2156 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 2157 ep_mii_setbit(sc, PHYSMGMT_CLK); 2158 2159 /* Even if an error occurs, must still clock out the cycle. */ 2160 for (i = 0; i < 16; i++) { 2161 val <<= 1; 2162 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2163 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 2164 val |= 1; 2165 ep_mii_setbit(sc, PHYSMGMT_CLK); 2166 } 2167 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2168 ep_mii_setbit(sc, PHYSMGMT_CLK); 2169 2170 GO_WINDOW(1); /* back to operating window */ 2171 2172 return (err ? 0 : val); 2173 } 2174 2175 void 2176 ep_mii_writereg(self, phy, reg, val) 2177 struct device *self; 2178 int phy, reg, val; 2179 { 2180 struct ep_softc *sc = (struct ep_softc *)self; 2181 2182 /* 2183 * Write the PHY register by manually driving the MII control lines. 2184 */ 2185 2186 GO_WINDOW(4); 2187 2188 ep_mii_sync(sc); 2189 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2190 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2191 ep_mii_sendbits(sc, phy, 5); 2192 ep_mii_sendbits(sc, reg, 5); 2193 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2194 ep_mii_sendbits(sc, val, 16); 2195 2196 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2197 ep_mii_setbit(sc, PHYSMGMT_CLK); 2198 2199 GO_WINDOW(1); /* back to operating window */ 2200 } 2201 2202 void 2203 ep_statchg(self) 2204 struct device *self; 2205 { 2206 struct ep_softc *sc = (struct ep_softc *)self; 2207 bus_space_tag_t iot = sc->sc_iot; 2208 bus_space_handle_t ioh = sc->sc_ioh; 2209 int mctl; 2210 2211 /* XXX Update ifp->if_baudrate */ 2212 2213 GO_WINDOW(3); 2214 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 2215 if (sc->sc_mii.mii_media_active & IFM_FDX) 2216 mctl |= MAC_CONTROL_FDX; 2217 else 2218 mctl &= ~MAC_CONTROL_FDX; 2219 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 2220 GO_WINDOW(1); /* back to operating window */ 2221 } 2222
Indexes created Mon Sep 29 03:10:08 GMT 2025