elink3.c revision 1.59
1 /* $NetBSD: elink3.c,v 1.59 1999/10/11 17:48:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #ifdef DEBUG 124 int epdebug = 0; 125 #endif 126 127 /* 128 * XXX endian workaround for big-endian CPUs with pcmcia: 129 * if stream methods for bus_space_multi are not provided, define them 130 * using non-stream bus_space_{read,write}_multi_. 131 * Assumes host CPU is same endian-ness as bus. 132 */ 133 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 134 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 135 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 136 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 137 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 138 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 139 140 /* 141 * Structure to map media-present bits in boards to ifmedia codes and 142 * printable media names. Used for table-driven ifmedia initialization. 143 */ 144 struct ep_media { 145 int epm_mpbit; /* media present bit */ 146 const char *epm_name; /* name of medium */ 147 int epm_ifmedia; /* ifmedia word for medium */ 148 int epm_epmedia; /* ELINKMEDIA_* constant */ 149 }; 150 151 /* 152 * Media table for the Demon/Vortex/Boomerang chipsets. 153 * 154 * Note that MII on the Demon and Vortex (3c59x) indicates an external 155 * MII connector (for connecting an external PHY) ... I think. Treat 156 * it as `manual' on these chips. 157 * 158 * Any Boomerang (3c90x) chips with MII really do have an internal 159 * MII and real PHYs attached; no `native' media. 160 */ 161 struct ep_media ep_vortex_media[] = { 162 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 163 ELINKMEDIA_10BASE_T }, 164 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 165 ELINKMEDIA_10BASE_T }, 166 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 167 ELINKMEDIA_AUI }, 168 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 169 ELINKMEDIA_10BASE_2 }, 170 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 171 ELINKMEDIA_100BASE_TX }, 172 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 173 ELINKMEDIA_100BASE_TX }, 174 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 175 ELINKMEDIA_100BASE_FX }, 176 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 177 ELINKMEDIA_MII }, 178 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 179 ELINKMEDIA_100BASE_T4 }, 180 { 0, NULL, 0, 181 0 }, 182 }; 183 184 /* 185 * Media table for the older 3Com Etherlink III chipset, used 186 * in the 3c509, 3c579, and 3c589. 187 */ 188 struct ep_media ep_509_media[] = { 189 { ELINK_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 190 ELINKMEDIA_10BASE_T }, 191 { ELINK_W0_CC_AUI, "10base5", IFM_ETHER|IFM_10_5, 192 ELINKMEDIA_AUI }, 193 { ELINK_W0_CC_BNC, "10base2", IFM_ETHER|IFM_10_2, 194 ELINKMEDIA_10BASE_2 }, 195 { 0, NULL, 0, 196 0 }, 197 }; 198 199 void ep_internalconfig __P((struct ep_softc *sc)); 200 void ep_vortex_probemedia __P((struct ep_softc *sc)); 201 void ep_509_probemedia __P((struct ep_softc *sc)); 202 203 static void eptxstat __P((struct ep_softc *)); 204 static int epstatus __P((struct ep_softc *)); 205 void epinit __P((struct ep_softc *)); 206 int epioctl __P((struct ifnet *, u_long, caddr_t)); 207 void epstart __P((struct ifnet *)); 208 void epwatchdog __P((struct ifnet *)); 209 void epreset __P((struct ep_softc *)); 210 static void epshutdown __P((void *)); 211 void epread __P((struct ep_softc *)); 212 struct mbuf *epget __P((struct ep_softc *, int)); 213 void epmbuffill __P((void *)); 214 void epmbufempty __P((struct ep_softc *)); 215 void epsetfilter __P((struct ep_softc *)); 216 void ep_roadrunner_mii_enable __P((struct ep_softc *)); 217 void epsetmedia __P((struct ep_softc *)); 218 219 /* ifmedia callbacks */ 220 int ep_media_change __P((struct ifnet *ifp)); 221 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 222 223 /* MII callbacks */ 224 int ep_mii_readreg __P((struct device *, int, int)); 225 void ep_mii_writereg __P((struct device *, int, int, int)); 226 void ep_statchg __P((struct device *)); 227 228 void ep_tick __P((void *)); 229 230 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 231 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 232 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 233 void ep_mii_sync __P((struct ep_softc *)); 234 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 235 236 static int epbusyeeprom __P((struct ep_softc *)); 237 u_int16_t ep_read_eeprom __P((struct ep_softc *, u_int16_t)); 238 static inline void ep_reset_cmd __P((struct ep_softc *sc, 239 u_int cmd, u_int arg)); 240 static inline void ep_finish_reset __P((bus_space_tag_t, bus_space_handle_t)); 241 static inline void ep_discard_rxtop __P((bus_space_tag_t, bus_space_handle_t)); 242 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 243 244 /* 245 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 246 * Window 1 registers offset! 247 */ 248 static __inline int 249 ep_w1_reg(sc, reg) 250 struct ep_softc *sc; 251 int reg; 252 { 253 254 switch (sc->ep_chipset) { 255 case ELINK_CHIPSET_CORKSCREW: 256 return (reg + 0x10); 257 258 case ELINK_CHIPSET_ROADRUNNER: 259 switch (reg) { 260 case ELINK_W1_FREE_TX: 261 case ELINK_W1_RUNNER_RDCTL: 262 case ELINK_W1_RUNNER_WRCTL: 263 return (reg); 264 } 265 return (reg + 0x10); 266 } 267 268 return (reg); 269 } 270 271 /* 272 * Wait for any pending reset to complete. 273 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 274 * but older hardware doesn't implement it and we must delay. 275 */ 276 static inline void 277 ep_finish_reset(iot, ioh) 278 bus_space_tag_t iot; 279 bus_space_handle_t ioh; 280 281 { 282 int i; 283 284 for (i = 0; i < 10000; i++) { 285 if ((bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) == 0) 286 break; 287 DELAY(10); 288 } 289 } 290 291 /* 292 * Issue a (reset) command, and be sure it has completed. 293 * Used for global reset, TX_RESET, RX_RESET. 294 */ 295 static inline void 296 ep_reset_cmd(sc, cmd, arg) 297 struct ep_softc *sc; 298 u_int cmd, arg; 299 { 300 register bus_space_tag_t iot = sc->sc_iot; 301 register bus_space_handle_t ioh = sc->sc_ioh; 302 303 bus_space_write_2(iot, ioh, cmd, arg); 304 ep_finish_reset(iot, ioh); 305 } 306 307 308 static inline void 309 ep_discard_rxtop(iot, ioh) 310 register bus_space_tag_t iot; 311 register bus_space_handle_t ioh; 312 { 313 int i; 314 315 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 316 317 /* 318 * Spin for about 1 msec, to avoid forcing a DELAY() between 319 * every received packet (adding latency and limiting pkt-recv rate). 320 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 321 * is about right. 322 */ 323 for (i = 0; i < 8000; i++) { 324 if ((bus_space_read_2(iot, ioh, ELINK_STATUS) & S_COMMAND_IN_PROGRESS) == 0) 325 return; 326 } 327 328 /* Didn't complete in a hurry. Do DELAY()s. */ 329 ep_finish_reset(iot, ioh); 330 } 331 332 /* 333 * Back-end attach and configure. 334 */ 335 void 336 epconfig(sc, chipset, enaddr) 337 struct ep_softc *sc; 338 u_short chipset; 339 u_int8_t *enaddr; 340 { 341 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 342 bus_space_tag_t iot = sc->sc_iot; 343 bus_space_handle_t ioh = sc->sc_ioh; 344 u_int16_t i; 345 u_int8_t myla[6]; 346 347 sc->ep_chipset = chipset; 348 349 /* 350 * We could have been groveling around in other register 351 * windows in the front-end; make sure we're in window 0 352 * to read the EEPROM. 353 */ 354 GO_WINDOW(0); 355 356 if (enaddr == NULL) { 357 /* 358 * Read the station address from the eeprom. 359 */ 360 for (i = 0; i < 3; i++) { 361 u_int16_t x = ep_read_eeprom(sc, i); 362 myla[(i << 1)] = x >> 8; 363 myla[(i << 1) + 1] = x; 364 } 365 enaddr = myla; 366 } 367 368 /* 369 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 370 * allow FDDI-sized (4500) byte packets. Commands only take an 371 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 372 * packet length. 373 * Commands to these cards implicitly upshift a packet size 374 * or threshold by 2 bits. 375 * To detect cards with large-packet support, we probe by setting 376 * the transmit threshold register, then change windows and 377 * read back the threshold register directly, and see if the 378 * threshold value was shifted or not. 379 */ 380 bus_space_write_2(iot, ioh, ELINK_COMMAND, 381 SET_TX_AVAIL_THRESH | ELINK_LARGEWIN_PROBE ); 382 GO_WINDOW(5); 383 i = bus_space_read_2(iot, ioh, ELINK_W5_TX_AVAIL_THRESH); 384 GO_WINDOW(1); 385 switch (i) { 386 case ELINK_LARGEWIN_PROBE: 387 case (ELINK_LARGEWIN_PROBE & ELINK_LARGEWIN_MASK): 388 sc->ep_pktlenshift = 0; 389 break; 390 391 case (ELINK_LARGEWIN_PROBE << 2): 392 sc->ep_pktlenshift = 2; 393 break; 394 395 default: 396 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 397 "Interface disabled\n", 398 sc->sc_dev.dv_xname, ELINK_LARGEWIN_PROBE, (int) i); 399 return; 400 } 401 402 /* 403 * Ensure Tx-available interrupts are enabled for 404 * start the interface. 405 * XXX should be in epinit()? 406 */ 407 bus_space_write_2(iot, ioh, ELINK_COMMAND, 408 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 409 410 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 411 ifp->if_softc = sc; 412 ifp->if_start = epstart; 413 ifp->if_ioctl = epioctl; 414 ifp->if_watchdog = epwatchdog; 415 ifp->if_flags = 416 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 417 418 if_attach(ifp); 419 ether_ifattach(ifp, enaddr); 420 421 /* 422 * Finish configuration: 423 * determine chipset if the front-end couldn't do so, 424 * show board details, set media. 425 */ 426 427 /* 428 * Print RAM size. We also print the Ethernet address in here. 429 * It's extracted from the ifp, so we have to make sure it's 430 * been attached first. 431 */ 432 ep_internalconfig(sc); 433 GO_WINDOW(0); 434 435 /* 436 * Display some additional information, if pertinent. 437 */ 438 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 439 printf("%s: RoadRunner FIFO buffer enabled\n", 440 sc->sc_dev.dv_xname); 441 442 /* 443 * Initialize our media structures and MII info. We'll 444 * probe the MII if we discover that we have one. 445 */ 446 sc->sc_mii.mii_ifp = ifp; 447 sc->sc_mii.mii_readreg = ep_mii_readreg; 448 sc->sc_mii.mii_writereg = ep_mii_writereg; 449 sc->sc_mii.mii_statchg = ep_statchg; 450 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 451 ep_media_status); 452 453 /* 454 * Now, determine which media we have. 455 */ 456 switch (sc->ep_chipset) { 457 case ELINK_CHIPSET_ROADRUNNER: 458 if (sc->ep_flags & ELINK_FLAGS_MII) { 459 ep_roadrunner_mii_enable(sc); 460 GO_WINDOW(0); 461 } 462 /* FALLTHROUGH */ 463 464 case ELINK_CHIPSET_BOOMERANG: 465 /* 466 * If the device has MII, probe it. We won't be using 467 * any `native' media in this case, only PHYs. If 468 * we don't, just treat the Boomerang like the Vortex. 469 */ 470 if (sc->ep_flags & ELINK_FLAGS_MII) { 471 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 472 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 473 ifmedia_add(&sc->sc_mii.mii_media, 474 IFM_ETHER|IFM_NONE, 0, NULL); 475 ifmedia_set(&sc->sc_mii.mii_media, 476 IFM_ETHER|IFM_NONE); 477 } else { 478 ifmedia_set(&sc->sc_mii.mii_media, 479 IFM_ETHER|IFM_AUTO); 480 } 481 break; 482 } 483 /* FALLTHROUGH */ 484 485 case ELINK_CHIPSET_VORTEX: 486 ep_vortex_probemedia(sc); 487 break; 488 489 default: 490 ep_509_probemedia(sc); 491 break; 492 } 493 494 GO_WINDOW(1); /* Window 1 is operating window */ 495 496 #if NBPFILTER > 0 497 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 498 sizeof(struct ether_header)); 499 #endif 500 501 #if NRND > 0 502 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 503 RND_TYPE_NET, 0); 504 #endif 505 506 sc->tx_start_thresh = 20; /* probably a good starting point. */ 507 508 /* Establish callback to reset card when we reboot. */ 509 shutdownhook_establish(epshutdown, sc); 510 511 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 512 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 513 } 514 515 516 /* 517 * Show interface-model-independent info from window 3 518 * internal-configuration register. 519 */ 520 void 521 ep_internalconfig(sc) 522 struct ep_softc *sc; 523 { 524 bus_space_tag_t iot = sc->sc_iot; 525 bus_space_handle_t ioh = sc->sc_ioh; 526 527 u_int config0; 528 u_int config1; 529 530 int ram_size, ram_width, ram_speed, rom_size, ram_split; 531 /* 532 * NVRAM buffer Rx:Tx config names for busmastering cards 533 * (Demon, Vortex, and later). 534 */ 535 const char *onboard_ram_config[] = { 536 "5:3", "3:1", "1:1", "3:5" }; 537 538 GO_WINDOW(3); 539 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 540 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 541 GO_WINDOW(0); 542 543 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 544 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 545 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 546 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 547 548 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 549 550 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 551 sc->sc_dev.dv_xname, 552 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 553 8 << ram_size, 554 (ram_width) ? "word" : "byte", 555 onboard_ram_config[ram_split]); 556 } 557 558 559 /* 560 * Find supported media on 3c509-generation hardware that doesn't have 561 * a "reset_options" register in window 3. 562 * Use the config_cntrl register in window 0 instead. 563 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 564 * that implement CONFIG_CTRL. We don't have a good way to set the 565 * default active mediuim; punt to ifconfig instead. 566 */ 567 void 568 ep_509_probemedia(sc) 569 struct ep_softc *sc; 570 { 571 bus_space_tag_t iot = sc->sc_iot; 572 bus_space_handle_t ioh = sc->sc_ioh; 573 struct ifmedia *ifm = &sc->sc_mii.mii_media; 574 u_int16_t ep_w0_config, port; 575 struct ep_media *epm; 576 const char *sep = "", *defmedianame = NULL; 577 int defmedia = 0; 578 579 GO_WINDOW(0); 580 ep_w0_config = bus_space_read_2(iot, ioh, ELINK_W0_CONFIG_CTRL); 581 582 printf("%s: ", sc->sc_dev.dv_xname); 583 584 /* Sanity check that there are any media! */ 585 if ((ep_w0_config & ELINK_W0_CC_MEDIAMASK) == 0) { 586 printf("no media present!\n"); 587 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 588 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 589 return; 590 } 591 592 /* 593 * Get the default media from the EEPROM. 594 */ 595 port = ep_read_eeprom(sc, EEPROM_ADDR_CFG) >> 14; 596 597 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 598 599 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 600 if (ep_w0_config & epm->epm_mpbit) { 601 /* 602 * This simple test works because 509 chipsets 603 * don't do full-duplex. 604 */ 605 if (epm->epm_epmedia == port || defmedia == 0) { 606 defmedia = epm->epm_ifmedia; 607 defmedianame = epm->epm_name; 608 } 609 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 610 NULL); 611 PRINT(epm->epm_name); 612 } 613 } 614 615 #undef PRINT 616 617 #ifdef DIAGNOSTIC 618 if (defmedia == 0) 619 panic("ep_509_probemedia: impossible"); 620 #endif 621 622 printf(" (default %s)\n", defmedianame); 623 ifmedia_set(ifm, defmedia); 624 } 625 626 /* 627 * Find media present on large-packet-capable elink3 devices. 628 * Show onboard configuration of large-packet-capable elink3 devices 629 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 630 * Use media and card-version info in window 3 instead. 631 */ 632 void 633 ep_vortex_probemedia(sc) 634 struct ep_softc *sc; 635 { 636 bus_space_tag_t iot = sc->sc_iot; 637 bus_space_handle_t ioh = sc->sc_ioh; 638 struct ifmedia *ifm = &sc->sc_mii.mii_media; 639 struct ep_media *epm; 640 u_int config1; 641 int reset_options; 642 int default_media; /* 3-bit encoding of default (EEPROM) media */ 643 int defmedia = 0; 644 const char *sep = "", *defmedianame = NULL; 645 646 GO_WINDOW(3); 647 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 648 reset_options = (int)bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 649 GO_WINDOW(0); 650 651 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 652 653 printf("%s: ", sc->sc_dev.dv_xname); 654 655 /* Sanity check that there are any media! */ 656 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 657 printf("no media present!\n"); 658 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 659 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 660 return; 661 } 662 663 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 664 665 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 666 if (reset_options & epm->epm_mpbit) { 667 /* 668 * Default media is a little more complicated 669 * on the Vortex. We support full-duplex which 670 * uses the same reset options bit. 671 * 672 * XXX Check EEPROM for default to FDX? 673 */ 674 if (epm->epm_epmedia == default_media) { 675 if ((epm->epm_ifmedia & IFM_FDX) == 0) { 676 defmedia = epm->epm_ifmedia; 677 defmedianame = epm->epm_name; 678 } 679 } else if (defmedia == 0) { 680 defmedia = epm->epm_ifmedia; 681 defmedianame = epm->epm_name; 682 } 683 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 684 NULL); 685 PRINT(epm->epm_name); 686 } 687 } 688 689 #undef PRINT 690 691 #ifdef DIAGNOSTIC 692 if (defmedia == 0) 693 panic("ep_vortex_probemedia: impossible"); 694 #endif 695 696 printf(" (default %s)\n", defmedianame); 697 ifmedia_set(ifm, defmedia); 698 } 699 700 /* 701 * One second timer, used to tick the MII. 702 */ 703 void 704 ep_tick(arg) 705 void *arg; 706 { 707 struct ep_softc *sc = arg; 708 int s; 709 710 #ifdef DIAGNOSTIC 711 if ((sc->ep_flags & ELINK_FLAGS_MII) == 0) 712 panic("ep_tick"); 713 #endif 714 715 s = splnet(); 716 mii_tick(&sc->sc_mii); 717 splx(s); 718 719 timeout(ep_tick, sc, hz); 720 } 721 722 /* 723 * Bring device up. 724 * 725 * The order in here seems important. Otherwise we may not receive 726 * interrupts. ?! 727 */ 728 void 729 epinit(sc) 730 register struct ep_softc *sc; 731 { 732 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 733 bus_space_tag_t iot = sc->sc_iot; 734 bus_space_handle_t ioh = sc->sc_ioh; 735 int i; 736 737 /* Make sure any pending reset has completed before touching board. */ 738 ep_finish_reset(iot, ioh); 739 740 741 if (sc->bustype != ELINK_BUS_PCI) { 742 GO_WINDOW(0); 743 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, 0); 744 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); 745 } 746 747 if (sc->bustype == ELINK_BUS_PCMCIA) { 748 bus_space_write_2(iot, ioh, ELINK_W0_RESOURCE_CFG, 0x3f00); 749 } 750 751 GO_WINDOW(2); 752 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 753 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 754 LLADDR(ifp->if_sadl)[i]); 755 756 /* 757 * Reset the station-address receive filter. 758 * A bug workaround for busmastering (Vortex, Demon) cards. 759 */ 760 for (i = 0; i < 6; i++) 761 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 762 763 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 764 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 765 766 GO_WINDOW(1); /* Window 1 is operating window */ 767 for (i = 0; i < 31; i++) 768 bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS)); 769 770 /* Set threshhold for for Tx-space avaiable interrupt. */ 771 bus_space_write_2(iot, ioh, ELINK_COMMAND, 772 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 773 774 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 775 /* 776 * Enable options in the PCMCIA LAN COR register, via 777 * RoadRunner Window 1. 778 * 779 * XXX MAGIC CONSTANTS! 780 */ 781 u_int16_t cor; 782 783 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, (1 << 11)); 784 785 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 786 if (sc->ep_flags & ELINK_FLAGS_USESHAREDMEM) 787 cor |= 0x10; 788 if (sc->ep_flags & ELINK_FLAGS_FORCENOWAIT) 789 cor |= 0x20; 790 bus_space_write_2(iot, ioh, 0, cor); 791 792 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 793 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 794 795 if (sc->ep_flags & ELINK_FLAGS_MII) { 796 ep_roadrunner_mii_enable(sc); 797 GO_WINDOW(1); 798 } 799 } 800 801 /* Enable interrupts. */ 802 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 803 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 804 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | 805 S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL); 806 807 /* 808 * Attempt to get rid of any stray interrupts that occured during 809 * configuration. On the i386 this isn't possible because one may 810 * already be queued. However, a single stray interrupt is 811 * unimportant. 812 */ 813 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 814 815 epsetfilter(sc); 816 epsetmedia(sc); 817 818 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 819 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 820 821 epmbuffill(sc); 822 823 /* Interface is now `running', with no output active. */ 824 ifp->if_flags |= IFF_RUNNING; 825 ifp->if_flags &= ~IFF_OACTIVE; 826 827 if (sc->ep_flags & ELINK_FLAGS_MII) { 828 /* Start the one second clock. */ 829 timeout(ep_tick, sc, hz); 830 } 831 832 /* Attempt to start output, if any. */ 833 epstart(ifp); 834 } 835 836 837 /* 838 * Set multicast receive filter. 839 * elink3 hardware has no selective multicast filter in hardware. 840 * Enable reception of all multicasts and filter in software. 841 */ 842 void 843 epsetfilter(sc) 844 register struct ep_softc *sc; 845 { 846 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 847 848 GO_WINDOW(1); /* Window 1 is operating window */ 849 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, SET_RX_FILTER | 850 FIL_INDIVIDUAL | FIL_BRDCST | 851 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) | 852 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 )); 853 } 854 855 int 856 ep_media_change(ifp) 857 struct ifnet *ifp; 858 { 859 register struct ep_softc *sc = ifp->if_softc; 860 861 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 862 epreset(sc); 863 864 return (0); 865 } 866 867 /* 868 * Reset and enable the MII on the RoadRunner. 869 */ 870 void 871 ep_roadrunner_mii_enable(sc) 872 struct ep_softc *sc; 873 { 874 bus_space_tag_t iot = sc->sc_iot; 875 bus_space_handle_t ioh = sc->sc_ioh; 876 877 GO_WINDOW(3); 878 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 879 ELINK_PCI_100BASE_MII|ELINK_RUNNER_ENABLE_MII); 880 delay(1000); 881 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 882 ELINK_PCI_100BASE_MII|ELINK_RUNNER_MII_RESET| 883 ELINK_RUNNER_ENABLE_MII); 884 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 885 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 886 delay(1000); 887 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 888 ELINK_PCI_100BASE_MII|ELINK_RUNNER_ENABLE_MII); 889 } 890 891 /* 892 * Set the card to use the specified media. 893 */ 894 void 895 epsetmedia(sc) 896 struct ep_softc *sc; 897 { 898 bus_space_tag_t iot = sc->sc_iot; 899 bus_space_handle_t ioh = sc->sc_ioh; 900 901 /* Turn everything off. First turn off linkbeat and UTP. */ 902 GO_WINDOW(4); 903 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0x0); 904 905 /* Turn off coax */ 906 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 907 delay(1000); 908 909 /* 910 * If the device has MII, select it, and then tell the 911 * PHY which media to use. 912 */ 913 if (sc->ep_flags & ELINK_FLAGS_MII) { 914 int config0, config1; 915 916 GO_WINDOW(3); 917 918 #if 0 919 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 920 int resopt; 921 922 resopt = bus_space_read_2(iot, ioh, 923 ELINK_W3_RESET_OPTIONS); 924 bus_space_write_2(iot, ioh, 925 ELINK_W3_RESET_OPTIONS, resopt|ELINK_RUNNER_ENABLE_MII); 926 } 927 #endif 928 929 config0 = (u_int)bus_space_read_2(iot, ioh, 930 ELINK_W3_INTERNAL_CONFIG); 931 config1 = (u_int)bus_space_read_2(iot, ioh, 932 ELINK_W3_INTERNAL_CONFIG + 2); 933 934 config1 = config1 & ~CONFIG_MEDIAMASK; 935 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 936 937 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 938 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 939 GO_WINDOW(1); /* back to operating window */ 940 941 mii_mediachg(&sc->sc_mii); 942 return; 943 } 944 945 /* 946 * Now turn on the selected media/transceiver. 947 */ 948 GO_WINDOW(4); 949 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 950 case IFM_10_T: 951 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 952 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 953 break; 954 955 case IFM_10_2: 956 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 957 DELAY(1000); /* 50ms not enmough? */ 958 break; 959 960 case IFM_100_TX: 961 case IFM_100_FX: 962 case IFM_100_T4: /* XXX check documentation */ 963 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 964 LINKBEAT_ENABLE); 965 DELAY(1000); /* not strictly necessary? */ 966 break; 967 968 case IFM_10_5: 969 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 970 SQE_ENABLE); 971 DELAY(1000); /* not strictly necessary? */ 972 break; 973 974 case IFM_MANUAL: 975 /* 976 * Nothing to do here; we are actually enabling the 977 * external PHY on the MII port. 978 */ 979 break; 980 981 case IFM_NONE: 982 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 983 return; 984 985 default: 986 panic("epsetmedia: impossible"); 987 } 988 989 /* 990 * Tell the chip which port to use. 991 */ 992 switch (sc->ep_chipset) { 993 case ELINK_CHIPSET_VORTEX: 994 case ELINK_CHIPSET_BOOMERANG: 995 { 996 int mctl, config0, config1; 997 998 GO_WINDOW(3); 999 config0 = (u_int)bus_space_read_2(iot, ioh, 1000 ELINK_W3_INTERNAL_CONFIG); 1001 config1 = (u_int)bus_space_read_2(iot, ioh, 1002 ELINK_W3_INTERNAL_CONFIG + 2); 1003 1004 config1 = config1 & ~CONFIG_MEDIAMASK; 1005 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 1006 CONFIG_MEDIAMASK_SHIFT); 1007 1008 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 1009 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, 1010 config1); 1011 1012 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1013 if (sc->sc_mii.mii_media.ifm_cur->ifm_media & IFM_FDX) 1014 mctl |= MAC_CONTROL_FDX; 1015 else 1016 mctl &= ~MAC_CONTROL_FDX; 1017 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1018 break; 1019 } 1020 default: 1021 { 1022 int w0_addr_cfg; 1023 1024 GO_WINDOW(0); 1025 w0_addr_cfg = bus_space_read_2(iot, ioh, ELINK_W0_ADDRESS_CFG); 1026 w0_addr_cfg &= 0x3fff; 1027 bus_space_write_2(iot, ioh, ELINK_W0_ADDRESS_CFG, w0_addr_cfg | 1028 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 1029 DELAY(1000); 1030 break; 1031 } 1032 } 1033 1034 GO_WINDOW(1); /* Window 1 is operating window */ 1035 } 1036 1037 /* 1038 * Get currently-selected media from card. 1039 * (if_media callback, may be called before interface is brought up). 1040 */ 1041 void 1042 ep_media_status(ifp, req) 1043 struct ifnet *ifp; 1044 struct ifmediareq *req; 1045 { 1046 register struct ep_softc *sc = ifp->if_softc; 1047 bus_space_tag_t iot = sc->sc_iot; 1048 bus_space_handle_t ioh = sc->sc_ioh; 1049 1050 if (sc->enabled == 0) { 1051 req->ifm_active = IFM_ETHER|IFM_NONE; 1052 req->ifm_status = 0; 1053 return; 1054 } 1055 1056 /* 1057 * If we have MII, go ask the PHY what's going on. 1058 */ 1059 if (sc->ep_flags & ELINK_FLAGS_MII) { 1060 mii_pollstat(&sc->sc_mii); 1061 req->ifm_active = sc->sc_mii.mii_media_active; 1062 req->ifm_status = sc->sc_mii.mii_media_status; 1063 return; 1064 } 1065 1066 /* 1067 * Ok, at this point we claim that our active media is 1068 * the currently selected media. We'll update our status 1069 * if our chipset allows us to detect link. 1070 */ 1071 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1072 req->ifm_status = 0; 1073 1074 switch (sc->ep_chipset) { 1075 case ELINK_CHIPSET_VORTEX: 1076 case ELINK_CHIPSET_BOOMERANG: 1077 GO_WINDOW(4); 1078 req->ifm_status = IFM_AVALID; 1079 if (bus_space_read_2(iot, ioh, ELINK_W4_MEDIA_TYPE) & 1080 LINKBEAT_DETECT) 1081 req->ifm_status |= IFM_ACTIVE; 1082 GO_WINDOW(1); /* back to operating window */ 1083 break; 1084 } 1085 } 1086 1087 1088 1089 /* 1090 * Start outputting on the interface. 1091 * Always called as splnet(). 1092 */ 1093 void 1094 epstart(ifp) 1095 struct ifnet *ifp; 1096 { 1097 register struct ep_softc *sc = ifp->if_softc; 1098 bus_space_tag_t iot = sc->sc_iot; 1099 bus_space_handle_t ioh = sc->sc_ioh; 1100 struct mbuf *m, *m0; 1101 int sh, len, pad; 1102 bus_addr_t txreg; 1103 1104 /* Don't transmit if interface is busy or not running */ 1105 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1106 return; 1107 1108 startagain: 1109 /* Sneak a peek at the next packet */ 1110 m0 = ifp->if_snd.ifq_head; 1111 if (m0 == 0) 1112 return; 1113 1114 /* We need to use m->m_pkthdr.len, so require the header */ 1115 if ((m0->m_flags & M_PKTHDR) == 0) 1116 panic("epstart: no header mbuf"); 1117 len = m0->m_pkthdr.len; 1118 1119 pad = (4 - len) & 3; 1120 1121 /* 1122 * The 3c509 automatically pads short packets to minimum ethernet 1123 * length, but we drop packets that are too large. Perhaps we should 1124 * truncate them instead? 1125 */ 1126 if (len + pad > ETHER_MAX_LEN) { 1127 /* packet is obviously too large: toss it */ 1128 ++ifp->if_oerrors; 1129 IF_DEQUEUE(&ifp->if_snd, m0); 1130 m_freem(m0); 1131 goto readcheck; 1132 } 1133 1134 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_FREE_TX)) < 1135 len + pad + 4) { 1136 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1137 SET_TX_AVAIL_THRESH | 1138 ((len + pad + 4) >> sc->ep_pktlenshift)); 1139 /* not enough room in FIFO */ 1140 ifp->if_flags |= IFF_OACTIVE; 1141 return; 1142 } else { 1143 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1144 SET_TX_AVAIL_THRESH | ELINK_THRESH_DISABLE ); 1145 } 1146 1147 IF_DEQUEUE(&ifp->if_snd, m0); 1148 if (m0 == 0) /* not really needed */ 1149 return; 1150 1151 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_TX_START_THRESH | 1152 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/) ); 1153 1154 #if NBPFILTER > 0 1155 if (ifp->if_bpf) 1156 bpf_mtap(ifp->if_bpf, m0); 1157 #endif 1158 1159 /* 1160 * Do the output at splhigh() so that an interrupt from another device 1161 * won't cause a FIFO underrun. 1162 */ 1163 sh = splhigh(); 1164 1165 txreg = ep_w1_reg(sc, ELINK_W1_TX_PIO_WR_1); 1166 1167 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1168 /* 1169 * Prime the FIFO buffer counter (number of 16-bit 1170 * words about to be written to the FIFO). 1171 * 1172 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1173 * COUNTER IS NON-ZERO! 1174 */ 1175 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 1176 (len + pad) >> 1); 1177 } 1178 1179 bus_space_write_2(iot, ioh, txreg, len); 1180 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1181 if (ELINK_IS_BUS_32(sc->bustype)) { 1182 for (m = m0; m; ) { 1183 if (m->m_len > 3) { 1184 /* align our reads from core */ 1185 if (mtod(m, u_long) & 3) { 1186 u_long count = 1187 4 - (mtod(m, u_long) & 3); 1188 bus_space_write_multi_1(iot, ioh, 1189 txreg, mtod(m, u_int8_t *), count); 1190 m->m_data = 1191 (void *)(mtod(m, u_long) + count); 1192 m->m_len -= count; 1193 } 1194 bus_space_write_multi_stream_4(iot, ioh, 1195 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1196 m->m_data = (void *)(mtod(m, u_long) + 1197 (u_long)(m->m_len & ~3)); 1198 m->m_len -= m->m_len & ~3; 1199 } 1200 if (m->m_len) { 1201 bus_space_write_multi_1(iot, ioh, 1202 txreg, mtod(m, u_int8_t *), m->m_len); 1203 } 1204 MFREE(m, m0); 1205 m = m0; 1206 } 1207 } else { 1208 for (m = m0; m; ) { 1209 if (m->m_len > 1) { 1210 if (mtod(m, u_long) & 1) { 1211 bus_space_write_1(iot, ioh, 1212 txreg, *(mtod(m, u_int8_t *))); 1213 m->m_data = 1214 (void *)(mtod(m, u_long) + 1); 1215 m->m_len -= 1; 1216 } 1217 bus_space_write_multi_stream_2(iot, ioh, 1218 txreg, mtod(m, u_int16_t *), 1219 m->m_len >> 1); 1220 } 1221 if (m->m_len & 1) { 1222 bus_space_write_1(iot, ioh, txreg, 1223 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1224 } 1225 MFREE(m, m0); 1226 m = m0; 1227 } 1228 } 1229 while (pad--) 1230 bus_space_write_1(iot, ioh, txreg, 0); 1231 1232 splx(sh); 1233 1234 ++ifp->if_opackets; 1235 1236 readcheck: 1237 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)) & 1238 ERR_INCOMPLETE) == 0) { 1239 /* We received a complete packet. */ 1240 u_int16_t status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1241 1242 if ((status & S_INTR_LATCH) == 0) { 1243 /* 1244 * No interrupt, read the packet and continue 1245 * Is this supposed to happen? Is my motherboard 1246 * completely busted? 1247 */ 1248 epread(sc); 1249 } else { 1250 /* Got an interrupt, return so that it gets serviced. */ 1251 return; 1252 } 1253 } else { 1254 /* Check if we are stuck and reset [see XXX comment] */ 1255 if (epstatus(sc)) { 1256 if (ifp->if_flags & IFF_DEBUG) 1257 printf("%s: adapter reset\n", 1258 sc->sc_dev.dv_xname); 1259 epreset(sc); 1260 } 1261 } 1262 1263 goto startagain; 1264 } 1265 1266 1267 /* 1268 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1269 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1270 * We detect this situation and we reset the adapter. 1271 * It happens at times when there is a lot of broadcast traffic 1272 * on the cable (once in a blue moon). 1273 */ 1274 static int 1275 epstatus(sc) 1276 register struct ep_softc *sc; 1277 { 1278 bus_space_tag_t iot = sc->sc_iot; 1279 bus_space_handle_t ioh = sc->sc_ioh; 1280 u_int16_t fifost; 1281 1282 /* 1283 * Check the FIFO status and act accordingly 1284 */ 1285 GO_WINDOW(4); 1286 fifost = bus_space_read_2(iot, ioh, ELINK_W4_FIFO_DIAG); 1287 GO_WINDOW(1); 1288 1289 if (fifost & FIFOS_RX_UNDERRUN) { 1290 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1291 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1292 epreset(sc); 1293 return 0; 1294 } 1295 1296 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1297 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1298 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1299 return 1; 1300 } 1301 1302 if (fifost & FIFOS_RX_OVERRUN) { 1303 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1304 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1305 return 1; 1306 } 1307 1308 if (fifost & FIFOS_TX_OVERRUN) { 1309 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1310 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1311 epreset(sc); 1312 return 0; 1313 } 1314 1315 return 0; 1316 } 1317 1318 1319 static void 1320 eptxstat(sc) 1321 register struct ep_softc *sc; 1322 { 1323 bus_space_tag_t iot = sc->sc_iot; 1324 bus_space_handle_t ioh = sc->sc_ioh; 1325 int i; 1326 1327 /* 1328 * We need to read+write TX_STATUS until we get a 0 status 1329 * in order to turn off the interrupt flag. 1330 */ 1331 while ((i = bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS))) 1332 & TXS_COMPLETE) { 1333 bus_space_write_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS), 1334 0x0); 1335 1336 if (i & TXS_JABBER) { 1337 ++sc->sc_ethercom.ec_if.if_oerrors; 1338 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1339 printf("%s: jabber (%x)\n", 1340 sc->sc_dev.dv_xname, i); 1341 #if 1 1342 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1343 #else 1344 epreset(sc); 1345 #endif 1346 } else if (i & TXS_UNDERRUN) { 1347 ++sc->sc_ethercom.ec_if.if_oerrors; 1348 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1349 printf("%s: fifo underrun (%x) @%d\n", 1350 sc->sc_dev.dv_xname, i, 1351 sc->tx_start_thresh); 1352 if (sc->tx_succ_ok < 100) 1353 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1354 sc->tx_start_thresh + 20); 1355 sc->tx_succ_ok = 0; 1356 #if 1 1357 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1358 #else 1359 epreset(sc); 1360 #endif 1361 } else if (i & TXS_MAX_COLLISION) { 1362 ++sc->sc_ethercom.ec_if.if_collisions; 1363 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 1364 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1365 } else 1366 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1367 } 1368 } 1369 1370 int 1371 epintr(arg) 1372 void *arg; 1373 { 1374 register struct ep_softc *sc = arg; 1375 bus_space_tag_t iot = sc->sc_iot; 1376 bus_space_handle_t ioh = sc->sc_ioh; 1377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1378 u_int16_t status; 1379 int ret = 0; 1380 int addrandom = 0; 1381 1382 if (sc->enabled == 0) 1383 return (0); 1384 1385 for (;;) { 1386 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1387 1388 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1389 1390 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1391 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1392 if ((status & S_INTR_LATCH) == 0) { 1393 #if 0 1394 printf("%s: intr latch cleared\n", 1395 sc->sc_dev.dv_xname); 1396 #endif 1397 break; 1398 } 1399 } 1400 1401 ret = 1; 1402 1403 /* 1404 * Acknowledge any interrupts. It's important that we do this 1405 * first, since there would otherwise be a race condition. 1406 * Due to the i386 interrupt queueing, we may get spurious 1407 * interrupts occasionally. 1408 */ 1409 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1410 (status & (C_INTR_LATCH | 1411 C_CARD_FAILURE | 1412 C_TX_COMPLETE | 1413 C_TX_AVAIL | 1414 C_RX_COMPLETE | 1415 C_RX_EARLY | 1416 C_INT_RQD | 1417 C_UPD_STATS))); 1418 1419 #if 0 1420 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1421 1422 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1423 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1424 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1425 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1426 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1427 #endif 1428 1429 if (status & S_RX_COMPLETE) { 1430 epread(sc); 1431 addrandom = 1; 1432 } 1433 if (status & S_TX_AVAIL) { 1434 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1435 epstart(&sc->sc_ethercom.ec_if); 1436 addrandom = 1; 1437 } 1438 if (status & S_CARD_FAILURE) { 1439 printf("%s: adapter failure (%x)\n", 1440 sc->sc_dev.dv_xname, status); 1441 #if 1 1442 epinit(sc); 1443 #else 1444 epreset(sc); 1445 #endif 1446 return (1); 1447 } 1448 if (status & S_TX_COMPLETE) { 1449 eptxstat(sc); 1450 epstart(ifp); 1451 addrandom = 1; 1452 } 1453 1454 #if NRND > 0 1455 if (status) 1456 rnd_add_uint32(&sc->rnd_source, status); 1457 #endif 1458 } 1459 1460 /* no more interrupts */ 1461 return (ret); 1462 } 1463 1464 void 1465 epread(sc) 1466 register struct ep_softc *sc; 1467 { 1468 bus_space_tag_t iot = sc->sc_iot; 1469 bus_space_handle_t ioh = sc->sc_ioh; 1470 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1471 struct mbuf *m; 1472 struct ether_header *eh; 1473 int len; 1474 1475 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1476 1477 again: 1478 if (ifp->if_flags & IFF_DEBUG) { 1479 int err = len & ERR_MASK; 1480 char *s = NULL; 1481 1482 if (len & ERR_INCOMPLETE) 1483 s = "incomplete packet"; 1484 else if (err == ERR_OVERRUN) 1485 s = "packet overrun"; 1486 else if (err == ERR_RUNT) 1487 s = "runt packet"; 1488 else if (err == ERR_ALIGNMENT) 1489 s = "bad alignment"; 1490 else if (err == ERR_CRC) 1491 s = "bad crc"; 1492 else if (err == ERR_OVERSIZE) 1493 s = "oversized packet"; 1494 else if (err == ERR_DRIBBLE) 1495 s = "dribble bits"; 1496 1497 if (s) 1498 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1499 } 1500 1501 if (len & ERR_INCOMPLETE) 1502 return; 1503 1504 if (len & ERR_RX) { 1505 ++ifp->if_ierrors; 1506 goto abort; 1507 } 1508 1509 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1510 1511 /* Pull packet off interface. */ 1512 m = epget(sc, len); 1513 if (m == 0) { 1514 ifp->if_ierrors++; 1515 goto abort; 1516 } 1517 1518 ++ifp->if_ipackets; 1519 1520 /* We assume the header fit entirely in one mbuf. */ 1521 eh = mtod(m, struct ether_header *); 1522 1523 #if NBPFILTER > 0 1524 /* 1525 * Check if there's a BPF listener on this interface. 1526 * If so, hand off the raw packet to BPF. 1527 */ 1528 if (ifp->if_bpf) { 1529 bpf_mtap(ifp->if_bpf, m); 1530 1531 /* 1532 * Note that the interface cannot be in promiscuous mode if 1533 * there are no BPF listeners. And if we are in promiscuous 1534 * mode, we have to check if this packet is really ours. 1535 */ 1536 if ((ifp->if_flags & IFF_PROMISC) && 1537 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1538 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1539 sizeof(eh->ether_dhost)) != 0) { 1540 m_freem(m); 1541 return; 1542 } 1543 } 1544 #endif 1545 (*ifp->if_input)(ifp, m); 1546 1547 /* 1548 * In periods of high traffic we can actually receive enough 1549 * packets so that the fifo overrun bit will be set at this point, 1550 * even though we just read a packet. In this case we 1551 * are not going to receive any more interrupts. We check for 1552 * this condition and read again until the fifo is not full. 1553 * We could simplify this test by not using epstatus(), but 1554 * rechecking the RX_STATUS register directly. This test could 1555 * result in unnecessary looping in cases where there is a new 1556 * packet but the fifo is not full, but it will not fix the 1557 * stuck behavior. 1558 * 1559 * Even with this improvement, we still get packet overrun errors 1560 * which are hurting performance. Maybe when I get some more time 1561 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1562 */ 1563 if (epstatus(sc)) { 1564 len = bus_space_read_2(iot, ioh, 1565 ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1566 /* Check if we are stuck and reset [see XXX comment] */ 1567 if (len & ERR_INCOMPLETE) { 1568 if (ifp->if_flags & IFF_DEBUG) 1569 printf("%s: adapter reset\n", 1570 sc->sc_dev.dv_xname); 1571 epreset(sc); 1572 return; 1573 } 1574 goto again; 1575 } 1576 1577 return; 1578 1579 abort: 1580 ep_discard_rxtop(iot, ioh); 1581 1582 } 1583 1584 struct mbuf * 1585 epget(sc, totlen) 1586 struct ep_softc *sc; 1587 int totlen; 1588 { 1589 bus_space_tag_t iot = sc->sc_iot; 1590 bus_space_handle_t ioh = sc->sc_ioh; 1591 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1592 struct mbuf *top, **mp, *m, *rv = NULL; 1593 bus_addr_t rxreg; 1594 int len, remaining; 1595 int sh; 1596 1597 m = sc->mb[sc->next_mb]; 1598 sc->mb[sc->next_mb] = 0; 1599 if (m == 0) { 1600 MGETHDR(m, M_DONTWAIT, MT_DATA); 1601 if (m == 0) 1602 return 0; 1603 } else { 1604 /* If the queue is no longer full, refill. */ 1605 if (sc->last_mb == sc->next_mb) 1606 timeout(epmbuffill, sc, 1); 1607 /* Convert one of our saved mbuf's. */ 1608 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1609 m->m_data = m->m_pktdat; 1610 m->m_flags = M_PKTHDR; 1611 } 1612 m->m_pkthdr.rcvif = ifp; 1613 m->m_pkthdr.len = totlen; 1614 len = MHLEN; 1615 top = 0; 1616 mp = ⊤ 1617 1618 /* 1619 * We read the packet at splhigh() so that an interrupt from another 1620 * device doesn't cause the card's buffer to overflow while we're 1621 * reading it. We may still lose packets at other times. 1622 */ 1623 sh = splhigh(); 1624 1625 rxreg = ep_w1_reg(sc, ELINK_W1_RX_PIO_RD_1); 1626 1627 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1628 /* 1629 * Prime the FIFO buffer counter (number of 16-bit 1630 * words about to be read from the FIFO). 1631 * 1632 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1633 * COUNTER IS NON-ZERO! 1634 */ 1635 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, totlen >> 1); 1636 } 1637 1638 while (totlen > 0) { 1639 if (top) { 1640 m = sc->mb[sc->next_mb]; 1641 sc->mb[sc->next_mb] = 0; 1642 if (m == 0) { 1643 MGET(m, M_DONTWAIT, MT_DATA); 1644 if (m == 0) { 1645 m_freem(top); 1646 goto out; 1647 } 1648 } else { 1649 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1650 } 1651 len = MLEN; 1652 } 1653 if (totlen >= MINCLSIZE) { 1654 MCLGET(m, M_DONTWAIT); 1655 if ((m->m_flags & M_EXT) == 0) { 1656 m_free(m); 1657 m_freem(top); 1658 goto out; 1659 } 1660 len = MCLBYTES; 1661 } 1662 if (top == 0) { 1663 /* align the struct ip header */ 1664 caddr_t newdata = (caddr_t) 1665 ALIGN(m->m_data + sizeof(struct ether_header)) 1666 - sizeof(struct ether_header); 1667 len -= newdata - m->m_data; 1668 m->m_data = newdata; 1669 } 1670 remaining = len = min(totlen, len); 1671 if (ELINK_IS_BUS_32(sc->bustype)) { 1672 u_long offset = mtod(m, u_long); 1673 /* 1674 * Read bytes up to the point where we are aligned. 1675 * (We can align to 4 bytes, rather than ALIGNBYTES, 1676 * here because we're later reading 4-byte chunks.) 1677 */ 1678 if ((remaining > 3) && (offset & 3)) { 1679 int count = (4 - (offset & 3)); 1680 bus_space_read_multi_1(iot, ioh, 1681 rxreg, (u_int8_t *) offset, count); 1682 offset += count; 1683 remaining -= count; 1684 } 1685 if (remaining > 3) { 1686 bus_space_read_multi_stream_4(iot, ioh, 1687 rxreg, (u_int32_t *) offset, 1688 remaining >> 2); 1689 offset += remaining & ~3; 1690 remaining &= 3; 1691 } 1692 if (remaining) { 1693 bus_space_read_multi_1(iot, ioh, 1694 rxreg, (u_int8_t *) offset, remaining); 1695 } 1696 } else { 1697 u_long offset = mtod(m, u_long); 1698 if ((remaining > 1) && (offset & 1)) { 1699 bus_space_read_multi_1(iot, ioh, 1700 rxreg, (u_int8_t *) offset, 1); 1701 remaining -= 1; 1702 offset += 1; 1703 } 1704 if (remaining > 1) { 1705 bus_space_read_multi_stream_2(iot, ioh, 1706 rxreg, (u_int16_t *) offset, 1707 remaining >> 1); 1708 offset += remaining & ~1; 1709 } 1710 if (remaining & 1) { 1711 bus_space_read_multi_1(iot, ioh, 1712 rxreg, (u_int8_t *) offset, remaining & 1); 1713 } 1714 } 1715 m->m_len = len; 1716 totlen -= len; 1717 *mp = m; 1718 mp = &m->m_next; 1719 } 1720 1721 rv = top; 1722 1723 ep_discard_rxtop(iot, ioh); 1724 1725 out: 1726 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 1727 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1728 splx(sh); 1729 1730 return rv; 1731 } 1732 1733 int 1734 epioctl(ifp, cmd, data) 1735 register struct ifnet *ifp; 1736 u_long cmd; 1737 caddr_t data; 1738 { 1739 struct ep_softc *sc = ifp->if_softc; 1740 struct ifaddr *ifa = (struct ifaddr *)data; 1741 struct ifreq *ifr = (struct ifreq *)data; 1742 int s, error = 0; 1743 1744 s = splnet(); 1745 1746 switch (cmd) { 1747 1748 case SIOCSIFADDR: 1749 if ((error = epenable(sc)) != 0) 1750 break; 1751 /* epinit is called just below */ 1752 ifp->if_flags |= IFF_UP; 1753 switch (ifa->ifa_addr->sa_family) { 1754 #ifdef INET 1755 case AF_INET: 1756 epinit(sc); 1757 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1758 break; 1759 #endif 1760 #ifdef NS 1761 case AF_NS: 1762 { 1763 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1764 1765 if (ns_nullhost(*ina)) 1766 ina->x_host = *(union ns_host *) 1767 LLADDR(ifp->if_sadl); 1768 else 1769 bcopy(ina->x_host.c_host, 1770 LLADDR(ifp->if_sadl), 1771 ifp->if_addrlen); 1772 /* Set new address. */ 1773 epinit(sc); 1774 break; 1775 } 1776 #endif 1777 default: 1778 epinit(sc); 1779 break; 1780 } 1781 break; 1782 1783 case SIOCSIFMEDIA: 1784 case SIOCGIFMEDIA: 1785 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1786 break; 1787 1788 case SIOCSIFFLAGS: 1789 if ((ifp->if_flags & IFF_UP) == 0 && 1790 (ifp->if_flags & IFF_RUNNING) != 0) { 1791 /* 1792 * If interface is marked down and it is running, then 1793 * stop it. 1794 */ 1795 epstop(sc); 1796 ifp->if_flags &= ~IFF_RUNNING; 1797 epdisable(sc); 1798 } else if ((ifp->if_flags & IFF_UP) != 0 && 1799 (ifp->if_flags & IFF_RUNNING) == 0) { 1800 /* 1801 * If interface is marked up and it is stopped, then 1802 * start it. 1803 */ 1804 if ((error = epenable(sc)) != 0) 1805 break; 1806 epinit(sc); 1807 } else if ((ifp->if_flags & IFF_UP) != 0) { 1808 /* 1809 * deal with flags changes: 1810 * IFF_MULTICAST, IFF_PROMISC. 1811 */ 1812 epsetfilter(sc); 1813 } 1814 break; 1815 1816 case SIOCADDMULTI: 1817 case SIOCDELMULTI: 1818 if (sc->enabled == 0) { 1819 error = EIO; 1820 break; 1821 } 1822 1823 error = (cmd == SIOCADDMULTI) ? 1824 ether_addmulti(ifr, &sc->sc_ethercom) : 1825 ether_delmulti(ifr, &sc->sc_ethercom); 1826 1827 if (error == ENETRESET) { 1828 /* 1829 * Multicast list has changed; set the hardware filter 1830 * accordingly. 1831 */ 1832 epreset(sc); 1833 error = 0; 1834 } 1835 break; 1836 1837 default: 1838 error = EINVAL; 1839 break; 1840 } 1841 1842 splx(s); 1843 return (error); 1844 } 1845 1846 void 1847 epreset(sc) 1848 struct ep_softc *sc; 1849 { 1850 int s; 1851 1852 s = splnet(); 1853 epstop(sc); 1854 epinit(sc); 1855 splx(s); 1856 } 1857 1858 void 1859 epwatchdog(ifp) 1860 struct ifnet *ifp; 1861 { 1862 struct ep_softc *sc = ifp->if_softc; 1863 1864 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1865 ++sc->sc_ethercom.ec_if.if_oerrors; 1866 1867 epreset(sc); 1868 } 1869 1870 void 1871 epstop(sc) 1872 register struct ep_softc *sc; 1873 { 1874 bus_space_tag_t iot = sc->sc_iot; 1875 bus_space_handle_t ioh = sc->sc_ioh; 1876 1877 if (sc->ep_flags & ELINK_FLAGS_MII) { 1878 /* Stop the one second clock. */ 1879 untimeout(ep_tick, sc); 1880 } 1881 1882 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 1883 /* 1884 * Clear the FIFO buffer count, thus halting 1885 * any currently-running transactions. 1886 */ 1887 GO_WINDOW(1); /* sanity */ 1888 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 1889 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1890 } 1891 1892 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1893 ep_discard_rxtop(iot, ioh); 1894 1895 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1896 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1897 1898 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 1899 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1900 1901 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1902 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK); 1903 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK); 1904 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RX_FILTER); 1905 1906 epmbufempty(sc); 1907 } 1908 1909 1910 /* 1911 * Before reboots, reset card completely. 1912 */ 1913 static void 1914 epshutdown(arg) 1915 void *arg; 1916 { 1917 register struct ep_softc *sc = arg; 1918 int s = splnet(); 1919 1920 if (sc->enabled) { 1921 epstop(sc); 1922 ep_reset_cmd(sc, ELINK_COMMAND, GLOBAL_RESET); 1923 sc->enabled = 0; 1924 } 1925 splx(s); 1926 } 1927 1928 /* 1929 * We get eeprom data from the id_port given an offset into the 1930 * eeprom. Basically; after the ID_sequence is sent to all of 1931 * the cards; they enter the ID_CMD state where they will accept 1932 * command requests. 0x80-0xbf loads the eeprom data. We then 1933 * read the port 16 times and with every read; the cards check 1934 * for contention (ie: if one card writes a 0 bit and another 1935 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1936 * each card compares the data on the bus; if there is a difference 1937 * then that card goes into ID_WAIT state again). In the meantime; 1938 * one bit of data is returned in the AX register which is conveniently 1939 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1940 * bit of data with each read. 1941 * 1942 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1943 */ 1944 u_int16_t 1945 epreadeeprom(iot, ioh, offset) 1946 bus_space_tag_t iot; 1947 bus_space_handle_t ioh; 1948 int offset; 1949 { 1950 u_int16_t data = 0; 1951 int i; 1952 1953 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1954 delay(1000); 1955 for (i = 0; i < 16; i++) 1956 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1957 return (data); 1958 } 1959 1960 static int 1961 epbusyeeprom(sc) 1962 struct ep_softc *sc; 1963 { 1964 bus_space_tag_t iot = sc->sc_iot; 1965 bus_space_handle_t ioh = sc->sc_ioh; 1966 int i = 100, j; 1967 1968 if (sc->bustype == ELINK_BUS_PCMCIA) { 1969 delay(1000); 1970 return 0; 1971 } 1972 1973 j = 0; /* bad GCC flow analysis */ 1974 while (i--) { 1975 j = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND); 1976 if (j & EEPROM_BUSY) 1977 delay(100); 1978 else 1979 break; 1980 } 1981 if (!i) { 1982 printf("\n%s: eeprom failed to come ready\n", 1983 sc->sc_dev.dv_xname); 1984 return (1); 1985 } 1986 if (j & EEPROM_TST_MODE) { 1987 /* XXX PnP mode? */ 1988 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1989 return (1); 1990 } 1991 return (0); 1992 } 1993 1994 u_int16_t 1995 ep_read_eeprom(sc, offset) 1996 struct ep_softc *sc; 1997 u_int16_t offset; 1998 { 1999 u_int16_t readcmd; 2000 2001 /* 2002 * RoadRunner has a larger EEPROM, so a different read command 2003 * is required. 2004 */ 2005 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) 2006 readcmd = READ_EEPROM_RR; 2007 else 2008 readcmd = READ_EEPROM; 2009 2010 if (epbusyeeprom(sc)) 2011 return (0); /* XXX why is eeprom busy? */ 2012 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W0_EEPROM_COMMAND, 2013 readcmd | offset); 2014 if (epbusyeeprom(sc)) 2015 return (0); /* XXX why is eeprom busy? */ 2016 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W0_EEPROM_DATA)); 2017 } 2018 2019 void 2020 epmbuffill(v) 2021 void *v; 2022 { 2023 struct ep_softc *sc = v; 2024 struct mbuf *m; 2025 int s, i; 2026 2027 s = splnet(); 2028 i = sc->last_mb; 2029 do { 2030 if (sc->mb[i] == 0) { 2031 MGET(m, M_DONTWAIT, MT_DATA); 2032 if (m == 0) 2033 break; 2034 sc->mb[i] = m; 2035 } 2036 i = (i + 1) % MAX_MBS; 2037 } while (i != sc->next_mb); 2038 sc->last_mb = i; 2039 /* If the queue was not filled, try again. */ 2040 if (sc->last_mb != sc->next_mb) 2041 timeout(epmbuffill, sc, 1); 2042 splx(s); 2043 } 2044 2045 void 2046 epmbufempty(sc) 2047 struct ep_softc *sc; 2048 { 2049 int s, i; 2050 2051 s = splnet(); 2052 for (i = 0; i<MAX_MBS; i++) { 2053 if (sc->mb[i]) { 2054 m_freem(sc->mb[i]); 2055 sc->mb[i] = NULL; 2056 } 2057 } 2058 sc->last_mb = sc->next_mb = 0; 2059 untimeout(epmbuffill, sc); 2060 splx(s); 2061 } 2062 2063 int 2064 epenable(sc) 2065 struct ep_softc *sc; 2066 { 2067 2068 if (sc->enabled == 0 && sc->enable != NULL) { 2069 if ((*sc->enable)(sc) != 0) { 2070 printf("%s: device enable failed\n", 2071 sc->sc_dev.dv_xname); 2072 return (EIO); 2073 } 2074 } 2075 2076 sc->enabled = 1; 2077 return (0); 2078 } 2079 2080 void 2081 epdisable(sc) 2082 struct ep_softc *sc; 2083 { 2084 2085 if (sc->enabled != 0 && sc->disable != NULL) { 2086 (*sc->disable)(sc); 2087 sc->enabled = 0; 2088 } 2089 } 2090 2091 int 2092 ep_activate(self, act) 2093 struct device *self; 2094 enum devact act; 2095 { 2096 struct ep_softc *sc = (struct ep_softc *)self; 2097 int rv = 0, s; 2098 2099 s = splnet(); 2100 switch (act) { 2101 case DVACT_ACTIVATE: 2102 rv = EOPNOTSUPP; 2103 break; 2104 2105 case DVACT_DEACTIVATE: 2106 #ifdef notyet 2107 /* First, kill off the interface. */ 2108 if_detach(sc->sc_ethercom.ec_if); 2109 #endif 2110 2111 /* Now disable the interface. */ 2112 epdisable(sc); 2113 break; 2114 } 2115 splx(s); 2116 return (rv); 2117 } 2118 2119 void 2120 ep_mii_setbit(sc, bit) 2121 struct ep_softc *sc; 2122 u_int16_t bit; 2123 { 2124 u_int16_t val; 2125 2126 /* We assume we're already in Window 4 */ 2127 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2128 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2129 val | bit); 2130 } 2131 2132 void 2133 ep_mii_clrbit(sc, bit) 2134 struct ep_softc *sc; 2135 u_int16_t bit; 2136 { 2137 u_int16_t val; 2138 2139 /* We assume we're already in Window 4 */ 2140 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2141 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2142 val & ~bit); 2143 } 2144 2145 u_int16_t 2146 ep_mii_readbit(sc, bit) 2147 struct ep_softc *sc; 2148 u_int16_t bit; 2149 { 2150 2151 /* We assume we're already in Window 4 */ 2152 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT) & 2153 bit); 2154 } 2155 2156 void 2157 ep_mii_sync(sc) 2158 struct ep_softc *sc; 2159 { 2160 int i; 2161 2162 /* We assume we're already in Window 4 */ 2163 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2164 for (i = 0; i < 32; i++) { 2165 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2166 ep_mii_setbit(sc, PHYSMGMT_CLK); 2167 } 2168 } 2169 2170 void 2171 ep_mii_sendbits(sc, data, nbits) 2172 struct ep_softc *sc; 2173 u_int32_t data; 2174 int nbits; 2175 { 2176 int i; 2177 2178 /* We assume we're already in Window 4 */ 2179 ep_mii_setbit(sc, PHYSMGMT_DIR); 2180 for (i = 1 << (nbits - 1); i; i = i >> 1) { 2181 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2182 ep_mii_readbit(sc, PHYSMGMT_CLK); 2183 if (data & i) 2184 ep_mii_setbit(sc, PHYSMGMT_DATA); 2185 else 2186 ep_mii_clrbit(sc, PHYSMGMT_DATA); 2187 ep_mii_setbit(sc, PHYSMGMT_CLK); 2188 ep_mii_readbit(sc, PHYSMGMT_CLK); 2189 } 2190 } 2191 2192 int 2193 ep_mii_readreg(self, phy, reg) 2194 struct device *self; 2195 int phy, reg; 2196 { 2197 struct ep_softc *sc = (struct ep_softc *)self; 2198 int val = 0, i, err; 2199 2200 /* 2201 * Read the PHY register by manually driving the MII control lines. 2202 */ 2203 2204 GO_WINDOW(4); 2205 2206 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 0); 2207 2208 ep_mii_sync(sc); 2209 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2210 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 2211 ep_mii_sendbits(sc, phy, 5); 2212 ep_mii_sendbits(sc, reg, 5); 2213 2214 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2215 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2216 ep_mii_setbit(sc, PHYSMGMT_CLK); 2217 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2218 2219 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 2220 ep_mii_setbit(sc, PHYSMGMT_CLK); 2221 2222 /* Even if an error occurs, must still clock out the cycle. */ 2223 for (i = 0; i < 16; i++) { 2224 val <<= 1; 2225 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2226 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 2227 val |= 1; 2228 ep_mii_setbit(sc, PHYSMGMT_CLK); 2229 } 2230 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2231 ep_mii_setbit(sc, PHYSMGMT_CLK); 2232 2233 GO_WINDOW(1); /* back to operating window */ 2234 2235 return (err ? 0 : val); 2236 } 2237 2238 void 2239 ep_mii_writereg(self, phy, reg, val) 2240 struct device *self; 2241 int phy, reg, val; 2242 { 2243 struct ep_softc *sc = (struct ep_softc *)self; 2244 2245 /* 2246 * Write the PHY register by manually driving the MII control lines. 2247 */ 2248 2249 GO_WINDOW(4); 2250 2251 ep_mii_sync(sc); 2252 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2253 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2254 ep_mii_sendbits(sc, phy, 5); 2255 ep_mii_sendbits(sc, reg, 5); 2256 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2257 ep_mii_sendbits(sc, val, 16); 2258 2259 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2260 ep_mii_setbit(sc, PHYSMGMT_CLK); 2261 2262 GO_WINDOW(1); /* back to operating window */ 2263 } 2264 2265 void 2266 ep_statchg(self) 2267 struct device *self; 2268 { 2269 struct ep_softc *sc = (struct ep_softc *)self; 2270 bus_space_tag_t iot = sc->sc_iot; 2271 bus_space_handle_t ioh = sc->sc_ioh; 2272 int mctl; 2273 2274 /* XXX Update ifp->if_baudrate */ 2275 2276 GO_WINDOW(3); 2277 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 2278 if (sc->sc_mii.mii_media_active & IFM_FDX) 2279 mctl |= MAC_CONTROL_FDX; 2280 else 2281 mctl &= ~MAC_CONTROL_FDX; 2282 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 2283 GO_WINDOW(1); /* back to operating window */ 2284 } 2285
Indexes created Tue Sep 30 07:10:03 GMT 2025