elink3.c revision 1.60
1 /* $NetBSD: elink3.c,v 1.60 1999/10/20 16:34:22 enami Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #ifdef DEBUG 124 int epdebug = 0; 125 #endif 126 127 /* 128 * XXX endian workaround for big-endian CPUs with pcmcia: 129 * if stream methods for bus_space_multi are not provided, define them 130 * using non-stream bus_space_{read,write}_multi_. 131 * Assumes host CPU is same endian-ness as bus. 132 */ 133 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 134 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 135 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 136 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 137 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 138 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 139 140 /* 141 * Structure to map media-present bits in boards to ifmedia codes and 142 * printable media names. Used for table-driven ifmedia initialization. 143 */ 144 struct ep_media { 145 int epm_mpbit; /* media present bit */ 146 const char *epm_name; /* name of medium */ 147 int epm_ifmedia; /* ifmedia word for medium */ 148 int epm_epmedia; /* ELINKMEDIA_* constant */ 149 }; 150 151 /* 152 * Media table for the Demon/Vortex/Boomerang chipsets. 153 * 154 * Note that MII on the Demon and Vortex (3c59x) indicates an external 155 * MII connector (for connecting an external PHY) ... I think. Treat 156 * it as `manual' on these chips. 157 * 158 * Any Boomerang (3c90x) chips with MII really do have an internal 159 * MII and real PHYs attached; no `native' media. 160 */ 161 struct ep_media ep_vortex_media[] = { 162 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 163 ELINKMEDIA_10BASE_T }, 164 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 165 ELINKMEDIA_10BASE_T }, 166 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 167 ELINKMEDIA_AUI }, 168 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 169 ELINKMEDIA_10BASE_2 }, 170 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 171 ELINKMEDIA_100BASE_TX }, 172 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 173 ELINKMEDIA_100BASE_TX }, 174 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 175 ELINKMEDIA_100BASE_FX }, 176 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 177 ELINKMEDIA_MII }, 178 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 179 ELINKMEDIA_100BASE_T4 }, 180 { 0, NULL, 0, 181 0 }, 182 }; 183 184 /* 185 * Media table for the older 3Com Etherlink III chipset, used 186 * in the 3c509, 3c579, and 3c589. 187 */ 188 struct ep_media ep_509_media[] = { 189 { ELINK_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 190 ELINKMEDIA_10BASE_T }, 191 { ELINK_W0_CC_AUI, "10base5", IFM_ETHER|IFM_10_5, 192 ELINKMEDIA_AUI }, 193 { ELINK_W0_CC_BNC, "10base2", IFM_ETHER|IFM_10_2, 194 ELINKMEDIA_10BASE_2 }, 195 { 0, NULL, 0, 196 0 }, 197 }; 198 199 void ep_internalconfig __P((struct ep_softc *sc)); 200 void ep_vortex_probemedia __P((struct ep_softc *sc)); 201 void ep_509_probemedia __P((struct ep_softc *sc)); 202 203 static void eptxstat __P((struct ep_softc *)); 204 static int epstatus __P((struct ep_softc *)); 205 void epinit __P((struct ep_softc *)); 206 int epioctl __P((struct ifnet *, u_long, caddr_t)); 207 void epstart __P((struct ifnet *)); 208 void epwatchdog __P((struct ifnet *)); 209 void epreset __P((struct ep_softc *)); 210 static void epshutdown __P((void *)); 211 void epread __P((struct ep_softc *)); 212 struct mbuf *epget __P((struct ep_softc *, int)); 213 void epmbuffill __P((void *)); 214 void epmbufempty __P((struct ep_softc *)); 215 void epsetfilter __P((struct ep_softc *)); 216 void ep_roadrunner_mii_enable __P((struct ep_softc *)); 217 void epsetmedia __P((struct ep_softc *)); 218 219 /* ifmedia callbacks */ 220 int ep_media_change __P((struct ifnet *ifp)); 221 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 222 223 /* MII callbacks */ 224 int ep_mii_readreg __P((struct device *, int, int)); 225 void ep_mii_writereg __P((struct device *, int, int, int)); 226 void ep_statchg __P((struct device *)); 227 228 void ep_tick __P((void *)); 229 230 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 231 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 232 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 233 void ep_mii_sync __P((struct ep_softc *)); 234 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 235 236 static int epbusyeeprom __P((struct ep_softc *)); 237 u_int16_t ep_read_eeprom __P((struct ep_softc *, u_int16_t)); 238 static inline void ep_reset_cmd __P((struct ep_softc *sc, 239 u_int cmd, u_int arg)); 240 static inline void ep_finish_reset __P((bus_space_tag_t, bus_space_handle_t)); 241 static inline void ep_discard_rxtop __P((bus_space_tag_t, bus_space_handle_t)); 242 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 243 244 /* 245 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 246 * Window 1 registers offset! 247 */ 248 static __inline int 249 ep_w1_reg(sc, reg) 250 struct ep_softc *sc; 251 int reg; 252 { 253 254 switch (sc->ep_chipset) { 255 case ELINK_CHIPSET_CORKSCREW: 256 return (reg + 0x10); 257 258 case ELINK_CHIPSET_ROADRUNNER: 259 switch (reg) { 260 case ELINK_W1_FREE_TX: 261 case ELINK_W1_RUNNER_RDCTL: 262 case ELINK_W1_RUNNER_WRCTL: 263 return (reg); 264 } 265 return (reg + 0x10); 266 } 267 268 return (reg); 269 } 270 271 /* 272 * Wait for any pending reset to complete. 273 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 274 * but older hardware doesn't implement it and we must delay. 275 */ 276 static inline void 277 ep_finish_reset(iot, ioh) 278 bus_space_tag_t iot; 279 bus_space_handle_t ioh; 280 281 { 282 int i; 283 284 for (i = 0; i < 10000; i++) { 285 if ((bus_space_read_2(iot, ioh, ELINK_STATUS) & 286 S_COMMAND_IN_PROGRESS) == 0) 287 break; 288 DELAY(10); 289 } 290 } 291 292 /* 293 * Issue a (reset) command, and be sure it has completed. 294 * Used for global reset, TX_RESET, RX_RESET. 295 */ 296 static inline void 297 ep_reset_cmd(sc, cmd, arg) 298 struct ep_softc *sc; 299 u_int cmd, arg; 300 { 301 register bus_space_tag_t iot = sc->sc_iot; 302 register bus_space_handle_t ioh = sc->sc_ioh; 303 304 bus_space_write_2(iot, ioh, cmd, arg); 305 ep_finish_reset(iot, ioh); 306 } 307 308 309 static inline void 310 ep_discard_rxtop(iot, ioh) 311 register bus_space_tag_t iot; 312 register bus_space_handle_t ioh; 313 { 314 int i; 315 316 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 317 318 /* 319 * Spin for about 1 msec, to avoid forcing a DELAY() between 320 * every received packet (adding latency and limiting pkt-recv rate). 321 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 322 * is about right. 323 */ 324 for (i = 0; i < 8000; i++) { 325 if ((bus_space_read_2(iot, ioh, ELINK_STATUS) & 326 S_COMMAND_IN_PROGRESS) == 0) 327 return; 328 } 329 330 /* Didn't complete in a hurry. Do DELAY()s. */ 331 ep_finish_reset(iot, ioh); 332 } 333 334 /* 335 * Back-end attach and configure. 336 */ 337 void 338 epconfig(sc, chipset, enaddr) 339 struct ep_softc *sc; 340 u_short chipset; 341 u_int8_t *enaddr; 342 { 343 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 344 bus_space_tag_t iot = sc->sc_iot; 345 bus_space_handle_t ioh = sc->sc_ioh; 346 u_int16_t i; 347 u_int8_t myla[6]; 348 349 sc->ep_chipset = chipset; 350 351 /* 352 * We could have been groveling around in other register 353 * windows in the front-end; make sure we're in window 0 354 * to read the EEPROM. 355 */ 356 GO_WINDOW(0); 357 358 if (enaddr == NULL) { 359 /* 360 * Read the station address from the eeprom. 361 */ 362 for (i = 0; i < 3; i++) { 363 u_int16_t x = ep_read_eeprom(sc, i); 364 myla[(i << 1)] = x >> 8; 365 myla[(i << 1) + 1] = x; 366 } 367 enaddr = myla; 368 } 369 370 /* 371 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 372 * allow FDDI-sized (4500) byte packets. Commands only take an 373 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 374 * packet length. 375 * Commands to these cards implicitly upshift a packet size 376 * or threshold by 2 bits. 377 * To detect cards with large-packet support, we probe by setting 378 * the transmit threshold register, then change windows and 379 * read back the threshold register directly, and see if the 380 * threshold value was shifted or not. 381 */ 382 bus_space_write_2(iot, ioh, ELINK_COMMAND, 383 SET_TX_AVAIL_THRESH | ELINK_LARGEWIN_PROBE); 384 GO_WINDOW(5); 385 i = bus_space_read_2(iot, ioh, ELINK_W5_TX_AVAIL_THRESH); 386 GO_WINDOW(1); 387 switch (i) { 388 case ELINK_LARGEWIN_PROBE: 389 case (ELINK_LARGEWIN_PROBE & ELINK_LARGEWIN_MASK): 390 sc->ep_pktlenshift = 0; 391 break; 392 393 case (ELINK_LARGEWIN_PROBE << 2): 394 sc->ep_pktlenshift = 2; 395 break; 396 397 default: 398 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 399 "Interface disabled\n", 400 sc->sc_dev.dv_xname, ELINK_LARGEWIN_PROBE, (int) i); 401 return; 402 } 403 404 /* 405 * Ensure Tx-available interrupts are enabled for 406 * start the interface. 407 * XXX should be in epinit()? 408 */ 409 bus_space_write_2(iot, ioh, ELINK_COMMAND, 410 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 411 412 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 413 ifp->if_softc = sc; 414 ifp->if_start = epstart; 415 ifp->if_ioctl = epioctl; 416 ifp->if_watchdog = epwatchdog; 417 ifp->if_flags = 418 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 419 420 if_attach(ifp); 421 ether_ifattach(ifp, enaddr); 422 423 /* 424 * Finish configuration: 425 * determine chipset if the front-end couldn't do so, 426 * show board details, set media. 427 */ 428 429 /* 430 * Print RAM size. We also print the Ethernet address in here. 431 * It's extracted from the ifp, so we have to make sure it's 432 * been attached first. 433 */ 434 ep_internalconfig(sc); 435 GO_WINDOW(0); 436 437 /* 438 * Display some additional information, if pertinent. 439 */ 440 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 441 printf("%s: RoadRunner FIFO buffer enabled\n", 442 sc->sc_dev.dv_xname); 443 444 /* 445 * Initialize our media structures and MII info. We'll 446 * probe the MII if we discover that we have one. 447 */ 448 sc->sc_mii.mii_ifp = ifp; 449 sc->sc_mii.mii_readreg = ep_mii_readreg; 450 sc->sc_mii.mii_writereg = ep_mii_writereg; 451 sc->sc_mii.mii_statchg = ep_statchg; 452 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 453 ep_media_status); 454 455 /* 456 * Now, determine which media we have. 457 */ 458 switch (sc->ep_chipset) { 459 case ELINK_CHIPSET_ROADRUNNER: 460 if (sc->ep_flags & ELINK_FLAGS_MII) { 461 ep_roadrunner_mii_enable(sc); 462 GO_WINDOW(0); 463 } 464 /* FALLTHROUGH */ 465 466 case ELINK_CHIPSET_BOOMERANG: 467 /* 468 * If the device has MII, probe it. We won't be using 469 * any `native' media in this case, only PHYs. If 470 * we don't, just treat the Boomerang like the Vortex. 471 */ 472 if (sc->ep_flags & ELINK_FLAGS_MII) { 473 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 474 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 475 ifmedia_add(&sc->sc_mii.mii_media, 476 IFM_ETHER|IFM_NONE, 0, NULL); 477 ifmedia_set(&sc->sc_mii.mii_media, 478 IFM_ETHER|IFM_NONE); 479 } else { 480 ifmedia_set(&sc->sc_mii.mii_media, 481 IFM_ETHER|IFM_AUTO); 482 } 483 break; 484 } 485 /* FALLTHROUGH */ 486 487 case ELINK_CHIPSET_VORTEX: 488 ep_vortex_probemedia(sc); 489 break; 490 491 default: 492 ep_509_probemedia(sc); 493 break; 494 } 495 496 GO_WINDOW(1); /* Window 1 is operating window */ 497 498 #if NBPFILTER > 0 499 bpfattach(ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 500 #endif 501 502 #if NRND > 0 503 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 504 RND_TYPE_NET, 0); 505 #endif 506 507 sc->tx_start_thresh = 20; /* probably a good starting point. */ 508 509 /* Establish callback to reset card when we reboot. */ 510 shutdownhook_establish(epshutdown, sc); 511 512 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 513 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 514 } 515 516 517 /* 518 * Show interface-model-independent info from window 3 519 * internal-configuration register. 520 */ 521 void 522 ep_internalconfig(sc) 523 struct ep_softc *sc; 524 { 525 bus_space_tag_t iot = sc->sc_iot; 526 bus_space_handle_t ioh = sc->sc_ioh; 527 528 u_int config0; 529 u_int config1; 530 531 int ram_size, ram_width, ram_speed, rom_size, ram_split; 532 /* 533 * NVRAM buffer Rx:Tx config names for busmastering cards 534 * (Demon, Vortex, and later). 535 */ 536 const char *onboard_ram_config[] = { 537 "5:3", "3:1", "1:1", "3:5" }; 538 539 GO_WINDOW(3); 540 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 541 config1 = (u_int)bus_space_read_2(iot, ioh, 542 ELINK_W3_INTERNAL_CONFIG + 2); 543 GO_WINDOW(0); 544 545 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 546 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 547 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 548 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 549 550 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 551 552 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 553 sc->sc_dev.dv_xname, 554 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 555 8 << ram_size, 556 (ram_width) ? "word" : "byte", 557 onboard_ram_config[ram_split]); 558 } 559 560 561 /* 562 * Find supported media on 3c509-generation hardware that doesn't have 563 * a "reset_options" register in window 3. 564 * Use the config_cntrl register in window 0 instead. 565 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 566 * that implement CONFIG_CTRL. We don't have a good way to set the 567 * default active mediuim; punt to ifconfig instead. 568 */ 569 void 570 ep_509_probemedia(sc) 571 struct ep_softc *sc; 572 { 573 bus_space_tag_t iot = sc->sc_iot; 574 bus_space_handle_t ioh = sc->sc_ioh; 575 struct ifmedia *ifm = &sc->sc_mii.mii_media; 576 u_int16_t ep_w0_config, port; 577 struct ep_media *epm; 578 const char *sep = "", *defmedianame = NULL; 579 int defmedia = 0; 580 581 GO_WINDOW(0); 582 ep_w0_config = bus_space_read_2(iot, ioh, ELINK_W0_CONFIG_CTRL); 583 584 printf("%s: ", sc->sc_dev.dv_xname); 585 586 /* Sanity check that there are any media! */ 587 if ((ep_w0_config & ELINK_W0_CC_MEDIAMASK) == 0) { 588 printf("no media present!\n"); 589 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 590 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 591 return; 592 } 593 594 /* 595 * Get the default media from the EEPROM. 596 */ 597 port = ep_read_eeprom(sc, EEPROM_ADDR_CFG) >> 14; 598 599 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 600 601 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 602 if (ep_w0_config & epm->epm_mpbit) { 603 /* 604 * This simple test works because 509 chipsets 605 * don't do full-duplex. 606 */ 607 if (epm->epm_epmedia == port || defmedia == 0) { 608 defmedia = epm->epm_ifmedia; 609 defmedianame = epm->epm_name; 610 } 611 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 612 NULL); 613 PRINT(epm->epm_name); 614 } 615 } 616 617 #undef PRINT 618 619 #ifdef DIAGNOSTIC 620 if (defmedia == 0) 621 panic("ep_509_probemedia: impossible"); 622 #endif 623 624 printf(" (default %s)\n", defmedianame); 625 ifmedia_set(ifm, defmedia); 626 } 627 628 /* 629 * Find media present on large-packet-capable elink3 devices. 630 * Show onboard configuration of large-packet-capable elink3 devices 631 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 632 * Use media and card-version info in window 3 instead. 633 */ 634 void 635 ep_vortex_probemedia(sc) 636 struct ep_softc *sc; 637 { 638 bus_space_tag_t iot = sc->sc_iot; 639 bus_space_handle_t ioh = sc->sc_ioh; 640 struct ifmedia *ifm = &sc->sc_mii.mii_media; 641 struct ep_media *epm; 642 u_int config1; 643 int reset_options; 644 int default_media; /* 3-bit encoding of default (EEPROM) media */ 645 int defmedia = 0; 646 const char *sep = "", *defmedianame = NULL; 647 648 GO_WINDOW(3); 649 config1 = (u_int)bus_space_read_2(iot, ioh, 650 ELINK_W3_INTERNAL_CONFIG + 2); 651 reset_options = (int)bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 652 GO_WINDOW(0); 653 654 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 655 656 printf("%s: ", sc->sc_dev.dv_xname); 657 658 /* Sanity check that there are any media! */ 659 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 660 printf("no media present!\n"); 661 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 662 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 663 return; 664 } 665 666 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 667 668 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 669 if (reset_options & epm->epm_mpbit) { 670 /* 671 * Default media is a little more complicated 672 * on the Vortex. We support full-duplex which 673 * uses the same reset options bit. 674 * 675 * XXX Check EEPROM for default to FDX? 676 */ 677 if (epm->epm_epmedia == default_media) { 678 if ((epm->epm_ifmedia & IFM_FDX) == 0) { 679 defmedia = epm->epm_ifmedia; 680 defmedianame = epm->epm_name; 681 } 682 } else if (defmedia == 0) { 683 defmedia = epm->epm_ifmedia; 684 defmedianame = epm->epm_name; 685 } 686 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 687 NULL); 688 PRINT(epm->epm_name); 689 } 690 } 691 692 #undef PRINT 693 694 #ifdef DIAGNOSTIC 695 if (defmedia == 0) 696 panic("ep_vortex_probemedia: impossible"); 697 #endif 698 699 printf(" (default %s)\n", defmedianame); 700 ifmedia_set(ifm, defmedia); 701 } 702 703 /* 704 * One second timer, used to tick the MII. 705 */ 706 void 707 ep_tick(arg) 708 void *arg; 709 { 710 struct ep_softc *sc = arg; 711 int s; 712 713 #ifdef DIAGNOSTIC 714 if ((sc->ep_flags & ELINK_FLAGS_MII) == 0) 715 panic("ep_tick"); 716 #endif 717 718 s = splnet(); 719 mii_tick(&sc->sc_mii); 720 splx(s); 721 722 timeout(ep_tick, sc, hz); 723 } 724 725 /* 726 * Bring device up. 727 * 728 * The order in here seems important. Otherwise we may not receive 729 * interrupts. ?! 730 */ 731 void 732 epinit(sc) 733 register struct ep_softc *sc; 734 { 735 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 736 bus_space_tag_t iot = sc->sc_iot; 737 bus_space_handle_t ioh = sc->sc_ioh; 738 int i; 739 740 /* Make sure any pending reset has completed before touching board. */ 741 ep_finish_reset(iot, ioh); 742 743 744 if (sc->bustype != ELINK_BUS_PCI) { 745 GO_WINDOW(0); 746 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, 0); 747 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, 748 ENABLE_DRQ_IRQ); 749 } 750 751 if (sc->bustype == ELINK_BUS_PCMCIA) { 752 bus_space_write_2(iot, ioh, ELINK_W0_RESOURCE_CFG, 0x3f00); 753 } 754 755 GO_WINDOW(2); 756 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 757 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 758 LLADDR(ifp->if_sadl)[i]); 759 760 /* 761 * Reset the station-address receive filter. 762 * A bug workaround for busmastering (Vortex, Demon) cards. 763 */ 764 for (i = 0; i < 6; i++) 765 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 766 767 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 768 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 769 770 GO_WINDOW(1); /* Window 1 is operating window */ 771 for (i = 0; i < 31; i++) 772 bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS)); 773 774 /* Set threshhold for for Tx-space avaiable interrupt. */ 775 bus_space_write_2(iot, ioh, ELINK_COMMAND, 776 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 777 778 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 779 /* 780 * Enable options in the PCMCIA LAN COR register, via 781 * RoadRunner Window 1. 782 * 783 * XXX MAGIC CONSTANTS! 784 */ 785 u_int16_t cor; 786 787 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, (1 << 11)); 788 789 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 790 if (sc->ep_flags & ELINK_FLAGS_USESHAREDMEM) 791 cor |= 0x10; 792 if (sc->ep_flags & ELINK_FLAGS_FORCENOWAIT) 793 cor |= 0x20; 794 bus_space_write_2(iot, ioh, 0, cor); 795 796 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 797 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 798 799 if (sc->ep_flags & ELINK_FLAGS_MII) { 800 ep_roadrunner_mii_enable(sc); 801 GO_WINDOW(1); 802 } 803 } 804 805 /* Enable interrupts. */ 806 bus_space_write_2(iot, ioh, ELINK_COMMAND, 807 SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | 808 S_TX_AVAIL); 809 bus_space_write_2(iot, ioh, ELINK_COMMAND, 810 SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | 811 S_TX_AVAIL); 812 813 /* 814 * Attempt to get rid of any stray interrupts that occured during 815 * configuration. On the i386 this isn't possible because one may 816 * already be queued. However, a single stray interrupt is 817 * unimportant. 818 */ 819 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 820 821 epsetfilter(sc); 822 epsetmedia(sc); 823 824 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 825 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 826 827 epmbuffill(sc); 828 829 /* Interface is now `running', with no output active. */ 830 ifp->if_flags |= IFF_RUNNING; 831 ifp->if_flags &= ~IFF_OACTIVE; 832 833 if (sc->ep_flags & ELINK_FLAGS_MII) { 834 /* Start the one second clock. */ 835 timeout(ep_tick, sc, hz); 836 } 837 838 /* Attempt to start output, if any. */ 839 epstart(ifp); 840 } 841 842 843 /* 844 * Set multicast receive filter. 845 * elink3 hardware has no selective multicast filter in hardware. 846 * Enable reception of all multicasts and filter in software. 847 */ 848 void 849 epsetfilter(sc) 850 register struct ep_softc *sc; 851 { 852 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 853 854 GO_WINDOW(1); /* Window 1 is operating window */ 855 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 856 SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST | 857 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0) | 858 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0)); 859 } 860 861 int 862 ep_media_change(ifp) 863 struct ifnet *ifp; 864 { 865 register struct ep_softc *sc = ifp->if_softc; 866 867 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 868 epreset(sc); 869 870 return (0); 871 } 872 873 /* 874 * Reset and enable the MII on the RoadRunner. 875 */ 876 void 877 ep_roadrunner_mii_enable(sc) 878 struct ep_softc *sc; 879 { 880 bus_space_tag_t iot = sc->sc_iot; 881 bus_space_handle_t ioh = sc->sc_ioh; 882 883 GO_WINDOW(3); 884 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 885 ELINK_PCI_100BASE_MII|ELINK_RUNNER_ENABLE_MII); 886 delay(1000); 887 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 888 ELINK_PCI_100BASE_MII|ELINK_RUNNER_MII_RESET| 889 ELINK_RUNNER_ENABLE_MII); 890 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 891 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 892 delay(1000); 893 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 894 ELINK_PCI_100BASE_MII|ELINK_RUNNER_ENABLE_MII); 895 } 896 897 /* 898 * Set the card to use the specified media. 899 */ 900 void 901 epsetmedia(sc) 902 struct ep_softc *sc; 903 { 904 bus_space_tag_t iot = sc->sc_iot; 905 bus_space_handle_t ioh = sc->sc_ioh; 906 907 /* Turn everything off. First turn off linkbeat and UTP. */ 908 GO_WINDOW(4); 909 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0x0); 910 911 /* Turn off coax */ 912 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 913 delay(1000); 914 915 /* 916 * If the device has MII, select it, and then tell the 917 * PHY which media to use. 918 */ 919 if (sc->ep_flags & ELINK_FLAGS_MII) { 920 int config0, config1; 921 922 GO_WINDOW(3); 923 924 #if 0 925 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 926 int resopt; 927 928 resopt = bus_space_read_2(iot, ioh, 929 ELINK_W3_RESET_OPTIONS); 930 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 931 resopt | ELINK_RUNNER_ENABLE_MII); 932 } 933 #endif 934 935 config0 = (u_int)bus_space_read_2(iot, ioh, 936 ELINK_W3_INTERNAL_CONFIG); 937 config1 = (u_int)bus_space_read_2(iot, ioh, 938 ELINK_W3_INTERNAL_CONFIG + 2); 939 940 config1 = config1 & ~CONFIG_MEDIAMASK; 941 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 942 943 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 944 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, 945 config1); 946 GO_WINDOW(1); /* back to operating window */ 947 948 mii_mediachg(&sc->sc_mii); 949 return; 950 } 951 952 /* 953 * Now turn on the selected media/transceiver. 954 */ 955 GO_WINDOW(4); 956 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 957 case IFM_10_T: 958 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 959 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 960 break; 961 962 case IFM_10_2: 963 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 964 DELAY(1000); /* 50ms not enmough? */ 965 break; 966 967 case IFM_100_TX: 968 case IFM_100_FX: 969 case IFM_100_T4: /* XXX check documentation */ 970 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 971 LINKBEAT_ENABLE); 972 DELAY(1000); /* not strictly necessary? */ 973 break; 974 975 case IFM_10_5: 976 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 977 SQE_ENABLE); 978 DELAY(1000); /* not strictly necessary? */ 979 break; 980 981 case IFM_MANUAL: 982 /* 983 * Nothing to do here; we are actually enabling the 984 * external PHY on the MII port. 985 */ 986 break; 987 988 case IFM_NONE: 989 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 990 return; 991 992 default: 993 panic("epsetmedia: impossible"); 994 } 995 996 /* 997 * Tell the chip which port to use. 998 */ 999 switch (sc->ep_chipset) { 1000 case ELINK_CHIPSET_VORTEX: 1001 case ELINK_CHIPSET_BOOMERANG: 1002 { 1003 int mctl, config0, config1; 1004 1005 GO_WINDOW(3); 1006 config0 = (u_int)bus_space_read_2(iot, ioh, 1007 ELINK_W3_INTERNAL_CONFIG); 1008 config1 = (u_int)bus_space_read_2(iot, ioh, 1009 ELINK_W3_INTERNAL_CONFIG + 2); 1010 1011 config1 = config1 & ~CONFIG_MEDIAMASK; 1012 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 1013 CONFIG_MEDIAMASK_SHIFT); 1014 1015 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 1016 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, 1017 config1); 1018 1019 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1020 if (sc->sc_mii.mii_media.ifm_cur->ifm_media & IFM_FDX) 1021 mctl |= MAC_CONTROL_FDX; 1022 else 1023 mctl &= ~MAC_CONTROL_FDX; 1024 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1025 break; 1026 } 1027 default: 1028 { 1029 int w0_addr_cfg; 1030 1031 GO_WINDOW(0); 1032 w0_addr_cfg = bus_space_read_2(iot, ioh, ELINK_W0_ADDRESS_CFG); 1033 w0_addr_cfg &= 0x3fff; 1034 bus_space_write_2(iot, ioh, ELINK_W0_ADDRESS_CFG, w0_addr_cfg | 1035 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 1036 DELAY(1000); 1037 break; 1038 } 1039 } 1040 1041 GO_WINDOW(1); /* Window 1 is operating window */ 1042 } 1043 1044 /* 1045 * Get currently-selected media from card. 1046 * (if_media callback, may be called before interface is brought up). 1047 */ 1048 void 1049 ep_media_status(ifp, req) 1050 struct ifnet *ifp; 1051 struct ifmediareq *req; 1052 { 1053 register struct ep_softc *sc = ifp->if_softc; 1054 bus_space_tag_t iot = sc->sc_iot; 1055 bus_space_handle_t ioh = sc->sc_ioh; 1056 1057 if (sc->enabled == 0) { 1058 req->ifm_active = IFM_ETHER|IFM_NONE; 1059 req->ifm_status = 0; 1060 return; 1061 } 1062 1063 /* 1064 * If we have MII, go ask the PHY what's going on. 1065 */ 1066 if (sc->ep_flags & ELINK_FLAGS_MII) { 1067 mii_pollstat(&sc->sc_mii); 1068 req->ifm_active = sc->sc_mii.mii_media_active; 1069 req->ifm_status = sc->sc_mii.mii_media_status; 1070 return; 1071 } 1072 1073 /* 1074 * Ok, at this point we claim that our active media is 1075 * the currently selected media. We'll update our status 1076 * if our chipset allows us to detect link. 1077 */ 1078 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1079 req->ifm_status = 0; 1080 1081 switch (sc->ep_chipset) { 1082 case ELINK_CHIPSET_VORTEX: 1083 case ELINK_CHIPSET_BOOMERANG: 1084 GO_WINDOW(4); 1085 req->ifm_status = IFM_AVALID; 1086 if (bus_space_read_2(iot, ioh, ELINK_W4_MEDIA_TYPE) & 1087 LINKBEAT_DETECT) 1088 req->ifm_status |= IFM_ACTIVE; 1089 GO_WINDOW(1); /* back to operating window */ 1090 break; 1091 } 1092 } 1093 1094 1095 1096 /* 1097 * Start outputting on the interface. 1098 * Always called as splnet(). 1099 */ 1100 void 1101 epstart(ifp) 1102 struct ifnet *ifp; 1103 { 1104 register struct ep_softc *sc = ifp->if_softc; 1105 bus_space_tag_t iot = sc->sc_iot; 1106 bus_space_handle_t ioh = sc->sc_ioh; 1107 struct mbuf *m, *m0; 1108 int sh, len, pad; 1109 bus_addr_t txreg; 1110 1111 /* Don't transmit if interface is busy or not running */ 1112 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1113 return; 1114 1115 startagain: 1116 /* Sneak a peek at the next packet */ 1117 m0 = ifp->if_snd.ifq_head; 1118 if (m0 == 0) 1119 return; 1120 1121 /* We need to use m->m_pkthdr.len, so require the header */ 1122 if ((m0->m_flags & M_PKTHDR) == 0) 1123 panic("epstart: no header mbuf"); 1124 len = m0->m_pkthdr.len; 1125 1126 pad = (4 - len) & 3; 1127 1128 /* 1129 * The 3c509 automatically pads short packets to minimum ethernet 1130 * length, but we drop packets that are too large. Perhaps we should 1131 * truncate them instead? 1132 */ 1133 if (len + pad > ETHER_MAX_LEN) { 1134 /* packet is obviously too large: toss it */ 1135 ++ifp->if_oerrors; 1136 IF_DEQUEUE(&ifp->if_snd, m0); 1137 m_freem(m0); 1138 goto readcheck; 1139 } 1140 1141 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_FREE_TX)) < 1142 len + pad + 4) { 1143 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1144 SET_TX_AVAIL_THRESH | 1145 ((len + pad + 4) >> sc->ep_pktlenshift)); 1146 /* not enough room in FIFO */ 1147 ifp->if_flags |= IFF_OACTIVE; 1148 return; 1149 } else { 1150 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1151 SET_TX_AVAIL_THRESH | ELINK_THRESH_DISABLE); 1152 } 1153 1154 IF_DEQUEUE(&ifp->if_snd, m0); 1155 if (m0 == 0) /* not really needed */ 1156 return; 1157 1158 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_TX_START_THRESH | 1159 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/)); 1160 1161 #if NBPFILTER > 0 1162 if (ifp->if_bpf) 1163 bpf_mtap(ifp->if_bpf, m0); 1164 #endif 1165 1166 /* 1167 * Do the output at splhigh() so that an interrupt from another device 1168 * won't cause a FIFO underrun. 1169 */ 1170 sh = splhigh(); 1171 1172 txreg = ep_w1_reg(sc, ELINK_W1_TX_PIO_WR_1); 1173 1174 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1175 /* 1176 * Prime the FIFO buffer counter (number of 16-bit 1177 * words about to be written to the FIFO). 1178 * 1179 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1180 * COUNTER IS NON-ZERO! 1181 */ 1182 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 1183 (len + pad) >> 1); 1184 } 1185 1186 bus_space_write_2(iot, ioh, txreg, len); 1187 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1188 if (ELINK_IS_BUS_32(sc->bustype)) { 1189 for (m = m0; m;) { 1190 if (m->m_len > 3) { 1191 /* align our reads from core */ 1192 if (mtod(m, u_long) & 3) { 1193 u_long count = 1194 4 - (mtod(m, u_long) & 3); 1195 bus_space_write_multi_1(iot, ioh, 1196 txreg, mtod(m, u_int8_t *), count); 1197 m->m_data = 1198 (void *)(mtod(m, u_long) + count); 1199 m->m_len -= count; 1200 } 1201 bus_space_write_multi_stream_4(iot, ioh, 1202 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1203 m->m_data = (void *)(mtod(m, u_long) + 1204 (u_long)(m->m_len & ~3)); 1205 m->m_len -= m->m_len & ~3; 1206 } 1207 if (m->m_len) { 1208 bus_space_write_multi_1(iot, ioh, 1209 txreg, mtod(m, u_int8_t *), m->m_len); 1210 } 1211 MFREE(m, m0); 1212 m = m0; 1213 } 1214 } else { 1215 for (m = m0; m;) { 1216 if (m->m_len > 1) { 1217 if (mtod(m, u_long) & 1) { 1218 bus_space_write_1(iot, ioh, 1219 txreg, *(mtod(m, u_int8_t *))); 1220 m->m_data = 1221 (void *)(mtod(m, u_long) + 1); 1222 m->m_len -= 1; 1223 } 1224 bus_space_write_multi_stream_2(iot, ioh, 1225 txreg, mtod(m, u_int16_t *), 1226 m->m_len >> 1); 1227 } 1228 if (m->m_len & 1) { 1229 bus_space_write_1(iot, ioh, txreg, 1230 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1231 } 1232 MFREE(m, m0); 1233 m = m0; 1234 } 1235 } 1236 while (pad--) 1237 bus_space_write_1(iot, ioh, txreg, 0); 1238 1239 splx(sh); 1240 1241 ++ifp->if_opackets; 1242 1243 readcheck: 1244 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)) & 1245 ERR_INCOMPLETE) == 0) { 1246 /* We received a complete packet. */ 1247 u_int16_t status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1248 1249 if ((status & S_INTR_LATCH) == 0) { 1250 /* 1251 * No interrupt, read the packet and continue 1252 * Is this supposed to happen? Is my motherboard 1253 * completely busted? 1254 */ 1255 epread(sc); 1256 } else { 1257 /* Got an interrupt, return so that it gets serviced. */ 1258 return; 1259 } 1260 } else { 1261 /* Check if we are stuck and reset [see XXX comment] */ 1262 if (epstatus(sc)) { 1263 if (ifp->if_flags & IFF_DEBUG) 1264 printf("%s: adapter reset\n", 1265 sc->sc_dev.dv_xname); 1266 epreset(sc); 1267 } 1268 } 1269 1270 goto startagain; 1271 } 1272 1273 1274 /* 1275 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1276 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1277 * We detect this situation and we reset the adapter. 1278 * It happens at times when there is a lot of broadcast traffic 1279 * on the cable (once in a blue moon). 1280 */ 1281 static int 1282 epstatus(sc) 1283 register struct ep_softc *sc; 1284 { 1285 bus_space_tag_t iot = sc->sc_iot; 1286 bus_space_handle_t ioh = sc->sc_ioh; 1287 u_int16_t fifost; 1288 1289 /* 1290 * Check the FIFO status and act accordingly 1291 */ 1292 GO_WINDOW(4); 1293 fifost = bus_space_read_2(iot, ioh, ELINK_W4_FIFO_DIAG); 1294 GO_WINDOW(1); 1295 1296 if (fifost & FIFOS_RX_UNDERRUN) { 1297 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1298 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1299 epreset(sc); 1300 return 0; 1301 } 1302 1303 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1304 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1305 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1306 return 1; 1307 } 1308 1309 if (fifost & FIFOS_RX_OVERRUN) { 1310 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1311 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1312 return 1; 1313 } 1314 1315 if (fifost & FIFOS_TX_OVERRUN) { 1316 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1317 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1318 epreset(sc); 1319 return 0; 1320 } 1321 1322 return 0; 1323 } 1324 1325 1326 static void 1327 eptxstat(sc) 1328 register struct ep_softc *sc; 1329 { 1330 bus_space_tag_t iot = sc->sc_iot; 1331 bus_space_handle_t ioh = sc->sc_ioh; 1332 int i; 1333 1334 /* 1335 * We need to read+write TX_STATUS until we get a 0 status 1336 * in order to turn off the interrupt flag. 1337 */ 1338 while ((i = bus_space_read_1(iot, ioh, 1339 ep_w1_reg(sc, ELINK_W1_TX_STATUS))) & TXS_COMPLETE) { 1340 bus_space_write_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS), 1341 0x0); 1342 1343 if (i & TXS_JABBER) { 1344 ++sc->sc_ethercom.ec_if.if_oerrors; 1345 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1346 printf("%s: jabber (%x)\n", 1347 sc->sc_dev.dv_xname, i); 1348 #if 1 1349 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1350 #else 1351 epreset(sc); 1352 #endif 1353 } else if (i & TXS_UNDERRUN) { 1354 ++sc->sc_ethercom.ec_if.if_oerrors; 1355 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1356 printf("%s: fifo underrun (%x) @%d\n", 1357 sc->sc_dev.dv_xname, i, 1358 sc->tx_start_thresh); 1359 if (sc->tx_succ_ok < 100) 1360 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1361 sc->tx_start_thresh + 20); 1362 sc->tx_succ_ok = 0; 1363 #if 1 1364 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1365 #else 1366 epreset(sc); 1367 #endif 1368 } else if (i & TXS_MAX_COLLISION) { 1369 ++sc->sc_ethercom.ec_if.if_collisions; 1370 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 1371 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1372 } else 1373 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1374 } 1375 } 1376 1377 int 1378 epintr(arg) 1379 void *arg; 1380 { 1381 register struct ep_softc *sc = arg; 1382 bus_space_tag_t iot = sc->sc_iot; 1383 bus_space_handle_t ioh = sc->sc_ioh; 1384 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1385 u_int16_t status; 1386 int ret = 0; 1387 int addrandom = 0; 1388 1389 if (sc->enabled == 0) 1390 return (0); 1391 1392 for (;;) { 1393 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1394 1395 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1396 1397 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1398 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1399 if ((status & S_INTR_LATCH) == 0) { 1400 #if 0 1401 printf("%s: intr latch cleared\n", 1402 sc->sc_dev.dv_xname); 1403 #endif 1404 break; 1405 } 1406 } 1407 1408 ret = 1; 1409 1410 /* 1411 * Acknowledge any interrupts. It's important that we do this 1412 * first, since there would otherwise be a race condition. 1413 * Due to the i386 interrupt queueing, we may get spurious 1414 * interrupts occasionally. 1415 */ 1416 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1417 (status & (C_INTR_LATCH | 1418 C_CARD_FAILURE | 1419 C_TX_COMPLETE | 1420 C_TX_AVAIL | 1421 C_RX_COMPLETE | 1422 C_RX_EARLY | 1423 C_INT_RQD | 1424 C_UPD_STATS))); 1425 1426 #if 0 1427 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1428 1429 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1430 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1431 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1432 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1433 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1434 #endif 1435 1436 if (status & S_RX_COMPLETE) { 1437 epread(sc); 1438 addrandom = 1; 1439 } 1440 if (status & S_TX_AVAIL) { 1441 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1442 epstart(&sc->sc_ethercom.ec_if); 1443 addrandom = 1; 1444 } 1445 if (status & S_CARD_FAILURE) { 1446 printf("%s: adapter failure (%x)\n", 1447 sc->sc_dev.dv_xname, status); 1448 #if 1 1449 epinit(sc); 1450 #else 1451 epreset(sc); 1452 #endif 1453 return (1); 1454 } 1455 if (status & S_TX_COMPLETE) { 1456 eptxstat(sc); 1457 epstart(ifp); 1458 addrandom = 1; 1459 } 1460 1461 #if NRND > 0 1462 if (status) 1463 rnd_add_uint32(&sc->rnd_source, status); 1464 #endif 1465 } 1466 1467 /* no more interrupts */ 1468 return (ret); 1469 } 1470 1471 void 1472 epread(sc) 1473 register struct ep_softc *sc; 1474 { 1475 bus_space_tag_t iot = sc->sc_iot; 1476 bus_space_handle_t ioh = sc->sc_ioh; 1477 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1478 struct mbuf *m; 1479 struct ether_header *eh; 1480 int len; 1481 1482 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1483 1484 again: 1485 if (ifp->if_flags & IFF_DEBUG) { 1486 int err = len & ERR_MASK; 1487 char *s = NULL; 1488 1489 if (len & ERR_INCOMPLETE) 1490 s = "incomplete packet"; 1491 else if (err == ERR_OVERRUN) 1492 s = "packet overrun"; 1493 else if (err == ERR_RUNT) 1494 s = "runt packet"; 1495 else if (err == ERR_ALIGNMENT) 1496 s = "bad alignment"; 1497 else if (err == ERR_CRC) 1498 s = "bad crc"; 1499 else if (err == ERR_OVERSIZE) 1500 s = "oversized packet"; 1501 else if (err == ERR_DRIBBLE) 1502 s = "dribble bits"; 1503 1504 if (s) 1505 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1506 } 1507 1508 if (len & ERR_INCOMPLETE) 1509 return; 1510 1511 if (len & ERR_RX) { 1512 ++ifp->if_ierrors; 1513 goto abort; 1514 } 1515 1516 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1517 1518 /* Pull packet off interface. */ 1519 m = epget(sc, len); 1520 if (m == 0) { 1521 ifp->if_ierrors++; 1522 goto abort; 1523 } 1524 1525 ++ifp->if_ipackets; 1526 1527 /* We assume the header fit entirely in one mbuf. */ 1528 eh = mtod(m, struct ether_header *); 1529 1530 #if NBPFILTER > 0 1531 /* 1532 * Check if there's a BPF listener on this interface. 1533 * If so, hand off the raw packet to BPF. 1534 */ 1535 if (ifp->if_bpf) { 1536 bpf_mtap(ifp->if_bpf, m); 1537 1538 /* 1539 * Note that the interface cannot be in promiscuous mode if 1540 * there are no BPF listeners. And if we are in promiscuous 1541 * mode, we have to check if this packet is really ours. 1542 */ 1543 if ((ifp->if_flags & IFF_PROMISC) && 1544 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1545 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1546 sizeof(eh->ether_dhost)) != 0) { 1547 m_freem(m); 1548 return; 1549 } 1550 } 1551 #endif 1552 (*ifp->if_input)(ifp, m); 1553 1554 /* 1555 * In periods of high traffic we can actually receive enough 1556 * packets so that the fifo overrun bit will be set at this point, 1557 * even though we just read a packet. In this case we 1558 * are not going to receive any more interrupts. We check for 1559 * this condition and read again until the fifo is not full. 1560 * We could simplify this test by not using epstatus(), but 1561 * rechecking the RX_STATUS register directly. This test could 1562 * result in unnecessary looping in cases where there is a new 1563 * packet but the fifo is not full, but it will not fix the 1564 * stuck behavior. 1565 * 1566 * Even with this improvement, we still get packet overrun errors 1567 * which are hurting performance. Maybe when I get some more time 1568 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1569 */ 1570 if (epstatus(sc)) { 1571 len = bus_space_read_2(iot, ioh, 1572 ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1573 /* Check if we are stuck and reset [see XXX comment] */ 1574 if (len & ERR_INCOMPLETE) { 1575 if (ifp->if_flags & IFF_DEBUG) 1576 printf("%s: adapter reset\n", 1577 sc->sc_dev.dv_xname); 1578 epreset(sc); 1579 return; 1580 } 1581 goto again; 1582 } 1583 1584 return; 1585 1586 abort: 1587 ep_discard_rxtop(iot, ioh); 1588 1589 } 1590 1591 struct mbuf * 1592 epget(sc, totlen) 1593 struct ep_softc *sc; 1594 int totlen; 1595 { 1596 bus_space_tag_t iot = sc->sc_iot; 1597 bus_space_handle_t ioh = sc->sc_ioh; 1598 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1599 struct mbuf *top, **mp, *m, *rv = NULL; 1600 bus_addr_t rxreg; 1601 int len, remaining; 1602 int sh; 1603 1604 m = sc->mb[sc->next_mb]; 1605 sc->mb[sc->next_mb] = 0; 1606 if (m == 0) { 1607 MGETHDR(m, M_DONTWAIT, MT_DATA); 1608 if (m == 0) 1609 return 0; 1610 } else { 1611 /* If the queue is no longer full, refill. */ 1612 if (sc->last_mb == sc->next_mb) 1613 timeout(epmbuffill, sc, 1); 1614 /* Convert one of our saved mbuf's. */ 1615 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1616 m->m_data = m->m_pktdat; 1617 m->m_flags = M_PKTHDR; 1618 } 1619 m->m_pkthdr.rcvif = ifp; 1620 m->m_pkthdr.len = totlen; 1621 len = MHLEN; 1622 top = 0; 1623 mp = ⊤ 1624 1625 /* 1626 * We read the packet at splhigh() so that an interrupt from another 1627 * device doesn't cause the card's buffer to overflow while we're 1628 * reading it. We may still lose packets at other times. 1629 */ 1630 sh = splhigh(); 1631 1632 rxreg = ep_w1_reg(sc, ELINK_W1_RX_PIO_RD_1); 1633 1634 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1635 /* 1636 * Prime the FIFO buffer counter (number of 16-bit 1637 * words about to be read from the FIFO). 1638 * 1639 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1640 * COUNTER IS NON-ZERO! 1641 */ 1642 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, totlen >> 1); 1643 } 1644 1645 while (totlen > 0) { 1646 if (top) { 1647 m = sc->mb[sc->next_mb]; 1648 sc->mb[sc->next_mb] = 0; 1649 if (m == 0) { 1650 MGET(m, M_DONTWAIT, MT_DATA); 1651 if (m == 0) { 1652 m_freem(top); 1653 goto out; 1654 } 1655 } else { 1656 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1657 } 1658 len = MLEN; 1659 } 1660 if (totlen >= MINCLSIZE) { 1661 MCLGET(m, M_DONTWAIT); 1662 if ((m->m_flags & M_EXT) == 0) { 1663 m_free(m); 1664 m_freem(top); 1665 goto out; 1666 } 1667 len = MCLBYTES; 1668 } 1669 if (top == 0) { 1670 /* align the struct ip header */ 1671 caddr_t newdata = (caddr_t) 1672 ALIGN(m->m_data + sizeof(struct ether_header)) 1673 - sizeof(struct ether_header); 1674 len -= newdata - m->m_data; 1675 m->m_data = newdata; 1676 } 1677 remaining = len = min(totlen, len); 1678 if (ELINK_IS_BUS_32(sc->bustype)) { 1679 u_long offset = mtod(m, u_long); 1680 /* 1681 * Read bytes up to the point where we are aligned. 1682 * (We can align to 4 bytes, rather than ALIGNBYTES, 1683 * here because we're later reading 4-byte chunks.) 1684 */ 1685 if ((remaining > 3) && (offset & 3)) { 1686 int count = (4 - (offset & 3)); 1687 bus_space_read_multi_1(iot, ioh, 1688 rxreg, (u_int8_t *) offset, count); 1689 offset += count; 1690 remaining -= count; 1691 } 1692 if (remaining > 3) { 1693 bus_space_read_multi_stream_4(iot, ioh, 1694 rxreg, (u_int32_t *) offset, 1695 remaining >> 2); 1696 offset += remaining & ~3; 1697 remaining &= 3; 1698 } 1699 if (remaining) { 1700 bus_space_read_multi_1(iot, ioh, 1701 rxreg, (u_int8_t *) offset, remaining); 1702 } 1703 } else { 1704 u_long offset = mtod(m, u_long); 1705 if ((remaining > 1) && (offset & 1)) { 1706 bus_space_read_multi_1(iot, ioh, 1707 rxreg, (u_int8_t *) offset, 1); 1708 remaining -= 1; 1709 offset += 1; 1710 } 1711 if (remaining > 1) { 1712 bus_space_read_multi_stream_2(iot, ioh, 1713 rxreg, (u_int16_t *) offset, 1714 remaining >> 1); 1715 offset += remaining & ~1; 1716 } 1717 if (remaining & 1) { 1718 bus_space_read_multi_1(iot, ioh, 1719 rxreg, (u_int8_t *) offset, remaining & 1); 1720 } 1721 } 1722 m->m_len = len; 1723 totlen -= len; 1724 *mp = m; 1725 mp = &m->m_next; 1726 } 1727 1728 rv = top; 1729 1730 ep_discard_rxtop(iot, ioh); 1731 1732 out: 1733 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 1734 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1735 splx(sh); 1736 1737 return rv; 1738 } 1739 1740 int 1741 epioctl(ifp, cmd, data) 1742 register struct ifnet *ifp; 1743 u_long cmd; 1744 caddr_t data; 1745 { 1746 struct ep_softc *sc = ifp->if_softc; 1747 struct ifaddr *ifa = (struct ifaddr *)data; 1748 struct ifreq *ifr = (struct ifreq *)data; 1749 int s, error = 0; 1750 1751 s = splnet(); 1752 1753 switch (cmd) { 1754 1755 case SIOCSIFADDR: 1756 if ((error = epenable(sc)) != 0) 1757 break; 1758 /* epinit is called just below */ 1759 ifp->if_flags |= IFF_UP; 1760 switch (ifa->ifa_addr->sa_family) { 1761 #ifdef INET 1762 case AF_INET: 1763 epinit(sc); 1764 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1765 break; 1766 #endif 1767 #ifdef NS 1768 case AF_NS: 1769 { 1770 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1771 1772 if (ns_nullhost(*ina)) 1773 ina->x_host = *(union ns_host *) 1774 LLADDR(ifp->if_sadl); 1775 else 1776 bcopy(ina->x_host.c_host, 1777 LLADDR(ifp->if_sadl), 1778 ifp->if_addrlen); 1779 /* Set new address. */ 1780 epinit(sc); 1781 break; 1782 } 1783 #endif 1784 default: 1785 epinit(sc); 1786 break; 1787 } 1788 break; 1789 1790 case SIOCSIFMEDIA: 1791 case SIOCGIFMEDIA: 1792 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1793 break; 1794 1795 case SIOCSIFFLAGS: 1796 if ((ifp->if_flags & IFF_UP) == 0 && 1797 (ifp->if_flags & IFF_RUNNING) != 0) { 1798 /* 1799 * If interface is marked down and it is running, then 1800 * stop it. 1801 */ 1802 epstop(sc); 1803 ifp->if_flags &= ~IFF_RUNNING; 1804 epdisable(sc); 1805 } else if ((ifp->if_flags & IFF_UP) != 0 && 1806 (ifp->if_flags & IFF_RUNNING) == 0) { 1807 /* 1808 * If interface is marked up and it is stopped, then 1809 * start it. 1810 */ 1811 if ((error = epenable(sc)) != 0) 1812 break; 1813 epinit(sc); 1814 } else if ((ifp->if_flags & IFF_UP) != 0) { 1815 /* 1816 * deal with flags changes: 1817 * IFF_MULTICAST, IFF_PROMISC. 1818 */ 1819 epsetfilter(sc); 1820 } 1821 break; 1822 1823 case SIOCADDMULTI: 1824 case SIOCDELMULTI: 1825 if (sc->enabled == 0) { 1826 error = EIO; 1827 break; 1828 } 1829 1830 error = (cmd == SIOCADDMULTI) ? 1831 ether_addmulti(ifr, &sc->sc_ethercom) : 1832 ether_delmulti(ifr, &sc->sc_ethercom); 1833 1834 if (error == ENETRESET) { 1835 /* 1836 * Multicast list has changed; set the hardware filter 1837 * accordingly. 1838 */ 1839 epreset(sc); 1840 error = 0; 1841 } 1842 break; 1843 1844 default: 1845 error = EINVAL; 1846 break; 1847 } 1848 1849 splx(s); 1850 return (error); 1851 } 1852 1853 void 1854 epreset(sc) 1855 struct ep_softc *sc; 1856 { 1857 int s; 1858 1859 s = splnet(); 1860 epstop(sc); 1861 epinit(sc); 1862 splx(s); 1863 } 1864 1865 void 1866 epwatchdog(ifp) 1867 struct ifnet *ifp; 1868 { 1869 struct ep_softc *sc = ifp->if_softc; 1870 1871 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1872 ++sc->sc_ethercom.ec_if.if_oerrors; 1873 1874 epreset(sc); 1875 } 1876 1877 void 1878 epstop(sc) 1879 register struct ep_softc *sc; 1880 { 1881 bus_space_tag_t iot = sc->sc_iot; 1882 bus_space_handle_t ioh = sc->sc_ioh; 1883 1884 if (sc->ep_flags & ELINK_FLAGS_MII) { 1885 /* Stop the one second clock. */ 1886 untimeout(ep_tick, sc); 1887 } 1888 1889 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 1890 /* 1891 * Clear the FIFO buffer count, thus halting 1892 * any currently-running transactions. 1893 */ 1894 GO_WINDOW(1); /* sanity */ 1895 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 1896 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1897 } 1898 1899 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1900 ep_discard_rxtop(iot, ioh); 1901 1902 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1903 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1904 1905 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 1906 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1907 1908 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1909 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK); 1910 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK); 1911 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RX_FILTER); 1912 1913 epmbufempty(sc); 1914 } 1915 1916 1917 /* 1918 * Before reboots, reset card completely. 1919 */ 1920 static void 1921 epshutdown(arg) 1922 void *arg; 1923 { 1924 register struct ep_softc *sc = arg; 1925 int s = splnet(); 1926 1927 if (sc->enabled) { 1928 epstop(sc); 1929 ep_reset_cmd(sc, ELINK_COMMAND, GLOBAL_RESET); 1930 sc->enabled = 0; 1931 } 1932 splx(s); 1933 } 1934 1935 /* 1936 * We get eeprom data from the id_port given an offset into the 1937 * eeprom. Basically; after the ID_sequence is sent to all of 1938 * the cards; they enter the ID_CMD state where they will accept 1939 * command requests. 0x80-0xbf loads the eeprom data. We then 1940 * read the port 16 times and with every read; the cards check 1941 * for contention (ie: if one card writes a 0 bit and another 1942 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1943 * each card compares the data on the bus; if there is a difference 1944 * then that card goes into ID_WAIT state again). In the meantime; 1945 * one bit of data is returned in the AX register which is conveniently 1946 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1947 * bit of data with each read. 1948 * 1949 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1950 */ 1951 u_int16_t 1952 epreadeeprom(iot, ioh, offset) 1953 bus_space_tag_t iot; 1954 bus_space_handle_t ioh; 1955 int offset; 1956 { 1957 u_int16_t data = 0; 1958 int i; 1959 1960 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1961 delay(1000); 1962 for (i = 0; i < 16; i++) 1963 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1964 return (data); 1965 } 1966 1967 static int 1968 epbusyeeprom(sc) 1969 struct ep_softc *sc; 1970 { 1971 bus_space_tag_t iot = sc->sc_iot; 1972 bus_space_handle_t ioh = sc->sc_ioh; 1973 int i = 100, j; 1974 1975 if (sc->bustype == ELINK_BUS_PCMCIA) { 1976 delay(1000); 1977 return 0; 1978 } 1979 1980 j = 0; /* bad GCC flow analysis */ 1981 while (i--) { 1982 j = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND); 1983 if (j & EEPROM_BUSY) 1984 delay(100); 1985 else 1986 break; 1987 } 1988 if (!i) { 1989 printf("\n%s: eeprom failed to come ready\n", 1990 sc->sc_dev.dv_xname); 1991 return (1); 1992 } 1993 if (j & EEPROM_TST_MODE) { 1994 /* XXX PnP mode? */ 1995 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1996 return (1); 1997 } 1998 return (0); 1999 } 2000 2001 u_int16_t 2002 ep_read_eeprom(sc, offset) 2003 struct ep_softc *sc; 2004 u_int16_t offset; 2005 { 2006 u_int16_t readcmd; 2007 2008 /* 2009 * RoadRunner has a larger EEPROM, so a different read command 2010 * is required. 2011 */ 2012 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) 2013 readcmd = READ_EEPROM_RR; 2014 else 2015 readcmd = READ_EEPROM; 2016 2017 if (epbusyeeprom(sc)) 2018 return (0); /* XXX why is eeprom busy? */ 2019 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W0_EEPROM_COMMAND, 2020 readcmd | offset); 2021 if (epbusyeeprom(sc)) 2022 return (0); /* XXX why is eeprom busy? */ 2023 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W0_EEPROM_DATA)); 2024 } 2025 2026 void 2027 epmbuffill(v) 2028 void *v; 2029 { 2030 struct ep_softc *sc = v; 2031 struct mbuf *m; 2032 int s, i; 2033 2034 s = splnet(); 2035 i = sc->last_mb; 2036 do { 2037 if (sc->mb[i] == 0) { 2038 MGET(m, M_DONTWAIT, MT_DATA); 2039 if (m == 0) 2040 break; 2041 sc->mb[i] = m; 2042 } 2043 i = (i + 1) % MAX_MBS; 2044 } while (i != sc->next_mb); 2045 sc->last_mb = i; 2046 /* If the queue was not filled, try again. */ 2047 if (sc->last_mb != sc->next_mb) 2048 timeout(epmbuffill, sc, 1); 2049 splx(s); 2050 } 2051 2052 void 2053 epmbufempty(sc) 2054 struct ep_softc *sc; 2055 { 2056 int s, i; 2057 2058 s = splnet(); 2059 for (i = 0; i<MAX_MBS; i++) { 2060 if (sc->mb[i]) { 2061 m_freem(sc->mb[i]); 2062 sc->mb[i] = NULL; 2063 } 2064 } 2065 sc->last_mb = sc->next_mb = 0; 2066 untimeout(epmbuffill, sc); 2067 splx(s); 2068 } 2069 2070 int 2071 epenable(sc) 2072 struct ep_softc *sc; 2073 { 2074 2075 if (sc->enabled == 0 && sc->enable != NULL) { 2076 if ((*sc->enable)(sc) != 0) { 2077 printf("%s: device enable failed\n", 2078 sc->sc_dev.dv_xname); 2079 return (EIO); 2080 } 2081 } 2082 2083 sc->enabled = 1; 2084 return (0); 2085 } 2086 2087 void 2088 epdisable(sc) 2089 struct ep_softc *sc; 2090 { 2091 2092 if (sc->enabled != 0 && sc->disable != NULL) { 2093 (*sc->disable)(sc); 2094 sc->enabled = 0; 2095 } 2096 } 2097 2098 int 2099 ep_activate(self, act) 2100 struct device *self; 2101 enum devact act; 2102 { 2103 struct ep_softc *sc = (struct ep_softc *)self; 2104 int rv = 0, s; 2105 2106 s = splnet(); 2107 switch (act) { 2108 case DVACT_ACTIVATE: 2109 rv = EOPNOTSUPP; 2110 break; 2111 2112 case DVACT_DEACTIVATE: 2113 #ifdef notyet 2114 /* First, kill off the interface. */ 2115 if_detach(sc->sc_ethercom.ec_if); 2116 #endif 2117 2118 /* Now disable the interface. */ 2119 epdisable(sc); 2120 break; 2121 } 2122 splx(s); 2123 return (rv); 2124 } 2125 2126 void 2127 ep_mii_setbit(sc, bit) 2128 struct ep_softc *sc; 2129 u_int16_t bit; 2130 { 2131 u_int16_t val; 2132 2133 /* We assume we're already in Window 4 */ 2134 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2135 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2136 val | bit); 2137 } 2138 2139 void 2140 ep_mii_clrbit(sc, bit) 2141 struct ep_softc *sc; 2142 u_int16_t bit; 2143 { 2144 u_int16_t val; 2145 2146 /* We assume we're already in Window 4 */ 2147 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2148 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2149 val & ~bit); 2150 } 2151 2152 u_int16_t 2153 ep_mii_readbit(sc, bit) 2154 struct ep_softc *sc; 2155 u_int16_t bit; 2156 { 2157 2158 /* We assume we're already in Window 4 */ 2159 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT) & 2160 bit); 2161 } 2162 2163 void 2164 ep_mii_sync(sc) 2165 struct ep_softc *sc; 2166 { 2167 int i; 2168 2169 /* We assume we're already in Window 4 */ 2170 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2171 for (i = 0; i < 32; i++) { 2172 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2173 ep_mii_setbit(sc, PHYSMGMT_CLK); 2174 } 2175 } 2176 2177 void 2178 ep_mii_sendbits(sc, data, nbits) 2179 struct ep_softc *sc; 2180 u_int32_t data; 2181 int nbits; 2182 { 2183 int i; 2184 2185 /* We assume we're already in Window 4 */ 2186 ep_mii_setbit(sc, PHYSMGMT_DIR); 2187 for (i = 1 << (nbits - 1); i; i = i >> 1) { 2188 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2189 ep_mii_readbit(sc, PHYSMGMT_CLK); 2190 if (data & i) 2191 ep_mii_setbit(sc, PHYSMGMT_DATA); 2192 else 2193 ep_mii_clrbit(sc, PHYSMGMT_DATA); 2194 ep_mii_setbit(sc, PHYSMGMT_CLK); 2195 ep_mii_readbit(sc, PHYSMGMT_CLK); 2196 } 2197 } 2198 2199 int 2200 ep_mii_readreg(self, phy, reg) 2201 struct device *self; 2202 int phy, reg; 2203 { 2204 struct ep_softc *sc = (struct ep_softc *)self; 2205 int val = 0, i, err; 2206 2207 /* 2208 * Read the PHY register by manually driving the MII control lines. 2209 */ 2210 2211 GO_WINDOW(4); 2212 2213 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 0); 2214 2215 ep_mii_sync(sc); 2216 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2217 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 2218 ep_mii_sendbits(sc, phy, 5); 2219 ep_mii_sendbits(sc, reg, 5); 2220 2221 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2222 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2223 ep_mii_setbit(sc, PHYSMGMT_CLK); 2224 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2225 2226 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 2227 ep_mii_setbit(sc, PHYSMGMT_CLK); 2228 2229 /* Even if an error occurs, must still clock out the cycle. */ 2230 for (i = 0; i < 16; i++) { 2231 val <<= 1; 2232 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2233 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 2234 val |= 1; 2235 ep_mii_setbit(sc, PHYSMGMT_CLK); 2236 } 2237 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2238 ep_mii_setbit(sc, PHYSMGMT_CLK); 2239 2240 GO_WINDOW(1); /* back to operating window */ 2241 2242 return (err ? 0 : val); 2243 } 2244 2245 void 2246 ep_mii_writereg(self, phy, reg, val) 2247 struct device *self; 2248 int phy, reg, val; 2249 { 2250 struct ep_softc *sc = (struct ep_softc *)self; 2251 2252 /* 2253 * Write the PHY register by manually driving the MII control lines. 2254 */ 2255 2256 GO_WINDOW(4); 2257 2258 ep_mii_sync(sc); 2259 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2260 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2261 ep_mii_sendbits(sc, phy, 5); 2262 ep_mii_sendbits(sc, reg, 5); 2263 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2264 ep_mii_sendbits(sc, val, 16); 2265 2266 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2267 ep_mii_setbit(sc, PHYSMGMT_CLK); 2268 2269 GO_WINDOW(1); /* back to operating window */ 2270 } 2271 2272 void 2273 ep_statchg(self) 2274 struct device *self; 2275 { 2276 struct ep_softc *sc = (struct ep_softc *)self; 2277 bus_space_tag_t iot = sc->sc_iot; 2278 bus_space_handle_t ioh = sc->sc_ioh; 2279 int mctl; 2280 2281 /* XXX Update ifp->if_baudrate */ 2282 2283 GO_WINDOW(3); 2284 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 2285 if (sc->sc_mii.mii_media_active & IFM_FDX) 2286 mctl |= MAC_CONTROL_FDX; 2287 else 2288 mctl &= ~MAC_CONTROL_FDX; 2289 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 2290 GO_WINDOW(1); /* back to operating window */ 2291 } 2292
Indexes created Sat Sep 27 22:09:54 GMT 2025