elink3.c revision 1.62
1 /* $NetBSD: elink3.c,v 1.62 1999/10/30 01:35:47 enami Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan (at) NetBSD.org> 42 * Copyright (c) 1994 Herb Peyerl <hpeyerl (at) beer.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Herb Peyerl. 56 * 4. The name of Herb Peyerl may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #include "opt_inet.h" 72 #include "opt_ns.h" 73 #include "bpfilter.h" 74 #include "rnd.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/syslog.h> 84 #include <sys/select.h> 85 #include <sys/device.h> 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <net/if.h> 91 #include <net/if_dl.h> 92 #include <net/if_ether.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/ic/elink3var.h> 121 #include <dev/ic/elink3reg.h> 122 123 #ifdef DEBUG 124 int epdebug = 0; 125 #endif 126 127 /* 128 * XXX endian workaround for big-endian CPUs with pcmcia: 129 * if stream methods for bus_space_multi are not provided, define them 130 * using non-stream bus_space_{read,write}_multi_. 131 * Assumes host CPU is same endian-ness as bus. 132 */ 133 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 134 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 135 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 136 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 137 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 138 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 139 140 /* 141 * Structure to map media-present bits in boards to ifmedia codes and 142 * printable media names. Used for table-driven ifmedia initialization. 143 */ 144 struct ep_media { 145 int epm_mpbit; /* media present bit */ 146 const char *epm_name; /* name of medium */ 147 int epm_ifmedia; /* ifmedia word for medium */ 148 int epm_epmedia; /* ELINKMEDIA_* constant */ 149 }; 150 151 /* 152 * Media table for the Demon/Vortex/Boomerang chipsets. 153 * 154 * Note that MII on the Demon and Vortex (3c59x) indicates an external 155 * MII connector (for connecting an external PHY) ... I think. Treat 156 * it as `manual' on these chips. 157 * 158 * Any Boomerang (3c90x) chips with MII really do have an internal 159 * MII and real PHYs attached; no `native' media. 160 */ 161 struct ep_media ep_vortex_media[] = { 162 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 163 ELINKMEDIA_10BASE_T }, 164 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 165 ELINKMEDIA_10BASE_T }, 166 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 167 ELINKMEDIA_AUI }, 168 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 169 ELINKMEDIA_10BASE_2 }, 170 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 171 ELINKMEDIA_100BASE_TX }, 172 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 173 ELINKMEDIA_100BASE_TX }, 174 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 175 ELINKMEDIA_100BASE_FX }, 176 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 177 ELINKMEDIA_MII }, 178 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 179 ELINKMEDIA_100BASE_T4 }, 180 { 0, NULL, 0, 181 0 }, 182 }; 183 184 /* 185 * Media table for the older 3Com Etherlink III chipset, used 186 * in the 3c509, 3c579, and 3c589. 187 */ 188 struct ep_media ep_509_media[] = { 189 { ELINK_W0_CC_UTP, "10baseT", IFM_ETHER|IFM_10_T, 190 ELINKMEDIA_10BASE_T }, 191 { ELINK_W0_CC_AUI, "10base5", IFM_ETHER|IFM_10_5, 192 ELINKMEDIA_AUI }, 193 { ELINK_W0_CC_BNC, "10base2", IFM_ETHER|IFM_10_2, 194 ELINKMEDIA_10BASE_2 }, 195 { 0, NULL, 0, 196 0 }, 197 }; 198 199 void ep_internalconfig __P((struct ep_softc *sc)); 200 void ep_vortex_probemedia __P((struct ep_softc *sc)); 201 void ep_509_probemedia __P((struct ep_softc *sc)); 202 203 static void eptxstat __P((struct ep_softc *)); 204 static int epstatus __P((struct ep_softc *)); 205 void epinit __P((struct ep_softc *)); 206 int epioctl __P((struct ifnet *, u_long, caddr_t)); 207 void epstart __P((struct ifnet *)); 208 void epwatchdog __P((struct ifnet *)); 209 void epreset __P((struct ep_softc *)); 210 static void epshutdown __P((void *)); 211 void epread __P((struct ep_softc *)); 212 struct mbuf *epget __P((struct ep_softc *, int)); 213 void epmbuffill __P((void *)); 214 void epmbufempty __P((struct ep_softc *)); 215 void epsetfilter __P((struct ep_softc *)); 216 void ep_roadrunner_mii_enable __P((struct ep_softc *)); 217 void epsetmedia __P((struct ep_softc *)); 218 219 /* ifmedia callbacks */ 220 int ep_media_change __P((struct ifnet *ifp)); 221 void ep_media_status __P((struct ifnet *ifp, struct ifmediareq *req)); 222 223 /* MII callbacks */ 224 int ep_mii_readreg __P((struct device *, int, int)); 225 void ep_mii_writereg __P((struct device *, int, int, int)); 226 void ep_statchg __P((struct device *)); 227 228 void ep_tick __P((void *)); 229 230 void ep_mii_setbit __P((struct ep_softc *, u_int16_t)); 231 void ep_mii_clrbit __P((struct ep_softc *, u_int16_t)); 232 u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t)); 233 void ep_mii_sync __P((struct ep_softc *)); 234 void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int)); 235 236 static int epbusyeeprom __P((struct ep_softc *)); 237 u_int16_t ep_read_eeprom __P((struct ep_softc *, u_int16_t)); 238 static inline void ep_reset_cmd __P((struct ep_softc *sc, 239 u_int cmd, u_int arg)); 240 static inline void ep_finish_reset __P((bus_space_tag_t, bus_space_handle_t)); 241 static inline void ep_discard_rxtop __P((bus_space_tag_t, bus_space_handle_t)); 242 static __inline int ep_w1_reg __P((struct ep_softc *, int)); 243 244 /* 245 * Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have 246 * Window 1 registers offset! 247 */ 248 static __inline int 249 ep_w1_reg(sc, reg) 250 struct ep_softc *sc; 251 int reg; 252 { 253 254 switch (sc->ep_chipset) { 255 case ELINK_CHIPSET_CORKSCREW: 256 return (reg + 0x10); 257 258 case ELINK_CHIPSET_ROADRUNNER: 259 switch (reg) { 260 case ELINK_W1_FREE_TX: 261 case ELINK_W1_RUNNER_RDCTL: 262 case ELINK_W1_RUNNER_WRCTL: 263 return (reg); 264 } 265 return (reg + 0x10); 266 } 267 268 return (reg); 269 } 270 271 /* 272 * Wait for any pending reset to complete. 273 * On newer hardware we could poll SC_COMMAND_IN_PROGRESS, 274 * but older hardware doesn't implement it and we must delay. 275 */ 276 static inline void 277 ep_finish_reset(iot, ioh) 278 bus_space_tag_t iot; 279 bus_space_handle_t ioh; 280 281 { 282 int i; 283 284 for (i = 0; i < 10000; i++) { 285 if ((bus_space_read_2(iot, ioh, ELINK_STATUS) & 286 S_COMMAND_IN_PROGRESS) == 0) 287 break; 288 DELAY(10); 289 } 290 } 291 292 /* 293 * Issue a (reset) command, and be sure it has completed. 294 * Used for global reset, TX_RESET, RX_RESET. 295 */ 296 static inline void 297 ep_reset_cmd(sc, cmd, arg) 298 struct ep_softc *sc; 299 u_int cmd, arg; 300 { 301 register bus_space_tag_t iot = sc->sc_iot; 302 register bus_space_handle_t ioh = sc->sc_ioh; 303 304 bus_space_write_2(iot, ioh, cmd, arg); 305 ep_finish_reset(iot, ioh); 306 } 307 308 309 static inline void 310 ep_discard_rxtop(iot, ioh) 311 register bus_space_tag_t iot; 312 register bus_space_handle_t ioh; 313 { 314 int i; 315 316 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISCARD_TOP_PACK); 317 318 /* 319 * Spin for about 1 msec, to avoid forcing a DELAY() between 320 * every received packet (adding latency and limiting pkt-recv rate). 321 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations 322 * is about right. 323 */ 324 for (i = 0; i < 8000; i++) { 325 if ((bus_space_read_2(iot, ioh, ELINK_STATUS) & 326 S_COMMAND_IN_PROGRESS) == 0) 327 return; 328 } 329 330 /* Didn't complete in a hurry. Do DELAY()s. */ 331 ep_finish_reset(iot, ioh); 332 } 333 334 /* 335 * Back-end attach and configure. 336 */ 337 void 338 epconfig(sc, chipset, enaddr) 339 struct ep_softc *sc; 340 u_short chipset; 341 u_int8_t *enaddr; 342 { 343 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 344 bus_space_tag_t iot = sc->sc_iot; 345 bus_space_handle_t ioh = sc->sc_ioh; 346 u_int16_t i; 347 u_int8_t myla[6]; 348 349 sc->ep_chipset = chipset; 350 351 /* 352 * We could have been groveling around in other register 353 * windows in the front-end; make sure we're in window 0 354 * to read the EEPROM. 355 */ 356 GO_WINDOW(0); 357 358 if (enaddr == NULL) { 359 /* 360 * Read the station address from the eeprom. 361 */ 362 for (i = 0; i < 3; i++) { 363 u_int16_t x = ep_read_eeprom(sc, i); 364 myla[(i << 1)] = x >> 8; 365 myla[(i << 1) + 1] = x; 366 } 367 enaddr = myla; 368 } 369 370 /* 371 * Vortex-based (3c59x pci,eisa) and Boomerang (3c900) cards 372 * allow FDDI-sized (4500) byte packets. Commands only take an 373 * 11-bit parameter, and 11 bits isn't enough to hold a full-size 374 * packet length. 375 * Commands to these cards implicitly upshift a packet size 376 * or threshold by 2 bits. 377 * To detect cards with large-packet support, we probe by setting 378 * the transmit threshold register, then change windows and 379 * read back the threshold register directly, and see if the 380 * threshold value was shifted or not. 381 */ 382 bus_space_write_2(iot, ioh, ELINK_COMMAND, 383 SET_TX_AVAIL_THRESH | ELINK_LARGEWIN_PROBE); 384 GO_WINDOW(5); 385 i = bus_space_read_2(iot, ioh, ELINK_W5_TX_AVAIL_THRESH); 386 GO_WINDOW(1); 387 switch (i) { 388 case ELINK_LARGEWIN_PROBE: 389 case (ELINK_LARGEWIN_PROBE & ELINK_LARGEWIN_MASK): 390 sc->ep_pktlenshift = 0; 391 break; 392 393 case (ELINK_LARGEWIN_PROBE << 2): 394 sc->ep_pktlenshift = 2; 395 break; 396 397 default: 398 printf("%s: wrote 0x%x to TX_AVAIL_THRESH, read back 0x%x. " 399 "Interface disabled\n", 400 sc->sc_dev.dv_xname, ELINK_LARGEWIN_PROBE, (int) i); 401 return; 402 } 403 404 /* 405 * Ensure Tx-available interrupts are enabled for 406 * start the interface. 407 * XXX should be in epinit()? 408 */ 409 bus_space_write_2(iot, ioh, ELINK_COMMAND, 410 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 411 412 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 413 ifp->if_softc = sc; 414 ifp->if_start = epstart; 415 ifp->if_ioctl = epioctl; 416 ifp->if_watchdog = epwatchdog; 417 ifp->if_flags = 418 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 419 420 if_attach(ifp); 421 ether_ifattach(ifp, enaddr); 422 423 /* 424 * Finish configuration: 425 * determine chipset if the front-end couldn't do so, 426 * show board details, set media. 427 */ 428 429 /* 430 * Print RAM size. We also print the Ethernet address in here. 431 * It's extracted from the ifp, so we have to make sure it's 432 * been attached first. 433 */ 434 ep_internalconfig(sc); 435 GO_WINDOW(0); 436 437 /* 438 * Display some additional information, if pertinent. 439 */ 440 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 441 printf("%s: RoadRunner FIFO buffer enabled\n", 442 sc->sc_dev.dv_xname); 443 444 /* 445 * Initialize our media structures and MII info. We'll 446 * probe the MII if we discover that we have one. 447 */ 448 sc->sc_mii.mii_ifp = ifp; 449 sc->sc_mii.mii_readreg = ep_mii_readreg; 450 sc->sc_mii.mii_writereg = ep_mii_writereg; 451 sc->sc_mii.mii_statchg = ep_statchg; 452 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change, 453 ep_media_status); 454 455 /* 456 * Now, determine which media we have. 457 */ 458 switch (sc->ep_chipset) { 459 case ELINK_CHIPSET_ROADRUNNER: 460 if (sc->ep_flags & ELINK_FLAGS_MII) { 461 ep_roadrunner_mii_enable(sc); 462 GO_WINDOW(0); 463 } 464 /* FALLTHROUGH */ 465 466 case ELINK_CHIPSET_BOOMERANG: 467 /* 468 * If the device has MII, probe it. We won't be using 469 * any `native' media in this case, only PHYs. If 470 * we don't, just treat the Boomerang like the Vortex. 471 */ 472 if (sc->ep_flags & ELINK_FLAGS_MII) { 473 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 474 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 475 ifmedia_add(&sc->sc_mii.mii_media, 476 IFM_ETHER|IFM_NONE, 0, NULL); 477 ifmedia_set(&sc->sc_mii.mii_media, 478 IFM_ETHER|IFM_NONE); 479 } else { 480 ifmedia_set(&sc->sc_mii.mii_media, 481 IFM_ETHER|IFM_AUTO); 482 } 483 break; 484 } 485 /* FALLTHROUGH */ 486 487 case ELINK_CHIPSET_VORTEX: 488 ep_vortex_probemedia(sc); 489 break; 490 491 default: 492 ep_509_probemedia(sc); 493 break; 494 } 495 496 GO_WINDOW(1); /* Window 1 is operating window */ 497 498 #if NBPFILTER > 0 499 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 500 #endif 501 502 #if NRND > 0 503 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 504 RND_TYPE_NET, 0); 505 #endif 506 507 sc->tx_start_thresh = 20; /* probably a good starting point. */ 508 509 /* Establish callback to reset card when we reboot. */ 510 shutdownhook_establish(epshutdown, sc); 511 512 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 513 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 514 } 515 516 517 /* 518 * Show interface-model-independent info from window 3 519 * internal-configuration register. 520 */ 521 void 522 ep_internalconfig(sc) 523 struct ep_softc *sc; 524 { 525 bus_space_tag_t iot = sc->sc_iot; 526 bus_space_handle_t ioh = sc->sc_ioh; 527 528 u_int config0; 529 u_int config1; 530 531 int ram_size, ram_width, ram_speed, rom_size, ram_split; 532 /* 533 * NVRAM buffer Rx:Tx config names for busmastering cards 534 * (Demon, Vortex, and later). 535 */ 536 const char *onboard_ram_config[] = { 537 "5:3", "3:1", "1:1", "3:5" }; 538 539 GO_WINDOW(3); 540 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 541 config1 = (u_int)bus_space_read_2(iot, ioh, 542 ELINK_W3_INTERNAL_CONFIG + 2); 543 GO_WINDOW(0); 544 545 ram_size = (config0 & CONFIG_RAMSIZE) >> CONFIG_RAMSIZE_SHIFT; 546 ram_width = (config0 & CONFIG_RAMWIDTH) >> CONFIG_RAMWIDTH_SHIFT; 547 ram_speed = (config0 & CONFIG_RAMSPEED) >> CONFIG_RAMSPEED_SHIFT; 548 rom_size = (config0 & CONFIG_ROMSIZE) >> CONFIG_ROMSIZE_SHIFT; 549 550 ram_split = (config1 & CONFIG_RAMSPLIT) >> CONFIG_RAMSPLIT_SHIFT; 551 552 printf("%s: address %s, %dKB %s-wide FIFO, %s Rx:Tx split\n", 553 sc->sc_dev.dv_xname, 554 ether_sprintf(LLADDR(sc->sc_ethercom.ec_if.if_sadl)), 555 8 << ram_size, 556 (ram_width) ? "word" : "byte", 557 onboard_ram_config[ram_split]); 558 } 559 560 561 /* 562 * Find supported media on 3c509-generation hardware that doesn't have 563 * a "reset_options" register in window 3. 564 * Use the config_cntrl register in window 0 instead. 565 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards 566 * that implement CONFIG_CTRL. We don't have a good way to set the 567 * default active mediuim; punt to ifconfig instead. 568 */ 569 void 570 ep_509_probemedia(sc) 571 struct ep_softc *sc; 572 { 573 bus_space_tag_t iot = sc->sc_iot; 574 bus_space_handle_t ioh = sc->sc_ioh; 575 struct ifmedia *ifm = &sc->sc_mii.mii_media; 576 u_int16_t ep_w0_config, port; 577 struct ep_media *epm; 578 const char *sep = "", *defmedianame = NULL; 579 int defmedia = 0; 580 581 GO_WINDOW(0); 582 ep_w0_config = bus_space_read_2(iot, ioh, ELINK_W0_CONFIG_CTRL); 583 584 printf("%s: ", sc->sc_dev.dv_xname); 585 586 /* Sanity check that there are any media! */ 587 if ((ep_w0_config & ELINK_W0_CC_MEDIAMASK) == 0) { 588 printf("no media present!\n"); 589 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 590 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 591 return; 592 } 593 594 /* 595 * Get the default media from the EEPROM. 596 */ 597 port = ep_read_eeprom(sc, EEPROM_ADDR_CFG) >> 14; 598 599 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 600 601 for (epm = ep_509_media; epm->epm_name != NULL; epm++) { 602 if (ep_w0_config & epm->epm_mpbit) { 603 /* 604 * This simple test works because 509 chipsets 605 * don't do full-duplex. 606 */ 607 if (epm->epm_epmedia == port || defmedia == 0) { 608 defmedia = epm->epm_ifmedia; 609 defmedianame = epm->epm_name; 610 } 611 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 612 NULL); 613 PRINT(epm->epm_name); 614 } 615 } 616 617 #undef PRINT 618 619 #ifdef DIAGNOSTIC 620 if (defmedia == 0) 621 panic("ep_509_probemedia: impossible"); 622 #endif 623 624 printf(" (default %s)\n", defmedianame); 625 ifmedia_set(ifm, defmedia); 626 } 627 628 /* 629 * Find media present on large-packet-capable elink3 devices. 630 * Show onboard configuration of large-packet-capable elink3 devices 631 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0. 632 * Use media and card-version info in window 3 instead. 633 */ 634 void 635 ep_vortex_probemedia(sc) 636 struct ep_softc *sc; 637 { 638 bus_space_tag_t iot = sc->sc_iot; 639 bus_space_handle_t ioh = sc->sc_ioh; 640 struct ifmedia *ifm = &sc->sc_mii.mii_media; 641 struct ep_media *epm; 642 u_int config1; 643 int reset_options; 644 int default_media; /* 3-bit encoding of default (EEPROM) media */ 645 int defmedia = 0; 646 const char *sep = "", *defmedianame = NULL; 647 648 GO_WINDOW(3); 649 config1 = (u_int)bus_space_read_2(iot, ioh, 650 ELINK_W3_INTERNAL_CONFIG + 2); 651 reset_options = (int)bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 652 GO_WINDOW(0); 653 654 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 655 656 printf("%s: ", sc->sc_dev.dv_xname); 657 658 /* Sanity check that there are any media! */ 659 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 660 printf("no media present!\n"); 661 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 662 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 663 return; 664 } 665 666 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 667 668 for (epm = ep_vortex_media; epm->epm_name != NULL; epm++) { 669 if (reset_options & epm->epm_mpbit) { 670 /* 671 * Default media is a little more complicated 672 * on the Vortex. We support full-duplex which 673 * uses the same reset options bit. 674 * 675 * XXX Check EEPROM for default to FDX? 676 */ 677 if (epm->epm_epmedia == default_media) { 678 if ((epm->epm_ifmedia & IFM_FDX) == 0) { 679 defmedia = epm->epm_ifmedia; 680 defmedianame = epm->epm_name; 681 } 682 } else if (defmedia == 0) { 683 defmedia = epm->epm_ifmedia; 684 defmedianame = epm->epm_name; 685 } 686 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_epmedia, 687 NULL); 688 PRINT(epm->epm_name); 689 } 690 } 691 692 #undef PRINT 693 694 #ifdef DIAGNOSTIC 695 if (defmedia == 0) 696 panic("ep_vortex_probemedia: impossible"); 697 #endif 698 699 printf(" (default %s)\n", defmedianame); 700 ifmedia_set(ifm, defmedia); 701 } 702 703 /* 704 * One second timer, used to tick the MII. 705 */ 706 void 707 ep_tick(arg) 708 void *arg; 709 { 710 struct ep_softc *sc = arg; 711 int s; 712 713 #ifdef DIAGNOSTIC 714 if ((sc->ep_flags & ELINK_FLAGS_MII) == 0) 715 panic("ep_tick"); 716 #endif 717 718 s = splnet(); 719 mii_tick(&sc->sc_mii); 720 splx(s); 721 722 timeout(ep_tick, sc, hz); 723 } 724 725 /* 726 * Bring device up. 727 * 728 * The order in here seems important. Otherwise we may not receive 729 * interrupts. ?! 730 */ 731 void 732 epinit(sc) 733 register struct ep_softc *sc; 734 { 735 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 736 bus_space_tag_t iot = sc->sc_iot; 737 bus_space_handle_t ioh = sc->sc_ioh; 738 int i; 739 740 /* Make sure any pending reset has completed before touching board. */ 741 ep_finish_reset(iot, ioh); 742 743 /* 744 * Cance any pending I/O. 745 */ 746 epstop(sc); 747 748 if (sc->bustype != ELINK_BUS_PCI) { 749 GO_WINDOW(0); 750 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, 0); 751 bus_space_write_2(iot, ioh, ELINK_W0_CONFIG_CTRL, 752 ENABLE_DRQ_IRQ); 753 } 754 755 if (sc->bustype == ELINK_BUS_PCMCIA) { 756 bus_space_write_2(iot, ioh, ELINK_W0_RESOURCE_CFG, 0x3f00); 757 } 758 759 GO_WINDOW(2); 760 for (i = 0; i < 6; i++) /* Reload the ether_addr. */ 761 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 762 LLADDR(ifp->if_sadl)[i]); 763 764 /* 765 * Reset the station-address receive filter. 766 * A bug workaround for busmastering (Vortex, Demon) cards. 767 */ 768 for (i = 0; i < 6; i++) 769 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 770 771 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 772 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 773 774 GO_WINDOW(1); /* Window 1 is operating window */ 775 for (i = 0; i < 31; i++) 776 bus_space_read_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS)); 777 778 /* Set threshhold for for Tx-space avaiable interrupt. */ 779 bus_space_write_2(iot, ioh, ELINK_COMMAND, 780 SET_TX_AVAIL_THRESH | (1600 >> sc->ep_pktlenshift)); 781 782 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 783 /* 784 * Enable options in the PCMCIA LAN COR register, via 785 * RoadRunner Window 1. 786 * 787 * XXX MAGIC CONSTANTS! 788 */ 789 u_int16_t cor; 790 791 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, (1 << 11)); 792 793 cor = bus_space_read_2(iot, ioh, 0) & ~0x30; 794 if (sc->ep_flags & ELINK_FLAGS_USESHAREDMEM) 795 cor |= 0x10; 796 if (sc->ep_flags & ELINK_FLAGS_FORCENOWAIT) 797 cor |= 0x20; 798 bus_space_write_2(iot, ioh, 0, cor); 799 800 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 801 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 802 803 if (sc->ep_flags & ELINK_FLAGS_MII) { 804 ep_roadrunner_mii_enable(sc); 805 GO_WINDOW(1); 806 } 807 } 808 809 /* Enable interrupts. */ 810 bus_space_write_2(iot, ioh, ELINK_COMMAND, 811 SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | 812 S_TX_AVAIL); 813 bus_space_write_2(iot, ioh, ELINK_COMMAND, 814 SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | 815 S_TX_AVAIL); 816 817 /* 818 * Attempt to get rid of any stray interrupts that occured during 819 * configuration. On the i386 this isn't possible because one may 820 * already be queued. However, a single stray interrupt is 821 * unimportant. 822 */ 823 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 824 825 epsetfilter(sc); 826 epsetmedia(sc); 827 828 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 829 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 830 831 epmbuffill(sc); 832 833 /* Interface is now `running', with no output active. */ 834 ifp->if_flags |= IFF_RUNNING; 835 ifp->if_flags &= ~IFF_OACTIVE; 836 837 if (sc->ep_flags & ELINK_FLAGS_MII) { 838 /* Start the one second clock. */ 839 timeout(ep_tick, sc, hz); 840 } 841 842 /* Attempt to start output, if any. */ 843 epstart(ifp); 844 } 845 846 847 /* 848 * Set multicast receive filter. 849 * elink3 hardware has no selective multicast filter in hardware. 850 * Enable reception of all multicasts and filter in software. 851 */ 852 void 853 epsetfilter(sc) 854 register struct ep_softc *sc; 855 { 856 register struct ifnet *ifp = &sc->sc_ethercom.ec_if; 857 858 GO_WINDOW(1); /* Window 1 is operating window */ 859 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 860 SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST | 861 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0) | 862 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0)); 863 } 864 865 int 866 ep_media_change(ifp) 867 struct ifnet *ifp; 868 { 869 register struct ep_softc *sc = ifp->if_softc; 870 871 if (sc->enabled && (ifp->if_flags & IFF_UP) != 0) 872 epreset(sc); 873 874 return (0); 875 } 876 877 /* 878 * Reset and enable the MII on the RoadRunner. 879 */ 880 void 881 ep_roadrunner_mii_enable(sc) 882 struct ep_softc *sc; 883 { 884 bus_space_tag_t iot = sc->sc_iot; 885 bus_space_handle_t ioh = sc->sc_ioh; 886 887 GO_WINDOW(3); 888 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 889 ELINK_PCI_100BASE_MII|ELINK_RUNNER_ENABLE_MII); 890 delay(1000); 891 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 892 ELINK_PCI_100BASE_MII|ELINK_RUNNER_MII_RESET| 893 ELINK_RUNNER_ENABLE_MII); 894 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 895 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 896 delay(1000); 897 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 898 ELINK_PCI_100BASE_MII|ELINK_RUNNER_ENABLE_MII); 899 } 900 901 /* 902 * Set the card to use the specified media. 903 */ 904 void 905 epsetmedia(sc) 906 struct ep_softc *sc; 907 { 908 bus_space_tag_t iot = sc->sc_iot; 909 bus_space_handle_t ioh = sc->sc_ioh; 910 911 /* Turn everything off. First turn off linkbeat and UTP. */ 912 GO_WINDOW(4); 913 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0x0); 914 915 /* Turn off coax */ 916 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 917 delay(1000); 918 919 /* 920 * If the device has MII, select it, and then tell the 921 * PHY which media to use. 922 */ 923 if (sc->ep_flags & ELINK_FLAGS_MII) { 924 int config0, config1; 925 926 GO_WINDOW(3); 927 928 #if 0 929 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 930 int resopt; 931 932 resopt = bus_space_read_2(iot, ioh, 933 ELINK_W3_RESET_OPTIONS); 934 bus_space_write_2(iot, ioh, ELINK_W3_RESET_OPTIONS, 935 resopt | ELINK_RUNNER_ENABLE_MII); 936 } 937 #endif 938 939 config0 = (u_int)bus_space_read_2(iot, ioh, 940 ELINK_W3_INTERNAL_CONFIG); 941 config1 = (u_int)bus_space_read_2(iot, ioh, 942 ELINK_W3_INTERNAL_CONFIG + 2); 943 944 config1 = config1 & ~CONFIG_MEDIAMASK; 945 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 946 947 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 948 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, 949 config1); 950 GO_WINDOW(1); /* back to operating window */ 951 952 mii_mediachg(&sc->sc_mii); 953 return; 954 } 955 956 /* 957 * Now turn on the selected media/transceiver. 958 */ 959 GO_WINDOW(4); 960 switch (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_cur->ifm_media)) { 961 case IFM_10_T: 962 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 963 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 964 break; 965 966 case IFM_10_2: 967 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 968 DELAY(1000); /* 50ms not enmough? */ 969 break; 970 971 case IFM_100_TX: 972 case IFM_100_FX: 973 case IFM_100_T4: /* XXX check documentation */ 974 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 975 LINKBEAT_ENABLE); 976 DELAY(1000); /* not strictly necessary? */ 977 break; 978 979 case IFM_10_5: 980 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 981 SQE_ENABLE); 982 DELAY(1000); /* not strictly necessary? */ 983 break; 984 985 case IFM_MANUAL: 986 /* 987 * Nothing to do here; we are actually enabling the 988 * external PHY on the MII port. 989 */ 990 break; 991 992 case IFM_NONE: 993 printf("%s: interface disabled\n", sc->sc_dev.dv_xname); 994 return; 995 996 default: 997 panic("epsetmedia: impossible"); 998 } 999 1000 /* 1001 * Tell the chip which port to use. 1002 */ 1003 switch (sc->ep_chipset) { 1004 case ELINK_CHIPSET_VORTEX: 1005 case ELINK_CHIPSET_BOOMERANG: 1006 { 1007 int mctl, config0, config1; 1008 1009 GO_WINDOW(3); 1010 config0 = (u_int)bus_space_read_2(iot, ioh, 1011 ELINK_W3_INTERNAL_CONFIG); 1012 config1 = (u_int)bus_space_read_2(iot, ioh, 1013 ELINK_W3_INTERNAL_CONFIG + 2); 1014 1015 config1 = config1 & ~CONFIG_MEDIAMASK; 1016 config1 |= (sc->sc_mii.mii_media.ifm_cur->ifm_data << 1017 CONFIG_MEDIAMASK_SHIFT); 1018 1019 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 1020 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, 1021 config1); 1022 1023 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1024 if (sc->sc_mii.mii_media.ifm_cur->ifm_media & IFM_FDX) 1025 mctl |= MAC_CONTROL_FDX; 1026 else 1027 mctl &= ~MAC_CONTROL_FDX; 1028 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1029 break; 1030 } 1031 default: 1032 { 1033 int w0_addr_cfg; 1034 1035 GO_WINDOW(0); 1036 w0_addr_cfg = bus_space_read_2(iot, ioh, ELINK_W0_ADDRESS_CFG); 1037 w0_addr_cfg &= 0x3fff; 1038 bus_space_write_2(iot, ioh, ELINK_W0_ADDRESS_CFG, w0_addr_cfg | 1039 (sc->sc_mii.mii_media.ifm_cur->ifm_data << 14)); 1040 DELAY(1000); 1041 break; 1042 } 1043 } 1044 1045 GO_WINDOW(1); /* Window 1 is operating window */ 1046 } 1047 1048 /* 1049 * Get currently-selected media from card. 1050 * (if_media callback, may be called before interface is brought up). 1051 */ 1052 void 1053 ep_media_status(ifp, req) 1054 struct ifnet *ifp; 1055 struct ifmediareq *req; 1056 { 1057 register struct ep_softc *sc = ifp->if_softc; 1058 bus_space_tag_t iot = sc->sc_iot; 1059 bus_space_handle_t ioh = sc->sc_ioh; 1060 1061 if (sc->enabled == 0) { 1062 req->ifm_active = IFM_ETHER|IFM_NONE; 1063 req->ifm_status = 0; 1064 return; 1065 } 1066 1067 /* 1068 * If we have MII, go ask the PHY what's going on. 1069 */ 1070 if (sc->ep_flags & ELINK_FLAGS_MII) { 1071 mii_pollstat(&sc->sc_mii); 1072 req->ifm_active = sc->sc_mii.mii_media_active; 1073 req->ifm_status = sc->sc_mii.mii_media_status; 1074 return; 1075 } 1076 1077 /* 1078 * Ok, at this point we claim that our active media is 1079 * the currently selected media. We'll update our status 1080 * if our chipset allows us to detect link. 1081 */ 1082 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1083 req->ifm_status = 0; 1084 1085 switch (sc->ep_chipset) { 1086 case ELINK_CHIPSET_VORTEX: 1087 case ELINK_CHIPSET_BOOMERANG: 1088 GO_WINDOW(4); 1089 req->ifm_status = IFM_AVALID; 1090 if (bus_space_read_2(iot, ioh, ELINK_W4_MEDIA_TYPE) & 1091 LINKBEAT_DETECT) 1092 req->ifm_status |= IFM_ACTIVE; 1093 GO_WINDOW(1); /* back to operating window */ 1094 break; 1095 } 1096 } 1097 1098 1099 1100 /* 1101 * Start outputting on the interface. 1102 * Always called as splnet(). 1103 */ 1104 void 1105 epstart(ifp) 1106 struct ifnet *ifp; 1107 { 1108 register struct ep_softc *sc = ifp->if_softc; 1109 bus_space_tag_t iot = sc->sc_iot; 1110 bus_space_handle_t ioh = sc->sc_ioh; 1111 struct mbuf *m, *m0; 1112 int sh, len, pad; 1113 bus_addr_t txreg; 1114 1115 /* Don't transmit if interface is busy or not running */ 1116 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1117 return; 1118 1119 startagain: 1120 /* Sneak a peek at the next packet */ 1121 m0 = ifp->if_snd.ifq_head; 1122 if (m0 == 0) 1123 return; 1124 1125 /* We need to use m->m_pkthdr.len, so require the header */ 1126 if ((m0->m_flags & M_PKTHDR) == 0) 1127 panic("epstart: no header mbuf"); 1128 len = m0->m_pkthdr.len; 1129 1130 pad = (4 - len) & 3; 1131 1132 /* 1133 * The 3c509 automatically pads short packets to minimum ethernet 1134 * length, but we drop packets that are too large. Perhaps we should 1135 * truncate them instead? 1136 */ 1137 if (len + pad > ETHER_MAX_LEN) { 1138 /* packet is obviously too large: toss it */ 1139 ++ifp->if_oerrors; 1140 IF_DEQUEUE(&ifp->if_snd, m0); 1141 m_freem(m0); 1142 goto readcheck; 1143 } 1144 1145 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_FREE_TX)) < 1146 len + pad + 4) { 1147 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1148 SET_TX_AVAIL_THRESH | 1149 ((len + pad + 4) >> sc->ep_pktlenshift)); 1150 /* not enough room in FIFO */ 1151 ifp->if_flags |= IFF_OACTIVE; 1152 return; 1153 } else { 1154 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1155 SET_TX_AVAIL_THRESH | ELINK_THRESH_DISABLE); 1156 } 1157 1158 IF_DEQUEUE(&ifp->if_snd, m0); 1159 if (m0 == 0) /* not really needed */ 1160 return; 1161 1162 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_TX_START_THRESH | 1163 ((len / 4 + sc->tx_start_thresh) /* >> sc->ep_pktlenshift*/)); 1164 1165 #if NBPFILTER > 0 1166 if (ifp->if_bpf) 1167 bpf_mtap(ifp->if_bpf, m0); 1168 #endif 1169 1170 /* 1171 * Do the output at splhigh() so that an interrupt from another device 1172 * won't cause a FIFO underrun. 1173 */ 1174 sh = splhigh(); 1175 1176 txreg = ep_w1_reg(sc, ELINK_W1_TX_PIO_WR_1); 1177 1178 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1179 /* 1180 * Prime the FIFO buffer counter (number of 16-bit 1181 * words about to be written to the FIFO). 1182 * 1183 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1184 * COUNTER IS NON-ZERO! 1185 */ 1186 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 1187 (len + pad) >> 1); 1188 } 1189 1190 bus_space_write_2(iot, ioh, txreg, len); 1191 bus_space_write_2(iot, ioh, txreg, 0xffff); /* Second is meaningless */ 1192 if (ELINK_IS_BUS_32(sc->bustype)) { 1193 for (m = m0; m;) { 1194 if (m->m_len > 3) { 1195 /* align our reads from core */ 1196 if (mtod(m, u_long) & 3) { 1197 u_long count = 1198 4 - (mtod(m, u_long) & 3); 1199 bus_space_write_multi_1(iot, ioh, 1200 txreg, mtod(m, u_int8_t *), count); 1201 m->m_data = 1202 (void *)(mtod(m, u_long) + count); 1203 m->m_len -= count; 1204 } 1205 bus_space_write_multi_stream_4(iot, ioh, 1206 txreg, mtod(m, u_int32_t *), m->m_len >> 2); 1207 m->m_data = (void *)(mtod(m, u_long) + 1208 (u_long)(m->m_len & ~3)); 1209 m->m_len -= m->m_len & ~3; 1210 } 1211 if (m->m_len) { 1212 bus_space_write_multi_1(iot, ioh, 1213 txreg, mtod(m, u_int8_t *), m->m_len); 1214 } 1215 MFREE(m, m0); 1216 m = m0; 1217 } 1218 } else { 1219 for (m = m0; m;) { 1220 if (m->m_len > 1) { 1221 if (mtod(m, u_long) & 1) { 1222 bus_space_write_1(iot, ioh, 1223 txreg, *(mtod(m, u_int8_t *))); 1224 m->m_data = 1225 (void *)(mtod(m, u_long) + 1); 1226 m->m_len -= 1; 1227 } 1228 bus_space_write_multi_stream_2(iot, ioh, 1229 txreg, mtod(m, u_int16_t *), 1230 m->m_len >> 1); 1231 } 1232 if (m->m_len & 1) { 1233 bus_space_write_1(iot, ioh, txreg, 1234 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1235 } 1236 MFREE(m, m0); 1237 m = m0; 1238 } 1239 } 1240 while (pad--) 1241 bus_space_write_1(iot, ioh, txreg, 0); 1242 1243 splx(sh); 1244 1245 ++ifp->if_opackets; 1246 1247 readcheck: 1248 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)) & 1249 ERR_INCOMPLETE) == 0) { 1250 /* We received a complete packet. */ 1251 u_int16_t status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1252 1253 if ((status & S_INTR_LATCH) == 0) { 1254 /* 1255 * No interrupt, read the packet and continue 1256 * Is this supposed to happen? Is my motherboard 1257 * completely busted? 1258 */ 1259 epread(sc); 1260 } else { 1261 /* Got an interrupt, return so that it gets serviced. */ 1262 return; 1263 } 1264 } else { 1265 /* Check if we are stuck and reset [see XXX comment] */ 1266 if (epstatus(sc)) { 1267 if (ifp->if_flags & IFF_DEBUG) 1268 printf("%s: adapter reset\n", 1269 sc->sc_dev.dv_xname); 1270 epreset(sc); 1271 } 1272 } 1273 1274 goto startagain; 1275 } 1276 1277 1278 /* 1279 * XXX: The 3c509 card can get in a mode where both the fifo status bit 1280 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set 1281 * We detect this situation and we reset the adapter. 1282 * It happens at times when there is a lot of broadcast traffic 1283 * on the cable (once in a blue moon). 1284 */ 1285 static int 1286 epstatus(sc) 1287 register struct ep_softc *sc; 1288 { 1289 bus_space_tag_t iot = sc->sc_iot; 1290 bus_space_handle_t ioh = sc->sc_ioh; 1291 u_int16_t fifost; 1292 1293 /* 1294 * Check the FIFO status and act accordingly 1295 */ 1296 GO_WINDOW(4); 1297 fifost = bus_space_read_2(iot, ioh, ELINK_W4_FIFO_DIAG); 1298 GO_WINDOW(1); 1299 1300 if (fifost & FIFOS_RX_UNDERRUN) { 1301 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1302 printf("%s: RX underrun\n", sc->sc_dev.dv_xname); 1303 epreset(sc); 1304 return 0; 1305 } 1306 1307 if (fifost & FIFOS_RX_STATUS_OVERRUN) { 1308 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1309 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname); 1310 return 1; 1311 } 1312 1313 if (fifost & FIFOS_RX_OVERRUN) { 1314 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1315 printf("%s: RX overrun\n", sc->sc_dev.dv_xname); 1316 return 1; 1317 } 1318 1319 if (fifost & FIFOS_TX_OVERRUN) { 1320 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1321 printf("%s: TX overrun\n", sc->sc_dev.dv_xname); 1322 epreset(sc); 1323 return 0; 1324 } 1325 1326 return 0; 1327 } 1328 1329 1330 static void 1331 eptxstat(sc) 1332 register struct ep_softc *sc; 1333 { 1334 bus_space_tag_t iot = sc->sc_iot; 1335 bus_space_handle_t ioh = sc->sc_ioh; 1336 int i; 1337 1338 /* 1339 * We need to read+write TX_STATUS until we get a 0 status 1340 * in order to turn off the interrupt flag. 1341 */ 1342 while ((i = bus_space_read_1(iot, ioh, 1343 ep_w1_reg(sc, ELINK_W1_TX_STATUS))) & TXS_COMPLETE) { 1344 bus_space_write_1(iot, ioh, ep_w1_reg(sc, ELINK_W1_TX_STATUS), 1345 0x0); 1346 1347 if (i & TXS_JABBER) { 1348 ++sc->sc_ethercom.ec_if.if_oerrors; 1349 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1350 printf("%s: jabber (%x)\n", 1351 sc->sc_dev.dv_xname, i); 1352 #if 1 1353 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1354 #else 1355 epreset(sc); 1356 #endif 1357 } else if (i & TXS_UNDERRUN) { 1358 ++sc->sc_ethercom.ec_if.if_oerrors; 1359 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 1360 printf("%s: fifo underrun (%x) @%d\n", 1361 sc->sc_dev.dv_xname, i, 1362 sc->tx_start_thresh); 1363 if (sc->tx_succ_ok < 100) 1364 sc->tx_start_thresh = min(ETHER_MAX_LEN, 1365 sc->tx_start_thresh + 20); 1366 sc->tx_succ_ok = 0; 1367 #if 1 1368 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1369 #else 1370 epreset(sc); 1371 #endif 1372 } else if (i & TXS_MAX_COLLISION) { 1373 ++sc->sc_ethercom.ec_if.if_collisions; 1374 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 1375 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1376 } else 1377 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 1378 } 1379 } 1380 1381 int 1382 epintr(arg) 1383 void *arg; 1384 { 1385 register struct ep_softc *sc = arg; 1386 bus_space_tag_t iot = sc->sc_iot; 1387 bus_space_handle_t ioh = sc->sc_ioh; 1388 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1389 u_int16_t status; 1390 int ret = 0; 1391 int addrandom = 0; 1392 1393 if (sc->enabled == 0) 1394 return (0); 1395 1396 for (;;) { 1397 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1398 1399 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1400 1401 if ((status & (S_TX_COMPLETE | S_TX_AVAIL | 1402 S_RX_COMPLETE | S_CARD_FAILURE)) == 0) { 1403 if ((status & S_INTR_LATCH) == 0) { 1404 #if 0 1405 printf("%s: intr latch cleared\n", 1406 sc->sc_dev.dv_xname); 1407 #endif 1408 break; 1409 } 1410 } 1411 1412 ret = 1; 1413 1414 /* 1415 * Acknowledge any interrupts. It's important that we do this 1416 * first, since there would otherwise be a race condition. 1417 * Due to the i386 interrupt queueing, we may get spurious 1418 * interrupts occasionally. 1419 */ 1420 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1421 (status & (C_INTR_LATCH | 1422 C_CARD_FAILURE | 1423 C_TX_COMPLETE | 1424 C_TX_AVAIL | 1425 C_RX_COMPLETE | 1426 C_RX_EARLY | 1427 C_INT_RQD | 1428 C_UPD_STATS))); 1429 1430 #if 0 1431 status = bus_space_read_2(iot, ioh, ELINK_STATUS); 1432 1433 printf("%s: intr%s%s%s%s\n", sc->sc_dev.dv_xname, 1434 (status & S_RX_COMPLETE)?" RX_COMPLETE":"", 1435 (status & S_TX_COMPLETE)?" TX_COMPLETE":"", 1436 (status & S_TX_AVAIL)?" TX_AVAIL":"", 1437 (status & S_CARD_FAILURE)?" CARD_FAILURE":""); 1438 #endif 1439 1440 if (status & S_RX_COMPLETE) { 1441 epread(sc); 1442 addrandom = 1; 1443 } 1444 if (status & S_TX_AVAIL) { 1445 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1446 epstart(&sc->sc_ethercom.ec_if); 1447 addrandom = 1; 1448 } 1449 if (status & S_CARD_FAILURE) { 1450 printf("%s: adapter failure (%x)\n", 1451 sc->sc_dev.dv_xname, status); 1452 #if 1 1453 epinit(sc); 1454 #else 1455 epreset(sc); 1456 #endif 1457 return (1); 1458 } 1459 if (status & S_TX_COMPLETE) { 1460 eptxstat(sc); 1461 epstart(ifp); 1462 addrandom = 1; 1463 } 1464 1465 #if NRND > 0 1466 if (status) 1467 rnd_add_uint32(&sc->rnd_source, status); 1468 #endif 1469 } 1470 1471 /* no more interrupts */ 1472 return (ret); 1473 } 1474 1475 void 1476 epread(sc) 1477 register struct ep_softc *sc; 1478 { 1479 bus_space_tag_t iot = sc->sc_iot; 1480 bus_space_handle_t ioh = sc->sc_ioh; 1481 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1482 struct mbuf *m; 1483 struct ether_header *eh; 1484 int len; 1485 1486 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1487 1488 again: 1489 if (ifp->if_flags & IFF_DEBUG) { 1490 int err = len & ERR_MASK; 1491 char *s = NULL; 1492 1493 if (len & ERR_INCOMPLETE) 1494 s = "incomplete packet"; 1495 else if (err == ERR_OVERRUN) 1496 s = "packet overrun"; 1497 else if (err == ERR_RUNT) 1498 s = "runt packet"; 1499 else if (err == ERR_ALIGNMENT) 1500 s = "bad alignment"; 1501 else if (err == ERR_CRC) 1502 s = "bad crc"; 1503 else if (err == ERR_OVERSIZE) 1504 s = "oversized packet"; 1505 else if (err == ERR_DRIBBLE) 1506 s = "dribble bits"; 1507 1508 if (s) 1509 printf("%s: %s\n", sc->sc_dev.dv_xname, s); 1510 } 1511 1512 if (len & ERR_INCOMPLETE) 1513 return; 1514 1515 if (len & ERR_RX) { 1516 ++ifp->if_ierrors; 1517 goto abort; 1518 } 1519 1520 len &= RX_BYTES_MASK; /* Lower 11 bits = RX bytes. */ 1521 1522 /* Pull packet off interface. */ 1523 m = epget(sc, len); 1524 if (m == 0) { 1525 ifp->if_ierrors++; 1526 goto abort; 1527 } 1528 1529 ++ifp->if_ipackets; 1530 1531 /* We assume the header fit entirely in one mbuf. */ 1532 eh = mtod(m, struct ether_header *); 1533 1534 #if NBPFILTER > 0 1535 /* 1536 * Check if there's a BPF listener on this interface. 1537 * If so, hand off the raw packet to BPF. 1538 */ 1539 if (ifp->if_bpf) { 1540 bpf_mtap(ifp->if_bpf, m); 1541 1542 /* 1543 * Note that the interface cannot be in promiscuous mode if 1544 * there are no BPF listeners. And if we are in promiscuous 1545 * mode, we have to check if this packet is really ours. 1546 */ 1547 if ((ifp->if_flags & IFF_PROMISC) && 1548 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 1549 bcmp(eh->ether_dhost, LLADDR(sc->sc_ethercom.ec_if.if_sadl), 1550 sizeof(eh->ether_dhost)) != 0) { 1551 m_freem(m); 1552 return; 1553 } 1554 } 1555 #endif 1556 (*ifp->if_input)(ifp, m); 1557 1558 /* 1559 * In periods of high traffic we can actually receive enough 1560 * packets so that the fifo overrun bit will be set at this point, 1561 * even though we just read a packet. In this case we 1562 * are not going to receive any more interrupts. We check for 1563 * this condition and read again until the fifo is not full. 1564 * We could simplify this test by not using epstatus(), but 1565 * rechecking the RX_STATUS register directly. This test could 1566 * result in unnecessary looping in cases where there is a new 1567 * packet but the fifo is not full, but it will not fix the 1568 * stuck behavior. 1569 * 1570 * Even with this improvement, we still get packet overrun errors 1571 * which are hurting performance. Maybe when I get some more time 1572 * I'll modify epread() so that it can handle RX_EARLY interrupts. 1573 */ 1574 if (epstatus(sc)) { 1575 len = bus_space_read_2(iot, ioh, 1576 ep_w1_reg(sc, ELINK_W1_RX_STATUS)); 1577 /* Check if we are stuck and reset [see XXX comment] */ 1578 if (len & ERR_INCOMPLETE) { 1579 if (ifp->if_flags & IFF_DEBUG) 1580 printf("%s: adapter reset\n", 1581 sc->sc_dev.dv_xname); 1582 epreset(sc); 1583 return; 1584 } 1585 goto again; 1586 } 1587 1588 return; 1589 1590 abort: 1591 ep_discard_rxtop(iot, ioh); 1592 1593 } 1594 1595 struct mbuf * 1596 epget(sc, totlen) 1597 struct ep_softc *sc; 1598 int totlen; 1599 { 1600 bus_space_tag_t iot = sc->sc_iot; 1601 bus_space_handle_t ioh = sc->sc_ioh; 1602 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1603 struct mbuf *top, **mp, *m, *rv = NULL; 1604 bus_addr_t rxreg; 1605 int len, remaining; 1606 int sh; 1607 1608 m = sc->mb[sc->next_mb]; 1609 sc->mb[sc->next_mb] = 0; 1610 if (m == 0) { 1611 MGETHDR(m, M_DONTWAIT, MT_DATA); 1612 if (m == 0) 1613 return 0; 1614 } else { 1615 /* If the queue is no longer full, refill. */ 1616 if (sc->last_mb == sc->next_mb) 1617 timeout(epmbuffill, sc, 1); 1618 /* Convert one of our saved mbuf's. */ 1619 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1620 m->m_data = m->m_pktdat; 1621 m->m_flags = M_PKTHDR; 1622 } 1623 m->m_pkthdr.rcvif = ifp; 1624 m->m_pkthdr.len = totlen; 1625 len = MHLEN; 1626 top = 0; 1627 mp = ⊤ 1628 1629 /* 1630 * We read the packet at splhigh() so that an interrupt from another 1631 * device doesn't cause the card's buffer to overflow while we're 1632 * reading it. We may still lose packets at other times. 1633 */ 1634 sh = splhigh(); 1635 1636 rxreg = ep_w1_reg(sc, ELINK_W1_RX_PIO_RD_1); 1637 1638 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) { 1639 /* 1640 * Prime the FIFO buffer counter (number of 16-bit 1641 * words about to be read from the FIFO). 1642 * 1643 * NOTE: NO OTHER ACCESS CAN BE PERFORMED WHILE THIS 1644 * COUNTER IS NON-ZERO! 1645 */ 1646 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, totlen >> 1); 1647 } 1648 1649 while (totlen > 0) { 1650 if (top) { 1651 m = sc->mb[sc->next_mb]; 1652 sc->mb[sc->next_mb] = 0; 1653 if (m == 0) { 1654 MGET(m, M_DONTWAIT, MT_DATA); 1655 if (m == 0) { 1656 m_freem(top); 1657 goto out; 1658 } 1659 } else { 1660 sc->next_mb = (sc->next_mb + 1) % MAX_MBS; 1661 } 1662 len = MLEN; 1663 } 1664 if (totlen >= MINCLSIZE) { 1665 MCLGET(m, M_DONTWAIT); 1666 if ((m->m_flags & M_EXT) == 0) { 1667 m_free(m); 1668 m_freem(top); 1669 goto out; 1670 } 1671 len = MCLBYTES; 1672 } 1673 if (top == 0) { 1674 /* align the struct ip header */ 1675 caddr_t newdata = (caddr_t) 1676 ALIGN(m->m_data + sizeof(struct ether_header)) 1677 - sizeof(struct ether_header); 1678 len -= newdata - m->m_data; 1679 m->m_data = newdata; 1680 } 1681 remaining = len = min(totlen, len); 1682 if (ELINK_IS_BUS_32(sc->bustype)) { 1683 u_long offset = mtod(m, u_long); 1684 /* 1685 * Read bytes up to the point where we are aligned. 1686 * (We can align to 4 bytes, rather than ALIGNBYTES, 1687 * here because we're later reading 4-byte chunks.) 1688 */ 1689 if ((remaining > 3) && (offset & 3)) { 1690 int count = (4 - (offset & 3)); 1691 bus_space_read_multi_1(iot, ioh, 1692 rxreg, (u_int8_t *) offset, count); 1693 offset += count; 1694 remaining -= count; 1695 } 1696 if (remaining > 3) { 1697 bus_space_read_multi_stream_4(iot, ioh, 1698 rxreg, (u_int32_t *) offset, 1699 remaining >> 2); 1700 offset += remaining & ~3; 1701 remaining &= 3; 1702 } 1703 if (remaining) { 1704 bus_space_read_multi_1(iot, ioh, 1705 rxreg, (u_int8_t *) offset, remaining); 1706 } 1707 } else { 1708 u_long offset = mtod(m, u_long); 1709 if ((remaining > 1) && (offset & 1)) { 1710 bus_space_read_multi_1(iot, ioh, 1711 rxreg, (u_int8_t *) offset, 1); 1712 remaining -= 1; 1713 offset += 1; 1714 } 1715 if (remaining > 1) { 1716 bus_space_read_multi_stream_2(iot, ioh, 1717 rxreg, (u_int16_t *) offset, 1718 remaining >> 1); 1719 offset += remaining & ~1; 1720 } 1721 if (remaining & 1) { 1722 bus_space_read_multi_1(iot, ioh, 1723 rxreg, (u_int8_t *) offset, remaining & 1); 1724 } 1725 } 1726 m->m_len = len; 1727 totlen -= len; 1728 *mp = m; 1729 mp = &m->m_next; 1730 } 1731 1732 rv = top; 1733 1734 ep_discard_rxtop(iot, ioh); 1735 1736 out: 1737 if (sc->ep_flags & ELINK_FLAGS_USEFIFOBUFFER) 1738 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1739 splx(sh); 1740 1741 return rv; 1742 } 1743 1744 int 1745 epioctl(ifp, cmd, data) 1746 register struct ifnet *ifp; 1747 u_long cmd; 1748 caddr_t data; 1749 { 1750 struct ep_softc *sc = ifp->if_softc; 1751 struct ifaddr *ifa = (struct ifaddr *)data; 1752 struct ifreq *ifr = (struct ifreq *)data; 1753 int s, error = 0; 1754 1755 s = splnet(); 1756 1757 switch (cmd) { 1758 1759 case SIOCSIFADDR: 1760 if ((error = epenable(sc)) != 0) 1761 break; 1762 /* epinit is called just below */ 1763 ifp->if_flags |= IFF_UP; 1764 switch (ifa->ifa_addr->sa_family) { 1765 #ifdef INET 1766 case AF_INET: 1767 epinit(sc); 1768 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1769 break; 1770 #endif 1771 #ifdef NS 1772 case AF_NS: 1773 { 1774 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1775 1776 if (ns_nullhost(*ina)) 1777 ina->x_host = *(union ns_host *) 1778 LLADDR(ifp->if_sadl); 1779 else 1780 bcopy(ina->x_host.c_host, 1781 LLADDR(ifp->if_sadl), 1782 ifp->if_addrlen); 1783 /* Set new address. */ 1784 epinit(sc); 1785 break; 1786 } 1787 #endif 1788 default: 1789 epinit(sc); 1790 break; 1791 } 1792 break; 1793 1794 case SIOCSIFMEDIA: 1795 case SIOCGIFMEDIA: 1796 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1797 break; 1798 1799 case SIOCSIFFLAGS: 1800 if ((ifp->if_flags & IFF_UP) == 0 && 1801 (ifp->if_flags & IFF_RUNNING) != 0) { 1802 /* 1803 * If interface is marked down and it is running, then 1804 * stop it. 1805 */ 1806 epstop(sc); 1807 ifp->if_flags &= ~IFF_RUNNING; 1808 epdisable(sc); 1809 } else if ((ifp->if_flags & IFF_UP) != 0 && 1810 (ifp->if_flags & IFF_RUNNING) == 0) { 1811 /* 1812 * If interface is marked up and it is stopped, then 1813 * start it. 1814 */ 1815 if ((error = epenable(sc)) != 0) 1816 break; 1817 epinit(sc); 1818 } else if ((ifp->if_flags & IFF_UP) != 0) { 1819 /* 1820 * deal with flags changes: 1821 * IFF_MULTICAST, IFF_PROMISC. 1822 */ 1823 epsetfilter(sc); 1824 } 1825 break; 1826 1827 case SIOCADDMULTI: 1828 case SIOCDELMULTI: 1829 if (sc->enabled == 0) { 1830 error = EIO; 1831 break; 1832 } 1833 1834 error = (cmd == SIOCADDMULTI) ? 1835 ether_addmulti(ifr, &sc->sc_ethercom) : 1836 ether_delmulti(ifr, &sc->sc_ethercom); 1837 1838 if (error == ENETRESET) { 1839 /* 1840 * Multicast list has changed; set the hardware filter 1841 * accordingly. 1842 */ 1843 epreset(sc); 1844 error = 0; 1845 } 1846 break; 1847 1848 default: 1849 error = EINVAL; 1850 break; 1851 } 1852 1853 splx(s); 1854 return (error); 1855 } 1856 1857 void 1858 epreset(sc) 1859 struct ep_softc *sc; 1860 { 1861 int s; 1862 1863 s = splnet(); 1864 epinit(sc); 1865 splx(s); 1866 } 1867 1868 void 1869 epwatchdog(ifp) 1870 struct ifnet *ifp; 1871 { 1872 struct ep_softc *sc = ifp->if_softc; 1873 1874 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1875 ++sc->sc_ethercom.ec_if.if_oerrors; 1876 1877 epreset(sc); 1878 } 1879 1880 void 1881 epstop(sc) 1882 register struct ep_softc *sc; 1883 { 1884 bus_space_tag_t iot = sc->sc_iot; 1885 bus_space_handle_t ioh = sc->sc_ioh; 1886 1887 if (sc->ep_flags & ELINK_FLAGS_MII) { 1888 /* Stop the one second clock. */ 1889 untimeout(ep_tick, sc); 1890 } 1891 1892 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) { 1893 /* 1894 * Clear the FIFO buffer count, thus halting 1895 * any currently-running transactions. 1896 */ 1897 GO_WINDOW(1); /* sanity */ 1898 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_WRCTL, 0); 1899 bus_space_write_2(iot, ioh, ELINK_W1_RUNNER_RDCTL, 0); 1900 } 1901 1902 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1903 ep_discard_rxtop(iot, ioh); 1904 1905 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1906 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1907 1908 ep_reset_cmd(sc, ELINK_COMMAND, RX_RESET); 1909 ep_reset_cmd(sc, ELINK_COMMAND, TX_RESET); 1910 1911 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1912 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK); 1913 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK); 1914 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RX_FILTER); 1915 1916 epmbufempty(sc); 1917 } 1918 1919 1920 /* 1921 * Before reboots, reset card completely. 1922 */ 1923 static void 1924 epshutdown(arg) 1925 void *arg; 1926 { 1927 register struct ep_softc *sc = arg; 1928 int s = splnet(); 1929 1930 if (sc->enabled) { 1931 epstop(sc); 1932 ep_reset_cmd(sc, ELINK_COMMAND, GLOBAL_RESET); 1933 sc->enabled = 0; 1934 } 1935 splx(s); 1936 } 1937 1938 /* 1939 * We get eeprom data from the id_port given an offset into the 1940 * eeprom. Basically; after the ID_sequence is sent to all of 1941 * the cards; they enter the ID_CMD state where they will accept 1942 * command requests. 0x80-0xbf loads the eeprom data. We then 1943 * read the port 16 times and with every read; the cards check 1944 * for contention (ie: if one card writes a 0 bit and another 1945 * writes a 1 bit then the host sees a 0. At the end of the cycle; 1946 * each card compares the data on the bus; if there is a difference 1947 * then that card goes into ID_WAIT state again). In the meantime; 1948 * one bit of data is returned in the AX register which is conveniently 1949 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one 1950 * bit of data with each read. 1951 * 1952 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT! 1953 */ 1954 u_int16_t 1955 epreadeeprom(iot, ioh, offset) 1956 bus_space_tag_t iot; 1957 bus_space_handle_t ioh; 1958 int offset; 1959 { 1960 u_int16_t data = 0; 1961 int i; 1962 1963 bus_space_write_1(iot, ioh, 0, 0x80 + offset); 1964 delay(1000); 1965 for (i = 0; i < 16; i++) 1966 data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1); 1967 return (data); 1968 } 1969 1970 static int 1971 epbusyeeprom(sc) 1972 struct ep_softc *sc; 1973 { 1974 bus_space_tag_t iot = sc->sc_iot; 1975 bus_space_handle_t ioh = sc->sc_ioh; 1976 int i = 100, j; 1977 1978 if (sc->bustype == ELINK_BUS_PCMCIA) { 1979 delay(1000); 1980 return 0; 1981 } 1982 1983 j = 0; /* bad GCC flow analysis */ 1984 while (i--) { 1985 j = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND); 1986 if (j & EEPROM_BUSY) 1987 delay(100); 1988 else 1989 break; 1990 } 1991 if (!i) { 1992 printf("\n%s: eeprom failed to come ready\n", 1993 sc->sc_dev.dv_xname); 1994 return (1); 1995 } 1996 if (j & EEPROM_TST_MODE) { 1997 /* XXX PnP mode? */ 1998 printf("\n%s: erase pencil mark!\n", sc->sc_dev.dv_xname); 1999 return (1); 2000 } 2001 return (0); 2002 } 2003 2004 u_int16_t 2005 ep_read_eeprom(sc, offset) 2006 struct ep_softc *sc; 2007 u_int16_t offset; 2008 { 2009 u_int16_t readcmd; 2010 2011 /* 2012 * RoadRunner has a larger EEPROM, so a different read command 2013 * is required. 2014 */ 2015 if (sc->ep_chipset == ELINK_CHIPSET_ROADRUNNER) 2016 readcmd = READ_EEPROM_RR; 2017 else 2018 readcmd = READ_EEPROM; 2019 2020 if (epbusyeeprom(sc)) 2021 return (0); /* XXX why is eeprom busy? */ 2022 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W0_EEPROM_COMMAND, 2023 readcmd | offset); 2024 if (epbusyeeprom(sc)) 2025 return (0); /* XXX why is eeprom busy? */ 2026 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W0_EEPROM_DATA)); 2027 } 2028 2029 void 2030 epmbuffill(v) 2031 void *v; 2032 { 2033 struct ep_softc *sc = v; 2034 struct mbuf *m; 2035 int s, i; 2036 2037 s = splnet(); 2038 i = sc->last_mb; 2039 do { 2040 if (sc->mb[i] == 0) { 2041 MGET(m, M_DONTWAIT, MT_DATA); 2042 if (m == 0) 2043 break; 2044 sc->mb[i] = m; 2045 } 2046 i = (i + 1) % MAX_MBS; 2047 } while (i != sc->next_mb); 2048 sc->last_mb = i; 2049 /* If the queue was not filled, try again. */ 2050 if (sc->last_mb != sc->next_mb) 2051 timeout(epmbuffill, sc, 1); 2052 splx(s); 2053 } 2054 2055 void 2056 epmbufempty(sc) 2057 struct ep_softc *sc; 2058 { 2059 int s, i; 2060 2061 s = splnet(); 2062 for (i = 0; i<MAX_MBS; i++) { 2063 if (sc->mb[i]) { 2064 m_freem(sc->mb[i]); 2065 sc->mb[i] = NULL; 2066 } 2067 } 2068 sc->last_mb = sc->next_mb = 0; 2069 untimeout(epmbuffill, sc); 2070 splx(s); 2071 } 2072 2073 int 2074 epenable(sc) 2075 struct ep_softc *sc; 2076 { 2077 2078 if (sc->enabled == 0 && sc->enable != NULL) { 2079 if ((*sc->enable)(sc) != 0) { 2080 printf("%s: device enable failed\n", 2081 sc->sc_dev.dv_xname); 2082 return (EIO); 2083 } 2084 } 2085 2086 sc->enabled = 1; 2087 return (0); 2088 } 2089 2090 void 2091 epdisable(sc) 2092 struct ep_softc *sc; 2093 { 2094 2095 if (sc->enabled != 0 && sc->disable != NULL) { 2096 (*sc->disable)(sc); 2097 sc->enabled = 0; 2098 } 2099 } 2100 2101 int 2102 ep_activate(self, act) 2103 struct device *self; 2104 enum devact act; 2105 { 2106 struct ep_softc *sc = (struct ep_softc *)self; 2107 int rv = 0, s; 2108 2109 s = splnet(); 2110 switch (act) { 2111 case DVACT_ACTIVATE: 2112 rv = EOPNOTSUPP; 2113 break; 2114 2115 case DVACT_DEACTIVATE: 2116 #ifdef notyet 2117 /* First, kill off the interface. */ 2118 if_detach(sc->sc_ethercom.ec_if); 2119 #endif 2120 2121 /* Now disable the interface. */ 2122 epdisable(sc); 2123 break; 2124 } 2125 splx(s); 2126 return (rv); 2127 } 2128 2129 void 2130 ep_mii_setbit(sc, bit) 2131 struct ep_softc *sc; 2132 u_int16_t bit; 2133 { 2134 u_int16_t val; 2135 2136 /* We assume we're already in Window 4 */ 2137 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2138 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2139 val | bit); 2140 } 2141 2142 void 2143 ep_mii_clrbit(sc, bit) 2144 struct ep_softc *sc; 2145 u_int16_t bit; 2146 { 2147 u_int16_t val; 2148 2149 /* We assume we're already in Window 4 */ 2150 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT); 2151 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 2152 val & ~bit); 2153 } 2154 2155 u_int16_t 2156 ep_mii_readbit(sc, bit) 2157 struct ep_softc *sc; 2158 u_int16_t bit; 2159 { 2160 2161 /* We assume we're already in Window 4 */ 2162 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT) & 2163 bit); 2164 } 2165 2166 void 2167 ep_mii_sync(sc) 2168 struct ep_softc *sc; 2169 { 2170 int i; 2171 2172 /* We assume we're already in Window 4 */ 2173 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2174 for (i = 0; i < 32; i++) { 2175 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2176 ep_mii_setbit(sc, PHYSMGMT_CLK); 2177 } 2178 } 2179 2180 void 2181 ep_mii_sendbits(sc, data, nbits) 2182 struct ep_softc *sc; 2183 u_int32_t data; 2184 int nbits; 2185 { 2186 int i; 2187 2188 /* We assume we're already in Window 4 */ 2189 ep_mii_setbit(sc, PHYSMGMT_DIR); 2190 for (i = 1 << (nbits - 1); i; i = i >> 1) { 2191 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2192 ep_mii_readbit(sc, PHYSMGMT_CLK); 2193 if (data & i) 2194 ep_mii_setbit(sc, PHYSMGMT_DATA); 2195 else 2196 ep_mii_clrbit(sc, PHYSMGMT_DATA); 2197 ep_mii_setbit(sc, PHYSMGMT_CLK); 2198 ep_mii_readbit(sc, PHYSMGMT_CLK); 2199 } 2200 } 2201 2202 int 2203 ep_mii_readreg(self, phy, reg) 2204 struct device *self; 2205 int phy, reg; 2206 { 2207 struct ep_softc *sc = (struct ep_softc *)self; 2208 int val = 0, i, err; 2209 2210 /* 2211 * Read the PHY register by manually driving the MII control lines. 2212 */ 2213 2214 GO_WINDOW(4); 2215 2216 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 0); 2217 2218 ep_mii_sync(sc); 2219 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2220 ep_mii_sendbits(sc, MII_COMMAND_READ, 2); 2221 ep_mii_sendbits(sc, phy, 5); 2222 ep_mii_sendbits(sc, reg, 5); 2223 2224 ep_mii_clrbit(sc, PHYSMGMT_DIR); 2225 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2226 ep_mii_setbit(sc, PHYSMGMT_CLK); 2227 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2228 2229 err = ep_mii_readbit(sc, PHYSMGMT_DATA); 2230 ep_mii_setbit(sc, PHYSMGMT_CLK); 2231 2232 /* Even if an error occurs, must still clock out the cycle. */ 2233 for (i = 0; i < 16; i++) { 2234 val <<= 1; 2235 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2236 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA)) 2237 val |= 1; 2238 ep_mii_setbit(sc, PHYSMGMT_CLK); 2239 } 2240 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2241 ep_mii_setbit(sc, PHYSMGMT_CLK); 2242 2243 GO_WINDOW(1); /* back to operating window */ 2244 2245 return (err ? 0 : val); 2246 } 2247 2248 void 2249 ep_mii_writereg(self, phy, reg, val) 2250 struct device *self; 2251 int phy, reg, val; 2252 { 2253 struct ep_softc *sc = (struct ep_softc *)self; 2254 2255 /* 2256 * Write the PHY register by manually driving the MII control lines. 2257 */ 2258 2259 GO_WINDOW(4); 2260 2261 ep_mii_sync(sc); 2262 ep_mii_sendbits(sc, MII_COMMAND_START, 2); 2263 ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 2264 ep_mii_sendbits(sc, phy, 5); 2265 ep_mii_sendbits(sc, reg, 5); 2266 ep_mii_sendbits(sc, MII_COMMAND_ACK, 2); 2267 ep_mii_sendbits(sc, val, 16); 2268 2269 ep_mii_clrbit(sc, PHYSMGMT_CLK); 2270 ep_mii_setbit(sc, PHYSMGMT_CLK); 2271 2272 GO_WINDOW(1); /* back to operating window */ 2273 } 2274 2275 void 2276 ep_statchg(self) 2277 struct device *self; 2278 { 2279 struct ep_softc *sc = (struct ep_softc *)self; 2280 bus_space_tag_t iot = sc->sc_iot; 2281 bus_space_handle_t ioh = sc->sc_ioh; 2282 int mctl; 2283 2284 /* XXX Update ifp->if_baudrate */ 2285 2286 GO_WINDOW(3); 2287 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 2288 if (sc->sc_mii.mii_media_active & IFM_FDX) 2289 mctl |= MAC_CONTROL_FDX; 2290 else 2291 mctl &= ~MAC_CONTROL_FDX; 2292 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 2293 GO_WINDOW(1); /* back to operating window */ 2294 } 2295
Indexes created Thu Sep 25 16:09:42 GMT 2025