elink3reg.h revision 1.10
1 /* $NetBSD: elink3reg.h,v 1.10 1996/12/29 13:25:23 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Herb Peyerl <hpeyerl (at) beer.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Herb Peyerl. 18 * 4. The name of Herb Peyerl may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * These define the EEPROM data structure. They are used in the probe 36 * function to verify the existance of the adapter after having sent 37 * the ID_Sequence. 38 * 39 * There are others but only the ones we use are defined here. 40 */ 41 #define EEPROM_NODE_ADDR_0 0x0 /* Word */ 42 #define EEPROM_NODE_ADDR_1 0x1 /* Word */ 43 #define EEPROM_NODE_ADDR_2 0x2 /* Word */ 44 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 45 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 46 #define EEPROM_ADDR_CFG 0x8 /* Base addr */ 47 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 48 49 /* 50 * These are the registers for the 3Com 3c509 and their bit patterns when 51 * applicable. They have been taken out the the "EtherLink III Parallel 52 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual 53 * from 3com. 54 */ 55 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */ 56 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */ 57 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */ 58 59 /* 60 * Window 0 registers. Setup. 61 */ 62 /* Write */ 63 #define EP_W0_EEPROM_DATA 0x0c 64 #define EP_W0_EEPROM_COMMAND 0x0a 65 #define EP_W0_RESOURCE_CFG 0x08 66 #define EP_W0_ADDRESS_CFG 0x06 67 #define EP_W0_CONFIG_CTRL 0x04 68 /* Read */ 69 #define EP_W0_PRODUCT_ID 0x02 70 #define EP_W0_MFG_ID 0x00 71 72 /* 73 * Window 1 registers. Operating Set. 74 */ 75 /* Write */ 76 #define EP_W1_TX_PIO_WR_2 0x02 77 #define EP_W1_TX_PIO_WR_1 0x00 78 /* Read */ 79 #define EP_W1_FREE_TX 0x0c 80 #define EP_W1_TX_STATUS 0x0b /* byte */ 81 #define EP_W1_TIMER 0x0a /* byte */ 82 #define EP_W1_RX_STATUS 0x08 83 #define EP_W1_RX_PIO_RD_2 0x02 84 #define EP_W1_RX_PIO_RD_1 0x00 85 86 /* 87 * Window 2 registers. Station Address Setup/Read 88 */ 89 /* Read/Write */ 90 #define EP_W2_RECVMASK_0 0x06 91 #define EP_W2_ADDR_5 0x05 92 #define EP_W2_ADDR_4 0x04 93 #define EP_W2_ADDR_3 0x03 94 #define EP_W2_ADDR_2 0x02 95 #define EP_W2_ADDR_1 0x01 96 #define EP_W2_ADDR_0 0x00 97 98 /* 99 * Window 3 registers. Configuration and FIFO Management. 100 */ 101 /* Read */ 102 #define EP_W3_FREE_TX 0x0c 103 #define EP_W3_FREE_RX 0x0a 104 /* Read/Write, at least on busmastering cards. */ 105 #define EP_W3_INTERNAL_CONFIG 0x00 /* 32 bits */ 106 #define EP_W3_OTHER_INT 0x04 /* 8 bits */ 107 #define EP_W3_PIO_RESERVED 0x05 /* 8 bits */ 108 #define EP_W3_MAC_CONTROL 0x06 /* 16 bits */ 109 #define EP_W3_RESET_OPTIONS 0x08 /* 16 bits */ 110 111 /* 112 * Window 4 registers. Diagnostics. 113 */ 114 /* Read/Write */ 115 #define EP_W4_MEDIA_TYPE 0x0a 116 #define EP_W4_CTRLR_STATUS 0x08 117 #define EP_W4_NET_DIAG 0x06 118 #define EP_W4_FIFO_DIAG 0x04 119 #define EP_W4_HOST_DIAG 0x02 120 #define EP_W4_TX_DIAG 0x00 121 122 /* 123 * Window 5 Registers. Results and Internal status. 124 */ 125 /* Read */ 126 #define EP_W5_READ_0_MASK 0x0c 127 #define EP_W5_INTR_MASK 0x0a 128 #define EP_W5_RX_FILTER 0x08 129 #define EP_W5_RX_EARLY_THRESH 0x06 130 #define EP_W5_TX_AVAIL_THRESH 0x02 131 #define EP_W5_TX_START_THRESH 0x00 132 133 /* 134 * Window 6 registers. Statistics. 135 */ 136 /* Read/Write */ 137 #define TX_TOTAL_OK 0x0c 138 #define RX_TOTAL_OK 0x0a 139 #define TX_DEFERRALS 0x08 140 #define RX_FRAMES_OK 0x07 141 #define TX_FRAMES_OK 0x06 142 #define RX_OVERRUNS 0x05 143 #define TX_COLLISIONS 0x04 144 #define TX_AFTER_1_COLLISION 0x03 145 #define TX_AFTER_X_COLLISIONS 0x02 146 #define TX_NO_SQE 0x01 147 #define TX_CD_LOST 0x00 148 149 /* 150 * Window 7 registers. 151 * Address and length for a single bus-master DMA transfer. 152 */ 153 #define EP_W7_MASTER_ADDDRES 0x00 154 #define EP_W7_RX_ERROR 0x04 155 #define EP_W7_MASTER_LEN 0x06 156 #define EP_W7_RX_STATUS 0x08 157 #define EP_W7_TIMER 0x0a 158 #define EP_W7_TX_STATUS 0x0b 159 #define EP_W7_MASTER_STATUS 0x0c 160 161 /* 162 * Register definitions. 163 */ 164 165 /* 166 * Command register. All windows. 167 * 168 * 16 bit register. 169 * 15-11: 5-bit code for command to be executed. 170 * 10-0: 11-bit arg if any. For commands with no args; 171 * this can be set to anything. 172 */ 173 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms after issuing */ 174 #define WINDOW_SELECT (u_short) (0x1<<11) 175 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to determine 176 whether this is needed. If so; 177 wait 800 uSec before using trans- 178 ceiver. */ 179 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on power-up */ 180 #define RX_ENABLE (u_short) (0x4<<11) 181 #define RX_RESET (u_short) (0x5<<11) 182 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 183 #define TX_ENABLE (u_short) (0x9<<11) 184 #define TX_DISABLE (u_short) (0xa<<11) 185 #define TX_RESET (u_short) (0xb<<11) 186 #define REQ_INTR (u_short) (0xc<<11) 187 188 /* busmastering-cards only? */ 189 #define STATUS_ENABLE (u_short) (0xf<<11) 190 191 /* 192 * The following C_* acknowledge the various interrupts. 193 * Some of them don't do anything. See the manual. 194 */ 195 #define ACK_INTR (u_short) (0x6800) 196 # define C_INTR_LATCH (u_short) (ACK_INTR|0x01) 197 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x02) 198 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x04) 199 # define C_TX_AVAIL (u_short) (ACK_INTR|0x08) 200 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 201 # define C_RX_EARLY (u_short) (ACK_INTR|0x20) 202 # define C_INT_RQD (u_short) (ACK_INTR|0x40) 203 # define C_UPD_STATS (u_short) (ACK_INTR|0x80) 204 #define SET_INTR_MASK (u_short) (0x0e<<11) 205 #define SET_RD_0_MASK (u_short) (0x0f<<11) 206 #define SET_RX_FILTER (u_short) (0x10<<11) 207 # define FIL_INDIVIDUAL (u_short) (0x01) 208 # define FIL_MULTICAST (u_short) (0x02) 209 # define FIL_BRDCST (u_short) (0x04) 210 # define FIL_PROMISC (u_short) (0x08) 211 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 212 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 213 #define SET_TX_START_THRESH (u_short) (0x13<<11) 214 #define START_DMA (u_short) (0x14<<11) /* busmaster-only */ 215 #define STATS_ENABLE (u_short) (0x15<<11) 216 #define STATS_DISABLE (u_short) (0x16<<11) 217 #define STOP_TRANSCEIVER (u_short) (0x17<<11) 218 219 /* Only on adapters that support power management: */ 220 #define POWERUP (u_short) (0x1b<<11) 221 #define POWERDOWN (u_short) (0x1c<<11) 222 #define POWERAUTO (u_short) (0x1d<<11) 223 224 225 226 /* 227 * Command parameter that disables threshold interrupts 228 * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work. 229 * "busmastering" cards need 8188. 230 * The implicit two-bit upshift done by busmastering cards means 231 * a value of 2047 disables threshold interrupts on both. 232 */ 233 #define EP_THRESH_DISABLE 2047 234 235 236 /* 237 * Status register. All windows. 238 * 239 * 15-13: Window number(0-7). 240 * 12: Command_in_progress. 241 * 11: reserved / DMA in progress on busmaster cards. 242 * 10: reserved. 243 * 9: reserved. 244 * 8: reserved / DMA done on busmaster cards. 245 * 7: Update Statistics. 246 * 6: Interrupt Requested. 247 * 5: RX Early. 248 * 4: RX Complete. 249 * 3: TX Available. 250 * 2: TX Complete. 251 * 1: Adapter Failure. 252 * 0: Interrupt Latch. 253 */ 254 #define S_INTR_LATCH (u_short) (0x0001) 255 #define S_CARD_FAILURE (u_short) (0x0002) 256 #define S_TX_COMPLETE (u_short) (0x0004) 257 #define S_TX_AVAIL (u_short) (0x0008) 258 #define S_RX_COMPLETE (u_short) (0x0010) 259 #define S_RX_EARLY (u_short) (0x0020) 260 #define S_INT_RQD (u_short) (0x0040) 261 #define S_UPD_STATS (u_short) (0x0080) 262 #define S_DMA_DONE (u_short) (0x0100) /* DMA cards only */ 263 #define S_DMA_IN_PROGRESS (u_short) (0x0800) /* DMA cards only */ 264 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 265 266 /* 267 * FIFO Registers. RX Status. 268 * 269 * 15: Incomplete or FIFO empty. 270 * 14: 1: Error in RX Packet 0: Incomplete or no error. 271 * 14-11: Type of error. [14-11] 272 * 1000 = Overrun. 273 * 1011 = Run Packet Error. 274 * 1100 = Alignment Error. 275 * 1101 = CRC Error. 276 * 1001 = Oversize Packet Error (>1514 bytes) 277 * 0010 = Dribble Bits. 278 * (all other error codes, no errors.) 279 * 280 * 10-0: RX Bytes (0-1514) 281 */ 282 #define ERR_INCOMPLETE (u_short) (0x8000) 283 #define ERR_RX (u_short) (0x4000) 284 #define ERR_MASK (u_short) (0x7800) 285 #define ERR_OVERRUN (u_short) (0x4000) 286 #define ERR_RUNT (u_short) (0x5800) 287 #define ERR_ALIGNMENT (u_short) (0x6000) 288 #define ERR_CRC (u_short) (0x6800) 289 #define ERR_OVERSIZE (u_short) (0x4800) 290 #define ERR_DRIBBLE (u_short) (0x1000) 291 292 /* 293 * TX Status 294 * 295 * Reports the transmit status of a completed transmission. Writing this 296 * register pops the transmit completion stack. 297 * 298 * Window 1/Port 0x0b. 299 * 300 * 7: Complete 301 * 6: Interrupt on successful transmission requested. 302 * 5: Jabber Error (TP Only, TX Reset required. ) 303 * 4: Underrun (TX Reset required. ) 304 * 3: Maximum Collisions. 305 * 2: TX Status Overflow. 306 * 1-0: Undefined. 307 * 308 */ 309 #define TXS_COMPLETE 0x80 310 #define TXS_INTR_REQ 0x40 311 #define TXS_JABBER 0x20 312 #define TXS_UNDERRUN 0x10 313 #define TXS_MAX_COLLISION 0x08 314 #define TXS_STATUS_OVERFLOW 0x04 315 316 /* 317 * Internal Config and MAC control (Window 3) 318 * Window 3 / Port 0: 32-bit internal config register: 319 * bits 0-2: fifo buffer ram size 320 * 3: ram width (word/byte) (ro) 321 * 4-5: ram speed 322 * 6-7: rom size 323 * 8-15: reserved 324 * 325 * 16-17: ram split (5:3, 3:1, or 1:1). 326 * 18-19: reserved 327 * 20-22: selected media type 328 * 21: unused 329 * 24: (nonvolatile) driver should autoselect media 330 * 25-31: reseerved 331 * 332 * The low-order 16 bits should generally not be changed by software. 333 * Offsets defined for two 16-bit words, to help out 16-bit busses. 334 */ 335 #define CONFIG_RAMSIZE (u_short) 0x0007 336 #define CONFIG_RAMSIZE_SHIFT (u_short) 0 337 338 #define CONFIG_RAMWIDTH (u_short) 0x0008 339 #define CONFIG_RAMWIDTH_SHIFT (u_short) 3 340 341 #define CONFIG_RAMSPEED (u_short) 0x0030 342 #define CONFIG_RAMSPEED_SHIFT (u_short) 4 343 #define CONFIG_ROMSIZE (u_short) 0x00c0 344 #define CONFIG_ROMSIZE_SHIFT (u_short) 6 345 346 /* Window 3/port 2 */ 347 #define CONFIG_RAMSPLIT (u_short) 0x0003 348 #define CONFIG_RAMSPLIT_SHIFT (u_short) 0 349 #define CONFIG_MEDIAMASK (u_short) 0x0070 350 #define CONFIG_MEDIAMASK_SHIFT (u_short) 4 351 352 #define CONFIG_MEDIA_10BASE_T (u_short) 0x00 353 #define CONFIG_MEDIA_AUI (u_short) 0x01 354 #define CONFIG_MEDIA_RESV1 (u_short) 0x02 355 #define CONFIG_MEDIA_10BASE_2 (u_short) 0x03 356 #define CONFIG_MEDIA_100BASE_TX (u_short) 0x04 357 #define CONFIG_MEDIA_100BASE_FX (u_short) 0x05 358 #define CONFIG_MEDIA_MII (u_short) 0x06 359 #define CONFIG_MEDIA_RESV2 (u_short) 0x07 /* 100Base-T4? */ 360 361 362 #define CONFIG_AUTOSELECT (u_short) 0x0100 363 #define CONFIG_AUTOSELECT_SHIFT (u_short) 8 364 365 /* 366 * FIFO Status (Window 4) 367 * 368 * Supports FIFO diagnostics 369 * 370 * Window 4/Port 0x04.1 371 * 372 * 15: 1=RX receiving (RO). Set when a packet is being received 373 * into the RX FIFO. 374 * 14: Reserved 375 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 376 * Requires RX Reset or Global Reset command to recover. 377 * It is generated when you read past the end of a packet - 378 * reading past what has been received so far will give bad 379 * data. 380 * 12: 1=RX status overrun (RO). Set when there are already 8 381 * packets in the RX FIFO. While this bit is set, no additional 382 * packets are received. Requires no action on the part of 383 * the host. The condition is cleared once a packet has been 384 * read out of the RX FIFO. 385 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 386 * may not be an overrun packet yet). While this bit is set, 387 * no additional packets will be received (some additional 388 * bytes can still be pending between the wire and the RX 389 * FIFO). Requires no action on the part of the host. The 390 * condition is cleared once a few bytes have been read out 391 * from the RX FIFO. 392 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 393 * Requires TX Reset or Global Reset command to recover. 394 * Disables Transmitter. 395 * 9-8: Unassigned. 396 * 7-0: Built in self test bits for the RX and TX FIFO's. 397 */ 398 #define FIFOS_RX_RECEIVING (u_short) 0x8000 399 #define FIFOS_RX_UNDERRUN (u_short) 0x2000 400 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000 401 #define FIFOS_RX_OVERRUN (u_short) 0x0800 402 #define FIFOS_TX_OVERRUN (u_short) 0x0400 403 404 /* 405 * Misc defines for various things. 406 */ 407 #define TAG_ADAPTER 0xd0 408 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff 409 #define ENABLE_DRQ_IRQ 0x0001 410 #define MFG_ID 0x506d /* `TCM' */ 411 #define PROD_ID 0x5090 412 #define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \ 413 sc->sc_ioh, EP_COMMAND, WINDOW_SELECT|x) 414 415 /* 416 * ep_connectors softc media-preset bitflags 417 */ 418 #define AUI 0x01 419 #define BNC 0x02 420 #define UTP 0x04 421 #define TX 0x08 422 #define FX 0x10 423 #define T4 0x20 424 #define MII 0x40 425 426 427 /* 428 * ISA/eisa CONFIG_CNTRL media-present bits. 429 * XXX Also used as bus-independent media flags to epconfig(). 430 */ 431 #define IS_AUI (1<<13) 432 #define IS_BNC (1<<12) 433 #define IS_UTP (1<<9) 434 /* 435 * XXX Bogus values to allow 10/100 PCI media. 436 * Should be replaced with Demon, 3c515, or 10/100 PCMCIA equivalents. 437 */ 438 #define IS_100BASE_T4 (1<<8) 439 #define IS_100BASE_TX (1<<9) 440 #define IS_100BASE_FX (1<<10) 441 #define IS_100BASE_MII (1<<11) 442 443 444 /* EEPROM state flags/commands */ 445 #define EEPROM_BUSY (1<<15) 446 #define EEPROM_TST_MODE (1<<14) 447 #define READ_EEPROM (1<<7) 448 449 #define ENABLE_UTP 0xc0 450 #define DISABLE_UTP 0x0 451 #define RX_BYTES_MASK (u_short) (0x07ff) 452 453 /* 454 * PCI configuration-space register media-present bits 455 * (same register as Vortex EP_W3_RESET_OPTIONS, mapped to pci-config space) 456 */ 457 #define IS_PCI_100BASE_T4 (1<<0) 458 #define IS_PCI_100BASE_TX (1<<1) 459 #define IS_PCI_100BASE_FX (1<<2) 460 #define IS_PCI_10BASE_T (1<<3) 461 # define IS_PCI_UTP IS_PCI_10BASE_T 462 #define IS_PCI_BNC (1<<4) 463 #define IS_PCI_AUI (1<<5) 464 #define IS_PCI_100BASE_MII (1<<6) 465 #define IS_PCI_INTERNAL_VCO (1<<8) 466 467 /* Used to probe for large-packet support. */ 468 #define EP_LARGEWIN_PROBE EP_THRESH_DISABLE 469 #define EP_LARGEWIN_MASK 0xffc 470
Indexes created Tue Sep 30 11:09:46 GMT 2025