elink3reg.h revision 1.14
1 /* $NetBSD: elink3reg.h,v 1.14 1998/08/12 18:51:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Herb Peyerl <hpeyerl (at) beer.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Herb Peyerl. 18 * 4. The name of Herb Peyerl may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * These define the EEPROM data structure. They are used in the probe 36 * function to verify the existance of the adapter after having sent 37 * the ID_Sequence. 38 * 39 * There are others but only the ones we use are defined here. 40 */ 41 #define EEPROM_NODE_ADDR_0 0x0 /* Word */ 42 #define EEPROM_NODE_ADDR_1 0x1 /* Word */ 43 #define EEPROM_NODE_ADDR_2 0x2 /* Word */ 44 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 45 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 46 #define EEPROM_ADDR_CFG 0x8 /* Base addr */ 47 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 48 49 /* 50 * These are the registers for the 3Com 3c509 and their bit patterns when 51 * applicable. They have been taken out the the "EtherLink III Parallel 52 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual 53 * from 3com. 54 */ 55 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */ 56 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */ 57 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */ 58 59 /* 60 * Window 0 registers. Setup. 61 */ 62 /* Write */ 63 #define EP_W0_EEPROM_DATA 0x0c 64 #define EP_W0_EEPROM_COMMAND 0x0a 65 #define EP_W0_RESOURCE_CFG 0x08 66 #define EP_W0_ADDRESS_CFG 0x06 67 #define EP_W0_CONFIG_CTRL 0x04 68 /* Read */ 69 #define EP_W0_PRODUCT_ID 0x02 70 #define EP_W0_MFG_ID 0x00 71 72 /* 73 * Window 1 registers. Operating Set. 74 */ 75 /* Write */ 76 #define EP_W1_TX_PIO_WR_2 0x02 77 #define EP_W1_TX_PIO_WR_1 0x00 78 /* Read */ 79 #define EP_W1_FREE_TX 0x0c 80 #define EP_W1_TX_STATUS 0x0b /* byte */ 81 #define EP_W1_TIMER 0x0a /* byte */ 82 #define EP_W1_RX_STATUS 0x08 83 #define EP_W1_RX_PIO_RD_2 0x02 84 #define EP_W1_RX_PIO_RD_1 0x00 85 86 /* 87 * Window 2 registers. Station Address Setup/Read 88 */ 89 /* Read/Write */ 90 #define EP_W2_RECVMASK_0 0x06 91 #define EP_W2_ADDR_5 0x05 92 #define EP_W2_ADDR_4 0x04 93 #define EP_W2_ADDR_3 0x03 94 #define EP_W2_ADDR_2 0x02 95 #define EP_W2_ADDR_1 0x01 96 #define EP_W2_ADDR_0 0x00 97 98 /* 99 * Window 3 registers. Configuration and FIFO Management. 100 */ 101 /* Read */ 102 #define EP_W3_FREE_TX 0x0c 103 #define EP_W3_FREE_RX 0x0a 104 /* Read/Write, at least on busmastering cards. */ 105 #define EP_W3_INTERNAL_CONFIG 0x00 /* 32 bits */ 106 #define EP_W3_OTHER_INT 0x04 /* 8 bits */ 107 #define EP_W3_PIO_RESERVED 0x05 /* 8 bits */ 108 #define EP_W3_MAC_CONTROL 0x06 /* 16 bits */ 109 #define EP_W3_RESET_OPTIONS 0x08 /* 16 bits */ 110 111 /* 112 * Window 4 registers. Diagnostics. 113 */ 114 /* Read/Write */ 115 #define EP_W4_MEDIA_TYPE 0x0a 116 #define EP_W4_CTRLR_STATUS 0x08 117 #define EP_W4_NET_DIAG 0x06 118 #define EP_W4_FIFO_DIAG 0x04 119 #define EP_W4_HOST_DIAG 0x02 120 #define EP_W4_TX_DIAG 0x00 121 122 /* 123 * Window 4 offset 8 is the PHY Management register on the 124 * 3c90x. 125 */ 126 #define EP_W4_BOOM_PHYSMGMT 0x08 127 #define PHYSMGMT_CLK 0x0001 128 #define PHYSMGMT_DATA 0x0002 129 #define PHYSMGMT_DIR 0x0004 130 131 /* 132 * Window 5 Registers. Results and Internal status. 133 */ 134 /* Read */ 135 #define EP_W5_READ_0_MASK 0x0c 136 #define EP_W5_INTR_MASK 0x0a 137 #define EP_W5_RX_FILTER 0x08 138 #define EP_W5_RX_EARLY_THRESH 0x06 139 #define EP_W5_TX_AVAIL_THRESH 0x02 140 #define EP_W5_TX_START_THRESH 0x00 141 142 /* 143 * Window 6 registers. Statistics. 144 */ 145 /* Read/Write */ 146 #define TX_TOTAL_OK 0x0c 147 #define RX_TOTAL_OK 0x0a 148 #define TX_DEFERRALS 0x08 149 #define RX_FRAMES_OK 0x07 150 #define TX_FRAMES_OK 0x06 151 #define RX_OVERRUNS 0x05 152 #define TX_COLLISIONS 0x04 153 #define TX_AFTER_1_COLLISION 0x03 154 #define TX_AFTER_X_COLLISIONS 0x02 155 #define TX_NO_SQE 0x01 156 #define TX_CD_LOST 0x00 157 158 /* 159 * Window 7 registers. 160 * Address and length for a single bus-master DMA transfer. 161 */ 162 #define EP_W7_MASTER_ADDDRES 0x00 163 #define EP_W7_RX_ERROR 0x04 164 #define EP_W7_MASTER_LEN 0x06 165 #define EP_W7_RX_STATUS 0x08 166 #define EP_W7_TIMER 0x0a 167 #define EP_W7_TX_STATUS 0x0b 168 #define EP_W7_MASTER_STATUS 0x0c 169 170 /* 171 * Register definitions. 172 */ 173 174 /* 175 * Command register. All windows. 176 * 177 * 16 bit register. 178 * 15-11: 5-bit code for command to be executed. 179 * 10-0: 11-bit arg if any. For commands with no args; 180 * this can be set to anything. 181 */ 182 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms after issuing */ 183 #define WINDOW_SELECT (u_short) (0x1<<11) 184 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to determine 185 whether this is needed. If so; 186 wait 800 uSec before using trans- 187 ceiver. */ 188 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on power-up */ 189 #define RX_ENABLE (u_short) (0x4<<11) 190 #define RX_RESET (u_short) (0x5<<11) 191 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 192 #define TX_ENABLE (u_short) (0x9<<11) 193 #define TX_DISABLE (u_short) (0xa<<11) 194 #define TX_RESET (u_short) (0xb<<11) 195 #define REQ_INTR (u_short) (0xc<<11) 196 197 /* 198 * The following C_* acknowledge the various interrupts. 199 * Some of them don't do anything. See the manual. 200 */ 201 #define ACK_INTR (u_short) (0xd << 11) 202 # define C_INTR_LATCH (u_short) (ACK_INTR|0x01) 203 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x02) 204 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x04) 205 # define C_TX_AVAIL (u_short) (ACK_INTR|0x08) 206 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 207 # define C_RX_EARLY (u_short) (ACK_INTR|0x20) 208 # define C_INT_RQD (u_short) (ACK_INTR|0x40) 209 # define C_UPD_STATS (u_short) (ACK_INTR|0x80) 210 211 #define SET_INTR_MASK (u_short) (0x0e<<11) 212 213 /* busmastering-cards only? */ 214 #define STATUS_ENABLE (u_short) (0xf<<11) 215 216 #define SET_RD_0_MASK (u_short) (0x0f<<11) 217 218 #define SET_RX_FILTER (u_short) (0x10<<11) 219 # define FIL_INDIVIDUAL (u_short) (0x01) 220 # define FIL_MULTICAST (u_short) (0x02) 221 # define FIL_BRDCST (u_short) (0x04) 222 # define FIL_PROMISC (u_short) (0x08) 223 224 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 225 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 226 #define SET_TX_START_THRESH (u_short) (0x13<<11) 227 #define START_DMA (u_short) (0x14<<11) /* busmaster-only */ 228 # define START_DMA_TX (START_DMA | 0x0)) /* busmaster-only */ 229 # define START_DMA_RX (START_DMA | 0x1) /* busmaster-only */ 230 #define STATS_ENABLE (u_short) (0x15<<11) 231 #define STATS_DISABLE (u_short) (0x16<<11) 232 #define STOP_TRANSCEIVER (u_short) (0x17<<11) 233 234 /* Only on adapters that support power management: */ 235 #define POWERUP (u_short) (0x1b<<11) 236 #define POWERDOWN (u_short) (0x1c<<11) 237 #define POWERAUTO (u_short) (0x1d<<11) 238 239 240 241 /* 242 * Command parameter that disables threshold interrupts 243 * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work. 244 * "busmastering" cards need 8188. 245 * The implicit two-bit upshift done by busmastering cards means 246 * a value of 2047 disables threshold interrupts on both. 247 */ 248 #define EP_THRESH_DISABLE 2047 249 250 251 /* 252 * Status register. All windows. 253 * 254 * 15-13: Window number(0-7). 255 * 12: Command_in_progress. 256 * 11: reserved / DMA in progress on busmaster cards. 257 * 10: reserved. 258 * 9: reserved. 259 * 8: reserved / DMA done on busmaster cards. 260 * 7: Update Statistics. 261 * 6: Interrupt Requested. 262 * 5: RX Early. 263 * 4: RX Complete. 264 * 3: TX Available. 265 * 2: TX Complete. 266 * 1: Adapter Failure. 267 * 0: Interrupt Latch. 268 */ 269 #define S_INTR_LATCH (u_short) (0x0001) 270 #define S_CARD_FAILURE (u_short) (0x0002) 271 #define S_TX_COMPLETE (u_short) (0x0004) 272 #define S_TX_AVAIL (u_short) (0x0008) 273 #define S_RX_COMPLETE (u_short) (0x0010) 274 #define S_RX_EARLY (u_short) (0x0020) 275 #define S_INT_RQD (u_short) (0x0040) 276 #define S_UPD_STATS (u_short) (0x0080) 277 #define S_DMA_DONE (u_short) (0x0100) /* DMA cards only */ 278 #define S_DMA_IN_PROGRESS (u_short) (0x0800) /* DMA cards only */ 279 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 280 281 /* 282 * FIFO Registers. RX Status. 283 * 284 * 15: Incomplete or FIFO empty. 285 * 14: 1: Error in RX Packet 0: Incomplete or no error. 286 * 14-11: Type of error. [14-11] 287 * 1000 = Overrun. 288 * 1011 = Run Packet Error. 289 * 1100 = Alignment Error. 290 * 1101 = CRC Error. 291 * 1001 = Oversize Packet Error (>1514 bytes) 292 * 0010 = Dribble Bits. 293 * (all other error codes, no errors.) 294 * 295 * 10-0: RX Bytes (0-1514) 296 */ 297 #define ERR_INCOMPLETE (u_short) (0x8000) 298 #define ERR_RX (u_short) (0x4000) 299 #define ERR_MASK (u_short) (0x7800) 300 #define ERR_OVERRUN (u_short) (0x4000) 301 #define ERR_RUNT (u_short) (0x5800) 302 #define ERR_ALIGNMENT (u_short) (0x6000) 303 #define ERR_CRC (u_short) (0x6800) 304 #define ERR_OVERSIZE (u_short) (0x4800) 305 #define ERR_DRIBBLE (u_short) (0x1000) 306 307 /* 308 * TX Status 309 * 310 * Reports the transmit status of a completed transmission. Writing this 311 * register pops the transmit completion stack. 312 * 313 * Window 1/Port 0x0b. 314 * 315 * 7: Complete 316 * 6: Interrupt on successful transmission requested. 317 * 5: Jabber Error (TP Only, TX Reset required. ) 318 * 4: Underrun (TX Reset required. ) 319 * 3: Maximum Collisions. 320 * 2: TX Status Overflow. 321 * 1-0: Undefined. 322 * 323 */ 324 #define TXS_COMPLETE 0x80 325 #define TXS_INTR_REQ 0x40 326 #define TXS_JABBER 0x20 327 #define TXS_UNDERRUN 0x10 328 #define TXS_MAX_COLLISION 0x08 329 #define TXS_STATUS_OVERFLOW 0x04 330 331 /* 332 * RX status 333 * Window 1/Port 0x08. 334 */ 335 #define RX_BYTES_MASK (u_short) (0x07ff) 336 337 /* 338 * Internal Config and MAC control (Window 3) 339 * Window 3 / Port 0: 32-bit internal config register: 340 * bits 0-2: fifo buffer ram size 341 * 3: ram width (word/byte) (ro) 342 * 4-5: ram speed 343 * 6-7: rom size 344 * 8-15: reserved 345 * 346 * 16-17: ram split (5:3, 3:1, or 1:1). 347 * 18-19: reserved 348 * 20-22: selected media type 349 * 21: unused 350 * 24: (nonvolatile) driver should autoselect media 351 * 25-31: reseerved 352 * 353 * The low-order 16 bits should generally not be changed by software. 354 * Offsets defined for two 16-bit words, to help out 16-bit busses. 355 */ 356 #define CONFIG_RAMSIZE (u_short) 0x0007 357 #define CONFIG_RAMSIZE_SHIFT (u_short) 0 358 359 #define CONFIG_RAMWIDTH (u_short) 0x0008 360 #define CONFIG_RAMWIDTH_SHIFT (u_short) 3 361 362 #define CONFIG_RAMSPEED (u_short) 0x0030 363 #define CONFIG_RAMSPEED_SHIFT (u_short) 4 364 #define CONFIG_ROMSIZE (u_short) 0x00c0 365 #define CONFIG_ROMSIZE_SHIFT (u_short) 6 366 367 /* Window 3/port 2 */ 368 #define CONFIG_RAMSPLIT (u_short) 0x0003 369 #define CONFIG_RAMSPLIT_SHIFT (u_short) 0 370 #define CONFIG_MEDIAMASK (u_short) 0x0070 371 #define CONFIG_MEDIAMASK_SHIFT (u_short) 4 372 373 /* Active media in EP_W3_RESET_OPTIONS mediamask bits */ 374 375 #define EPMEDIA_10BASE_T (u_short) 0x00 376 #define EPMEDIA_AUI (u_short) 0x01 377 #define EPMEDIA_RESV1 (u_short) 0x02 378 #define EPMEDIA_10BASE_2 (u_short) 0x03 379 #define EPMEDIA_100BASE_TX (u_short) 0x04 380 #define EPMEDIA_100BASE_FX (u_short) 0x05 381 #define EPMEDIA_MII (u_short) 0x06 382 #define EPMEDIA_100BASE_T4 (u_short) 0x07 383 384 385 #define CONFIG_AUTOSELECT (u_short) 0x0100 386 #define CONFIG_AUTOSELECT_SHIFT (u_short) 8 387 388 /* 389 * RESET_OPTIONS (Window 4, on Demon/Vortex/Bomerang only) 390 * also mapped to PCI configuration space on PCI adaptors. 391 * 392 * (same register as Vortex EP_W3_RESET_OPTIONS, mapped to pci-config space) 393 */ 394 #define EP_PCI_100BASE_T4 (1<<0) 395 #define EP_PCI_100BASE_TX (1<<1) 396 #define EP_PCI_100BASE_FX (1<<2) 397 #define EP_PCI_10BASE_T (1<<3) 398 #define EP_PCI_BNC (1<<4) 399 #define EP_PCI_AUI (1<<5) 400 #define EP_PCI_100BASE_MII (1<<6) 401 #define EP_PCI_INTERNAL_VCO (1<<8) 402 403 #define EP_PCI_MEDIAMASK (EP_PCI_100BASE_T4|EP_PCI_100BASE_TX| \ 404 EP_PCI_100BASE_FX|EP_PCI_10BASE_T| \ 405 EP_PCI_BNC|EP_PCI_AUI|EP_PCI_100BASE_MII) 406 407 /* 408 * FIFO Status (Window 4) 409 * 410 * Supports FIFO diagnostics 411 * 412 * Window 4/Port 0x04.1 413 * 414 * 15: 1=RX receiving (RO). Set when a packet is being received 415 * into the RX FIFO. 416 * 14: Reserved 417 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 418 * Requires RX Reset or Global Reset command to recover. 419 * It is generated when you read past the end of a packet - 420 * reading past what has been received so far will give bad 421 * data. 422 * 12: 1=RX status overrun (RO). Set when there are already 8 423 * packets in the RX FIFO. While this bit is set, no additional 424 * packets are received. Requires no action on the part of 425 * the host. The condition is cleared once a packet has been 426 * read out of the RX FIFO. 427 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 428 * may not be an overrun packet yet). While this bit is set, 429 * no additional packets will be received (some additional 430 * bytes can still be pending between the wire and the RX 431 * FIFO). Requires no action on the part of the host. The 432 * condition is cleared once a few bytes have been read out 433 * from the RX FIFO. 434 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 435 * Requires TX Reset or Global Reset command to recover. 436 * Disables Transmitter. 437 * 9-8: Unassigned. 438 * 7-0: Built in self test bits for the RX and TX FIFO's. 439 */ 440 #define FIFOS_RX_RECEIVING (u_short) 0x8000 441 #define FIFOS_RX_UNDERRUN (u_short) 0x2000 442 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000 443 #define FIFOS_RX_OVERRUN (u_short) 0x0800 444 #define FIFOS_TX_OVERRUN (u_short) 0x0400 445 446 /* 447 * ISA/eisa CONFIG_CNTRL media-present bits. 448 */ 449 #define EP_W0_CC_AUI (1<<13) 450 #define EP_W0_CC_BNC (1<<12) 451 #define EP_W0_CC_UTP (1<<9) 452 #define EP_W0_CC_MEDIAMASK (EP_W0_CC_AUI|EP_W0_CC_BNC|EP_W0_CC_UTP) 453 454 455 /* EEPROM state flags/commands */ 456 #define EEPROM_BUSY (1<<15) 457 #define EEPROM_TST_MODE (1<<14) 458 #define READ_EEPROM (1<<7) 459 460 /* window 4, MEDIA_STATUS bits */ 461 #define SQE_ENABLE 0x08 /* Enables SQE on AUI ports */ 462 #define JABBER_GUARD_ENABLE 0x40 463 #define LINKBEAT_ENABLE 0x80 464 #define DISABLE_UTP 0x0 465 #define LINKBEAT_DETECT 0x800 466 467 /* 468 * Misc defines for various things. 469 */ 470 #define TAG_ADAPTER 0xd0 471 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff 472 #define ENABLE_DRQ_IRQ 0x0001 473 #define MFG_ID 0x506d /* `TCM' */ 474 #define PROD_ID_3C509 0x5090 /* 509[0-f] */ 475 #define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \ 476 sc->sc_ioh, EP_COMMAND, WINDOW_SELECT|x) 477 478 479 /* Used to probe for large-packet support. */ 480 #define EP_LARGEWIN_PROBE EP_THRESH_DISABLE 481 #define EP_LARGEWIN_MASK 0xffc 482
Indexes created Tue Sep 30 07:10:03 GMT 2025