elink3reg.h revision 1.16
1 /* $NetBSD: elink3reg.h,v 1.16 1998/08/15 16:47:30 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Herb Peyerl <hpeyerl (at) beer.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Herb Peyerl. 18 * 4. The name of Herb Peyerl may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * These define the EEPROM data structure. They are used in the probe 36 * function to verify the existance of the adapter after having sent 37 * the ID_Sequence. 38 * 39 * There are others but only the ones we use are defined here. 40 */ 41 #define EEPROM_NODE_ADDR_0 0x0 /* Word */ 42 #define EEPROM_NODE_ADDR_1 0x1 /* Word */ 43 #define EEPROM_NODE_ADDR_2 0x2 /* Word */ 44 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 45 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 46 #define EEPROM_ADDR_CFG 0x8 /* Base addr */ 47 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 48 49 /* 50 * These are the registers for the 3Com 3c509 and their bit patterns when 51 * applicable. They have been taken out the the "EtherLink III Parallel 52 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual 53 * from 3com. 54 */ 55 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */ 56 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */ 57 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */ 58 59 /* 60 * Window 0 registers. Setup. 61 */ 62 /* Write */ 63 #define EP_W0_EEPROM_DATA 0x0c 64 #define EP_W0_EEPROM_COMMAND 0x0a 65 #define EP_W0_RESOURCE_CFG 0x08 66 #define EP_W0_ADDRESS_CFG 0x06 67 #define EP_W0_CONFIG_CTRL 0x04 68 /* Read */ 69 #define EP_W0_PRODUCT_ID 0x02 70 #define EP_W0_MFG_ID 0x00 71 72 /* 73 * Window 1 registers. Operating Set. 74 */ 75 /* Write */ 76 #define EP_W1_TX_PIO_WR_2 0x02 77 #define EP_W1_TX_PIO_WR_1 0x00 78 /* Read */ 79 #define EP_W1_FREE_TX 0x0c 80 #define EP_W1_TX_STATUS 0x0b /* byte */ 81 #define EP_W1_TIMER 0x0a /* byte */ 82 #define EP_W1_RX_STATUS 0x08 83 #define EP_W1_RX_PIO_RD_2 0x02 84 #define EP_W1_RX_PIO_RD_1 0x00 85 86 /* 87 * Special registers used by the RoadRunner. These are used to program 88 * a FIFO buffer to reduce the PCMCIA->PCI bridge latency during PIO. 89 */ 90 #define EP_W1_RUNNER_RDCTL 0x16 91 #define EP_W1_RUNNER_WRCTL 0x1c 92 93 /* 94 * Window 2 registers. Station Address Setup/Read 95 */ 96 /* Read/Write */ 97 #define EP_W2_RECVMASK_0 0x06 98 #define EP_W2_ADDR_5 0x05 99 #define EP_W2_ADDR_4 0x04 100 #define EP_W2_ADDR_3 0x03 101 #define EP_W2_ADDR_2 0x02 102 #define EP_W2_ADDR_1 0x01 103 #define EP_W2_ADDR_0 0x00 104 105 /* 106 * Window 3 registers. Configuration and FIFO Management. 107 */ 108 /* Read */ 109 #define EP_W3_FREE_TX 0x0c 110 #define EP_W3_FREE_RX 0x0a 111 /* Read/Write, at least on busmastering cards. */ 112 #define EP_W3_INTERNAL_CONFIG 0x00 /* 32 bits */ 113 #define EP_W3_OTHER_INT 0x04 /* 8 bits */ 114 #define EP_W3_PIO_RESERVED 0x05 /* 8 bits */ 115 #define EP_W3_MAC_CONTROL 0x06 /* 16 bits */ 116 #define EP_W3_RESET_OPTIONS 0x08 /* 16 bits */ 117 118 /* 119 * Window 4 registers. Diagnostics. 120 */ 121 /* Read/Write */ 122 #define EP_W4_MEDIA_TYPE 0x0a 123 #define EP_W4_CTRLR_STATUS 0x08 124 #define EP_W4_NET_DIAG 0x06 125 #define EP_W4_FIFO_DIAG 0x04 126 #define EP_W4_HOST_DIAG 0x02 127 #define EP_W4_TX_DIAG 0x00 128 129 /* 130 * Window 4 offset 8 is the PHY Management register on the 131 * 3c90x. 132 */ 133 #define EP_W4_BOOM_PHYSMGMT 0x08 134 #define PHYSMGMT_CLK 0x0001 135 #define PHYSMGMT_DATA 0x0002 136 #define PHYSMGMT_DIR 0x0004 137 138 /* 139 * Window 5 Registers. Results and Internal status. 140 */ 141 /* Read */ 142 #define EP_W5_READ_0_MASK 0x0c 143 #define EP_W5_INTR_MASK 0x0a 144 #define EP_W5_RX_FILTER 0x08 145 #define EP_W5_RX_EARLY_THRESH 0x06 146 #define EP_W5_TX_AVAIL_THRESH 0x02 147 #define EP_W5_TX_START_THRESH 0x00 148 149 /* 150 * Window 6 registers. Statistics. 151 */ 152 /* Read/Write */ 153 #define TX_TOTAL_OK 0x0c 154 #define RX_TOTAL_OK 0x0a 155 #define TX_DEFERRALS 0x08 156 #define RX_FRAMES_OK 0x07 157 #define TX_FRAMES_OK 0x06 158 #define RX_OVERRUNS 0x05 159 #define TX_COLLISIONS 0x04 160 #define TX_AFTER_1_COLLISION 0x03 161 #define TX_AFTER_X_COLLISIONS 0x02 162 #define TX_NO_SQE 0x01 163 #define TX_CD_LOST 0x00 164 165 /* 166 * Window 7 registers. 167 * Address and length for a single bus-master DMA transfer. 168 */ 169 #define EP_W7_MASTER_ADDDRES 0x00 170 #define EP_W7_RX_ERROR 0x04 171 #define EP_W7_MASTER_LEN 0x06 172 #define EP_W7_RX_STATUS 0x08 173 #define EP_W7_TIMER 0x0a 174 #define EP_W7_TX_STATUS 0x0b 175 #define EP_W7_MASTER_STATUS 0x0c 176 177 /* 178 * Register definitions. 179 */ 180 181 /* 182 * Command register. All windows. 183 * 184 * 16 bit register. 185 * 15-11: 5-bit code for command to be executed. 186 * 10-0: 11-bit arg if any. For commands with no args; 187 * this can be set to anything. 188 */ 189 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms after issuing */ 190 #define WINDOW_SELECT (u_short) (0x1<<11) 191 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to determine 192 whether this is needed. If so; 193 wait 800 uSec before using trans- 194 ceiver. */ 195 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on power-up */ 196 #define RX_ENABLE (u_short) (0x4<<11) 197 #define RX_RESET (u_short) (0x5<<11) 198 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 199 #define TX_ENABLE (u_short) (0x9<<11) 200 #define TX_DISABLE (u_short) (0xa<<11) 201 #define TX_RESET (u_short) (0xb<<11) 202 #define REQ_INTR (u_short) (0xc<<11) 203 204 /* 205 * The following C_* acknowledge the various interrupts. 206 * Some of them don't do anything. See the manual. 207 */ 208 #define ACK_INTR (u_short) (0xd << 11) 209 # define C_INTR_LATCH (u_short) (ACK_INTR|0x01) 210 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x02) 211 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x04) 212 # define C_TX_AVAIL (u_short) (ACK_INTR|0x08) 213 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 214 # define C_RX_EARLY (u_short) (ACK_INTR|0x20) 215 # define C_INT_RQD (u_short) (ACK_INTR|0x40) 216 # define C_UPD_STATS (u_short) (ACK_INTR|0x80) 217 218 #define SET_INTR_MASK (u_short) (0x0e<<11) 219 220 /* busmastering-cards only? */ 221 #define STATUS_ENABLE (u_short) (0xf<<11) 222 223 #define SET_RD_0_MASK (u_short) (0x0f<<11) 224 225 #define SET_RX_FILTER (u_short) (0x10<<11) 226 # define FIL_INDIVIDUAL (u_short) (0x01) 227 # define FIL_MULTICAST (u_short) (0x02) 228 # define FIL_BRDCST (u_short) (0x04) 229 # define FIL_PROMISC (u_short) (0x08) 230 231 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 232 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 233 #define SET_TX_START_THRESH (u_short) (0x13<<11) 234 #define START_DMA (u_short) (0x14<<11) /* busmaster-only */ 235 # define START_DMA_TX (START_DMA | 0x0)) /* busmaster-only */ 236 # define START_DMA_RX (START_DMA | 0x1) /* busmaster-only */ 237 #define STATS_ENABLE (u_short) (0x15<<11) 238 #define STATS_DISABLE (u_short) (0x16<<11) 239 #define STOP_TRANSCEIVER (u_short) (0x17<<11) 240 241 /* Only on adapters that support power management: */ 242 #define POWERUP (u_short) (0x1b<<11) 243 #define POWERDOWN (u_short) (0x1c<<11) 244 #define POWERAUTO (u_short) (0x1d<<11) 245 246 247 248 /* 249 * Command parameter that disables threshold interrupts 250 * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work. 251 * "busmastering" cards need 8188. 252 * The implicit two-bit upshift done by busmastering cards means 253 * a value of 2047 disables threshold interrupts on both. 254 */ 255 #define EP_THRESH_DISABLE 2047 256 257 258 /* 259 * Status register. All windows. 260 * 261 * 15-13: Window number(0-7). 262 * 12: Command_in_progress. 263 * 11: reserved / DMA in progress on busmaster cards. 264 * 10: reserved. 265 * 9: reserved. 266 * 8: reserved / DMA done on busmaster cards. 267 * 7: Update Statistics. 268 * 6: Interrupt Requested. 269 * 5: RX Early. 270 * 4: RX Complete. 271 * 3: TX Available. 272 * 2: TX Complete. 273 * 1: Adapter Failure. 274 * 0: Interrupt Latch. 275 */ 276 #define S_INTR_LATCH (u_short) (0x0001) 277 #define S_CARD_FAILURE (u_short) (0x0002) 278 #define S_TX_COMPLETE (u_short) (0x0004) 279 #define S_TX_AVAIL (u_short) (0x0008) 280 #define S_RX_COMPLETE (u_short) (0x0010) 281 #define S_RX_EARLY (u_short) (0x0020) 282 #define S_INT_RQD (u_short) (0x0040) 283 #define S_UPD_STATS (u_short) (0x0080) 284 #define S_DMA_DONE (u_short) (0x0100) /* DMA cards only */ 285 #define S_DMA_IN_PROGRESS (u_short) (0x0800) /* DMA cards only */ 286 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 287 288 /* 289 * FIFO Registers. RX Status. 290 * 291 * 15: Incomplete or FIFO empty. 292 * 14: 1: Error in RX Packet 0: Incomplete or no error. 293 * 14-11: Type of error. [14-11] 294 * 1000 = Overrun. 295 * 1011 = Run Packet Error. 296 * 1100 = Alignment Error. 297 * 1101 = CRC Error. 298 * 1001 = Oversize Packet Error (>1514 bytes) 299 * 0010 = Dribble Bits. 300 * (all other error codes, no errors.) 301 * 302 * 10-0: RX Bytes (0-1514) 303 */ 304 #define ERR_INCOMPLETE (u_short) (0x8000) 305 #define ERR_RX (u_short) (0x4000) 306 #define ERR_MASK (u_short) (0x7800) 307 #define ERR_OVERRUN (u_short) (0x4000) 308 #define ERR_RUNT (u_short) (0x5800) 309 #define ERR_ALIGNMENT (u_short) (0x6000) 310 #define ERR_CRC (u_short) (0x6800) 311 #define ERR_OVERSIZE (u_short) (0x4800) 312 #define ERR_DRIBBLE (u_short) (0x1000) 313 314 /* 315 * TX Status 316 * 317 * Reports the transmit status of a completed transmission. Writing this 318 * register pops the transmit completion stack. 319 * 320 * Window 1/Port 0x0b. 321 * 322 * 7: Complete 323 * 6: Interrupt on successful transmission requested. 324 * 5: Jabber Error (TP Only, TX Reset required. ) 325 * 4: Underrun (TX Reset required. ) 326 * 3: Maximum Collisions. 327 * 2: TX Status Overflow. 328 * 1-0: Undefined. 329 * 330 */ 331 #define TXS_COMPLETE 0x80 332 #define TXS_INTR_REQ 0x40 333 #define TXS_JABBER 0x20 334 #define TXS_UNDERRUN 0x10 335 #define TXS_MAX_COLLISION 0x08 336 #define TXS_STATUS_OVERFLOW 0x04 337 338 /* 339 * RX status 340 * Window 1/Port 0x08. 341 */ 342 #define RX_BYTES_MASK (u_short) (0x07ff) 343 344 /* 345 * Internal Config and MAC control (Window 3) 346 * Window 3 / Port 0: 32-bit internal config register: 347 * bits 0-2: fifo buffer ram size 348 * 3: ram width (word/byte) (ro) 349 * 4-5: ram speed 350 * 6-7: rom size 351 * 8-15: reserved 352 * 353 * 16-17: ram split (5:3, 3:1, or 1:1). 354 * 18-19: reserved 355 * 20-22: selected media type 356 * 21: unused 357 * 24: (nonvolatile) driver should autoselect media 358 * 25-31: reseerved 359 * 360 * The low-order 16 bits should generally not be changed by software. 361 * Offsets defined for two 16-bit words, to help out 16-bit busses. 362 */ 363 #define CONFIG_RAMSIZE (u_short) 0x0007 364 #define CONFIG_RAMSIZE_SHIFT (u_short) 0 365 366 #define CONFIG_RAMWIDTH (u_short) 0x0008 367 #define CONFIG_RAMWIDTH_SHIFT (u_short) 3 368 369 #define CONFIG_RAMSPEED (u_short) 0x0030 370 #define CONFIG_RAMSPEED_SHIFT (u_short) 4 371 #define CONFIG_ROMSIZE (u_short) 0x00c0 372 #define CONFIG_ROMSIZE_SHIFT (u_short) 6 373 374 /* Window 3/port 2 */ 375 #define CONFIG_RAMSPLIT (u_short) 0x0003 376 #define CONFIG_RAMSPLIT_SHIFT (u_short) 0 377 #define CONFIG_MEDIAMASK (u_short) 0x0070 378 #define CONFIG_MEDIAMASK_SHIFT (u_short) 4 379 380 /* Active media in EP_W3_RESET_OPTIONS mediamask bits */ 381 382 #define EPMEDIA_10BASE_T (u_short) 0x00 383 #define EPMEDIA_AUI (u_short) 0x01 384 #define EPMEDIA_RESV1 (u_short) 0x02 385 #define EPMEDIA_10BASE_2 (u_short) 0x03 386 #define EPMEDIA_100BASE_TX (u_short) 0x04 387 #define EPMEDIA_100BASE_FX (u_short) 0x05 388 #define EPMEDIA_MII (u_short) 0x06 389 #define EPMEDIA_100BASE_T4 (u_short) 0x07 390 391 392 #define CONFIG_AUTOSELECT (u_short) 0x0100 393 #define CONFIG_AUTOSELECT_SHIFT (u_short) 8 394 395 /* 396 * RESET_OPTIONS (Window 3, on Demon/Vortex/Bomerang only) 397 * also mapped to PCI configuration space on PCI adaptors. 398 * 399 * (same register as Vortex EP_W3_RESET_OPTIONS, mapped to pci-config space) 400 */ 401 #define EP_PCI_100BASE_T4 (1<<0) 402 #define EP_PCI_100BASE_TX (1<<1) 403 #define EP_PCI_100BASE_FX (1<<2) 404 #define EP_PCI_10BASE_T (1<<3) 405 #define EP_PCI_BNC (1<<4) 406 #define EP_PCI_AUI (1<<5) 407 #define EP_PCI_100BASE_MII (1<<6) 408 #define EP_PCI_INTERNAL_VCO (1<<8) 409 410 #define EP_PCI_MEDIAMASK (EP_PCI_100BASE_T4|EP_PCI_100BASE_TX| \ 411 EP_PCI_100BASE_FX|EP_PCI_10BASE_T| \ 412 EP_PCI_BNC|EP_PCI_AUI|EP_PCI_100BASE_MII) 413 414 /* 415 * FIFO Status (Window 4) 416 * 417 * Supports FIFO diagnostics 418 * 419 * Window 4/Port 0x04.1 420 * 421 * 15: 1=RX receiving (RO). Set when a packet is being received 422 * into the RX FIFO. 423 * 14: Reserved 424 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 425 * Requires RX Reset or Global Reset command to recover. 426 * It is generated when you read past the end of a packet - 427 * reading past what has been received so far will give bad 428 * data. 429 * 12: 1=RX status overrun (RO). Set when there are already 8 430 * packets in the RX FIFO. While this bit is set, no additional 431 * packets are received. Requires no action on the part of 432 * the host. The condition is cleared once a packet has been 433 * read out of the RX FIFO. 434 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 435 * may not be an overrun packet yet). While this bit is set, 436 * no additional packets will be received (some additional 437 * bytes can still be pending between the wire and the RX 438 * FIFO). Requires no action on the part of the host. The 439 * condition is cleared once a few bytes have been read out 440 * from the RX FIFO. 441 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 442 * Requires TX Reset or Global Reset command to recover. 443 * Disables Transmitter. 444 * 9-8: Unassigned. 445 * 7-0: Built in self test bits for the RX and TX FIFO's. 446 */ 447 #define FIFOS_RX_RECEIVING (u_short) 0x8000 448 #define FIFOS_RX_UNDERRUN (u_short) 0x2000 449 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000 450 #define FIFOS_RX_OVERRUN (u_short) 0x0800 451 #define FIFOS_TX_OVERRUN (u_short) 0x0400 452 453 /* 454 * ISA/eisa CONFIG_CNTRL media-present bits. 455 */ 456 #define EP_W0_CC_AUI (1<<13) 457 #define EP_W0_CC_BNC (1<<12) 458 #define EP_W0_CC_UTP (1<<9) 459 #define EP_W0_CC_MEDIAMASK (EP_W0_CC_AUI|EP_W0_CC_BNC|EP_W0_CC_UTP) 460 461 462 /* EEPROM state flags/commands */ 463 #define EEPROM_BUSY (1<<15) 464 #define EEPROM_TST_MODE (1<<14) 465 #define READ_EEPROM (1<<7) 466 467 /* window 4, MEDIA_STATUS bits */ 468 #define SQE_ENABLE 0x08 /* Enables SQE on AUI ports */ 469 #define JABBER_GUARD_ENABLE 0x40 470 #define LINKBEAT_ENABLE 0x80 471 #define DISABLE_UTP 0x0 472 #define LINKBEAT_DETECT 0x800 473 474 /* 475 * Misc defines for various things. 476 */ 477 #define TAG_ADAPTER 0xd0 478 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff 479 #define ENABLE_DRQ_IRQ 0x0001 480 #define MFG_ID 0x506d /* `TCM' */ 481 #define PROD_ID_3C509 0x5090 /* 509[0-f] */ 482 #define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \ 483 sc->sc_ioh, EP_COMMAND, WINDOW_SELECT|x) 484 485 486 /* Used to probe for large-packet support. */ 487 #define EP_LARGEWIN_PROBE EP_THRESH_DISABLE 488 #define EP_LARGEWIN_MASK 0xffc 489
Indexes created Tue Sep 30 20:09:53 GMT 2025