elink3reg.h revision 1.20
1 /* $NetBSD: elink3reg.h,v 1.20 1999/04/28 22:47:44 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Herb Peyerl <hpeyerl (at) beer.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Herb Peyerl. 18 * 4. The name of Herb Peyerl may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * These define the EEPROM data structure. They are used in the probe 36 * function to verify the existance of the adapter after having sent 37 * the ID_Sequence. 38 */ 39 #define EEPROM_NODE_ADDR_0 0x0 /* Word */ 40 #define EEPROM_NODE_ADDR_1 0x1 /* Word */ 41 #define EEPROM_NODE_ADDR_2 0x2 /* Word */ 42 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 43 #define EEPROM_MFG_DATE 0x4 /* Manufacturing date */ 44 #define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */ 45 #define EEPROM_MFG_PRODUCT 0x6 /* Product code */ 46 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 47 #define EEPROM_ADDR_CFG 0x8 /* Base addr */ 48 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 49 #define EEPROM_OEM_ADDR0 0xa 50 #define EEPROM_OEM_ADDR1 0xb 51 #define EEPROM_OEM_ADDR2 0xc 52 #define EEPROM_SOFTINFO 0xd 53 #define EEPROM_COMPAT 0xe 54 #define EEPROM_SOFTINFO2 0xf 55 #define EEPROM_CAP 0x10 56 #define EEPROM_CONFIG_LOW 0x12 57 #define EEPROM_CONFIG_HIGH 0x13 58 #define EEPROM_SSI 0x14 59 #define EEPROM_CHECKSUM_EL3 0x17 60 61 /* 62 * These are the registers for the 3Com 3c509 and their bit patterns when 63 * applicable. They have been taken out the the "EtherLink III Parallel 64 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual 65 * from 3com. 66 */ 67 #define ELINK_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */ 68 #define ELINK_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */ 69 #define ELINK_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */ 70 71 /* 72 * Window 0 registers. Setup. 73 */ 74 /* Write */ 75 #define ELINK_W0_EEPROM_DATA 0x0c 76 #define ELINK_W0_EEPROM_COMMAND 0x0a 77 #define ELINK_W0_RESOURCE_CFG 0x08 78 #define ELINK_W0_ADDRESS_CFG 0x06 79 #define ELINK_W0_CONFIG_CTRL 0x04 80 /* Read */ 81 #define ELINK_W0_PRODUCT_ID 0x02 82 #define ELINK_W0_MFG_ID 0x00 83 84 /* 85 * Window 1 registers. Operating Set. 86 */ 87 /* Write */ 88 #define ELINK_W1_TX_PIO_WR_2 0x02 89 #define ELINK_W1_TX_PIO_WR_1 0x00 90 /* Read */ 91 #define ELINK_W1_FREE_TX 0x0c 92 #define ELINK_W1_TX_STATUS 0x0b /* byte */ 93 #define ELINK_W1_TIMER 0x0a /* byte */ 94 #define ELINK_W1_RX_STATUS 0x08 95 #define ELINK_W1_RX_PIO_RD_2 0x02 96 #define ELINK_W1_RX_PIO_RD_1 0x00 97 /* 98 * Special registers used by the RoadRunner. These are used to program 99 * a FIFO buffer to reduce the PCMCIA->PCI bridge latency during PIO. 100 */ 101 #define ELINK_W1_RUNNER_RDCTL 0x16 102 #define ELINK_W1_RUNNER_WRCTL 0x1c 103 104 /* 105 * Window 2 registers. Station Address Setup/Read 106 */ 107 /* Read/Write */ 108 #define ELINK_W2_RECVMASK_0 0x06 109 #define ELINK_W2_ADDR_5 0x05 110 #define ELINK_W2_ADDR_4 0x04 111 #define ELINK_W2_ADDR_3 0x03 112 #define ELINK_W2_ADDR_2 0x02 113 #define ELINK_W2_ADDR_1 0x01 114 #define ELINK_W2_ADDR_0 0x00 115 116 /* 117 * Window 3 registers. Configuration and FIFO Management. 118 */ 119 /* Read */ 120 #define ELINK_W3_FREE_TX 0x0c 121 #define ELINK_W3_FREE_RX 0x0a 122 /* Read/Write, at least on busmastering cards. */ 123 #define ELINK_W3_INTERNAL_CONFIG 0x00 /* 32 bits */ 124 #define ELINK_W3_OTHER_INT 0x04 /* 8 bits */ 125 #define ELINK_W3_PIO_RESERVED 0x05 /* 8 bits */ 126 #define ELINK_W3_MAC_CONTROL 0x06 /* 16 bits */ 127 #define ELINK_W3_RESET_OPTIONS 0x08 /* 16 bits */ 128 129 /* 130 * Window 4 registers. Diagnostics. 131 */ 132 /* Read/Write */ 133 #define ELINK_W4_MEDIA_TYPE 0x0a 134 #define ELINK_W4_CTRLR_STATUS 0x08 135 #define ELINK_W4_NET_DIAG 0x06 136 #define ELINK_W4_FIFO_DIAG 0x04 137 #define ELINK_W4_HOST_DIAG 0x02 138 #define ELINK_W4_TX_DIAG 0x00 139 140 /* 141 * Window 4 offset 8 is the PHY Management register on the 142 * 3c90x. 143 */ 144 #define ELINK_W4_BOOM_PHYSMGMT 0x08 145 #define PHYSMGMT_CLK 0x0001 146 #define PHYSMGMT_DATA 0x0002 147 #define PHYSMGMT_DIR 0x0004 148 149 150 /* 151 * Window 5 Registers. Results and Internal status. 152 */ 153 /* Read */ 154 #define ELINK_W5_READ_0_MASK 0x0c 155 #define ELINK_W5_INTR_MASK 0x0a 156 #define ELINK_W5_RX_FILTER 0x08 157 #define ELINK_W5_RX_EARLY_THRESH 0x06 158 #define ELINK_W5_TX_AVAIL_THRESH 0x02 159 #define ELINK_W5_TX_START_THRESH 0x00 160 161 /* 162 * Window 6 registers. Statistics. 163 */ 164 /* Read/Write */ 165 #define TX_TOTAL_OK 0x0c 166 #define RX_TOTAL_OK 0x0a 167 #define UPPER_FRAMES_OK 0x09 168 #define TX_DEFERRALS 0x08 169 #define RX_FRAMES_OK 0x07 170 #define TX_FRAMES_OK 0x06 171 #define RX_OVERRUNS 0x05 172 #define TX_COLLISIONS 0x04 173 #define TX_AFTER_1_COLLISION 0x03 174 #define TX_AFTER_X_COLLISIONS 0x02 175 #define TX_NO_SQE 0x01 176 #define TX_CD_LOST 0x00 177 178 /* 179 * Window 7 registers. 180 * Address and length for a single bus-master DMA transfer. 181 * Unused for elink3 cards. 182 */ 183 #define ELINK_W7_MASTER_ADDDRES 0x00 184 #define ELINK_W7_RX_ERROR 0x04 185 #define ELINK_W7_MASTER_LEN 0x06 186 #define ELINK_W7_RX_STATUS 0x08 187 #define ELINK_W7_TIMER 0x0a 188 #define ELINK_W7_TX_STATUS 0x0b 189 #define ELINK_W7_MASTER_STATUS 0x0c 190 191 /* 192 * Register definitions. 193 */ 194 195 /* 196 * Command register. All windows. 197 * 198 * 16 bit register. 199 * 15-11: 5-bit code for command to be executed. 200 * 10-0: 11-bit arg if any. For commands with no args; 201 * this can be set to anything. 202 */ 203 #define GLOBAL_RESET (u_int16_t) 0x0000 /* Wait at least 1ms after issuing */ 204 #define WINDOW_SELECT (u_int16_t) (0x1<<11) 205 #define START_TRANSCEIVER (u_int16_t) (0x2<<11) /* Read ADDR_CFG reg to determine 206 whether this is needed. If so; 207 wait 800 uSec before using trans- 208 ceiver. */ 209 #define RX_DISABLE (u_int16_t) (0x3<<11) /* state disabled on power-up */ 210 #define RX_ENABLE (u_int16_t) (0x4<<11) 211 #define RX_RESET (u_int16_t) (0x5<<11) 212 #define RX_DISCARD_TOP_PACK (u_int16_t) (0x8<<11) 213 #define TX_ENABLE (u_int16_t) (0x9<<11) 214 #define TX_DISABLE (u_int16_t) (0xa<<11) 215 #define TX_RESET (u_int16_t) (0xb<<11) 216 #define REQ_INTR (u_int16_t) (0xc<<11) 217 218 /* 219 * The following C_* acknowledge the various interrupts. 220 * Some of them don't do anything. See the manual. 221 */ 222 #define ACK_INTR (u_int16_t) (0xd << 11) 223 # define C_INTR_LATCH (u_int16_t) (ACK_INTR|0x01) 224 # define C_CARD_FAILURE (u_int16_t) (ACK_INTR|0x02) 225 # define C_TX_COMPLETE (u_int16_t) (ACK_INTR|0x04) 226 # define C_TX_AVAIL (u_int16_t) (ACK_INTR|0x08) 227 # define C_RX_COMPLETE (u_int16_t) (ACK_INTR|0x10) 228 # define C_RX_EARLY (u_int16_t) (ACK_INTR|0x20) 229 # define C_INT_RQD (u_int16_t) (ACK_INTR|0x40) 230 # define C_UPD_STATS (u_int16_t) (ACK_INTR|0x80) 231 232 #define SET_INTR_MASK (u_int16_t) (0x0e<<11) 233 234 /* busmastering-cards only? */ 235 #define STATUS_ENABLE (u_int16_t) (0xf<<11) 236 237 #define SET_RD_0_MASK (u_int16_t) (0x0f<<11) 238 239 #define SET_RX_FILTER (u_int16_t) (0x10<<11) 240 # define FIL_INDIVIDUAL (u_int16_t) (0x01) 241 # define FIL_MULTICAST (u_int16_t) (0x02) 242 # define FIL_BRDCST (u_int16_t) (0x04) 243 # define FIL_PROMISC (u_int16_t) (0x08) 244 245 #define SET_RX_EARLY_THRESH (u_int16_t) (0x11<<11) 246 #define SET_TX_AVAIL_THRESH (u_int16_t) (0x12<<11) 247 #define SET_TX_START_THRESH (u_int16_t) (0x13<<11) 248 #define START_DMA (u_int16_t) (0x14<<11) /* busmaster-only */ 249 # define START_DMA_TX (START_DMA | 0x0)) /* busmaster-only */ 250 # define START_DMA_RX (START_DMA | 0x1) /* busmaster-only */ 251 #define STATS_ENABLE (u_int16_t) (0x15<<11) 252 #define STATS_DISABLE (u_int16_t) (0x16<<11) 253 #define STOP_TRANSCEIVER (u_int16_t) (0x17<<11) 254 255 /* Only on adapters that support power management: */ 256 #define POWERUP (u_int16_t) (0x1b<<11) 257 #define POWERDOWN (u_int16_t) (0x1c<<11) 258 #define POWERAUTO (u_int16_t) (0x1d<<11) 259 260 261 262 /* 263 * Command parameter that disables threshold interrupts 264 * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work. 265 * "busmastering" cards need 8188. 266 * The implicit two-bit upshift done by busmastering cards means 267 * a value of 2047 disables threshold interrupts on both. 268 */ 269 #define ELINK_THRESH_DISABLE 2047 270 271 272 /* 273 * Status register. All windows. 274 * 275 * 15-13: Window number(0-7). 276 * 12: Command_in_progress. 277 * 11: reserved / DMA in progress on busmaster cards. 278 * 10: reserved. 279 * 9: reserved. 280 * 8: reserved / DMA done on busmaster cards. 281 * 7: Update Statistics. 282 * 6: Interrupt Requested. 283 * 5: RX Early. 284 * 4: RX Complete. 285 * 3: TX Available. 286 * 2: TX Complete. 287 * 1: Adapter Failure. 288 * 0: Interrupt Latch. 289 */ 290 #define S_INTR_LATCH (u_int16_t) (0x0001) 291 #define S_CARD_FAILURE (u_int16_t) (0x0002) 292 #define S_TX_COMPLETE (u_int16_t) (0x0004) 293 #define S_TX_AVAIL (u_int16_t) (0x0008) 294 #define S_RX_COMPLETE (u_int16_t) (0x0010) 295 #define S_RX_EARLY (u_int16_t) (0x0020) 296 #define S_INT_RQD (u_int16_t) (0x0040) 297 #define S_UPD_STATS (u_int16_t) (0x0080) 298 #define S_DMA_DONE (u_int16_t) (0x0100) /* DMA cards only */ 299 #define S_DMA_IN_PROGRESS (u_int16_t) (0x0800) /* DMA cards only */ 300 #define S_COMMAND_IN_PROGRESS (u_int16_t) (0x1000) 301 302 /* 303 * FIFO Registers. RX Status. 304 * 305 * 15: Incomplete or FIFO empty. 306 * 14: 1: Error in RX Packet 0: Incomplete or no error. 307 * 14-11: Type of error. [14-11] 308 * 1000 = Overrun. 309 * 1011 = Run Packet Error. 310 * 1100 = Alignment Error. 311 * 1101 = CRC Error. 312 * 1001 = Oversize Packet Error (>1514 bytes) 313 * 0010 = Dribble Bits. 314 * (all other error codes, no errors.) 315 * 316 * 10-0: RX Bytes (0-1514) 317 */ 318 #define ERR_INCOMPLETE (u_int16_t) (0x8000) 319 #define ERR_RX (u_int16_t) (0x4000) 320 #define ERR_MASK (u_int16_t) (0x7800) 321 #define ERR_OVERRUN (u_int16_t) (0x4000) 322 #define ERR_RUNT (u_int16_t) (0x5800) 323 #define ERR_ALIGNMENT (u_int16_t) (0x6000) 324 #define ERR_CRC (u_int16_t) (0x6800) 325 #define ERR_OVERSIZE (u_int16_t) (0x4800) 326 #define ERR_DRIBBLE (u_int16_t) (0x1000) 327 328 /* 329 * TX Status 330 * 331 * Reports the transmit status of a completed transmission. Writing this 332 * register pops the transmit completion stack. 333 * 334 * Window 1/Port 0x0b. 335 * 336 * 7: Complete 337 * 6: Interrupt on successful transmission requested. 338 * 5: Jabber Error (TP Only, TX Reset required. ) 339 * 4: Underrun (TX Reset required. ) 340 * 3: Maximum Collisions. 341 * 2: TX Status Overflow. 342 * 1-0: Undefined. 343 * 344 */ 345 #define TXS_COMPLETE 0x80 346 #define TXS_INTR_REQ 0x40 347 #define TXS_JABBER 0x20 348 #define TXS_UNDERRUN 0x10 349 #define TXS_MAX_COLLISION 0x08 350 #define TXS_STATUS_OVERFLOW 0x04 351 352 /* 353 * RX status 354 * Window 1/Port 0x08. 355 */ 356 #define RX_BYTES_MASK (u_int16_t) (0x07ff) 357 358 /* 359 * Internal Config and MAC control (Window 3) 360 * Window 3 / Port 0: 32-bit internal config register: 361 * bits 0-2: fifo buffer ram size 362 * 3: ram width (word/byte) (ro) 363 * 4-5: ram speed 364 * 6-7: rom size 365 * 8-15: reserved 366 * 367 * 16-17: ram split (5:3, 3:1, or 1:1). 368 * 18-19: reserved 369 * 20-22: selected media type 370 * 21: unused 371 * 24: (nonvolatile) driver should autoselect media 372 * 25-31: reseerved 373 * 374 * The low-order 16 bits should generally not be changed by software. 375 * Offsets defined for two 16-bit words, to help out 16-bit busses. 376 */ 377 #define CONFIG_RAMSIZE (u_int16_t) 0x0007 378 #define CONFIG_RAMSIZE_SHIFT 0 379 380 #define CONFIG_RAMWIDTH (u_int16_t) 0x0008 381 #define CONFIG_RAMWIDTH_SHIFT 3 382 383 #define CONFIG_RAMSPEED (u_int16_t) 0x0030 384 #define CONFIG_RAMSPEED_SHIFT 4 385 #define CONFIG_ROMSIZE (u_int16_t) 0x00c0 386 #define CONFIG_ROMSIZE_SHIFT 6 387 388 /* Window 3/port 2 */ 389 #define CONFIG_RAMSPLIT (u_int16_t) 0x0003 390 #define CONFIG_RAMSPLIT_SHIFT 0 391 #define CONFIG_MEDIAMASK (u_int16_t) 0x0070 392 #define CONFIG_MEDIAMASK_SHIFT 4 393 394 #define CONFIG_AUTOSELECT (u_int16_t) 0x0100 395 #define CONFIG_AUTOSELECT_SHIFT 8 396 397 /* 398 * MAC_CONTROL (Window 3) 399 */ 400 #define MAC_CONTROL_FDX 0x20 /* full-duplex mode */ 401 402 403 /* Active media in INTERNAL_CONFIG media bits */ 404 405 #define ELINKMEDIA_10BASE_T (u_int16_t) 0x00 406 #define ELINKMEDIA_AUI (u_int16_t) 0x01 407 #define ELINKMEDIA_RESV1 (u_int16_t) 0x02 408 #define ELINKMEDIA_10BASE_2 (u_int16_t) 0x03 409 #define ELINKMEDIA_100BASE_TX (u_int16_t) 0x04 410 #define ELINKMEDIA_100BASE_FX (u_int16_t) 0x05 411 #define ELINKMEDIA_MII (u_int16_t) 0x06 412 #define ELINKMEDIA_100BASE_T4 (u_int16_t) 0x07 413 414 415 /* 416 * RESET_OPTIONS (Window 3, on Demon/Vortex/Bomerang only) 417 * also mapped to PCI configuration space on PCI adaptors. 418 * 419 * (same register as Vortex ELINK_W3_RESET_OPTIONS, mapped to pci-config space) 420 */ 421 #define ELINK_PCI_100BASE_T4 (1<<0) 422 #define ELINK_PCI_100BASE_TX (1<<1) 423 #define ELINK_PCI_100BASE_FX (1<<2) 424 #define ELINK_PCI_10BASE_T (1<<3) 425 #define ELINK_PCI_BNC (1<<4) 426 #define ELINK_PCI_AUI (1<<5) 427 #define ELINK_PCI_100BASE_MII (1<<6) 428 #define ELINK_PCI_INTERNAL_VCO (1<<8) 429 430 #define ELINK_PCI_MEDIAMASK (ELINK_PCI_100BASE_T4|ELINK_PCI_100BASE_TX| \ 431 ELINK_PCI_100BASE_FX|ELINK_PCI_10BASE_T| \ 432 ELINK_PCI_BNC|ELINK_PCI_AUI| \ 433 ELINK_PCI_100BASE_MII) 434 435 #define ELINK_RUNNER_ENABLE_MII 0x8000 436 437 /* 438 * FIFO Status (Window 4) 439 * 440 * Supports FIFO diagnostics 441 * 442 * Window 4/Port 0x04.1 443 * 444 * 15: 1=RX receiving (RO). Set when a packet is being received 445 * into the RX FIFO. 446 * 14: Reserved 447 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 448 * Requires RX Reset or Global Reset command to recover. 449 * It is generated when you read past the end of a packet - 450 * reading past what has been received so far will give bad 451 * data. 452 * 12: 1=RX status overrun (RO). Set when there are already 8 453 * packets in the RX FIFO. While this bit is set, no additional 454 * packets are received. Requires no action on the part of 455 * the host. The condition is cleared once a packet has been 456 * read out of the RX FIFO. 457 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 458 * may not be an overrun packet yet). While this bit is set, 459 * no additional packets will be received (some additional 460 * bytes can still be pending between the wire and the RX 461 * FIFO). Requires no action on the part of the host. The 462 * condition is cleared once a few bytes have been read out 463 * from the RX FIFO. 464 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 465 * Requires TX Reset or Global Reset command to recover. 466 * Disables Transmitter. 467 * 9-8: Unassigned. 468 * 7-0: Built in self test bits for the RX and TX FIFO's. 469 */ 470 #define FIFOS_RX_RECEIVING (u_int16_t) 0x8000 471 #define FIFOS_RX_UNDERRUN (u_int16_t) 0x2000 472 #define FIFOS_RX_STATUS_OVERRUN (u_int16_t) 0x1000 473 #define FIFOS_RX_OVERRUN (u_int16_t) 0x0800 474 #define FIFOS_TX_OVERRUN (u_int16_t) 0x0400 475 476 /* 477 * ISA/eisa CONFIG_CNTRL media-present bits. 478 */ 479 #define ELINK_W0_CC_AUI (1<<13) 480 #define ELINK_W0_CC_BNC (1<<12) 481 #define ELINK_W0_CC_UTP (1<<9) 482 #define ELINK_W0_CC_MEDIAMASK (ELINK_W0_CC_AUI|ELINK_W0_CC_BNC| \ 483 ELINK_W0_CC_UTP) 484 485 /* EEPROM state flags/commands */ 486 #define EEPROM_BUSY (1<<15) 487 #define EEPROM_TST_MODE (1<<14) 488 #define READ_EEPROM (1<<7) 489 490 /* window 4, MEDIA_STATUS bits */ 491 #define SQE_ENABLE 0x08 /* Enables SQE on AUI ports */ 492 #define JABBER_GUARD_ENABLE 0x40 493 #define LINKBEAT_ENABLE 0x80 494 #define DISABLE_UTP 0x0 495 #define LINKBEAT_DETECT 0x800 496 497 /* 498 * Misc defines for various things. 499 */ 500 #define TAG_ADAPTER 0xd0 501 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff 502 #define ENABLE_DRQ_IRQ 0x0001 503 #define MFG_ID 0x506d /* `TCM' */ 504 #define PROD_ID_3C509 0x5090 /* 509[0-f] */ 505 #define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \ 506 sc->sc_ioh, ELINK_COMMAND, WINDOW_SELECT|x) 507 508 509 /* Used to probe for large-packet support. */ 510 #define ELINK_LARGEWIN_PROBE ELINK_THRESH_DISABLE 511 #define ELINK_LARGEWIN_MASK 0xffc 512
Indexes created Tue Sep 30 17:09:57 GMT 2025