elink3reg.h revision 1.4
1 /* $NetBSD: elink3reg.h,v 1.4 1996/09/29 11:19:43 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Herb Peyerl <hpeyerl (at) beer.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Herb Peyerl. 18 * 4. The name of Herb Peyerl may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * These define the EEPROM data structure. They are used in the probe 36 * function to verify the existance of the adapter after having sent 37 * the ID_Sequence. 38 * 39 * There are others but only the ones we use are defined here. 40 */ 41 #define EEPROM_NODE_ADDR_0 0x0 /* Word */ 42 #define EEPROM_NODE_ADDR_1 0x1 /* Word */ 43 #define EEPROM_NODE_ADDR_2 0x2 /* Word */ 44 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 45 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 46 #define EEPROM_ADDR_CFG 0x8 /* Base addr */ 47 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 48 49 /* 50 * These are the registers for the 3Com 3c509 and their bit patterns when 51 * applicable. They have been taken out the the "EtherLink III Parallel 52 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual 53 * from 3com. 54 */ 55 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */ 56 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */ 57 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */ 58 59 /* 60 * Window 0 registers. Setup. 61 */ 62 /* Write */ 63 #define EP_W0_EEPROM_DATA 0x0c 64 #define EP_W0_EEPROM_COMMAND 0x0a 65 #define EP_W0_RESOURCE_CFG 0x08 66 #define EP_W0_ADDRESS_CFG 0x06 67 #define EP_W0_CONFIG_CTRL 0x04 68 /* Read */ 69 #define EP_W0_PRODUCT_ID 0x02 70 #define EP_W0_MFG_ID 0x00 71 72 /* 73 * Window 1 registers. Operating Set. 74 */ 75 /* Write */ 76 #define EP_W1_TX_PIO_WR_2 0x02 77 #define EP_W1_TX_PIO_WR_1 0x00 78 /* Read */ 79 #define EP_W1_FREE_TX 0x0c 80 #define EP_W1_TX_STATUS 0x0b /* byte */ 81 #define EP_W1_TIMER 0x0a /* byte */ 82 #define EP_W1_RX_STATUS 0x08 83 #define EP_W1_RX_PIO_RD_2 0x02 84 #define EP_W1_RX_PIO_RD_1 0x00 85 86 /* 87 * Window 2 registers. Station Address Setup/Read 88 */ 89 /* Read/Write */ 90 #define EP_W2_RECVMASK_0 0x06 91 #define EP_W2_ADDR_5 0x05 92 #define EP_W2_ADDR_4 0x04 93 #define EP_W2_ADDR_3 0x03 94 #define EP_W2_ADDR_2 0x02 95 #define EP_W2_ADDR_1 0x01 96 #define EP_W2_ADDR_0 0x00 97 98 /* 99 * Window 3 registers. FIFO Management. 100 */ 101 /* Read */ 102 #define EP_W3_FREE_TX 0x0c 103 #define EP_W3_FREE_RX 0x0a 104 105 /* 106 * Window 4 registers. Diagnostics. 107 */ 108 /* Read/Write */ 109 #define EP_W4_MEDIA_TYPE 0x0a 110 #define EP_W4_CTRLR_STATUS 0x08 111 #define EP_W4_NET_DIAG 0x06 112 #define EP_W4_FIFO_DIAG 0x04 113 #define EP_W4_HOST_DIAG 0x02 114 #define EP_W4_TX_DIAG 0x00 115 116 /* 117 * Window 5 Registers. Results and Internal status. 118 */ 119 /* Read */ 120 #define EP_W5_READ_0_MASK 0x0c 121 #define EP_W5_INTR_MASK 0x0a 122 #define EP_W5_RX_FILTER 0x08 123 #define EP_W5_RX_EARLY_THRESH 0x06 124 #define EP_W5_TX_AVAIL_THRESH 0x02 125 #define EP_W5_TX_START_THRESH 0x00 126 127 /* 128 * Window 6 registers. Statistics. 129 */ 130 /* Read/Write */ 131 #define TX_TOTAL_OK 0x0c 132 #define RX_TOTAL_OK 0x0a 133 #define TX_DEFERRALS 0x08 134 #define RX_FRAMES_OK 0x07 135 #define TX_FRAMES_OK 0x06 136 #define RX_OVERRUNS 0x05 137 #define TX_COLLISIONS 0x04 138 #define TX_AFTER_1_COLLISION 0x03 139 #define TX_AFTER_X_COLLISIONS 0x02 140 #define TX_NO_SQE 0x01 141 #define TX_CD_LOST 0x00 142 143 /* 144 * Window 7 registers. 145 * Address and length for a single bus-master DMA transfer. 146 */ 147 #define EP_W7_MASTER_ADDDRES 0x00 148 #define EP_W7_RX_ERROR 0x04 149 #define EP_W7_MASTER_LEN 0x06 150 #define EP_W7_RX_STATUS 0x08 151 #define EP_W7_TIMER 0x0a 152 #define EP_W7_TX_STATUS 0x0b 153 #define EP_W7_MASTER_STATUS 0x0c 154 155 /* 156 * Register definitions. 157 */ 158 159 /* 160 * Command register. All windows. 161 * 162 * 16 bit register. 163 * 15-11: 5-bit code for command to be executed. 164 * 10-0: 11-bit arg if any. For commands with no args; 165 * this can be set to anything. 166 */ 167 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms after issuing */ 168 #define WINDOW_SELECT (u_short) (0x1<<11) 169 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to determine 170 whether this is needed. If so; 171 wait 800 uSec before using trans- 172 ceiver. */ 173 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on power-up */ 174 #define RX_ENABLE (u_short) (0x4<<11) 175 #define RX_RESET (u_short) (0x5<<11) 176 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 177 #define TX_ENABLE (u_short) (0x9<<11) 178 #define TX_DISABLE (u_short) (0xa<<11) 179 #define TX_RESET (u_short) (0xb<<11) 180 #define REQ_INTR (u_short) (0xc<<11) 181 182 /* 183 * The following C_* acknowledge the various interrupts. 184 * Some of them don't do anything. See the manual. 185 */ 186 #define ACK_INTR (u_short) (0x6800) 187 # define C_INTR_LATCH (u_short) (ACK_INTR|0x01) 188 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x02) 189 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x04) 190 # define C_TX_AVAIL (u_short) (ACK_INTR|0x08) 191 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 192 # define C_RX_EARLY (u_short) (ACK_INTR|0x20) 193 # define C_INT_RQD (u_short) (ACK_INTR|0x40) 194 # define C_UPD_STATS (u_short) (ACK_INTR|0x80) 195 #define SET_INTR_MASK (u_short) (0x0e<<11) 196 #define SET_RD_0_MASK (u_short) (0x0f<<11) 197 #define SET_RX_FILTER (u_short) (0x10<<11) 198 # define FIL_INDIVIDUAL (u_short) (0x01) 199 # define FIL_MULTICAST (u_short) (0x02) 200 # define FIL_BRDCST (u_short) (0x04) 201 # define FIL_PROMISC (u_short) (0x08) 202 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 203 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 204 #define SET_TX_START_THRESH (u_short) (0x13<<11) 205 #define STATS_ENABLE (u_short) (0x15<<11) 206 #define STATS_DISABLE (u_short) (0x16<<11) 207 #define STOP_TRANSCEIVER (u_short) (0x17<<11) 208 209 /* 210 * Status register. All windows. 211 * 212 * 15-13: Window number(0-7). 213 * 12: Command_in_progress. 214 * 11: reserved. 215 * 10: reserved. 216 * 9: reserved. 217 * 8: reserved. 218 * 7: Update Statistics. 219 * 6: Interrupt Requested. 220 * 5: RX Early. 221 * 4: RX Complete. 222 * 3: TX Available. 223 * 2: TX Complete. 224 * 1: Adapter Failure. 225 * 0: Interrupt Latch. 226 */ 227 #define S_INTR_LATCH (u_short) (0x0001) 228 #define S_CARD_FAILURE (u_short) (0x0002) 229 #define S_TX_COMPLETE (u_short) (0x0004) 230 #define S_TX_AVAIL (u_short) (0x0008) 231 #define S_RX_COMPLETE (u_short) (0x0010) 232 #define S_RX_EARLY (u_short) (0x0020) 233 #define S_INT_RQD (u_short) (0x0040) 234 #define S_UPD_STATS (u_short) (0x0080) 235 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 236 237 /* 238 * FIFO Registers. RX Status. 239 * 240 * 15: Incomplete or FIFO empty. 241 * 14: 1: Error in RX Packet 0: Incomplete or no error. 242 * 14-11: Type of error. [14-11] 243 * 1000 = Overrun. 244 * 1011 = Run Packet Error. 245 * 1100 = Alignment Error. 246 * 1101 = CRC Error. 247 * 1001 = Oversize Packet Error (>1514 bytes) 248 * 0010 = Dribble Bits. 249 * (all other error codes, no errors.) 250 * 251 * 10-0: RX Bytes (0-1514) 252 */ 253 #define ERR_INCOMPLETE (u_short) (0x8000) 254 #define ERR_RX (u_short) (0x4000) 255 #define ERR_MASK (u_short) (0x7800) 256 #define ERR_OVERRUN (u_short) (0x4000) 257 #define ERR_RUNT (u_short) (0x5800) 258 #define ERR_ALIGNMENT (u_short) (0x6000) 259 #define ERR_CRC (u_short) (0x6800) 260 #define ERR_OVERSIZE (u_short) (0x4800) 261 #define ERR_DRIBBLE (u_short) (0x1000) 262 263 /* 264 * TX Status 265 * 266 * Reports the transmit status of a completed transmission. Writing this 267 * register pops the transmit completion stack. 268 * 269 * Window 1/Port 0x0b. 270 * 271 * 7: Complete 272 * 6: Interrupt on successful transmission requested. 273 * 5: Jabber Error (TP Only, TX Reset required. ) 274 * 4: Underrun (TX Reset required. ) 275 * 3: Maximum Collisions. 276 * 2: TX Status Overflow. 277 * 1-0: Undefined. 278 * 279 */ 280 #define TXS_COMPLETE 0x80 281 #define TXS_INTR_REQ 0x40 282 #define TXS_JABBER 0x20 283 #define TXS_UNDERRUN 0x10 284 #define TXS_MAX_COLLISION 0x08 285 #define TXS_STATUS_OVERFLOW 0x04 286 287 /* 288 * FIFO Status (Window 4) 289 * 290 * Supports FIFO diagnostics 291 * 292 * Window 4/Port 0x04.1 293 * 294 * 15: 1=RX receiving (RO). Set when a packet is being received 295 * into the RX FIFO. 296 * 14: Reserved 297 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 298 * Requires RX Reset or Global Reset command to recover. 299 * It is generated when you read past the end of a packet - 300 * reading past what has been received so far will give bad 301 * data. 302 * 12: 1=RX status overrun (RO). Set when there are already 8 303 * packets in the RX FIFO. While this bit is set, no additional 304 * packets are received. Requires no action on the part of 305 * the host. The condition is cleared once a packet has been 306 * read out of the RX FIFO. 307 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 308 * may not be an overrun packet yet). While this bit is set, 309 * no additional packets will be received (some additional 310 * bytes can still be pending between the wire and the RX 311 * FIFO). Requires no action on the part of the host. The 312 * condition is cleared once a few bytes have been read out 313 * from the RX FIFO. 314 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 315 * Requires TX Reset or Global Reset command to recover. 316 * Disables Transmitter. 317 * 9-8: Unassigned. 318 * 7-0: Built in self test bits for the RX and TX FIFO's. 319 */ 320 #define FIFOS_RX_RECEIVING (u_short) 0x8000 321 #define FIFOS_RX_UNDERRUN (u_short) 0x2000 322 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000 323 #define FIFOS_RX_OVERRUN (u_short) 0x0800 324 #define FIFOS_TX_OVERRUN (u_short) 0x0400 325 326 /* 327 * Misc defines for various things. 328 */ 329 #define TAG_ADAPTER 0xd0 330 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff 331 #define ENABLE_DRQ_IRQ 0x0001 332 #define MFG_ID 0x506d /* `TCM' */ 333 #define PROD_ID 0x5090 334 #define GO_WINDOW(x) bus_io_write_2(sc->sc_bc, \ 335 sc->sc_ioh, EP_COMMAND, WINDOW_SELECT|x) 336 #define AUI 0x1 337 #define BNC 0x2 338 #define UTP 0x4 339 #define IS_AUI (1<<13) 340 #define IS_BNC (1<<12) 341 #define IS_UTP (1<<9) 342 #define EEPROM_BUSY (1<<15) 343 #define EEPROM_TST_MODE (1<<14) 344 #define READ_EEPROM (1<<7) 345 #define ENABLE_UTP 0xc0 346 #define DISABLE_UTP 0x0 347 #define RX_BYTES_MASK (u_short) (0x07ff) 348 349 #define IS_PCI_AUI (1<<5) 350 #define IS_PCI_BNC (1<<4) 351 #define IS_PCI_UTP (1<<3) 352
Indexes created Mon Sep 29 21:09:56 GMT 2025