elinkxl.c revision 1.47.2.5 1 1.47.2.5 nathanw /* $NetBSD: elinkxl.c,v 1.47.2.5 2001/11/14 19:14:22 nathanw Exp $ */
2 1.1 fvdl
3 1.1 fvdl /*-
4 1.1 fvdl * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 1.1 fvdl * All rights reserved.
6 1.1 fvdl *
7 1.1 fvdl * This code is derived from software contributed to The NetBSD Foundation
8 1.1 fvdl * by Frank van der Linden.
9 1.1 fvdl *
10 1.1 fvdl * Redistribution and use in source and binary forms, with or without
11 1.1 fvdl * modification, are permitted provided that the following conditions
12 1.1 fvdl * are met:
13 1.1 fvdl * 1. Redistributions of source code must retain the above copyright
14 1.1 fvdl * notice, this list of conditions and the following disclaimer.
15 1.1 fvdl * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 fvdl * notice, this list of conditions and the following disclaimer in the
17 1.1 fvdl * documentation and/or other materials provided with the distribution.
18 1.1 fvdl * 3. All advertising materials mentioning features or use of this software
19 1.1 fvdl * must display the following acknowledgement:
20 1.1 fvdl * This product includes software developed by the NetBSD
21 1.1 fvdl * Foundation, Inc. and its contributors.
22 1.1 fvdl * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 fvdl * contributors may be used to endorse or promote products derived
24 1.1 fvdl * from this software without specific prior written permission.
25 1.1 fvdl *
26 1.1 fvdl * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 fvdl * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 fvdl * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 fvdl * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 fvdl * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 fvdl * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 fvdl * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 fvdl * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 fvdl * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 fvdl * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 fvdl * POSSIBILITY OF SUCH DAMAGE.
37 1.1 fvdl */
38 1.1 fvdl
39 1.47.2.5 nathanw #include <sys/cdefs.h>
40 1.47.2.5 nathanw __KERNEL_RCSID(0, "$NetBSD: elinkxl.c,v 1.47.2.5 2001/11/14 19:14:22 nathanw Exp $");
41 1.47.2.5 nathanw
42 1.1 fvdl #include "bpfilter.h"
43 1.1 fvdl #include "rnd.h"
44 1.1 fvdl
45 1.1 fvdl #include <sys/param.h>
46 1.1 fvdl #include <sys/systm.h>
47 1.30 thorpej #include <sys/callout.h>
48 1.1 fvdl #include <sys/kernel.h>
49 1.1 fvdl #include <sys/mbuf.h>
50 1.1 fvdl #include <sys/socket.h>
51 1.1 fvdl #include <sys/ioctl.h>
52 1.1 fvdl #include <sys/errno.h>
53 1.1 fvdl #include <sys/syslog.h>
54 1.1 fvdl #include <sys/select.h>
55 1.1 fvdl #include <sys/device.h>
56 1.1 fvdl #if NRND > 0
57 1.1 fvdl #include <sys/rnd.h>
58 1.1 fvdl #endif
59 1.1 fvdl
60 1.44 thorpej #include <uvm/uvm_extern.h>
61 1.44 thorpej
62 1.1 fvdl #include <net/if.h>
63 1.1 fvdl #include <net/if_dl.h>
64 1.1 fvdl #include <net/if_ether.h>
65 1.1 fvdl #include <net/if_media.h>
66 1.1 fvdl
67 1.1 fvdl #if NBPFILTER > 0
68 1.1 fvdl #include <net/bpf.h>
69 1.1 fvdl #include <net/bpfdesc.h>
70 1.1 fvdl #endif
71 1.1 fvdl
72 1.1 fvdl #include <machine/cpu.h>
73 1.1 fvdl #include <machine/bus.h>
74 1.1 fvdl #include <machine/intr.h>
75 1.21 thorpej #include <machine/endian.h>
76 1.1 fvdl
77 1.1 fvdl #include <dev/mii/miivar.h>
78 1.1 fvdl #include <dev/mii/mii.h>
79 1.19 thorpej #include <dev/mii/mii_bitbang.h>
80 1.1 fvdl
81 1.1 fvdl #include <dev/ic/elink3reg.h>
82 1.1 fvdl /* #include <dev/ic/elink3var.h> */
83 1.1 fvdl #include <dev/ic/elinkxlreg.h>
84 1.1 fvdl #include <dev/ic/elinkxlvar.h>
85 1.1 fvdl
86 1.1 fvdl #ifdef DEBUG
87 1.1 fvdl int exdebug = 0;
88 1.1 fvdl #endif
89 1.1 fvdl
90 1.1 fvdl /* ifmedia callbacks */
91 1.1 fvdl int ex_media_chg __P((struct ifnet *ifp));
92 1.1 fvdl void ex_media_stat __P((struct ifnet *ifp, struct ifmediareq *req));
93 1.1 fvdl
94 1.1 fvdl void ex_probe_media __P((struct ex_softc *));
95 1.1 fvdl void ex_set_filter __P((struct ex_softc *));
96 1.1 fvdl void ex_set_media __P((struct ex_softc *));
97 1.1 fvdl struct mbuf *ex_get __P((struct ex_softc *, int));
98 1.1 fvdl u_int16_t ex_read_eeprom __P((struct ex_softc *, int));
99 1.42 thorpej int ex_init __P((struct ifnet *));
100 1.1 fvdl void ex_read __P((struct ex_softc *));
101 1.1 fvdl void ex_reset __P((struct ex_softc *));
102 1.1 fvdl void ex_set_mc __P((struct ex_softc *));
103 1.1 fvdl void ex_getstats __P((struct ex_softc *));
104 1.1 fvdl void ex_printstats __P((struct ex_softc *));
105 1.1 fvdl void ex_tick __P((void *));
106 1.1 fvdl
107 1.47 thorpej int ex_enable __P((struct ex_softc *));
108 1.47 thorpej void ex_disable __P((struct ex_softc *));
109 1.47 thorpej void ex_power __P((int, void *));
110 1.47 thorpej
111 1.1 fvdl static int ex_eeprom_busy __P((struct ex_softc *));
112 1.1 fvdl static int ex_add_rxbuf __P((struct ex_softc *, struct ex_rxdesc *));
113 1.1 fvdl static void ex_init_txdescs __P((struct ex_softc *));
114 1.1 fvdl
115 1.1 fvdl static void ex_shutdown __P((void *));
116 1.1 fvdl static void ex_start __P((struct ifnet *));
117 1.1 fvdl static void ex_txstat __P((struct ex_softc *));
118 1.1 fvdl
119 1.1 fvdl int ex_mii_readreg __P((struct device *, int, int));
120 1.1 fvdl void ex_mii_writereg __P((struct device *, int, int, int));
121 1.1 fvdl void ex_mii_statchg __P((struct device *));
122 1.1 fvdl
123 1.2 thorpej void ex_probemedia __P((struct ex_softc *));
124 1.2 thorpej
125 1.2 thorpej /*
126 1.2 thorpej * Structure to map media-present bits in boards to ifmedia codes and
127 1.2 thorpej * printable media names. Used for table-driven ifmedia initialization.
128 1.2 thorpej */
129 1.2 thorpej struct ex_media {
130 1.2 thorpej int exm_mpbit; /* media present bit */
131 1.2 thorpej const char *exm_name; /* name of medium */
132 1.2 thorpej int exm_ifmedia; /* ifmedia word for medium */
133 1.2 thorpej int exm_epmedia; /* ELINKMEDIA_* constant */
134 1.2 thorpej };
135 1.2 thorpej
136 1.2 thorpej /*
137 1.2 thorpej * Media table for 3c90x chips. Note that chips with MII have no
138 1.2 thorpej * `native' media.
139 1.2 thorpej */
140 1.2 thorpej struct ex_media ex_native_media[] = {
141 1.2 thorpej { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T,
142 1.2 thorpej ELINKMEDIA_10BASE_T },
143 1.2 thorpej { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX,
144 1.2 thorpej ELINKMEDIA_10BASE_T },
145 1.2 thorpej { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5,
146 1.2 thorpej ELINKMEDIA_AUI },
147 1.2 thorpej { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2,
148 1.2 thorpej ELINKMEDIA_10BASE_2 },
149 1.2 thorpej { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX,
150 1.2 thorpej ELINKMEDIA_100BASE_TX },
151 1.2 thorpej { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX,
152 1.2 thorpej ELINKMEDIA_100BASE_TX },
153 1.2 thorpej { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX,
154 1.2 thorpej ELINKMEDIA_100BASE_FX },
155 1.2 thorpej { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL,
156 1.2 thorpej ELINKMEDIA_MII },
157 1.2 thorpej { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4,
158 1.2 thorpej ELINKMEDIA_100BASE_T4 },
159 1.2 thorpej { 0, NULL, 0,
160 1.2 thorpej 0 },
161 1.2 thorpej };
162 1.2 thorpej
163 1.1 fvdl /*
164 1.19 thorpej * MII bit-bang glue.
165 1.19 thorpej */
166 1.19 thorpej u_int32_t ex_mii_bitbang_read __P((struct device *));
167 1.19 thorpej void ex_mii_bitbang_write __P((struct device *, u_int32_t));
168 1.19 thorpej
169 1.19 thorpej const struct mii_bitbang_ops ex_mii_bitbang_ops = {
170 1.19 thorpej ex_mii_bitbang_read,
171 1.19 thorpej ex_mii_bitbang_write,
172 1.19 thorpej {
173 1.19 thorpej ELINK_PHY_DATA, /* MII_BIT_MDO */
174 1.19 thorpej ELINK_PHY_DATA, /* MII_BIT_MDI */
175 1.19 thorpej ELINK_PHY_CLK, /* MII_BIT_MDC */
176 1.19 thorpej ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */
177 1.19 thorpej 0, /* MII_BIT_DIR_PHY_HOST */
178 1.19 thorpej }
179 1.19 thorpej };
180 1.19 thorpej
181 1.19 thorpej /*
182 1.1 fvdl * Back-end attach and configure.
183 1.1 fvdl */
184 1.1 fvdl void
185 1.1 fvdl ex_config(sc)
186 1.1 fvdl struct ex_softc *sc;
187 1.1 fvdl {
188 1.1 fvdl struct ifnet *ifp;
189 1.1 fvdl u_int16_t val;
190 1.1 fvdl u_int8_t macaddr[ETHER_ADDR_LEN] = {0};
191 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
192 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
193 1.25 augustss int i, error, attach_stage;
194 1.1 fvdl
195 1.30 thorpej callout_init(&sc->ex_mii_callout);
196 1.30 thorpej
197 1.1 fvdl ex_reset(sc);
198 1.1 fvdl
199 1.1 fvdl val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0);
200 1.1 fvdl macaddr[0] = val >> 8;
201 1.1 fvdl macaddr[1] = val & 0xff;
202 1.1 fvdl val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1);
203 1.1 fvdl macaddr[2] = val >> 8;
204 1.1 fvdl macaddr[3] = val & 0xff;
205 1.1 fvdl val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2);
206 1.1 fvdl macaddr[4] = val >> 8;
207 1.1 fvdl macaddr[5] = val & 0xff;
208 1.1 fvdl
209 1.1 fvdl printf("%s: MAC address %s\n", sc->sc_dev.dv_xname,
210 1.1 fvdl ether_sprintf(macaddr));
211 1.1 fvdl
212 1.40 fvdl if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY|EX_CONF_PHY_POWER)) {
213 1.40 fvdl GO_WINDOW(2);
214 1.40 fvdl val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS);
215 1.40 fvdl if (sc->ex_conf & EX_CONF_INV_LED_POLARITY)
216 1.40 fvdl val |= ELINK_RESET_OPT_LEDPOLAR;
217 1.40 fvdl if (sc->ex_conf & EX_CONF_PHY_POWER)
218 1.40 fvdl val |= ELINK_RESET_OPT_PHYPOWER;
219 1.40 fvdl bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val);
220 1.15 haya }
221 1.15 haya
222 1.1 fvdl attach_stage = 0;
223 1.1 fvdl
224 1.1 fvdl /*
225 1.1 fvdl * Allocate the upload descriptors, and create and load the DMA
226 1.1 fvdl * map for them.
227 1.1 fvdl */
228 1.1 fvdl if ((error = bus_dmamem_alloc(sc->sc_dmat,
229 1.44 thorpej EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1,
230 1.25 augustss &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) {
231 1.1 fvdl printf("%s: can't allocate upload descriptors, error = %d\n",
232 1.1 fvdl sc->sc_dev.dv_xname, error);
233 1.1 fvdl goto fail;
234 1.1 fvdl }
235 1.1 fvdl
236 1.1 fvdl attach_stage = 1;
237 1.1 fvdl
238 1.25 augustss if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg,
239 1.1 fvdl EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd,
240 1.1 fvdl BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
241 1.1 fvdl printf("%s: can't map upload descriptors, error = %d\n",
242 1.1 fvdl sc->sc_dev.dv_xname, error);
243 1.1 fvdl goto fail;
244 1.1 fvdl }
245 1.1 fvdl
246 1.1 fvdl attach_stage = 2;
247 1.1 fvdl
248 1.1 fvdl if ((error = bus_dmamap_create(sc->sc_dmat,
249 1.1 fvdl EX_NUPD * sizeof (struct ex_upd), 1,
250 1.1 fvdl EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT,
251 1.1 fvdl &sc->sc_upd_dmamap)) != 0) {
252 1.1 fvdl printf("%s: can't create upload desc. DMA map, error = %d\n",
253 1.1 fvdl sc->sc_dev.dv_xname, error);
254 1.1 fvdl goto fail;
255 1.1 fvdl }
256 1.1 fvdl
257 1.1 fvdl attach_stage = 3;
258 1.1 fvdl
259 1.1 fvdl if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap,
260 1.1 fvdl sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL,
261 1.1 fvdl BUS_DMA_NOWAIT)) != 0) {
262 1.1 fvdl printf("%s: can't load upload desc. DMA map, error = %d\n",
263 1.1 fvdl sc->sc_dev.dv_xname, error);
264 1.1 fvdl goto fail;
265 1.1 fvdl }
266 1.1 fvdl
267 1.1 fvdl attach_stage = 4;
268 1.1 fvdl
269 1.1 fvdl /*
270 1.1 fvdl * Allocate the download descriptors, and create and load the DMA
271 1.1 fvdl * map for them.
272 1.1 fvdl */
273 1.1 fvdl if ((error = bus_dmamem_alloc(sc->sc_dmat,
274 1.44 thorpej EX_NDPD * sizeof (struct ex_dpd), PAGE_SIZE, 0, &sc->sc_dseg, 1,
275 1.25 augustss &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) {
276 1.1 fvdl printf("%s: can't allocate download descriptors, error = %d\n",
277 1.1 fvdl sc->sc_dev.dv_xname, error);
278 1.1 fvdl goto fail;
279 1.1 fvdl }
280 1.1 fvdl
281 1.1 fvdl attach_stage = 5;
282 1.1 fvdl
283 1.25 augustss if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg,
284 1.1 fvdl EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd,
285 1.1 fvdl BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
286 1.1 fvdl printf("%s: can't map download descriptors, error = %d\n",
287 1.1 fvdl sc->sc_dev.dv_xname, error);
288 1.1 fvdl goto fail;
289 1.1 fvdl }
290 1.47.2.2 nathanw memset(sc->sc_dpd, 0, EX_NDPD * sizeof (struct ex_dpd));
291 1.1 fvdl
292 1.1 fvdl attach_stage = 6;
293 1.1 fvdl
294 1.1 fvdl if ((error = bus_dmamap_create(sc->sc_dmat,
295 1.1 fvdl EX_NDPD * sizeof (struct ex_dpd), 1,
296 1.1 fvdl EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT,
297 1.1 fvdl &sc->sc_dpd_dmamap)) != 0) {
298 1.1 fvdl printf("%s: can't create download desc. DMA map, error = %d\n",
299 1.1 fvdl sc->sc_dev.dv_xname, error);
300 1.1 fvdl goto fail;
301 1.1 fvdl }
302 1.1 fvdl
303 1.1 fvdl attach_stage = 7;
304 1.1 fvdl
305 1.1 fvdl if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap,
306 1.1 fvdl sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL,
307 1.1 fvdl BUS_DMA_NOWAIT)) != 0) {
308 1.1 fvdl printf("%s: can't load download desc. DMA map, error = %d\n",
309 1.1 fvdl sc->sc_dev.dv_xname, error);
310 1.1 fvdl goto fail;
311 1.1 fvdl }
312 1.1 fvdl
313 1.1 fvdl attach_stage = 8;
314 1.1 fvdl
315 1.1 fvdl
316 1.1 fvdl /*
317 1.1 fvdl * Create the transmit buffer DMA maps.
318 1.1 fvdl */
319 1.1 fvdl for (i = 0; i < EX_NDPD; i++) {
320 1.1 fvdl if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
321 1.1 fvdl EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
322 1.1 fvdl &sc->sc_tx_dmamaps[i])) != 0) {
323 1.1 fvdl printf("%s: can't create tx DMA map %d, error = %d\n",
324 1.1 fvdl sc->sc_dev.dv_xname, i, error);
325 1.1 fvdl goto fail;
326 1.1 fvdl }
327 1.1 fvdl }
328 1.1 fvdl
329 1.1 fvdl attach_stage = 9;
330 1.1 fvdl
331 1.1 fvdl /*
332 1.1 fvdl * Create the receive buffer DMA maps.
333 1.1 fvdl */
334 1.1 fvdl for (i = 0; i < EX_NUPD; i++) {
335 1.1 fvdl if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
336 1.1 fvdl EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
337 1.1 fvdl &sc->sc_rx_dmamaps[i])) != 0) {
338 1.1 fvdl printf("%s: can't create rx DMA map %d, error = %d\n",
339 1.1 fvdl sc->sc_dev.dv_xname, i, error);
340 1.1 fvdl goto fail;
341 1.1 fvdl }
342 1.1 fvdl }
343 1.1 fvdl
344 1.1 fvdl attach_stage = 10;
345 1.1 fvdl
346 1.1 fvdl /*
347 1.1 fvdl * Create ring of upload descriptors, only once. The DMA engine
348 1.1 fvdl * will loop over this when receiving packets, stalling if it
349 1.1 fvdl * hits an UPD with a finished receive.
350 1.1 fvdl */
351 1.1 fvdl for (i = 0; i < EX_NUPD; i++) {
352 1.1 fvdl sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i];
353 1.1 fvdl sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i];
354 1.9 thorpej sc->sc_upd[i].upd_frags[0].fr_len =
355 1.21 thorpej htole32((MCLBYTES - 2) | EX_FR_LAST);
356 1.1 fvdl if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) {
357 1.1 fvdl printf("%s: can't allocate or map rx buffers\n",
358 1.1 fvdl sc->sc_dev.dv_xname);
359 1.1 fvdl goto fail;
360 1.1 fvdl }
361 1.1 fvdl }
362 1.1 fvdl
363 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0,
364 1.1 fvdl EX_NUPD * sizeof (struct ex_upd),
365 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
366 1.1 fvdl
367 1.1 fvdl ex_init_txdescs(sc);
368 1.1 fvdl
369 1.1 fvdl attach_stage = 11;
370 1.1 fvdl
371 1.1 fvdl
372 1.1 fvdl GO_WINDOW(3);
373 1.1 fvdl val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS);
374 1.1 fvdl if (val & ELINK_MEDIACAP_MII)
375 1.1 fvdl sc->ex_conf |= EX_CONF_MII;
376 1.1 fvdl
377 1.1 fvdl ifp = &sc->sc_ethercom.ec_if;
378 1.1 fvdl
379 1.2 thorpej /*
380 1.2 thorpej * Initialize our media structures and MII info. We'll
381 1.2 thorpej * probe the MII if we discover that we have one.
382 1.2 thorpej */
383 1.2 thorpej sc->ex_mii.mii_ifp = ifp;
384 1.2 thorpej sc->ex_mii.mii_readreg = ex_mii_readreg;
385 1.2 thorpej sc->ex_mii.mii_writereg = ex_mii_writereg;
386 1.2 thorpej sc->ex_mii.mii_statchg = ex_mii_statchg;
387 1.2 thorpej ifmedia_init(&sc->ex_mii.mii_media, 0, ex_media_chg,
388 1.2 thorpej ex_media_stat);
389 1.2 thorpej
390 1.1 fvdl if (sc->ex_conf & EX_CONF_MII) {
391 1.1 fvdl /*
392 1.1 fvdl * Find PHY, extract media information from it.
393 1.14 fvdl * First, select the right transceiver.
394 1.1 fvdl */
395 1.14 fvdl u_int32_t icfg;
396 1.14 fvdl
397 1.14 fvdl GO_WINDOW(3);
398 1.14 fvdl icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG);
399 1.14 fvdl icfg &= ~(CONFIG_XCVR_SEL << 16);
400 1.14 fvdl if (val & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4))
401 1.14 fvdl icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16);
402 1.14 fvdl if (val & ELINK_MEDIACAP_100BASETX)
403 1.14 fvdl icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16);
404 1.14 fvdl if (val & ELINK_MEDIACAP_100BASEFX)
405 1.14 fvdl icfg |= ELINKMEDIA_100BASE_FX
406 1.14 fvdl << (CONFIG_XCVR_SEL_SHIFT + 16);
407 1.14 fvdl bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg);
408 1.14 fvdl
409 1.23 thorpej mii_attach(&sc->sc_dev, &sc->ex_mii, 0xffffffff,
410 1.24 thorpej MII_PHY_ANY, MII_OFFSET_ANY, 0);
411 1.1 fvdl if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) {
412 1.1 fvdl ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE,
413 1.1 fvdl 0, NULL);
414 1.1 fvdl ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE);
415 1.1 fvdl } else {
416 1.1 fvdl ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO);
417 1.1 fvdl }
418 1.2 thorpej } else
419 1.2 thorpej ex_probemedia(sc);
420 1.1 fvdl
421 1.47.2.2 nathanw strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
422 1.1 fvdl ifp->if_softc = sc;
423 1.1 fvdl ifp->if_start = ex_start;
424 1.1 fvdl ifp->if_ioctl = ex_ioctl;
425 1.1 fvdl ifp->if_watchdog = ex_watchdog;
426 1.42 thorpej ifp->if_init = ex_init;
427 1.42 thorpej ifp->if_stop = ex_stop;
428 1.1 fvdl ifp->if_flags =
429 1.1 fvdl IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
430 1.46 thorpej IFQ_SET_READY(&ifp->if_snd);
431 1.1 fvdl
432 1.43 bouyer /*
433 1.43 bouyer * We can support 802.1Q VLAN-sized frames.
434 1.43 bouyer */
435 1.43 bouyer sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
436 1.43 bouyer
437 1.47.2.1 nathanw /*
438 1.47.2.1 nathanw * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support.
439 1.47.2.1 nathanw */
440 1.47.2.1 nathanw if (sc->ex_conf & EX_CONF_90XB)
441 1.47.2.1 nathanw sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 |
442 1.47.2.1 nathanw IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
443 1.47.2.1 nathanw
444 1.1 fvdl if_attach(ifp);
445 1.1 fvdl ether_ifattach(ifp, macaddr);
446 1.1 fvdl
447 1.1 fvdl GO_WINDOW(1);
448 1.1 fvdl
449 1.1 fvdl sc->tx_start_thresh = 20;
450 1.1 fvdl sc->tx_succ_ok = 0;
451 1.1 fvdl
452 1.1 fvdl /* TODO: set queues to 0 */
453 1.1 fvdl
454 1.1 fvdl #if NRND > 0
455 1.5 explorer rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
456 1.5 explorer RND_TYPE_NET, 0);
457 1.1 fvdl #endif
458 1.1 fvdl
459 1.1 fvdl /* Establish callback to reset card when we reboot. */
460 1.25 augustss sc->sc_sdhook = shutdownhook_establish(ex_shutdown, sc);
461 1.47 thorpej if (sc->sc_sdhook == NULL)
462 1.47 thorpej printf("%s: WARNING: unable to establish shutdown hook\n",
463 1.47 thorpej sc->sc_dev.dv_xname);
464 1.47 thorpej
465 1.47.2.1 nathanw /* Add a suspend hook to make sure we come back up after a resume. */
466 1.47 thorpej sc->sc_powerhook = powerhook_establish(ex_power, sc);
467 1.47 thorpej if (sc->sc_powerhook == NULL)
468 1.47 thorpej printf("%s: WARNING: unable to establish power hook\n",
469 1.47 thorpej sc->sc_dev.dv_xname);
470 1.34 jhawk
471 1.34 jhawk /* The attach is successful. */
472 1.34 jhawk sc->ex_flags |= EX_FLAGS_ATTACHED;
473 1.1 fvdl return;
474 1.1 fvdl
475 1.1 fvdl fail:
476 1.1 fvdl /*
477 1.1 fvdl * Free any resources we've allocated during the failed attach
478 1.1 fvdl * attempt. Do this in reverse order and fall though.
479 1.1 fvdl */
480 1.1 fvdl switch (attach_stage) {
481 1.1 fvdl case 11:
482 1.1 fvdl {
483 1.1 fvdl struct ex_rxdesc *rxd;
484 1.1 fvdl
485 1.1 fvdl for (i = 0; i < EX_NUPD; i++) {
486 1.1 fvdl rxd = &sc->sc_rxdescs[i];
487 1.1 fvdl if (rxd->rx_mbhead != NULL) {
488 1.1 fvdl bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
489 1.1 fvdl m_freem(rxd->rx_mbhead);
490 1.1 fvdl }
491 1.1 fvdl }
492 1.1 fvdl }
493 1.1 fvdl /* FALLTHROUGH */
494 1.1 fvdl
495 1.1 fvdl case 10:
496 1.1 fvdl for (i = 0; i < EX_NUPD; i++)
497 1.1 fvdl bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]);
498 1.1 fvdl /* FALLTHROUGH */
499 1.1 fvdl
500 1.1 fvdl case 9:
501 1.1 fvdl for (i = 0; i < EX_NDPD; i++)
502 1.1 fvdl bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]);
503 1.1 fvdl /* FALLTHROUGH */
504 1.1 fvdl case 8:
505 1.1 fvdl bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap);
506 1.1 fvdl /* FALLTHROUGH */
507 1.1 fvdl
508 1.1 fvdl case 7:
509 1.1 fvdl bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap);
510 1.1 fvdl /* FALLTHROUGH */
511 1.1 fvdl
512 1.1 fvdl case 6:
513 1.1 fvdl bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd,
514 1.1 fvdl EX_NDPD * sizeof (struct ex_dpd));
515 1.1 fvdl /* FALLTHROUGH */
516 1.1 fvdl
517 1.1 fvdl case 5:
518 1.25 augustss bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg);
519 1.1 fvdl break;
520 1.1 fvdl
521 1.1 fvdl case 4:
522 1.1 fvdl bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap);
523 1.1 fvdl /* FALLTHROUGH */
524 1.1 fvdl
525 1.1 fvdl case 3:
526 1.1 fvdl bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap);
527 1.1 fvdl /* FALLTHROUGH */
528 1.1 fvdl
529 1.1 fvdl case 2:
530 1.1 fvdl bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd,
531 1.1 fvdl EX_NUPD * sizeof (struct ex_upd));
532 1.1 fvdl /* FALLTHROUGH */
533 1.1 fvdl
534 1.1 fvdl case 1:
535 1.25 augustss bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg);
536 1.1 fvdl break;
537 1.1 fvdl }
538 1.1 fvdl
539 1.2 thorpej }
540 1.2 thorpej
541 1.2 thorpej /*
542 1.2 thorpej * Find the media present on non-MII chips.
543 1.2 thorpej */
544 1.2 thorpej void
545 1.2 thorpej ex_probemedia(sc)
546 1.2 thorpej struct ex_softc *sc;
547 1.2 thorpej {
548 1.2 thorpej bus_space_tag_t iot = sc->sc_iot;
549 1.2 thorpej bus_space_handle_t ioh = sc->sc_ioh;
550 1.2 thorpej struct ifmedia *ifm = &sc->ex_mii.mii_media;
551 1.2 thorpej struct ex_media *exm;
552 1.2 thorpej u_int16_t config1, reset_options, default_media;
553 1.2 thorpej int defmedia = 0;
554 1.2 thorpej const char *sep = "", *defmedianame = NULL;
555 1.2 thorpej
556 1.2 thorpej GO_WINDOW(3);
557 1.2 thorpej config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2);
558 1.2 thorpej reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS);
559 1.2 thorpej GO_WINDOW(0);
560 1.2 thorpej
561 1.2 thorpej default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT;
562 1.2 thorpej
563 1.2 thorpej printf("%s: ", sc->sc_dev.dv_xname);
564 1.2 thorpej
565 1.2 thorpej /* Sanity check that there are any media! */
566 1.2 thorpej if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) {
567 1.2 thorpej printf("no media present!\n");
568 1.2 thorpej ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL);
569 1.2 thorpej ifmedia_set(ifm, IFM_ETHER|IFM_NONE);
570 1.2 thorpej return;
571 1.2 thorpej }
572 1.2 thorpej
573 1.47.2.5 nathanw #define PRINT(str) printf("%s%s", sep, str); sep = ", "
574 1.2 thorpej
575 1.2 thorpej for (exm = ex_native_media; exm->exm_name != NULL; exm++) {
576 1.2 thorpej if (reset_options & exm->exm_mpbit) {
577 1.2 thorpej /*
578 1.2 thorpej * Default media is a little complicated. We
579 1.2 thorpej * support full-duplex which uses the same
580 1.2 thorpej * reset options bit.
581 1.2 thorpej *
582 1.2 thorpej * XXX Check EEPROM for default to FDX?
583 1.2 thorpej */
584 1.2 thorpej if (exm->exm_epmedia == default_media) {
585 1.2 thorpej if ((exm->exm_ifmedia & IFM_FDX) == 0) {
586 1.2 thorpej defmedia = exm->exm_ifmedia;
587 1.2 thorpej defmedianame = exm->exm_name;
588 1.2 thorpej }
589 1.2 thorpej } else if (defmedia == 0) {
590 1.2 thorpej defmedia = exm->exm_ifmedia;
591 1.2 thorpej defmedianame = exm->exm_name;
592 1.2 thorpej }
593 1.2 thorpej ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia,
594 1.2 thorpej NULL);
595 1.2 thorpej PRINT(exm->exm_name);
596 1.2 thorpej }
597 1.2 thorpej }
598 1.2 thorpej
599 1.2 thorpej #undef PRINT
600 1.2 thorpej
601 1.2 thorpej #ifdef DIAGNOSTIC
602 1.2 thorpej if (defmedia == 0)
603 1.2 thorpej panic("ex_probemedia: impossible");
604 1.2 thorpej #endif
605 1.2 thorpej
606 1.2 thorpej printf(", default %s\n", defmedianame);
607 1.2 thorpej ifmedia_set(ifm, defmedia);
608 1.1 fvdl }
609 1.1 fvdl
610 1.1 fvdl /*
611 1.1 fvdl * Bring device up.
612 1.1 fvdl */
613 1.42 thorpej int
614 1.42 thorpej ex_init(ifp)
615 1.42 thorpej struct ifnet *ifp;
616 1.1 fvdl {
617 1.42 thorpej struct ex_softc *sc = ifp->if_softc;
618 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
619 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
620 1.47 thorpej int i;
621 1.47 thorpej int error = 0;
622 1.1 fvdl
623 1.47 thorpej if ((error = ex_enable(sc)) != 0)
624 1.47 thorpej goto out;
625 1.1 fvdl
626 1.1 fvdl ex_waitcmd(sc);
627 1.42 thorpej ex_stop(ifp, 0);
628 1.1 fvdl
629 1.1 fvdl /*
630 1.1 fvdl * Set the station address and clear the station mask. The latter
631 1.1 fvdl * is needed for 90x cards, 0 is the default for 90xB cards.
632 1.1 fvdl */
633 1.1 fvdl GO_WINDOW(2);
634 1.1 fvdl for (i = 0; i < ETHER_ADDR_LEN; i++) {
635 1.1 fvdl bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i,
636 1.1 fvdl LLADDR(ifp->if_sadl)[i]);
637 1.1 fvdl bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0);
638 1.1 fvdl }
639 1.1 fvdl
640 1.1 fvdl GO_WINDOW(3);
641 1.1 fvdl
642 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET);
643 1.1 fvdl ex_waitcmd(sc);
644 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET);
645 1.1 fvdl ex_waitcmd(sc);
646 1.1 fvdl
647 1.1 fvdl /*
648 1.1 fvdl * Disable reclaim threshold for 90xB, set free threshold to
649 1.1 fvdl * 6 * 256 = 1536 for 90x.
650 1.1 fvdl */
651 1.1 fvdl if (sc->ex_conf & EX_CONF_90XB)
652 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND,
653 1.1 fvdl ELINK_TXRECLTHRESH | 255);
654 1.1 fvdl else
655 1.1 fvdl bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6);
656 1.1 fvdl
657 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND,
658 1.1 fvdl SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE);
659 1.1 fvdl
660 1.1 fvdl bus_space_write_4(iot, ioh, ELINK_DMACTRL,
661 1.1 fvdl bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN);
662 1.1 fvdl
663 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_MASK);
664 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_MASK);
665 1.1 fvdl
666 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff);
667 1.15 haya if (sc->intr_ack)
668 1.15 haya (* sc->intr_ack)(sc);
669 1.1 fvdl ex_set_media(sc);
670 1.1 fvdl ex_set_mc(sc);
671 1.1 fvdl
672 1.1 fvdl
673 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE);
674 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE);
675 1.1 fvdl bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma);
676 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE);
677 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL);
678 1.38 haya
679 1.38 haya if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) {
680 1.38 haya u_int16_t cbcard_config;
681 1.38 haya
682 1.38 haya GO_WINDOW(2);
683 1.38 haya cbcard_config = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 0x0c);
684 1.38 haya if (sc->ex_conf & EX_CONF_PHY_POWER) {
685 1.38 haya cbcard_config |= 0x4000; /* turn on PHY power */
686 1.38 haya }
687 1.38 haya if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) {
688 1.39 haya cbcard_config |= 0x0010; /* invert LED polarity */
689 1.38 haya }
690 1.38 haya bus_space_write_2(sc->sc_iot, sc->sc_ioh, 0x0c, cbcard_config);
691 1.38 haya
692 1.38 haya GO_WINDOW(3);
693 1.38 haya }
694 1.1 fvdl
695 1.1 fvdl ifp->if_flags |= IFF_RUNNING;
696 1.1 fvdl ifp->if_flags &= ~IFF_OACTIVE;
697 1.1 fvdl ex_start(ifp);
698 1.1 fvdl
699 1.1 fvdl GO_WINDOW(1);
700 1.1 fvdl
701 1.30 thorpej callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc);
702 1.42 thorpej
703 1.47 thorpej out:
704 1.47 thorpej if (error) {
705 1.47 thorpej ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
706 1.47 thorpej ifp->if_timer = 0;
707 1.47 thorpej printf("%s: interface not running\n", sc->sc_dev.dv_xname);
708 1.47 thorpej }
709 1.47 thorpej return (error);
710 1.1 fvdl }
711 1.1 fvdl
712 1.33 thorpej #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & 0xff)
713 1.1 fvdl
714 1.1 fvdl /*
715 1.1 fvdl * Set multicast receive filter. Also take care of promiscuous mode
716 1.1 fvdl * here (XXX).
717 1.1 fvdl */
718 1.1 fvdl void
719 1.1 fvdl ex_set_mc(sc)
720 1.31 augustss struct ex_softc *sc;
721 1.1 fvdl {
722 1.1 fvdl struct ifnet *ifp = &sc->sc_ethercom.ec_if;
723 1.1 fvdl struct ethercom *ec = &sc->sc_ethercom;
724 1.1 fvdl struct ether_multi *enm;
725 1.1 fvdl struct ether_multistep estep;
726 1.1 fvdl int i;
727 1.1 fvdl u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST;
728 1.1 fvdl
729 1.1 fvdl if (ifp->if_flags & IFF_PROMISC)
730 1.1 fvdl mask |= FIL_PROMISC;
731 1.1 fvdl
732 1.1 fvdl if (!(ifp->if_flags & IFF_MULTICAST))
733 1.1 fvdl goto out;
734 1.1 fvdl
735 1.1 fvdl if (!(sc->ex_conf & EX_CONF_90XB) || ifp->if_flags & IFF_ALLMULTI) {
736 1.1 fvdl mask |= (ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0;
737 1.1 fvdl } else {
738 1.1 fvdl ETHER_FIRST_MULTI(estep, ec, enm);
739 1.1 fvdl while (enm != NULL) {
740 1.47.2.2 nathanw if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
741 1.1 fvdl ETHER_ADDR_LEN) != 0)
742 1.1 fvdl goto out;
743 1.1 fvdl i = ex_mchash(enm->enm_addrlo);
744 1.1 fvdl bus_space_write_2(sc->sc_iot, sc->sc_ioh,
745 1.1 fvdl ELINK_COMMAND, ELINK_SETHASHFILBIT | i);
746 1.1 fvdl ETHER_NEXT_MULTI(estep, enm);
747 1.1 fvdl }
748 1.1 fvdl mask |= FIL_MULTIHASH;
749 1.1 fvdl }
750 1.1 fvdl out:
751 1.1 fvdl bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND,
752 1.1 fvdl SET_RX_FILTER | mask);
753 1.1 fvdl }
754 1.1 fvdl
755 1.1 fvdl
756 1.1 fvdl static void
757 1.1 fvdl ex_txstat(sc)
758 1.1 fvdl struct ex_softc *sc;
759 1.1 fvdl {
760 1.42 thorpej struct ifnet *ifp = &sc->sc_ethercom.ec_if;
761 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
762 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
763 1.1 fvdl int i;
764 1.1 fvdl
765 1.1 fvdl /*
766 1.1 fvdl * We need to read+write TX_STATUS until we get a 0 status
767 1.1 fvdl * in order to turn off the interrupt flag.
768 1.1 fvdl */
769 1.1 fvdl while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) {
770 1.1 fvdl bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0);
771 1.1 fvdl
772 1.1 fvdl if (i & TXS_JABBER) {
773 1.1 fvdl ++sc->sc_ethercom.ec_if.if_oerrors;
774 1.1 fvdl if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG)
775 1.1 fvdl printf("%s: jabber (%x)\n",
776 1.1 fvdl sc->sc_dev.dv_xname, i);
777 1.42 thorpej ex_init(ifp);
778 1.1 fvdl /* TODO: be more subtle here */
779 1.1 fvdl } else if (i & TXS_UNDERRUN) {
780 1.1 fvdl ++sc->sc_ethercom.ec_if.if_oerrors;
781 1.1 fvdl if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG)
782 1.1 fvdl printf("%s: fifo underrun (%x) @%d\n",
783 1.1 fvdl sc->sc_dev.dv_xname, i,
784 1.1 fvdl sc->tx_start_thresh);
785 1.1 fvdl if (sc->tx_succ_ok < 100)
786 1.1 fvdl sc->tx_start_thresh = min(ETHER_MAX_LEN,
787 1.1 fvdl sc->tx_start_thresh + 20);
788 1.1 fvdl sc->tx_succ_ok = 0;
789 1.42 thorpej ex_init(ifp);
790 1.1 fvdl /* TODO: be more subtle here */
791 1.1 fvdl } else if (i & TXS_MAX_COLLISION) {
792 1.1 fvdl ++sc->sc_ethercom.ec_if.if_collisions;
793 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE);
794 1.1 fvdl sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE;
795 1.1 fvdl } else
796 1.1 fvdl sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127;
797 1.1 fvdl }
798 1.1 fvdl }
799 1.1 fvdl
800 1.1 fvdl int
801 1.1 fvdl ex_media_chg(ifp)
802 1.1 fvdl struct ifnet *ifp;
803 1.1 fvdl {
804 1.1 fvdl
805 1.1 fvdl if (ifp->if_flags & IFF_UP)
806 1.42 thorpej ex_init(ifp);
807 1.1 fvdl return 0;
808 1.1 fvdl }
809 1.1 fvdl
810 1.1 fvdl void
811 1.1 fvdl ex_set_media(sc)
812 1.1 fvdl struct ex_softc *sc;
813 1.1 fvdl {
814 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
815 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
816 1.37 haya u_int32_t configreg;
817 1.1 fvdl
818 1.1 fvdl if (((sc->ex_conf & EX_CONF_MII) &&
819 1.1 fvdl (sc->ex_mii.mii_media_active & IFM_FDX))
820 1.1 fvdl || (!(sc->ex_conf & EX_CONF_MII) &&
821 1.1 fvdl (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) {
822 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL,
823 1.1 fvdl MAC_CONTROL_FDX);
824 1.1 fvdl } else {
825 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0);
826 1.1 fvdl }
827 1.1 fvdl
828 1.1 fvdl /*
829 1.1 fvdl * If the device has MII, select it, and then tell the
830 1.1 fvdl * PHY which media to use.
831 1.1 fvdl */
832 1.1 fvdl if (sc->ex_conf & EX_CONF_MII) {
833 1.1 fvdl GO_WINDOW(3);
834 1.1 fvdl
835 1.37 haya configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG);
836 1.1 fvdl
837 1.37 haya configreg &= ~(CONFIG_MEDIAMASK << 16);
838 1.37 haya configreg |= (ELINKMEDIA_MII << (CONFIG_MEDIAMASK_SHIFT + 16));
839 1.1 fvdl
840 1.37 haya bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg);
841 1.1 fvdl mii_mediachg(&sc->ex_mii);
842 1.1 fvdl return;
843 1.1 fvdl }
844 1.1 fvdl
845 1.1 fvdl GO_WINDOW(4);
846 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0);
847 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER);
848 1.1 fvdl delay(800);
849 1.1 fvdl
850 1.1 fvdl /*
851 1.1 fvdl * Now turn on the selected media/transceiver.
852 1.1 fvdl */
853 1.1 fvdl switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) {
854 1.1 fvdl case IFM_10_T:
855 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE,
856 1.1 fvdl JABBER_GUARD_ENABLE|LINKBEAT_ENABLE);
857 1.1 fvdl break;
858 1.1 fvdl
859 1.1 fvdl case IFM_10_2:
860 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER);
861 1.1 fvdl DELAY(800);
862 1.1 fvdl break;
863 1.1 fvdl
864 1.1 fvdl case IFM_100_TX:
865 1.1 fvdl case IFM_100_FX:
866 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE,
867 1.1 fvdl LINKBEAT_ENABLE);
868 1.1 fvdl DELAY(800);
869 1.1 fvdl break;
870 1.1 fvdl
871 1.1 fvdl case IFM_10_5:
872 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE,
873 1.1 fvdl SQE_ENABLE);
874 1.1 fvdl DELAY(800);
875 1.1 fvdl break;
876 1.1 fvdl
877 1.1 fvdl case IFM_MANUAL:
878 1.1 fvdl break;
879 1.1 fvdl
880 1.1 fvdl case IFM_NONE:
881 1.1 fvdl return;
882 1.1 fvdl
883 1.1 fvdl default:
884 1.1 fvdl panic("ex_set_media: impossible");
885 1.1 fvdl }
886 1.1 fvdl
887 1.1 fvdl GO_WINDOW(3);
888 1.37 haya configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG);
889 1.1 fvdl
890 1.37 haya configreg &= ~(CONFIG_MEDIAMASK << 16);
891 1.37 haya configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data <<
892 1.37 haya (CONFIG_MEDIAMASK_SHIFT + 16));
893 1.1 fvdl
894 1.37 haya bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg);
895 1.1 fvdl }
896 1.1 fvdl
897 1.1 fvdl /*
898 1.1 fvdl * Get currently-selected media from card.
899 1.1 fvdl * (if_media callback, may be called before interface is brought up).
900 1.1 fvdl */
901 1.1 fvdl void
902 1.1 fvdl ex_media_stat(ifp, req)
903 1.1 fvdl struct ifnet *ifp;
904 1.1 fvdl struct ifmediareq *req;
905 1.1 fvdl {
906 1.1 fvdl struct ex_softc *sc = ifp->if_softc;
907 1.1 fvdl
908 1.1 fvdl if (sc->ex_conf & EX_CONF_MII) {
909 1.1 fvdl mii_pollstat(&sc->ex_mii);
910 1.1 fvdl req->ifm_status = sc->ex_mii.mii_media_status;
911 1.1 fvdl req->ifm_active = sc->ex_mii.mii_media_active;
912 1.1 fvdl } else {
913 1.1 fvdl GO_WINDOW(4);
914 1.1 fvdl req->ifm_status = IFM_AVALID;
915 1.1 fvdl req->ifm_active = sc->ex_mii.mii_media.ifm_cur->ifm_media;
916 1.1 fvdl if (bus_space_read_2(sc->sc_iot, sc->sc_ioh,
917 1.1 fvdl ELINK_W4_MEDIA_TYPE) & LINKBEAT_DETECT)
918 1.1 fvdl req->ifm_status |= IFM_ACTIVE;
919 1.1 fvdl GO_WINDOW(1);
920 1.1 fvdl }
921 1.1 fvdl }
922 1.1 fvdl
923 1.1 fvdl
924 1.1 fvdl
925 1.1 fvdl /*
926 1.1 fvdl * Start outputting on the interface.
927 1.1 fvdl */
928 1.1 fvdl static void
929 1.1 fvdl ex_start(ifp)
930 1.1 fvdl struct ifnet *ifp;
931 1.1 fvdl {
932 1.1 fvdl struct ex_softc *sc = ifp->if_softc;
933 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
934 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
935 1.1 fvdl volatile struct ex_fraghdr *fr = NULL;
936 1.1 fvdl volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL;
937 1.1 fvdl struct ex_txdesc *txp;
938 1.46 thorpej struct mbuf *mb_head;
939 1.1 fvdl bus_dmamap_t dmamap;
940 1.46 thorpej int offset, totlen, segment, error;
941 1.47.2.1 nathanw u_int32_t csum_flags;
942 1.1 fvdl
943 1.1 fvdl if (sc->tx_head || sc->tx_free == NULL)
944 1.1 fvdl return;
945 1.1 fvdl
946 1.1 fvdl txp = NULL;
947 1.1 fvdl
948 1.1 fvdl /*
949 1.1 fvdl * We're finished if there is nothing more to add to the list or if
950 1.1 fvdl * we're all filled up with buffers to transmit.
951 1.1 fvdl */
952 1.46 thorpej while (sc->tx_free != NULL) {
953 1.1 fvdl /*
954 1.1 fvdl * Grab a packet to transmit.
955 1.1 fvdl */
956 1.46 thorpej IFQ_DEQUEUE(&ifp->if_snd, mb_head);
957 1.46 thorpej if (mb_head == NULL)
958 1.46 thorpej break;
959 1.1 fvdl
960 1.1 fvdl /*
961 1.1 fvdl * Get pointer to next available tx desc.
962 1.1 fvdl */
963 1.1 fvdl txp = sc->tx_free;
964 1.1 fvdl dmamap = txp->tx_dmamap;
965 1.1 fvdl
966 1.1 fvdl /*
967 1.1 fvdl * Go through each of the mbufs in the chain and initialize
968 1.1 fvdl * the transmit buffer descriptors with the physical address
969 1.1 fvdl * and size of the mbuf.
970 1.1 fvdl */
971 1.1 fvdl reload:
972 1.1 fvdl error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
973 1.47.2.2 nathanw mb_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
974 1.1 fvdl switch (error) {
975 1.1 fvdl case 0:
976 1.1 fvdl /* Success. */
977 1.1 fvdl break;
978 1.1 fvdl
979 1.1 fvdl case EFBIG:
980 1.1 fvdl {
981 1.1 fvdl struct mbuf *mn;
982 1.1 fvdl
983 1.1 fvdl /*
984 1.1 fvdl * We ran out of segments. We have to recopy this
985 1.1 fvdl * mbuf chain first. Bail out if we can't get the
986 1.1 fvdl * new buffers.
987 1.1 fvdl */
988 1.1 fvdl printf("%s: too many segments, ", sc->sc_dev.dv_xname);
989 1.1 fvdl
990 1.1 fvdl MGETHDR(mn, M_DONTWAIT, MT_DATA);
991 1.1 fvdl if (mn == NULL) {
992 1.1 fvdl m_freem(mb_head);
993 1.1 fvdl printf("aborting\n");
994 1.1 fvdl goto out;
995 1.1 fvdl }
996 1.1 fvdl if (mb_head->m_pkthdr.len > MHLEN) {
997 1.1 fvdl MCLGET(mn, M_DONTWAIT);
998 1.1 fvdl if ((mn->m_flags & M_EXT) == 0) {
999 1.1 fvdl m_freem(mn);
1000 1.1 fvdl m_freem(mb_head);
1001 1.1 fvdl printf("aborting\n");
1002 1.1 fvdl goto out;
1003 1.1 fvdl }
1004 1.1 fvdl }
1005 1.1 fvdl m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1006 1.1 fvdl mtod(mn, caddr_t));
1007 1.1 fvdl mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1008 1.1 fvdl m_freem(mb_head);
1009 1.1 fvdl mb_head = mn;
1010 1.1 fvdl printf("retrying\n");
1011 1.1 fvdl goto reload;
1012 1.1 fvdl }
1013 1.1 fvdl
1014 1.1 fvdl default:
1015 1.1 fvdl /*
1016 1.1 fvdl * Some other problem; report it.
1017 1.1 fvdl */
1018 1.1 fvdl printf("%s: can't load mbuf chain, error = %d\n",
1019 1.1 fvdl sc->sc_dev.dv_xname, error);
1020 1.1 fvdl m_freem(mb_head);
1021 1.1 fvdl goto out;
1022 1.1 fvdl }
1023 1.1 fvdl
1024 1.47.2.4 nathanw /*
1025 1.47.2.4 nathanw * remove our tx desc from freelist.
1026 1.47.2.4 nathanw */
1027 1.47.2.4 nathanw sc->tx_free = txp->tx_next;
1028 1.47.2.4 nathanw txp->tx_next = NULL;
1029 1.47.2.4 nathanw
1030 1.1 fvdl fr = &txp->tx_dpd->dpd_frags[0];
1031 1.1 fvdl totlen = 0;
1032 1.1 fvdl for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) {
1033 1.21 thorpej fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr);
1034 1.21 thorpej fr->fr_len = htole32(dmamap->dm_segs[segment].ds_len);
1035 1.9 thorpej totlen += dmamap->dm_segs[segment].ds_len;
1036 1.1 fvdl }
1037 1.1 fvdl fr--;
1038 1.21 thorpej fr->fr_len |= htole32(EX_FR_LAST);
1039 1.1 fvdl txp->tx_mbhead = mb_head;
1040 1.1 fvdl
1041 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
1042 1.1 fvdl BUS_DMASYNC_PREWRITE);
1043 1.1 fvdl
1044 1.1 fvdl dpd = txp->tx_dpd;
1045 1.1 fvdl dpd->dpd_nextptr = 0;
1046 1.21 thorpej dpd->dpd_fsh = htole32(totlen);
1047 1.1 fvdl
1048 1.47.2.1 nathanw /* Byte-swap constants to compiler can optimize. */
1049 1.47.2.1 nathanw
1050 1.47.2.1 nathanw if (sc->ex_conf & EX_CONF_90XB) {
1051 1.47.2.1 nathanw csum_flags = 0;
1052 1.47.2.1 nathanw
1053 1.47.2.1 nathanw if (mb_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
1054 1.47.2.1 nathanw csum_flags |= htole32(EX_DPD_IPCKSUM);
1055 1.47.2.1 nathanw
1056 1.47.2.1 nathanw if (mb_head->m_pkthdr.csum_flags & M_CSUM_TCPv4)
1057 1.47.2.1 nathanw csum_flags |= htole32(EX_DPD_TCPCKSUM);
1058 1.47.2.1 nathanw else if (mb_head->m_pkthdr.csum_flags & M_CSUM_UDPv4)
1059 1.47.2.1 nathanw csum_flags |= htole32(EX_DPD_UDPCKSUM);
1060 1.47.2.1 nathanw
1061 1.47.2.1 nathanw dpd->dpd_fsh |= csum_flags;
1062 1.47.2.1 nathanw } else {
1063 1.47.2.1 nathanw KDASSERT((mb_head->m_pkthdr.csum_flags &
1064 1.47.2.1 nathanw (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) == 0);
1065 1.47.2.1 nathanw }
1066 1.47.2.1 nathanw
1067 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1068 1.1 fvdl ((caddr_t)dpd - (caddr_t)sc->sc_dpd),
1069 1.1 fvdl sizeof (struct ex_dpd),
1070 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1071 1.1 fvdl
1072 1.1 fvdl /*
1073 1.1 fvdl * No need to stall the download engine, we know it's
1074 1.1 fvdl * not busy right now.
1075 1.1 fvdl *
1076 1.1 fvdl * Fix up pointers in both the "soft" tx and the physical
1077 1.1 fvdl * tx list.
1078 1.1 fvdl */
1079 1.1 fvdl if (sc->tx_head != NULL) {
1080 1.1 fvdl prevdpd = sc->tx_tail->tx_dpd;
1081 1.1 fvdl offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd);
1082 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1083 1.1 fvdl offset, sizeof (struct ex_dpd),
1084 1.1 fvdl BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1085 1.21 thorpej prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp));
1086 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1087 1.1 fvdl offset, sizeof (struct ex_dpd),
1088 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1089 1.1 fvdl sc->tx_tail->tx_next = txp;
1090 1.1 fvdl sc->tx_tail = txp;
1091 1.1 fvdl } else {
1092 1.1 fvdl sc->tx_tail = sc->tx_head = txp;
1093 1.1 fvdl }
1094 1.1 fvdl
1095 1.1 fvdl #if NBPFILTER > 0
1096 1.1 fvdl /*
1097 1.1 fvdl * Pass packet to bpf if there is a listener.
1098 1.1 fvdl */
1099 1.1 fvdl if (ifp->if_bpf)
1100 1.1 fvdl bpf_mtap(ifp->if_bpf, mb_head);
1101 1.1 fvdl #endif
1102 1.1 fvdl }
1103 1.1 fvdl out:
1104 1.1 fvdl if (sc->tx_head) {
1105 1.21 thorpej sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND);
1106 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1107 1.1 fvdl ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd),
1108 1.1 fvdl sizeof (struct ex_dpd),
1109 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1110 1.1 fvdl ifp->if_flags |= IFF_OACTIVE;
1111 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL);
1112 1.1 fvdl bus_space_write_4(iot, ioh, ELINK_DNLISTPTR,
1113 1.1 fvdl DPD_DMADDR(sc, sc->tx_head));
1114 1.3 drochner
1115 1.3 drochner /* trigger watchdog */
1116 1.3 drochner ifp->if_timer = 5;
1117 1.1 fvdl }
1118 1.1 fvdl }
1119 1.1 fvdl
1120 1.1 fvdl
1121 1.1 fvdl int
1122 1.1 fvdl ex_intr(arg)
1123 1.1 fvdl void *arg;
1124 1.1 fvdl {
1125 1.1 fvdl struct ex_softc *sc = arg;
1126 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
1127 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
1128 1.1 fvdl u_int16_t stat;
1129 1.1 fvdl int ret = 0;
1130 1.1 fvdl struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1131 1.1 fvdl
1132 1.47 thorpej if ((ifp->if_flags & IFF_RUNNING) == 0 ||
1133 1.28 enami (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0)
1134 1.28 enami return (0);
1135 1.28 enami
1136 1.1 fvdl for (;;) {
1137 1.1 fvdl stat = bus_space_read_2(iot, ioh, ELINK_STATUS);
1138 1.22 mycroft
1139 1.22 mycroft if ((stat & S_MASK) == 0) {
1140 1.22 mycroft if ((stat & S_INTR_LATCH) == 0) {
1141 1.22 mycroft #if 0
1142 1.22 mycroft printf("%s: intr latch cleared\n",
1143 1.22 mycroft sc->sc_dev.dv_xname);
1144 1.22 mycroft #endif
1145 1.22 mycroft break;
1146 1.22 mycroft }
1147 1.22 mycroft }
1148 1.22 mycroft
1149 1.22 mycroft ret = 1;
1150 1.22 mycroft
1151 1.1 fvdl /*
1152 1.1 fvdl * Acknowledge interrupts.
1153 1.1 fvdl */
1154 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR |
1155 1.47.2.4 nathanw (stat & (S_MASK | S_INTR_LATCH)));
1156 1.15 haya if (sc->intr_ack)
1157 1.22 mycroft (*sc->intr_ack)(sc);
1158 1.22 mycroft
1159 1.1 fvdl if (stat & S_HOST_ERROR) {
1160 1.1 fvdl printf("%s: adapter failure (%x)\n",
1161 1.1 fvdl sc->sc_dev.dv_xname, stat);
1162 1.1 fvdl ex_reset(sc);
1163 1.42 thorpej ex_init(ifp);
1164 1.1 fvdl return 1;
1165 1.1 fvdl }
1166 1.1 fvdl if (stat & S_TX_COMPLETE) {
1167 1.1 fvdl ex_txstat(sc);
1168 1.1 fvdl }
1169 1.1 fvdl if (stat & S_UPD_STATS) {
1170 1.1 fvdl ex_getstats(sc);
1171 1.1 fvdl }
1172 1.1 fvdl if (stat & S_DN_COMPLETE) {
1173 1.1 fvdl struct ex_txdesc *txp, *ptxp = NULL;
1174 1.1 fvdl bus_dmamap_t txmap;
1175 1.3 drochner
1176 1.3 drochner /* reset watchdog timer, was set in ex_start() */
1177 1.3 drochner ifp->if_timer = 0;
1178 1.3 drochner
1179 1.1 fvdl for (txp = sc->tx_head; txp != NULL;
1180 1.1 fvdl txp = txp->tx_next) {
1181 1.1 fvdl bus_dmamap_sync(sc->sc_dmat,
1182 1.1 fvdl sc->sc_dpd_dmamap,
1183 1.1 fvdl (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd,
1184 1.1 fvdl sizeof (struct ex_dpd),
1185 1.1 fvdl BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1186 1.1 fvdl if (txp->tx_mbhead != NULL) {
1187 1.1 fvdl txmap = txp->tx_dmamap;
1188 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, txmap,
1189 1.1 fvdl 0, txmap->dm_mapsize,
1190 1.1 fvdl BUS_DMASYNC_POSTWRITE);
1191 1.1 fvdl bus_dmamap_unload(sc->sc_dmat, txmap);
1192 1.1 fvdl m_freem(txp->tx_mbhead);
1193 1.1 fvdl txp->tx_mbhead = NULL;
1194 1.1 fvdl }
1195 1.1 fvdl ptxp = txp;
1196 1.1 fvdl }
1197 1.1 fvdl
1198 1.1 fvdl /*
1199 1.1 fvdl * Move finished tx buffers back to the tx free list.
1200 1.1 fvdl */
1201 1.1 fvdl if (sc->tx_free) {
1202 1.1 fvdl sc->tx_ftail->tx_next = sc->tx_head;
1203 1.1 fvdl sc->tx_ftail = ptxp;
1204 1.1 fvdl } else
1205 1.1 fvdl sc->tx_ftail = sc->tx_free = sc->tx_head;
1206 1.1 fvdl
1207 1.1 fvdl sc->tx_head = sc->tx_tail = NULL;
1208 1.1 fvdl ifp->if_flags &= ~IFF_OACTIVE;
1209 1.1 fvdl }
1210 1.1 fvdl
1211 1.1 fvdl if (stat & S_UP_COMPLETE) {
1212 1.1 fvdl struct ex_rxdesc *rxd;
1213 1.1 fvdl struct mbuf *m;
1214 1.1 fvdl struct ex_upd *upd;
1215 1.1 fvdl bus_dmamap_t rxmap;
1216 1.1 fvdl u_int32_t pktstat;
1217 1.1 fvdl
1218 1.1 fvdl rcvloop:
1219 1.1 fvdl rxd = sc->rx_head;
1220 1.1 fvdl rxmap = rxd->rx_dmamap;
1221 1.1 fvdl m = rxd->rx_mbhead;
1222 1.1 fvdl upd = rxd->rx_upd;
1223 1.1 fvdl
1224 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, rxmap, 0,
1225 1.1 fvdl rxmap->dm_mapsize,
1226 1.1 fvdl BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1227 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap,
1228 1.1 fvdl ((caddr_t)upd - (caddr_t)sc->sc_upd),
1229 1.1 fvdl sizeof (struct ex_upd),
1230 1.1 fvdl BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1231 1.32 tsutsui pktstat = le32toh(upd->upd_pktstatus);
1232 1.1 fvdl
1233 1.1 fvdl if (pktstat & EX_UPD_COMPLETE) {
1234 1.1 fvdl /*
1235 1.1 fvdl * Remove first packet from the chain.
1236 1.1 fvdl */
1237 1.1 fvdl sc->rx_head = rxd->rx_next;
1238 1.1 fvdl rxd->rx_next = NULL;
1239 1.1 fvdl
1240 1.1 fvdl /*
1241 1.1 fvdl * Add a new buffer to the receive chain.
1242 1.1 fvdl * If this fails, the old buffer is recycled
1243 1.1 fvdl * instead.
1244 1.1 fvdl */
1245 1.1 fvdl if (ex_add_rxbuf(sc, rxd) == 0) {
1246 1.1 fvdl u_int16_t total_len;
1247 1.1 fvdl
1248 1.43 bouyer if (pktstat &
1249 1.43 bouyer ((sc->sc_ethercom.ec_capenable &
1250 1.43 bouyer ETHERCAP_VLAN_MTU) ?
1251 1.43 bouyer EX_UPD_ERR_VLAN : EX_UPD_ERR)) {
1252 1.1 fvdl ifp->if_ierrors++;
1253 1.1 fvdl m_freem(m);
1254 1.1 fvdl goto rcvloop;
1255 1.1 fvdl }
1256 1.1 fvdl
1257 1.1 fvdl total_len = pktstat & EX_UPD_PKTLENMASK;
1258 1.1 fvdl if (total_len <
1259 1.1 fvdl sizeof(struct ether_header)) {
1260 1.1 fvdl m_freem(m);
1261 1.1 fvdl goto rcvloop;
1262 1.1 fvdl }
1263 1.1 fvdl m->m_pkthdr.rcvif = ifp;
1264 1.13 thorpej m->m_pkthdr.len = m->m_len = total_len;
1265 1.1 fvdl #if NBPFILTER > 0
1266 1.41 thorpej if (ifp->if_bpf)
1267 1.41 thorpej bpf_mtap(ifp->if_bpf, m);
1268 1.41 thorpej #endif
1269 1.47.2.1 nathanw /*
1270 1.47.2.1 nathanw * Set the incoming checksum information for the packet.
1271 1.47.2.1 nathanw */
1272 1.47.2.1 nathanw if ((sc->ex_conf & EX_CONF_90XB) != 0 &&
1273 1.47.2.1 nathanw (pktstat & EX_UPD_IPCHECKED) != 0) {
1274 1.47.2.1 nathanw m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1275 1.47.2.1 nathanw if (pktstat & EX_UPD_IPCKSUMERR)
1276 1.47.2.1 nathanw m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1277 1.47.2.1 nathanw if (pktstat & EX_UPD_TCPCHECKED) {
1278 1.47.2.1 nathanw m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1279 1.47.2.1 nathanw if (pktstat & EX_UPD_TCPCKSUMERR)
1280 1.47.2.1 nathanw m->m_pkthdr.csum_flags |=
1281 1.47.2.1 nathanw M_CSUM_TCP_UDP_BAD;
1282 1.47.2.1 nathanw } else if (pktstat & EX_UPD_UDPCHECKED) {
1283 1.47.2.1 nathanw m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1284 1.47.2.1 nathanw if (pktstat & EX_UPD_UDPCKSUMERR)
1285 1.47.2.1 nathanw m->m_pkthdr.csum_flags |=
1286 1.47.2.1 nathanw M_CSUM_TCP_UDP_BAD;
1287 1.47.2.1 nathanw }
1288 1.47.2.1 nathanw }
1289 1.13 thorpej (*ifp->if_input)(ifp, m);
1290 1.1 fvdl }
1291 1.1 fvdl goto rcvloop;
1292 1.1 fvdl }
1293 1.1 fvdl /*
1294 1.1 fvdl * Just in case we filled up all UPDs and the DMA engine
1295 1.3 drochner * stalled. We could be more subtle about this.
1296 1.1 fvdl */
1297 1.3 drochner if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) {
1298 1.3 drochner printf("%s: uplistptr was 0\n",
1299 1.3 drochner sc->sc_dev.dv_xname);
1300 1.42 thorpej ex_init(ifp);
1301 1.3 drochner } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS)
1302 1.3 drochner & 0x2000) {
1303 1.3 drochner printf("%s: receive stalled\n",
1304 1.3 drochner sc->sc_dev.dv_xname);
1305 1.3 drochner bus_space_write_2(iot, ioh, ELINK_COMMAND,
1306 1.3 drochner ELINK_UPUNSTALL);
1307 1.3 drochner }
1308 1.1 fvdl }
1309 1.1 fvdl }
1310 1.22 mycroft
1311 1.22 mycroft /* no more interrupts */
1312 1.46 thorpej if (ret && IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1313 1.22 mycroft ex_start(ifp);
1314 1.1 fvdl return ret;
1315 1.1 fvdl }
1316 1.1 fvdl
1317 1.1 fvdl int
1318 1.1 fvdl ex_ioctl(ifp, cmd, data)
1319 1.31 augustss struct ifnet *ifp;
1320 1.1 fvdl u_long cmd;
1321 1.1 fvdl caddr_t data;
1322 1.1 fvdl {
1323 1.1 fvdl struct ex_softc *sc = ifp->if_softc;
1324 1.1 fvdl struct ifreq *ifr = (struct ifreq *)data;
1325 1.42 thorpej int s, error;
1326 1.1 fvdl
1327 1.1 fvdl s = splnet();
1328 1.1 fvdl
1329 1.1 fvdl switch (cmd) {
1330 1.1 fvdl case SIOCSIFMEDIA:
1331 1.1 fvdl case SIOCGIFMEDIA:
1332 1.1 fvdl error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd);
1333 1.1 fvdl break;
1334 1.1 fvdl
1335 1.42 thorpej default:
1336 1.42 thorpej error = ether_ioctl(ifp, cmd, data);
1337 1.1 fvdl if (error == ENETRESET) {
1338 1.47 thorpej if (sc->enabled) {
1339 1.1 fvdl /*
1340 1.1 fvdl * Multicast list has changed; set the hardware filter
1341 1.1 fvdl * accordingly.
1342 1.1 fvdl */
1343 1.47 thorpej ex_set_mc(sc);
1344 1.47 thorpej }
1345 1.1 fvdl error = 0;
1346 1.1 fvdl }
1347 1.1 fvdl break;
1348 1.1 fvdl }
1349 1.1 fvdl
1350 1.1 fvdl splx(s);
1351 1.1 fvdl return (error);
1352 1.1 fvdl }
1353 1.1 fvdl
1354 1.1 fvdl void
1355 1.1 fvdl ex_getstats(sc)
1356 1.1 fvdl struct ex_softc *sc;
1357 1.1 fvdl {
1358 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
1359 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
1360 1.1 fvdl struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1361 1.1 fvdl u_int8_t upperok;
1362 1.1 fvdl
1363 1.1 fvdl GO_WINDOW(6);
1364 1.1 fvdl upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK);
1365 1.1 fvdl ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK);
1366 1.1 fvdl ifp->if_ipackets += (upperok & 0x03) << 8;
1367 1.1 fvdl ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK);
1368 1.1 fvdl ifp->if_opackets += (upperok & 0x30) << 4;
1369 1.1 fvdl ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS);
1370 1.1 fvdl ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS);
1371 1.1 fvdl /*
1372 1.1 fvdl * There seems to be no way to get the exact number of collisions,
1373 1.47.2.3 nathanw * this is the number that occurred at the very least.
1374 1.1 fvdl */
1375 1.1 fvdl ifp->if_collisions += 2 * bus_space_read_1(iot, ioh,
1376 1.1 fvdl TX_AFTER_X_COLLISIONS);
1377 1.1 fvdl ifp->if_ibytes += bus_space_read_2(iot, ioh, RX_TOTAL_OK);
1378 1.1 fvdl ifp->if_obytes += bus_space_read_2(iot, ioh, TX_TOTAL_OK);
1379 1.1 fvdl
1380 1.1 fvdl /*
1381 1.1 fvdl * Clear the following to avoid stats overflow interrupts
1382 1.1 fvdl */
1383 1.12 drochner bus_space_read_1(iot, ioh, TX_DEFERRALS);
1384 1.1 fvdl bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION);
1385 1.1 fvdl bus_space_read_1(iot, ioh, TX_NO_SQE);
1386 1.1 fvdl bus_space_read_1(iot, ioh, TX_CD_LOST);
1387 1.1 fvdl GO_WINDOW(4);
1388 1.1 fvdl bus_space_read_1(iot, ioh, ELINK_W4_BADSSD);
1389 1.1 fvdl upperok = bus_space_read_1(iot, ioh, ELINK_W4_UBYTESOK);
1390 1.1 fvdl ifp->if_ibytes += (upperok & 0x0f) << 16;
1391 1.1 fvdl ifp->if_obytes += (upperok & 0xf0) << 12;
1392 1.1 fvdl GO_WINDOW(1);
1393 1.1 fvdl }
1394 1.1 fvdl
1395 1.1 fvdl void
1396 1.1 fvdl ex_printstats(sc)
1397 1.1 fvdl struct ex_softc *sc;
1398 1.1 fvdl {
1399 1.1 fvdl struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1400 1.1 fvdl
1401 1.1 fvdl ex_getstats(sc);
1402 1.20 bouyer printf("in %llu out %llu ierror %llu oerror %llu ibytes %llu obytes "
1403 1.20 bouyer "%llu\n", (unsigned long long)ifp->if_ipackets,
1404 1.20 bouyer (unsigned long long)ifp->if_opackets,
1405 1.20 bouyer (unsigned long long)ifp->if_ierrors,
1406 1.20 bouyer (unsigned long long)ifp->if_oerrors,
1407 1.20 bouyer (unsigned long long)ifp->if_ibytes,
1408 1.20 bouyer (unsigned long long)ifp->if_obytes);
1409 1.1 fvdl }
1410 1.1 fvdl
1411 1.1 fvdl void
1412 1.1 fvdl ex_tick(arg)
1413 1.1 fvdl void *arg;
1414 1.1 fvdl {
1415 1.1 fvdl struct ex_softc *sc = arg;
1416 1.28 enami int s;
1417 1.28 enami
1418 1.28 enami if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0)
1419 1.28 enami return;
1420 1.28 enami
1421 1.28 enami s = splnet();
1422 1.1 fvdl
1423 1.1 fvdl if (sc->ex_conf & EX_CONF_MII)
1424 1.1 fvdl mii_tick(&sc->ex_mii);
1425 1.1 fvdl
1426 1.1 fvdl if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS)
1427 1.1 fvdl & S_COMMAND_IN_PROGRESS))
1428 1.1 fvdl ex_getstats(sc);
1429 1.1 fvdl
1430 1.1 fvdl splx(s);
1431 1.1 fvdl
1432 1.30 thorpej callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc);
1433 1.1 fvdl }
1434 1.1 fvdl
1435 1.1 fvdl void
1436 1.1 fvdl ex_reset(sc)
1437 1.1 fvdl struct ex_softc *sc;
1438 1.1 fvdl {
1439 1.40 fvdl u_int16_t val = GLOBAL_RESET;
1440 1.40 fvdl
1441 1.40 fvdl if (sc->ex_conf & EX_CONF_RESETHACK)
1442 1.47.2.1 nathanw val |= 0x10;
1443 1.40 fvdl bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val);
1444 1.47.2.1 nathanw /*
1445 1.47.2.1 nathanw * XXX apparently the command in progress bit can't be trusted
1446 1.47.2.1 nathanw * during a reset, so we just always wait this long. Fortunately
1447 1.47.2.1 nathanw * we normally only reset the chip during autoconfig.
1448 1.47.2.1 nathanw */
1449 1.47.2.1 nathanw delay(100000);
1450 1.1 fvdl ex_waitcmd(sc);
1451 1.1 fvdl }
1452 1.1 fvdl
1453 1.1 fvdl void
1454 1.1 fvdl ex_watchdog(ifp)
1455 1.1 fvdl struct ifnet *ifp;
1456 1.1 fvdl {
1457 1.1 fvdl struct ex_softc *sc = ifp->if_softc;
1458 1.1 fvdl
1459 1.1 fvdl log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
1460 1.1 fvdl ++sc->sc_ethercom.ec_if.if_oerrors;
1461 1.1 fvdl
1462 1.1 fvdl ex_reset(sc);
1463 1.42 thorpej ex_init(ifp);
1464 1.1 fvdl }
1465 1.1 fvdl
1466 1.1 fvdl void
1467 1.42 thorpej ex_stop(ifp, disable)
1468 1.42 thorpej struct ifnet *ifp;
1469 1.42 thorpej int disable;
1470 1.1 fvdl {
1471 1.42 thorpej struct ex_softc *sc = ifp->if_softc;
1472 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
1473 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
1474 1.1 fvdl struct ex_txdesc *tx;
1475 1.1 fvdl struct ex_rxdesc *rx;
1476 1.1 fvdl int i;
1477 1.1 fvdl
1478 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE);
1479 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE);
1480 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER);
1481 1.1 fvdl
1482 1.1 fvdl for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) {
1483 1.1 fvdl if (tx->tx_mbhead == NULL)
1484 1.1 fvdl continue;
1485 1.1 fvdl m_freem(tx->tx_mbhead);
1486 1.1 fvdl tx->tx_mbhead = NULL;
1487 1.1 fvdl bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap);
1488 1.1 fvdl tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0;
1489 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1490 1.1 fvdl ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd),
1491 1.1 fvdl sizeof (struct ex_dpd),
1492 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1493 1.1 fvdl }
1494 1.1 fvdl sc->tx_tail = sc->tx_head = NULL;
1495 1.1 fvdl ex_init_txdescs(sc);
1496 1.1 fvdl
1497 1.1 fvdl sc->rx_tail = sc->rx_head = 0;
1498 1.1 fvdl for (i = 0; i < EX_NUPD; i++) {
1499 1.1 fvdl rx = &sc->sc_rxdescs[i];
1500 1.1 fvdl if (rx->rx_mbhead != NULL) {
1501 1.1 fvdl bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap);
1502 1.1 fvdl m_freem(rx->rx_mbhead);
1503 1.1 fvdl rx->rx_mbhead = NULL;
1504 1.1 fvdl }
1505 1.1 fvdl ex_add_rxbuf(sc, rx);
1506 1.1 fvdl }
1507 1.1 fvdl
1508 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH);
1509 1.1 fvdl
1510 1.30 thorpej callout_stop(&sc->ex_mii_callout);
1511 1.17 thorpej if (sc->ex_conf & EX_CONF_MII)
1512 1.17 thorpej mii_down(&sc->ex_mii);
1513 1.1 fvdl
1514 1.47 thorpej if (disable)
1515 1.47 thorpej ex_disable(sc);
1516 1.47 thorpej
1517 1.1 fvdl ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1518 1.1 fvdl ifp->if_timer = 0;
1519 1.1 fvdl }
1520 1.1 fvdl
1521 1.1 fvdl static void
1522 1.1 fvdl ex_init_txdescs(sc)
1523 1.1 fvdl struct ex_softc *sc;
1524 1.1 fvdl {
1525 1.1 fvdl int i;
1526 1.1 fvdl
1527 1.1 fvdl for (i = 0; i < EX_NDPD; i++) {
1528 1.1 fvdl sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i];
1529 1.1 fvdl sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i];
1530 1.1 fvdl if (i < EX_NDPD - 1)
1531 1.1 fvdl sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1];
1532 1.1 fvdl else
1533 1.1 fvdl sc->sc_txdescs[i].tx_next = NULL;
1534 1.1 fvdl }
1535 1.1 fvdl sc->tx_free = &sc->sc_txdescs[0];
1536 1.1 fvdl sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1];
1537 1.1 fvdl }
1538 1.1 fvdl
1539 1.25 augustss
1540 1.25 augustss int
1541 1.25 augustss ex_activate(self, act)
1542 1.25 augustss struct device *self;
1543 1.25 augustss enum devact act;
1544 1.25 augustss {
1545 1.25 augustss struct ex_softc *sc = (void *) self;
1546 1.25 augustss int s, error = 0;
1547 1.25 augustss
1548 1.25 augustss s = splnet();
1549 1.25 augustss switch (act) {
1550 1.25 augustss case DVACT_ACTIVATE:
1551 1.25 augustss error = EOPNOTSUPP;
1552 1.25 augustss break;
1553 1.25 augustss
1554 1.25 augustss case DVACT_DEACTIVATE:
1555 1.27 thorpej if (sc->ex_conf & EX_CONF_MII)
1556 1.27 thorpej mii_activate(&sc->ex_mii, act, MII_PHY_ANY,
1557 1.27 thorpej MII_OFFSET_ANY);
1558 1.25 augustss if_deactivate(&sc->sc_ethercom.ec_if);
1559 1.25 augustss break;
1560 1.25 augustss }
1561 1.25 augustss splx(s);
1562 1.25 augustss
1563 1.25 augustss return (error);
1564 1.25 augustss }
1565 1.25 augustss
1566 1.25 augustss int
1567 1.25 augustss ex_detach(sc)
1568 1.25 augustss struct ex_softc *sc;
1569 1.25 augustss {
1570 1.25 augustss struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1571 1.25 augustss struct ex_rxdesc *rxd;
1572 1.25 augustss int i;
1573 1.34 jhawk
1574 1.34 jhawk /* Succeed now if there's no work to do. */
1575 1.34 jhawk if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0)
1576 1.34 jhawk return (0);
1577 1.25 augustss
1578 1.25 augustss /* Unhook our tick handler. */
1579 1.30 thorpej callout_stop(&sc->ex_mii_callout);
1580 1.25 augustss
1581 1.26 thorpej if (sc->ex_conf & EX_CONF_MII) {
1582 1.26 thorpej /* Detach all PHYs */
1583 1.26 thorpej mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1584 1.26 thorpej }
1585 1.25 augustss
1586 1.25 augustss /* Delete all remaining media. */
1587 1.25 augustss ifmedia_delete_instance(&sc->ex_mii.mii_media, IFM_INST_ANY);
1588 1.25 augustss
1589 1.25 augustss #if NRND > 0
1590 1.25 augustss rnd_detach_source(&sc->rnd_source);
1591 1.25 augustss #endif
1592 1.25 augustss ether_ifdetach(ifp);
1593 1.25 augustss if_detach(ifp);
1594 1.25 augustss
1595 1.25 augustss for (i = 0; i < EX_NUPD; i++) {
1596 1.25 augustss rxd = &sc->sc_rxdescs[i];
1597 1.25 augustss if (rxd->rx_mbhead != NULL) {
1598 1.25 augustss bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
1599 1.25 augustss m_freem(rxd->rx_mbhead);
1600 1.25 augustss rxd->rx_mbhead = NULL;
1601 1.25 augustss }
1602 1.25 augustss }
1603 1.25 augustss for (i = 0; i < EX_NUPD; i++)
1604 1.25 augustss bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]);
1605 1.25 augustss for (i = 0; i < EX_NDPD; i++)
1606 1.25 augustss bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]);
1607 1.25 augustss bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap);
1608 1.25 augustss bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap);
1609 1.25 augustss bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd,
1610 1.25 augustss EX_NDPD * sizeof (struct ex_dpd));
1611 1.25 augustss bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg);
1612 1.25 augustss bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap);
1613 1.25 augustss bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap);
1614 1.25 augustss bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd,
1615 1.25 augustss EX_NUPD * sizeof (struct ex_upd));
1616 1.25 augustss bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg);
1617 1.25 augustss
1618 1.25 augustss shutdownhook_disestablish(sc->sc_sdhook);
1619 1.47.2.1 nathanw powerhook_disestablish(sc->sc_powerhook);
1620 1.25 augustss
1621 1.25 augustss return (0);
1622 1.25 augustss }
1623 1.1 fvdl
1624 1.1 fvdl /*
1625 1.1 fvdl * Before reboots, reset card completely.
1626 1.1 fvdl */
1627 1.1 fvdl static void
1628 1.1 fvdl ex_shutdown(arg)
1629 1.1 fvdl void *arg;
1630 1.1 fvdl {
1631 1.31 augustss struct ex_softc *sc = arg;
1632 1.1 fvdl
1633 1.47 thorpej ex_stop(&sc->sc_ethercom.ec_if, 1);
1634 1.1 fvdl }
1635 1.1 fvdl
1636 1.1 fvdl /*
1637 1.1 fvdl * Read EEPROM data.
1638 1.1 fvdl * XXX what to do if EEPROM doesn't unbusy?
1639 1.1 fvdl */
1640 1.1 fvdl u_int16_t
1641 1.1 fvdl ex_read_eeprom(sc, offset)
1642 1.1 fvdl struct ex_softc *sc;
1643 1.1 fvdl int offset;
1644 1.1 fvdl {
1645 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
1646 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
1647 1.40 fvdl u_int16_t data = 0, cmd = READ_EEPROM;
1648 1.40 fvdl int off;
1649 1.40 fvdl
1650 1.40 fvdl off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0;
1651 1.40 fvdl cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM;
1652 1.1 fvdl
1653 1.1 fvdl GO_WINDOW(0);
1654 1.1 fvdl if (ex_eeprom_busy(sc))
1655 1.1 fvdl goto out;
1656 1.40 fvdl bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND,
1657 1.40 fvdl cmd | (off + (offset & 0x3f)));
1658 1.1 fvdl if (ex_eeprom_busy(sc))
1659 1.1 fvdl goto out;
1660 1.1 fvdl data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA);
1661 1.1 fvdl out:
1662 1.1 fvdl return data;
1663 1.1 fvdl }
1664 1.1 fvdl
1665 1.1 fvdl static int
1666 1.1 fvdl ex_eeprom_busy(sc)
1667 1.1 fvdl struct ex_softc *sc;
1668 1.1 fvdl {
1669 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
1670 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
1671 1.1 fvdl int i = 100;
1672 1.1 fvdl
1673 1.1 fvdl while (i--) {
1674 1.1 fvdl if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) &
1675 1.1 fvdl EEPROM_BUSY))
1676 1.1 fvdl return 0;
1677 1.1 fvdl delay(100);
1678 1.1 fvdl }
1679 1.1 fvdl printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname);
1680 1.1 fvdl return (1);
1681 1.1 fvdl }
1682 1.1 fvdl
1683 1.1 fvdl /*
1684 1.1 fvdl * Create a new rx buffer and add it to the 'soft' rx list.
1685 1.1 fvdl */
1686 1.1 fvdl static int
1687 1.1 fvdl ex_add_rxbuf(sc, rxd)
1688 1.1 fvdl struct ex_softc *sc;
1689 1.1 fvdl struct ex_rxdesc *rxd;
1690 1.1 fvdl {
1691 1.1 fvdl struct mbuf *m, *oldm;
1692 1.1 fvdl bus_dmamap_t rxmap;
1693 1.1 fvdl int error, rval = 0;
1694 1.1 fvdl
1695 1.1 fvdl oldm = rxd->rx_mbhead;
1696 1.1 fvdl rxmap = rxd->rx_dmamap;
1697 1.1 fvdl
1698 1.1 fvdl MGETHDR(m, M_DONTWAIT, MT_DATA);
1699 1.1 fvdl if (m != NULL) {
1700 1.1 fvdl MCLGET(m, M_DONTWAIT);
1701 1.1 fvdl if ((m->m_flags & M_EXT) == 0) {
1702 1.1 fvdl m_freem(m);
1703 1.1 fvdl if (oldm == NULL)
1704 1.1 fvdl return 1;
1705 1.1 fvdl m = oldm;
1706 1.1 fvdl m->m_data = m->m_ext.ext_buf;
1707 1.1 fvdl rval = 1;
1708 1.1 fvdl }
1709 1.1 fvdl } else {
1710 1.1 fvdl if (oldm == NULL)
1711 1.1 fvdl return 1;
1712 1.1 fvdl m = oldm;
1713 1.1 fvdl m->m_data = m->m_ext.ext_buf;
1714 1.1 fvdl rval = 1;
1715 1.1 fvdl }
1716 1.1 fvdl
1717 1.1 fvdl /*
1718 1.1 fvdl * Setup the DMA map for this receive buffer.
1719 1.1 fvdl */
1720 1.1 fvdl if (m != oldm) {
1721 1.1 fvdl if (oldm != NULL)
1722 1.1 fvdl bus_dmamap_unload(sc->sc_dmat, rxmap);
1723 1.1 fvdl error = bus_dmamap_load(sc->sc_dmat, rxmap,
1724 1.47.2.2 nathanw m->m_ext.ext_buf, MCLBYTES, NULL,
1725 1.47.2.2 nathanw BUS_DMA_READ|BUS_DMA_NOWAIT);
1726 1.1 fvdl if (error) {
1727 1.1 fvdl printf("%s: can't load rx buffer, error = %d\n",
1728 1.1 fvdl sc->sc_dev.dv_xname, error);
1729 1.1 fvdl panic("ex_add_rxbuf"); /* XXX */
1730 1.1 fvdl }
1731 1.1 fvdl }
1732 1.1 fvdl
1733 1.1 fvdl /*
1734 1.1 fvdl * Align for data after 14 byte header.
1735 1.1 fvdl */
1736 1.1 fvdl m->m_data += 2;
1737 1.1 fvdl
1738 1.1 fvdl rxd->rx_mbhead = m;
1739 1.21 thorpej rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2);
1740 1.9 thorpej rxd->rx_upd->upd_frags[0].fr_addr =
1741 1.21 thorpej htole32(rxmap->dm_segs[0].ds_addr + 2);
1742 1.1 fvdl rxd->rx_upd->upd_nextptr = 0;
1743 1.1 fvdl
1744 1.1 fvdl /*
1745 1.1 fvdl * Attach it to the end of the list.
1746 1.1 fvdl */
1747 1.1 fvdl if (sc->rx_head != NULL) {
1748 1.1 fvdl sc->rx_tail->rx_next = rxd;
1749 1.21 thorpej sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma +
1750 1.9 thorpej ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd));
1751 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap,
1752 1.1 fvdl (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd,
1753 1.1 fvdl sizeof (struct ex_upd),
1754 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1755 1.1 fvdl } else {
1756 1.1 fvdl sc->rx_head = rxd;
1757 1.1 fvdl }
1758 1.1 fvdl sc->rx_tail = rxd;
1759 1.1 fvdl
1760 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize,
1761 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1762 1.1 fvdl bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap,
1763 1.1 fvdl ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd),
1764 1.1 fvdl sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1765 1.1 fvdl return (rval);
1766 1.1 fvdl }
1767 1.1 fvdl
1768 1.19 thorpej u_int32_t
1769 1.19 thorpej ex_mii_bitbang_read(self)
1770 1.19 thorpej struct device *self;
1771 1.1 fvdl {
1772 1.19 thorpej struct ex_softc *sc = (void *) self;
1773 1.1 fvdl
1774 1.19 thorpej /* We're already in Window 4. */
1775 1.19 thorpej return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT));
1776 1.1 fvdl }
1777 1.1 fvdl
1778 1.1 fvdl void
1779 1.19 thorpej ex_mii_bitbang_write(self, val)
1780 1.19 thorpej struct device *self;
1781 1.19 thorpej u_int32_t val;
1782 1.1 fvdl {
1783 1.19 thorpej struct ex_softc *sc = (void *) self;
1784 1.1 fvdl
1785 1.19 thorpej /* We're already in Window 4. */
1786 1.1 fvdl bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val);
1787 1.1 fvdl }
1788 1.1 fvdl
1789 1.1 fvdl int
1790 1.1 fvdl ex_mii_readreg(v, phy, reg)
1791 1.1 fvdl struct device *v;
1792 1.18 thorpej int phy, reg;
1793 1.1 fvdl {
1794 1.1 fvdl struct ex_softc *sc = (struct ex_softc *)v;
1795 1.19 thorpej int val;
1796 1.1 fvdl
1797 1.1 fvdl if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID)
1798 1.1 fvdl return 0;
1799 1.1 fvdl
1800 1.1 fvdl GO_WINDOW(4);
1801 1.1 fvdl
1802 1.19 thorpej val = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg);
1803 1.1 fvdl
1804 1.1 fvdl GO_WINDOW(1);
1805 1.1 fvdl
1806 1.19 thorpej return (val);
1807 1.1 fvdl }
1808 1.1 fvdl
1809 1.1 fvdl void
1810 1.1 fvdl ex_mii_writereg(v, phy, reg, data)
1811 1.1 fvdl struct device *v;
1812 1.1 fvdl int phy;
1813 1.1 fvdl int reg;
1814 1.1 fvdl int data;
1815 1.1 fvdl {
1816 1.1 fvdl struct ex_softc *sc = (struct ex_softc *)v;
1817 1.1 fvdl
1818 1.1 fvdl GO_WINDOW(4);
1819 1.1 fvdl
1820 1.19 thorpej mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, data);
1821 1.1 fvdl
1822 1.1 fvdl GO_WINDOW(1);
1823 1.1 fvdl }
1824 1.1 fvdl
1825 1.1 fvdl void
1826 1.1 fvdl ex_mii_statchg(v)
1827 1.1 fvdl struct device *v;
1828 1.1 fvdl {
1829 1.1 fvdl struct ex_softc *sc = (struct ex_softc *)v;
1830 1.1 fvdl bus_space_tag_t iot = sc->sc_iot;
1831 1.1 fvdl bus_space_handle_t ioh = sc->sc_ioh;
1832 1.1 fvdl int mctl;
1833 1.1 fvdl
1834 1.1 fvdl GO_WINDOW(3);
1835 1.1 fvdl mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL);
1836 1.1 fvdl if (sc->ex_mii.mii_media_active & IFM_FDX)
1837 1.1 fvdl mctl |= MAC_CONTROL_FDX;
1838 1.1 fvdl else
1839 1.1 fvdl mctl &= ~MAC_CONTROL_FDX;
1840 1.1 fvdl bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl);
1841 1.1 fvdl GO_WINDOW(1); /* back to operating window */
1842 1.47 thorpej }
1843 1.47 thorpej
1844 1.47 thorpej int
1845 1.47 thorpej ex_enable(sc)
1846 1.47 thorpej struct ex_softc *sc;
1847 1.47 thorpej {
1848 1.47 thorpej if (sc->enabled == 0 && sc->enable != NULL) {
1849 1.47 thorpej if ((*sc->enable)(sc) != 0) {
1850 1.47 thorpej printf("%s: de/vice enable failed\n",
1851 1.47 thorpej sc->sc_dev.dv_xname);
1852 1.47 thorpej return (EIO);
1853 1.47 thorpej }
1854 1.47 thorpej sc->enabled = 1;
1855 1.47 thorpej }
1856 1.47 thorpej return (0);
1857 1.47 thorpej }
1858 1.47 thorpej
1859 1.47 thorpej void
1860 1.47 thorpej ex_disable(sc)
1861 1.47 thorpej struct ex_softc *sc;
1862 1.47 thorpej {
1863 1.47 thorpej if (sc->enabled == 1 && sc->disable != NULL) {
1864 1.47 thorpej (*sc->disable)(sc);
1865 1.47 thorpej sc->enabled = 0;
1866 1.47 thorpej }
1867 1.47 thorpej }
1868 1.47 thorpej
1869 1.47 thorpej void
1870 1.47 thorpej ex_power(why, arg)
1871 1.47 thorpej int why;
1872 1.47 thorpej void *arg;
1873 1.47 thorpej {
1874 1.47 thorpej struct ex_softc *sc = (void *)arg;
1875 1.47 thorpej struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1876 1.47 thorpej int s;
1877 1.47 thorpej
1878 1.47 thorpej s = splnet();
1879 1.47.2.1 nathanw switch (why) {
1880 1.47.2.1 nathanw case PWR_SUSPEND:
1881 1.47.2.1 nathanw case PWR_STANDBY:
1882 1.47 thorpej ex_stop(ifp, 0);
1883 1.47 thorpej if (sc->power != NULL)
1884 1.47 thorpej (*sc->power)(sc, why);
1885 1.47.2.1 nathanw break;
1886 1.47.2.1 nathanw case PWR_RESUME:
1887 1.47.2.1 nathanw if (ifp->if_flags & IFF_UP) {
1888 1.47.2.1 nathanw if (sc->power != NULL)
1889 1.47.2.1 nathanw (*sc->power)(sc, why);
1890 1.47.2.1 nathanw ex_init(ifp);
1891 1.47.2.1 nathanw }
1892 1.47.2.1 nathanw break;
1893 1.47.2.1 nathanw case PWR_SOFTSUSPEND:
1894 1.47.2.1 nathanw case PWR_SOFTSTANDBY:
1895 1.47.2.1 nathanw case PWR_SOFTRESUME:
1896 1.47.2.1 nathanw break;
1897 1.47 thorpej }
1898 1.47 thorpej splx(s);
1899 1.1 fvdl }
1900