elinkxl.c revision 1.1
1 /* $NetBSD: elinkxl.c,v 1.1 1998/11/04 00:29:29 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mbuf.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/syslog.h> 52 #include <sys/select.h> 53 #include <sys/device.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_ether.h> 61 #include <net/if_media.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #ifdef NS 72 #include <netns/ns.h> 73 #include <netns/ns_if.h> 74 #endif 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #include <net/bpfdesc.h> 79 #endif 80 81 #include <machine/cpu.h> 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #include <vm/vm.h> 86 #include <vm/pmap.h> 87 88 #include <dev/mii/miivar.h> 89 #include <dev/mii/mii.h> 90 91 #include <dev/ic/elink3reg.h> 92 /* #include <dev/ic/elink3var.h> */ 93 #include <dev/ic/elinkxlreg.h> 94 #include <dev/ic/elinkxlvar.h> 95 96 #define ETHER_MIN_LEN 64 97 #define ETHER_MAX_LEN 1518 98 #define ETHER_ADDR_LEN 6 99 100 #ifdef DEBUG 101 int exdebug = 0; 102 #endif 103 104 /* ifmedia callbacks */ 105 int ex_media_chg __P((struct ifnet *ifp)); 106 void ex_media_stat __P((struct ifnet *ifp, struct ifmediareq *req)); 107 108 void ex_probe_media __P((struct ex_softc *)); 109 void ex_set_filter __P((struct ex_softc *)); 110 void ex_set_media __P((struct ex_softc *)); 111 struct mbuf *ex_get __P((struct ex_softc *, int)); 112 u_int16_t ex_read_eeprom __P((struct ex_softc *, int)); 113 void ex_init __P((struct ex_softc *)); 114 void ex_read __P((struct ex_softc *)); 115 void ex_reset __P((struct ex_softc *)); 116 void ex_set_mc __P((struct ex_softc *)); 117 void ex_getstats __P((struct ex_softc *)); 118 void ex_printstats __P((struct ex_softc *)); 119 void ex_tick __P((void *)); 120 121 static int ex_eeprom_busy __P((struct ex_softc *)); 122 static int ex_add_rxbuf __P((struct ex_softc *, struct ex_rxdesc *)); 123 static void ex_init_txdescs __P((struct ex_softc *)); 124 125 static void ex_shutdown __P((void *)); 126 static void ex_start __P((struct ifnet *)); 127 static void ex_txstat __P((struct ex_softc *)); 128 static u_int16_t ex_mchash __P((u_char *)); 129 static void ex_mii_writebits __P((struct ex_softc *, u_int, int)); 130 131 void ex_mii_setbit __P((void *, u_int16_t)); 132 void ex_mii_clrbit __P((void *, u_int16_t)); 133 u_int16_t ex_mii_readbit __P((void *, u_int16_t)); 134 int ex_mii_readreg __P((struct device *, int, int)); 135 void ex_mii_writereg __P((struct device *, int, int, int)); 136 void ex_mii_statchg __P((struct device *)); 137 138 /* 139 * Back-end attach and configure. 140 */ 141 void 142 ex_config(sc) 143 struct ex_softc *sc; 144 { 145 struct ifnet *ifp; 146 u_int16_t val; 147 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 148 bus_space_tag_t iot = sc->sc_iot; 149 bus_space_handle_t ioh = sc->sc_ioh; 150 bus_dma_segment_t useg, dseg; 151 int urseg, drseg, i, error, attach_stage; 152 153 ex_reset(sc); 154 155 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 156 macaddr[0] = val >> 8; 157 macaddr[1] = val & 0xff; 158 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 159 macaddr[2] = val >> 8; 160 macaddr[3] = val & 0xff; 161 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 162 macaddr[4] = val >> 8; 163 macaddr[5] = val & 0xff; 164 165 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 166 ether_sprintf(macaddr)); 167 168 attach_stage = 0; 169 170 /* 171 * Allocate the upload descriptors, and create and load the DMA 172 * map for them. 173 */ 174 if ((error = bus_dmamem_alloc(sc->sc_dmat, 175 EX_NUPD * sizeof (struct ex_upd), NBPG, 0, &useg, 1, &urseg, 176 BUS_DMA_NOWAIT)) != 0) { 177 printf("%s: can't allocate upload descriptors, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail; 180 } 181 182 attach_stage = 1; 183 184 if ((error = bus_dmamem_map(sc->sc_dmat, &useg, urseg, 185 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 186 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 187 printf("%s: can't map upload descriptors, error = %d\n", 188 sc->sc_dev.dv_xname, error); 189 goto fail; 190 } 191 192 attach_stage = 2; 193 194 if ((error = bus_dmamap_create(sc->sc_dmat, 195 EX_NUPD * sizeof (struct ex_upd), 1, 196 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 197 &sc->sc_upd_dmamap)) != 0) { 198 printf("%s: can't create upload desc. DMA map, error = %d\n", 199 sc->sc_dev.dv_xname, error); 200 goto fail; 201 } 202 203 attach_stage = 3; 204 205 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 206 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 207 BUS_DMA_NOWAIT)) != 0) { 208 printf("%s: can't load upload desc. DMA map, error = %d\n", 209 sc->sc_dev.dv_xname, error); 210 goto fail; 211 } 212 213 attach_stage = 4; 214 215 /* 216 * Allocate the download descriptors, and create and load the DMA 217 * map for them. 218 */ 219 if ((error = bus_dmamem_alloc(sc->sc_dmat, 220 EX_NDPD * sizeof (struct ex_dpd), NBPG, 0, &dseg, 1, &drseg, 221 BUS_DMA_NOWAIT)) != 0) { 222 printf("%s: can't allocate download descriptors, error = %d\n", 223 sc->sc_dev.dv_xname, error); 224 goto fail; 225 } 226 227 attach_stage = 5; 228 229 if ((error = bus_dmamem_map(sc->sc_dmat, &dseg, drseg, 230 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 231 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 232 printf("%s: can't map download descriptors, error = %d\n", 233 sc->sc_dev.dv_xname, error); 234 goto fail; 235 } 236 bzero(sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd)); 237 238 attach_stage = 6; 239 240 if ((error = bus_dmamap_create(sc->sc_dmat, 241 EX_NDPD * sizeof (struct ex_dpd), 1, 242 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 243 &sc->sc_dpd_dmamap)) != 0) { 244 printf("%s: can't create download desc. DMA map, error = %d\n", 245 sc->sc_dev.dv_xname, error); 246 goto fail; 247 } 248 249 attach_stage = 7; 250 251 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 252 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 253 BUS_DMA_NOWAIT)) != 0) { 254 printf("%s: can't load download desc. DMA map, error = %d\n", 255 sc->sc_dev.dv_xname, error); 256 goto fail; 257 } 258 259 attach_stage = 8; 260 261 262 /* 263 * Create the transmit buffer DMA maps. 264 */ 265 for (i = 0; i < EX_NDPD; i++) { 266 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 267 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 268 &sc->sc_tx_dmamaps[i])) != 0) { 269 printf("%s: can't create tx DMA map %d, error = %d\n", 270 sc->sc_dev.dv_xname, i, error); 271 goto fail; 272 } 273 } 274 275 attach_stage = 9; 276 277 /* 278 * Create the receive buffer DMA maps. 279 */ 280 for (i = 0; i < EX_NUPD; i++) { 281 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 282 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 283 &sc->sc_rx_dmamaps[i])) != 0) { 284 printf("%s: can't create rx DMA map %d, error = %d\n", 285 sc->sc_dev.dv_xname, i, error); 286 goto fail; 287 } 288 } 289 290 attach_stage = 10; 291 292 /* 293 * Create ring of upload descriptors, only once. The DMA engine 294 * will loop over this when receiving packets, stalling if it 295 * hits an UPD with a finished receive. 296 */ 297 for (i = 0; i < EX_NUPD; i++) { 298 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 299 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 300 sc->sc_upd[i].upd_frags[0].fr_len = (MCLBYTES - 2) | EX_FR_LAST; 301 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 302 printf("%s: can't allocate or map rx buffers\n", 303 sc->sc_dev.dv_xname); 304 goto fail; 305 } 306 } 307 308 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 309 EX_NUPD * sizeof (struct ex_upd), 310 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 311 312 ex_init_txdescs(sc); 313 314 attach_stage = 11; 315 316 317 GO_WINDOW(3); 318 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 319 if (val & ELINK_MEDIACAP_MII) 320 sc->ex_conf |= EX_CONF_MII; 321 322 ifp = &sc->sc_ethercom.ec_if; 323 324 if (sc->ex_conf & EX_CONF_MII) { 325 /* 326 * Find PHY, extract media information from it. 327 */ 328 sc->ex_mii.mii_ifp = ifp; 329 sc->ex_mii.mii_readreg = ex_mii_readreg; 330 sc->ex_mii.mii_writereg = ex_mii_writereg; 331 sc->ex_mii.mii_statchg = ex_mii_statchg; 332 ifmedia_init(&sc->ex_mii.mii_media, 0, ex_media_chg, 333 ex_media_stat); 334 mii_phy_probe(&sc->sc_dev, &sc->ex_mii, 0xffffffff); 335 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 336 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 337 0, NULL); 338 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 339 } else { 340 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 341 } 342 } else { 343 ifmedia_init(&sc->ex_mii.mii_media, IFM_FDX, ex_media_chg, 344 ex_media_stat); 345 /* 346 * Extract media information from registers. 347 */ 348 if (val & ELINK_MEDIACAP_100BASET4) 349 ifmedia_add(&sc->ex_mii.mii_media, 350 IFM_ETHER | IFM_100_T4, ELINKMEDIA_100BASE_T4, 351 NULL); 352 else if (val & ELINK_MEDIACAP_100BASETX) 353 ifmedia_add(&sc->ex_mii.mii_media, 354 IFM_ETHER | IFM_100_TX, ELINKMEDIA_100BASE_TX, 355 NULL); 356 else if (val & ELINK_MEDIACAP_100BASEFX) 357 ifmedia_add(&sc->ex_mii.mii_media, 358 IFM_ETHER | IFM_100_FX, ELINKMEDIA_100BASE_FX, 359 NULL); 360 else if (val & ELINK_MEDIACAP_10BASET) 361 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER | IFM_10_T, 362 ELINKMEDIA_10BASE_T, NULL); 363 else if (val & ELINK_MEDIACAP_10BASE2) 364 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER | IFM_10_2, 365 ELINKMEDIA_10BASE_2, NULL); 366 else if (val & ELINK_MEDIACAP_10BASE5) 367 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER | IFM_10_5, 368 ELINKMEDIA_AUI, NULL); 369 #ifdef notyet 370 else if (val & ELINK_MEDIACAP_10BASEFL) 371 ifmedia_add(&sc->ex_mii.mii_media, 372 IFM_ETHER | IFM_10_FL, 0, NULL); 373 #endif 374 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER | IFM_NONE, 0, 375 NULL); 376 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER | IFM_NONE); 377 } 378 379 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 380 ifp->if_softc = sc; 381 ifp->if_start = ex_start; 382 ifp->if_ioctl = ex_ioctl; 383 ifp->if_watchdog = ex_watchdog; 384 ifp->if_flags = 385 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 386 387 if_attach(ifp); 388 ether_ifattach(ifp, macaddr); 389 390 GO_WINDOW(1); 391 392 sc->tx_start_thresh = 20; 393 sc->tx_succ_ok = 0; 394 395 /* TODO: set queues to 0 */ 396 397 #if NBPFILTER > 0 398 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 399 sizeof(struct ether_header)); 400 #endif 401 402 #if NRND > 0 403 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET); 404 #endif 405 406 /* Establish callback to reset card when we reboot. */ 407 shutdownhook_establish(ex_shutdown, sc); 408 return; 409 410 fail: 411 /* 412 * Free any resources we've allocated during the failed attach 413 * attempt. Do this in reverse order and fall though. 414 */ 415 switch (attach_stage) { 416 case 11: 417 { 418 struct ex_rxdesc *rxd; 419 420 for (i = 0; i < EX_NUPD; i++) { 421 rxd = &sc->sc_rxdescs[i]; 422 if (rxd->rx_mbhead != NULL) { 423 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 424 m_freem(rxd->rx_mbhead); 425 } 426 } 427 } 428 /* FALLTHROUGH */ 429 430 case 10: 431 for (i = 0; i < EX_NUPD; i++) 432 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 433 /* FALLTHROUGH */ 434 435 case 9: 436 for (i = 0; i < EX_NDPD; i++) 437 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 438 /* FALLTHROUGH */ 439 case 8: 440 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 441 /* FALLTHROUGH */ 442 443 case 7: 444 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 445 /* FALLTHROUGH */ 446 447 case 6: 448 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 449 EX_NDPD * sizeof (struct ex_dpd)); 450 /* FALLTHROUGH */ 451 452 case 5: 453 bus_dmamem_free(sc->sc_dmat, &dseg, drseg); 454 break; 455 456 case 4: 457 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 458 /* FALLTHROUGH */ 459 460 case 3: 461 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 462 /* FALLTHROUGH */ 463 464 case 2: 465 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 466 EX_NUPD * sizeof (struct ex_upd)); 467 /* FALLTHROUGH */ 468 469 case 1: 470 bus_dmamem_free(sc->sc_dmat, &useg, urseg); 471 break; 472 } 473 474 } 475 476 /* 477 * Bring device up. 478 */ 479 void 480 ex_init(sc) 481 struct ex_softc *sc; 482 { 483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 484 bus_space_tag_t iot = sc->sc_iot; 485 bus_space_handle_t ioh = sc->sc_ioh; 486 int s, i; 487 488 s = splnet(); 489 490 ex_waitcmd(sc); 491 ex_stop(sc); 492 493 /* 494 * Set the station address and clear the station mask. The latter 495 * is needed for 90x cards, 0 is the default for 90xB cards. 496 */ 497 GO_WINDOW(2); 498 for (i = 0; i < ETHER_ADDR_LEN; i++) { 499 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 500 LLADDR(ifp->if_sadl)[i]); 501 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 502 } 503 504 GO_WINDOW(3); 505 506 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 507 ex_waitcmd(sc); 508 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 509 ex_waitcmd(sc); 510 511 /* 512 * Disable reclaim threshold for 90xB, set free threshold to 513 * 6 * 256 = 1536 for 90x. 514 */ 515 if (sc->ex_conf & EX_CONF_90XB) 516 bus_space_write_2(iot, ioh, ELINK_COMMAND, 517 ELINK_TXRECLTHRESH | 255); 518 else 519 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 520 521 bus_space_write_2(iot, ioh, ELINK_COMMAND, 522 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 523 524 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 525 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 526 527 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_MASK); 528 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_MASK); 529 530 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 531 532 ex_set_media(sc); 533 ex_set_mc(sc); 534 535 536 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 537 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 538 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 539 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 540 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 541 542 ifp->if_flags |= IFF_RUNNING; 543 ifp->if_flags &= ~IFF_OACTIVE; 544 ex_start(ifp); 545 546 GO_WINDOW(1); 547 548 splx(s); 549 550 timeout(ex_tick, sc, hz); 551 } 552 553 /* 554 * Multicast hash filter according to the 3Com spec. 555 */ 556 static u_int16_t 557 ex_mchash(addr) 558 u_char *addr; 559 { 560 u_int32_t crc, carry; 561 int i, j; 562 u_char c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xffffffff; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = addr[i]; 569 for (j = 0; i < 8; i++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* Return the filter bit position. */ 579 return(crc & 0x000000ff); 580 } 581 582 583 /* 584 * Set multicast receive filter. Also take care of promiscuous mode 585 * here (XXX). 586 */ 587 void 588 ex_set_mc(sc) 589 register struct ex_softc *sc; 590 { 591 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 592 struct ethercom *ec = &sc->sc_ethercom; 593 struct ether_multi *enm; 594 struct ether_multistep estep; 595 int i; 596 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 597 598 if (ifp->if_flags & IFF_PROMISC) 599 mask |= FIL_PROMISC; 600 601 if (!(ifp->if_flags & IFF_MULTICAST)) 602 goto out; 603 604 if (!(sc->ex_conf & EX_CONF_90XB) || ifp->if_flags & IFF_ALLMULTI) { 605 mask |= (ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0; 606 } else { 607 ETHER_FIRST_MULTI(estep, ec, enm); 608 while (enm != NULL) { 609 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 610 ETHER_ADDR_LEN) != 0) 611 goto out; 612 i = ex_mchash(enm->enm_addrlo); 613 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 614 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 615 ETHER_NEXT_MULTI(estep, enm); 616 } 617 mask |= FIL_MULTIHASH; 618 } 619 out: 620 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 621 SET_RX_FILTER | mask); 622 } 623 624 625 static void 626 ex_txstat(sc) 627 struct ex_softc *sc; 628 { 629 bus_space_tag_t iot = sc->sc_iot; 630 bus_space_handle_t ioh = sc->sc_ioh; 631 int i; 632 633 /* 634 * We need to read+write TX_STATUS until we get a 0 status 635 * in order to turn off the interrupt flag. 636 */ 637 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) { 638 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0); 639 640 if (i & TXS_JABBER) { 641 ++sc->sc_ethercom.ec_if.if_oerrors; 642 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 643 printf("%s: jabber (%x)\n", 644 sc->sc_dev.dv_xname, i); 645 ex_init(sc); 646 /* TODO: be more subtle here */ 647 } else if (i & TXS_UNDERRUN) { 648 ++sc->sc_ethercom.ec_if.if_oerrors; 649 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 650 printf("%s: fifo underrun (%x) @%d\n", 651 sc->sc_dev.dv_xname, i, 652 sc->tx_start_thresh); 653 if (sc->tx_succ_ok < 100) 654 sc->tx_start_thresh = min(ETHER_MAX_LEN, 655 sc->tx_start_thresh + 20); 656 sc->tx_succ_ok = 0; 657 ex_init(sc); 658 /* TODO: be more subtle here */ 659 } else if (i & TXS_MAX_COLLISION) { 660 ++sc->sc_ethercom.ec_if.if_collisions; 661 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 662 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 663 } else 664 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 665 } 666 } 667 668 int 669 ex_media_chg(ifp) 670 struct ifnet *ifp; 671 { 672 struct ex_softc *sc = ifp->if_softc; 673 674 if (ifp->if_flags & IFF_UP) 675 ex_init(sc); 676 return 0; 677 } 678 679 void 680 ex_set_media(sc) 681 struct ex_softc *sc; 682 { 683 bus_space_tag_t iot = sc->sc_iot; 684 bus_space_handle_t ioh = sc->sc_ioh; 685 int config0, config1; 686 687 if (((sc->ex_conf & EX_CONF_MII) && 688 (sc->ex_mii.mii_media_active & IFM_FDX)) 689 || (!(sc->ex_conf & EX_CONF_MII) && 690 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 691 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 692 MAC_CONTROL_FDX); 693 } else { 694 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 695 } 696 697 /* 698 * If the device has MII, select it, and then tell the 699 * PHY which media to use. 700 */ 701 if (sc->ex_conf & EX_CONF_MII) { 702 GO_WINDOW(3); 703 704 config0 = (u_int)bus_space_read_2(iot, ioh, 705 ELINK_W3_INTERNAL_CONFIG); 706 config1 = (u_int)bus_space_read_2(iot, ioh, 707 ELINK_W3_INTERNAL_CONFIG + 2); 708 709 config1 = config1 & ~CONFIG_MEDIAMASK; 710 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 711 712 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 713 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 714 mii_mediachg(&sc->ex_mii); 715 return; 716 } 717 718 GO_WINDOW(4); 719 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 720 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 721 delay(800); 722 723 /* 724 * Now turn on the selected media/transceiver. 725 */ 726 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 727 case IFM_10_T: 728 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 729 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 730 break; 731 732 case IFM_10_2: 733 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 734 DELAY(800); 735 break; 736 737 case IFM_100_TX: 738 case IFM_100_FX: 739 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 740 LINKBEAT_ENABLE); 741 DELAY(800); 742 break; 743 744 case IFM_10_5: 745 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 746 SQE_ENABLE); 747 DELAY(800); 748 break; 749 750 case IFM_MANUAL: 751 break; 752 753 case IFM_NONE: 754 return; 755 756 default: 757 panic("ex_set_media: impossible"); 758 } 759 760 GO_WINDOW(3); 761 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 762 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 763 764 config1 = config1 & ~CONFIG_MEDIAMASK; 765 config1 |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 766 CONFIG_MEDIAMASK_SHIFT); 767 768 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 769 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 770 } 771 772 /* 773 * Get currently-selected media from card. 774 * (if_media callback, may be called before interface is brought up). 775 */ 776 void 777 ex_media_stat(ifp, req) 778 struct ifnet *ifp; 779 struct ifmediareq *req; 780 { 781 struct ex_softc *sc = ifp->if_softc; 782 783 if (sc->ex_conf & EX_CONF_MII) { 784 mii_pollstat(&sc->ex_mii); 785 req->ifm_status = sc->ex_mii.mii_media_status; 786 req->ifm_active = sc->ex_mii.mii_media_active; 787 } else { 788 GO_WINDOW(4); 789 req->ifm_status = IFM_AVALID; 790 req->ifm_active = sc->ex_mii.mii_media.ifm_cur->ifm_media; 791 if (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 792 ELINK_W4_MEDIA_TYPE) & LINKBEAT_DETECT) 793 req->ifm_status |= IFM_ACTIVE; 794 GO_WINDOW(1); 795 } 796 } 797 798 799 800 /* 801 * Start outputting on the interface. 802 */ 803 static void 804 ex_start(ifp) 805 struct ifnet *ifp; 806 { 807 struct ex_softc *sc = ifp->if_softc; 808 bus_space_tag_t iot = sc->sc_iot; 809 bus_space_handle_t ioh = sc->sc_ioh; 810 volatile struct ex_fraghdr *fr = NULL; 811 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 812 struct ex_txdesc *txp; 813 bus_dmamap_t dmamap; 814 int offset, totlen; 815 816 if (sc->tx_head || sc->tx_free == NULL) 817 return; 818 819 txp = NULL; 820 821 /* 822 * We're finished if there is nothing more to add to the list or if 823 * we're all filled up with buffers to transmit. 824 */ 825 while (ifp->if_snd.ifq_head != NULL && sc->tx_free != NULL) { 826 struct mbuf *mb_head; 827 int segment, error; 828 829 /* 830 * Grab a packet to transmit. 831 */ 832 IF_DEQUEUE(&ifp->if_snd, mb_head); 833 834 /* 835 * Get pointer to next available tx desc. 836 */ 837 txp = sc->tx_free; 838 sc->tx_free = txp->tx_next; 839 txp->tx_next = NULL; 840 dmamap = txp->tx_dmamap; 841 842 /* 843 * Go through each of the mbufs in the chain and initialize 844 * the transmit buffer descriptors with the physical address 845 * and size of the mbuf. 846 */ 847 reload: 848 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 849 mb_head, BUS_DMA_NOWAIT); 850 switch (error) { 851 case 0: 852 /* Success. */ 853 break; 854 855 case EFBIG: 856 { 857 struct mbuf *mn; 858 859 /* 860 * We ran out of segments. We have to recopy this 861 * mbuf chain first. Bail out if we can't get the 862 * new buffers. 863 */ 864 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 865 866 MGETHDR(mn, M_DONTWAIT, MT_DATA); 867 if (mn == NULL) { 868 m_freem(mb_head); 869 printf("aborting\n"); 870 goto out; 871 } 872 if (mb_head->m_pkthdr.len > MHLEN) { 873 MCLGET(mn, M_DONTWAIT); 874 if ((mn->m_flags & M_EXT) == 0) { 875 m_freem(mn); 876 m_freem(mb_head); 877 printf("aborting\n"); 878 goto out; 879 } 880 } 881 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 882 mtod(mn, caddr_t)); 883 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 884 m_freem(mb_head); 885 mb_head = mn; 886 printf("retrying\n"); 887 goto reload; 888 } 889 890 default: 891 /* 892 * Some other problem; report it. 893 */ 894 printf("%s: can't load mbuf chain, error = %d\n", 895 sc->sc_dev.dv_xname, error); 896 m_freem(mb_head); 897 goto out; 898 } 899 900 fr = &txp->tx_dpd->dpd_frags[0]; 901 totlen = 0; 902 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 903 fr->fr_addr = dmamap->dm_segs[segment].ds_addr; 904 fr->fr_len = dmamap->dm_segs[segment].ds_len; 905 totlen += fr->fr_len; 906 } 907 fr--; 908 fr->fr_len |= EX_FR_LAST; 909 txp->tx_mbhead = mb_head; 910 911 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 912 BUS_DMASYNC_PREWRITE); 913 914 dpd = txp->tx_dpd; 915 dpd->dpd_nextptr = 0; 916 dpd->dpd_fsh = totlen; 917 918 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 919 ((caddr_t)dpd - (caddr_t)sc->sc_dpd), 920 sizeof (struct ex_dpd), 921 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 922 923 /* 924 * No need to stall the download engine, we know it's 925 * not busy right now. 926 * 927 * Fix up pointers in both the "soft" tx and the physical 928 * tx list. 929 */ 930 if (sc->tx_head != NULL) { 931 prevdpd = sc->tx_tail->tx_dpd; 932 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd); 933 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 934 offset, sizeof (struct ex_dpd), 935 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 936 prevdpd->dpd_nextptr = DPD_DMADDR(sc, txp); 937 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 938 offset, sizeof (struct ex_dpd), 939 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 940 sc->tx_tail->tx_next = txp; 941 sc->tx_tail = txp; 942 } else { 943 sc->tx_tail = sc->tx_head = txp; 944 } 945 946 #if NBPFILTER > 0 947 /* 948 * Pass packet to bpf if there is a listener. 949 */ 950 if (ifp->if_bpf) 951 bpf_mtap(ifp->if_bpf, mb_head); 952 #endif 953 } 954 out: 955 if (sc->tx_head) { 956 sc->tx_tail->tx_dpd->dpd_fsh |= EX_DPD_DNIND; 957 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 958 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 959 sizeof (struct ex_dpd), 960 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 961 ifp->if_flags |= IFF_OACTIVE; 962 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 963 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 964 DPD_DMADDR(sc, sc->tx_head)); 965 } 966 } 967 968 969 int 970 ex_intr(arg) 971 void *arg; 972 { 973 struct ex_softc *sc = arg; 974 bus_space_tag_t iot = sc->sc_iot; 975 bus_space_handle_t ioh = sc->sc_ioh; 976 u_int16_t stat; 977 int ret = 0; 978 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 979 980 for (;;) { 981 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 982 if (!(stat & S_MASK)) 983 break; 984 /* 985 * Acknowledge interrupts. 986 */ 987 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 988 (stat & S_MASK)); 989 ret = 1; 990 if (stat & S_HOST_ERROR) { 991 printf("%s: adapter failure (%x)\n", 992 sc->sc_dev.dv_xname, stat); 993 bus_space_write_2(iot, ioh, ELINK_COMMAND, 994 C_INTR_LATCH); 995 ex_reset(sc); 996 ex_init(sc); 997 return 1; 998 } 999 if (stat & S_TX_COMPLETE) { 1000 ex_txstat(sc); 1001 } 1002 if (stat & S_UPD_STATS) { 1003 ex_getstats(sc); 1004 } 1005 if (stat & S_DN_COMPLETE) { 1006 struct ex_txdesc *txp, *ptxp = NULL; 1007 bus_dmamap_t txmap; 1008 for (txp = sc->tx_head; txp != NULL; 1009 txp = txp->tx_next) { 1010 bus_dmamap_sync(sc->sc_dmat, 1011 sc->sc_dpd_dmamap, 1012 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1013 sizeof (struct ex_dpd), 1014 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1015 if (txp->tx_mbhead != NULL) { 1016 txmap = txp->tx_dmamap; 1017 bus_dmamap_sync(sc->sc_dmat, txmap, 1018 0, txmap->dm_mapsize, 1019 BUS_DMASYNC_POSTWRITE); 1020 bus_dmamap_unload(sc->sc_dmat, txmap); 1021 m_freem(txp->tx_mbhead); 1022 txp->tx_mbhead = NULL; 1023 } 1024 ptxp = txp; 1025 } 1026 1027 /* 1028 * Move finished tx buffers back to the tx free list. 1029 */ 1030 if (sc->tx_free) { 1031 sc->tx_ftail->tx_next = sc->tx_head; 1032 sc->tx_ftail = ptxp; 1033 } else 1034 sc->tx_ftail = sc->tx_free = sc->tx_head; 1035 1036 sc->tx_head = sc->tx_tail = NULL; 1037 ifp->if_flags &= ~IFF_OACTIVE; 1038 } 1039 1040 if (stat & S_UP_COMPLETE) { 1041 struct ex_rxdesc *rxd; 1042 struct mbuf *m; 1043 struct ex_upd *upd; 1044 bus_dmamap_t rxmap; 1045 u_int32_t pktstat; 1046 1047 rcvloop: 1048 rxd = sc->rx_head; 1049 rxmap = rxd->rx_dmamap; 1050 m = rxd->rx_mbhead; 1051 upd = rxd->rx_upd; 1052 pktstat = upd->upd_pktstatus; 1053 1054 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1055 rxmap->dm_mapsize, 1056 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1057 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1058 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1059 sizeof (struct ex_upd), 1060 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1061 1062 if (pktstat & EX_UPD_COMPLETE) { 1063 /* 1064 * Remove first packet from the chain. 1065 */ 1066 sc->rx_head = rxd->rx_next; 1067 rxd->rx_next = NULL; 1068 1069 /* 1070 * Add a new buffer to the receive chain. 1071 * If this fails, the old buffer is recycled 1072 * instead. 1073 */ 1074 if (ex_add_rxbuf(sc, rxd) == 0) { 1075 struct ether_header *eh; 1076 u_int16_t total_len; 1077 1078 1079 if (pktstat & EX_UPD_ERR) { 1080 ifp->if_ierrors++; 1081 m_freem(m); 1082 goto rcvloop; 1083 } 1084 1085 total_len = pktstat & EX_UPD_PKTLENMASK; 1086 if (total_len < 1087 sizeof(struct ether_header)) { 1088 m_freem(m); 1089 goto rcvloop; 1090 } 1091 m->m_pkthdr.rcvif = ifp; 1092 m->m_pkthdr.len = m->m_len = 1093 total_len - 1094 sizeof(struct ether_header); 1095 eh = mtod(m, struct ether_header *); 1096 #if NBPFILTER > 0 1097 if (ifp->if_bpf) { 1098 bpf_tap(ifp->if_bpf, 1099 mtod(m, caddr_t), 1100 total_len); 1101 /* 1102 * Only pass this packet up 1103 * if it is for us. 1104 */ 1105 if ((ifp->if_flags & 1106 IFF_PROMISC) && 1107 (eh->ether_dhost[0] & 1) 1108 == 0 && 1109 bcmp(eh->ether_dhost, 1110 LLADDR(ifp->if_sadl), 1111 sizeof(eh->ether_dhost)) 1112 != 0) { 1113 m_freem(m); 1114 goto rcvloop; 1115 } 1116 } 1117 #endif /* NBPFILTER > 0 */ 1118 m->m_data += 1119 sizeof(struct ether_header); 1120 ether_input(ifp, eh, m); 1121 } 1122 goto rcvloop; 1123 } 1124 /* 1125 * Just in case we filled up all UPDs and the DMA engine 1126 * stalled. We could be more subtle about this, 1127 * but we can only do that by reading a register 1128 * first, so just always do it. 1129 */ 1130 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1131 ELINK_UPUNSTALL); 1132 } 1133 } 1134 if (ret) { 1135 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1136 if (ifp->if_snd.ifq_head != NULL) 1137 ex_start(ifp); 1138 } 1139 return ret; 1140 } 1141 1142 int 1143 ex_ioctl(ifp, cmd, data) 1144 register struct ifnet *ifp; 1145 u_long cmd; 1146 caddr_t data; 1147 { 1148 struct ex_softc *sc = ifp->if_softc; 1149 struct ifaddr *ifa = (struct ifaddr *)data; 1150 struct ifreq *ifr = (struct ifreq *)data; 1151 int s, error = 0; 1152 1153 s = splnet(); 1154 1155 switch (cmd) { 1156 1157 case SIOCSIFADDR: 1158 ifp->if_flags |= IFF_UP; 1159 switch (ifa->ifa_addr->sa_family) { 1160 #ifdef INET 1161 case AF_INET: 1162 ex_init(sc); 1163 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1164 break; 1165 #endif 1166 #ifdef NS 1167 case AF_NS: 1168 { 1169 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1170 1171 if (ns_nullhost(*ina)) 1172 ina->x_host = *(union ns_host *) 1173 LLADDR(ifp->if_sadl); 1174 else 1175 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1176 ifp->if_addrlen); 1177 /* Set new address. */ 1178 ex_init(sc); 1179 break; 1180 } 1181 #endif 1182 default: 1183 ex_init(sc); 1184 break; 1185 } 1186 break; 1187 case SIOCSIFMEDIA: 1188 case SIOCGIFMEDIA: 1189 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1190 break; 1191 1192 case SIOCSIFFLAGS: 1193 if ((ifp->if_flags & IFF_UP) == 0 && 1194 (ifp->if_flags & IFF_RUNNING) != 0) { 1195 /* 1196 * If interface is marked down and it is running, then 1197 * stop it. 1198 */ 1199 ex_stop(sc); 1200 ifp->if_flags &= ~IFF_RUNNING; 1201 } else if ((ifp->if_flags & IFF_UP) != 0 && 1202 (ifp->if_flags & IFF_RUNNING) == 0) { 1203 /* 1204 * If interface is marked up and it is stopped, then 1205 * start it. 1206 */ 1207 ex_init(sc); 1208 } else 1209 ex_set_mc(sc); 1210 break; 1211 1212 case SIOCADDMULTI: 1213 case SIOCDELMULTI: 1214 error = (cmd == SIOCADDMULTI) ? 1215 ether_addmulti(ifr, &sc->sc_ethercom) : 1216 ether_delmulti(ifr, &sc->sc_ethercom); 1217 1218 if (error == ENETRESET) { 1219 /* 1220 * Multicast list has changed; set the hardware filter 1221 * accordingly. 1222 */ 1223 ex_set_mc(sc); 1224 error = 0; 1225 } 1226 break; 1227 1228 default: 1229 error = EINVAL; 1230 break; 1231 } 1232 1233 splx(s); 1234 return (error); 1235 } 1236 1237 void 1238 ex_getstats(sc) 1239 struct ex_softc *sc; 1240 { 1241 bus_space_handle_t ioh = sc->sc_ioh; 1242 bus_space_tag_t iot = sc->sc_iot; 1243 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1244 u_int8_t upperok; 1245 1246 GO_WINDOW(6); 1247 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1248 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1249 ifp->if_ipackets += (upperok & 0x03) << 8; 1250 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1251 ifp->if_opackets += (upperok & 0x30) << 4; 1252 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1253 ifp->if_oerrors += bus_space_read_1(iot, ioh, TX_DEFERRALS); 1254 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1255 /* 1256 * There seems to be no way to get the exact number of collisions, 1257 * this is the number that occured at the very least. 1258 */ 1259 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1260 TX_AFTER_X_COLLISIONS); 1261 ifp->if_ibytes += bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1262 ifp->if_obytes += bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1263 1264 /* 1265 * Clear the following to avoid stats overflow interrupts 1266 */ 1267 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1268 bus_space_read_1(iot, ioh, TX_NO_SQE); 1269 bus_space_read_1(iot, ioh, TX_CD_LOST); 1270 GO_WINDOW(4); 1271 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1272 upperok = bus_space_read_1(iot, ioh, ELINK_W4_UBYTESOK); 1273 ifp->if_ibytes += (upperok & 0x0f) << 16; 1274 ifp->if_obytes += (upperok & 0xf0) << 12; 1275 GO_WINDOW(1); 1276 } 1277 1278 void 1279 ex_printstats(sc) 1280 struct ex_softc *sc; 1281 { 1282 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1283 1284 ex_getstats(sc); 1285 printf("in %ld out %ld ierror %ld oerror %ld ibytes %ld obytes %ld\n", 1286 ifp->if_ipackets, ifp->if_opackets, ifp->if_ierrors, 1287 ifp->if_oerrors, ifp->if_ibytes, ifp->if_obytes); 1288 } 1289 1290 void 1291 ex_tick(arg) 1292 void *arg; 1293 { 1294 struct ex_softc *sc = arg; 1295 int s = splnet(); 1296 1297 if (sc->ex_conf & EX_CONF_MII) 1298 mii_tick(&sc->ex_mii); 1299 1300 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1301 & S_COMMAND_IN_PROGRESS)) 1302 ex_getstats(sc); 1303 1304 splx(s); 1305 1306 timeout(ex_tick, sc, hz); 1307 } 1308 1309 1310 void 1311 ex_reset(sc) 1312 struct ex_softc *sc; 1313 { 1314 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, GLOBAL_RESET); 1315 ex_waitcmd(sc); 1316 } 1317 1318 void 1319 ex_watchdog(ifp) 1320 struct ifnet *ifp; 1321 { 1322 struct ex_softc *sc = ifp->if_softc; 1323 1324 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1325 ++sc->sc_ethercom.ec_if.if_oerrors; 1326 1327 ex_reset(sc); 1328 ex_init(sc); 1329 } 1330 1331 void 1332 ex_stop(sc) 1333 struct ex_softc *sc; 1334 { 1335 bus_space_tag_t iot = sc->sc_iot; 1336 bus_space_handle_t ioh = sc->sc_ioh; 1337 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1338 struct ex_txdesc *tx; 1339 struct ex_rxdesc *rx; 1340 int i; 1341 1342 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1343 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1344 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1345 1346 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1347 if (tx->tx_mbhead == NULL) 1348 continue; 1349 m_freem(tx->tx_mbhead); 1350 tx->tx_mbhead = NULL; 1351 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1352 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1353 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1354 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1355 sizeof (struct ex_dpd), 1356 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1357 } 1358 sc->tx_tail = sc->tx_head = NULL; 1359 ex_init_txdescs(sc); 1360 1361 sc->rx_tail = sc->rx_head = 0; 1362 for (i = 0; i < EX_NUPD; i++) { 1363 rx = &sc->sc_rxdescs[i]; 1364 if (rx->rx_mbhead != NULL) { 1365 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1366 m_freem(rx->rx_mbhead); 1367 rx->rx_mbhead = NULL; 1368 } 1369 ex_add_rxbuf(sc, rx); 1370 } 1371 1372 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1373 1374 untimeout(ex_tick, sc); 1375 1376 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1377 ifp->if_timer = 0; 1378 } 1379 1380 static void 1381 ex_init_txdescs(sc) 1382 struct ex_softc *sc; 1383 { 1384 int i; 1385 1386 for (i = 0; i < EX_NDPD; i++) { 1387 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1388 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1389 if (i < EX_NDPD - 1) 1390 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1391 else 1392 sc->sc_txdescs[i].tx_next = NULL; 1393 } 1394 sc->tx_free = &sc->sc_txdescs[0]; 1395 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1396 } 1397 1398 1399 /* 1400 * Before reboots, reset card completely. 1401 */ 1402 static void 1403 ex_shutdown(arg) 1404 void *arg; 1405 { 1406 register struct ex_softc *sc = arg; 1407 1408 ex_stop(sc); 1409 } 1410 1411 /* 1412 * Read EEPROM data. 1413 * XXX what to do if EEPROM doesn't unbusy? 1414 */ 1415 u_int16_t 1416 ex_read_eeprom(sc, offset) 1417 struct ex_softc *sc; 1418 int offset; 1419 { 1420 bus_space_tag_t iot = sc->sc_iot; 1421 bus_space_handle_t ioh = sc->sc_ioh; 1422 u_int16_t data = 0; 1423 1424 GO_WINDOW(0); 1425 if (ex_eeprom_busy(sc)) 1426 goto out; 1427 bus_space_write_1(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1428 READ_EEPROM | (offset & 0x3f)); 1429 if (ex_eeprom_busy(sc)) 1430 goto out; 1431 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1432 out: 1433 return data; 1434 } 1435 1436 static int 1437 ex_eeprom_busy(sc) 1438 struct ex_softc *sc; 1439 { 1440 bus_space_tag_t iot = sc->sc_iot; 1441 bus_space_handle_t ioh = sc->sc_ioh; 1442 int i = 100; 1443 1444 while (i--) { 1445 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1446 EEPROM_BUSY)) 1447 return 0; 1448 delay(100); 1449 } 1450 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1451 return (1); 1452 } 1453 1454 /* 1455 * Create a new rx buffer and add it to the 'soft' rx list. 1456 */ 1457 static int 1458 ex_add_rxbuf(sc, rxd) 1459 struct ex_softc *sc; 1460 struct ex_rxdesc *rxd; 1461 { 1462 struct mbuf *m, *oldm; 1463 bus_dmamap_t rxmap; 1464 int error, rval = 0; 1465 1466 oldm = rxd->rx_mbhead; 1467 rxmap = rxd->rx_dmamap; 1468 1469 MGETHDR(m, M_DONTWAIT, MT_DATA); 1470 if (m != NULL) { 1471 MCLGET(m, M_DONTWAIT); 1472 if ((m->m_flags & M_EXT) == 0) { 1473 m_freem(m); 1474 if (oldm == NULL) 1475 return 1; 1476 m = oldm; 1477 m->m_data = m->m_ext.ext_buf; 1478 rval = 1; 1479 } 1480 } else { 1481 if (oldm == NULL) 1482 return 1; 1483 m = oldm; 1484 m->m_data = m->m_ext.ext_buf; 1485 rval = 1; 1486 } 1487 1488 /* 1489 * Setup the DMA map for this receive buffer. 1490 */ 1491 if (m != oldm) { 1492 if (oldm != NULL) 1493 bus_dmamap_unload(sc->sc_dmat, rxmap); 1494 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1495 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_NOWAIT); 1496 if (error) { 1497 printf("%s: can't load rx buffer, error = %d\n", 1498 sc->sc_dev.dv_xname, error); 1499 panic("ex_add_rxbuf"); /* XXX */ 1500 } 1501 } 1502 1503 /* 1504 * Align for data after 14 byte header. 1505 */ 1506 m->m_data += 2; 1507 1508 rxd->rx_mbhead = m; 1509 rxd->rx_upd->upd_pktstatus = MCLBYTES - 2; 1510 rxd->rx_upd->upd_frags[0].fr_addr = rxmap->dm_segs[0].ds_addr + 2; 1511 rxd->rx_upd->upd_nextptr = 0; 1512 1513 /* 1514 * Attach it to the end of the list. 1515 */ 1516 if (sc->rx_head != NULL) { 1517 sc->rx_tail->rx_next = rxd; 1518 sc->rx_tail->rx_upd->upd_nextptr = sc->sc_upddma + 1519 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd); 1520 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1521 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1522 sizeof (struct ex_upd), 1523 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1524 } else { 1525 sc->rx_head = rxd; 1526 } 1527 sc->rx_tail = rxd; 1528 1529 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1530 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1531 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1532 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1533 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1534 return (rval); 1535 } 1536 1537 void 1538 ex_mii_setbit(v, bit) 1539 void *v; 1540 u_int16_t bit; 1541 { 1542 struct ex_softc *sc = v; 1543 u_int16_t val; 1544 1545 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1546 val |= bit; 1547 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1548 } 1549 1550 void 1551 ex_mii_clrbit(v, bit) 1552 void *v; 1553 u_int16_t bit; 1554 { 1555 struct ex_softc *sc = v; 1556 u_int16_t val; 1557 1558 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1559 val &= ~bit; 1560 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1561 } 1562 1563 u_int16_t 1564 ex_mii_readbit(v, bit) 1565 void *v; 1566 u_int16_t bit; 1567 { 1568 struct ex_softc *sc = v; 1569 u_int16_t val; 1570 1571 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1572 return (val & bit); 1573 } 1574 1575 /* 1576 * The reason why all this stuff below is here, is that we need a special 1577 * readreg function. It needs to check if we're accessing the internal 1578 * PHY on 905B-TX boards, or not. If so, the read must fail immediately, 1579 * because 905B-TX boards seem to return garbage from the MII if you 1580 * try to access non-existing PHYs. 1581 */ 1582 1583 int 1584 ex_mii_readreg(v, phy, reg) 1585 struct device *v; 1586 int phy; 1587 int reg; 1588 { 1589 struct ex_softc *sc = (struct ex_softc *)v; 1590 int val = 0; 1591 int err =0; 1592 int i; 1593 1594 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1595 return 0; 1596 1597 GO_WINDOW(4); 1598 1599 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, 0); 1600 1601 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1602 for (i = 0; i < 32; i++) { 1603 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1604 ex_mii_setbit(sc, ELINK_PHY_CLK); 1605 } 1606 ex_mii_writebits(sc, MII_COMMAND_START, 2); 1607 ex_mii_writebits(sc, MII_COMMAND_READ, 2); 1608 ex_mii_writebits(sc, phy, 5); 1609 ex_mii_writebits(sc, reg, 5); 1610 1611 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1612 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1613 ex_mii_setbit(sc, ELINK_PHY_CLK); 1614 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1615 1616 err = ex_mii_readbit(sc, ELINK_PHY_DATA); 1617 ex_mii_setbit(sc, ELINK_PHY_CLK); 1618 1619 for (i = 0; i < 16; i++) { 1620 val <<= 1; 1621 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1622 if (err == 0 && ex_mii_readbit(sc, ELINK_PHY_DATA)) 1623 val |= 1; 1624 ex_mii_setbit(sc, ELINK_PHY_CLK); 1625 } 1626 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1627 ex_mii_setbit(sc, ELINK_PHY_CLK); 1628 1629 GO_WINDOW(1); 1630 1631 return (err ? 0 : val); 1632 } 1633 1634 static void 1635 ex_mii_writebits(sc, data, nbits) 1636 struct ex_softc *sc; 1637 unsigned int data; 1638 int nbits; 1639 { 1640 int i; 1641 1642 ex_mii_setbit(sc, ELINK_PHY_DIR); 1643 for (i = 1 << (nbits -1); i; i = i >> 1) { 1644 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1645 ex_mii_readbit(sc, ELINK_PHY_CLK); 1646 if (data & i) 1647 ex_mii_setbit(sc, ELINK_PHY_DATA); 1648 else 1649 ex_mii_clrbit(sc, ELINK_PHY_DATA); 1650 ex_mii_setbit(sc, ELINK_PHY_CLK); 1651 ex_mii_readbit(sc, ELINK_PHY_CLK); 1652 } 1653 } 1654 1655 void 1656 ex_mii_writereg(v, phy, reg, data) 1657 struct device *v; 1658 int phy; 1659 int reg; 1660 int data; 1661 { 1662 struct ex_softc *sc = (struct ex_softc *)v; 1663 int i; 1664 1665 GO_WINDOW(4); 1666 1667 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1668 for (i = 0; i < 32; i++) { 1669 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1670 ex_mii_setbit(sc, ELINK_PHY_CLK); 1671 } 1672 ex_mii_writebits(sc, MII_COMMAND_START, 2); 1673 ex_mii_writebits(sc, MII_COMMAND_WRITE, 2); 1674 ex_mii_writebits(sc, phy, 5); 1675 ex_mii_writebits(sc, reg, 5); 1676 ex_mii_writebits(sc, MII_COMMAND_ACK, 2); 1677 ex_mii_writebits(sc, data, 16); 1678 1679 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1680 ex_mii_setbit(sc, ELINK_PHY_CLK); 1681 1682 GO_WINDOW(1); 1683 } 1684 1685 void 1686 ex_mii_statchg(v) 1687 struct device *v; 1688 { 1689 struct ex_softc *sc = (struct ex_softc *)v; 1690 bus_space_tag_t iot = sc->sc_iot; 1691 bus_space_handle_t ioh = sc->sc_ioh; 1692 int mctl; 1693 1694 /* XXX Update ifp->if_baudrate */ 1695 1696 GO_WINDOW(3); 1697 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1698 if (sc->ex_mii.mii_media_active & IFM_FDX) 1699 mctl |= MAC_CONTROL_FDX; 1700 else 1701 mctl &= ~MAC_CONTROL_FDX; 1702 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1703 GO_WINDOW(1); /* back to operating window */ 1704 } 1705
Indexes created Wed Oct 22 13:09:56 GMT 2025